phase9: merge cycle 1 — 57 claims verified, 39 new regions (206 distinct bodies)
Coordinator-verified every staged claim with its own range runs (57/57 MATCH, one required the staged gp symbol g_80122158). Merged to a candidate, whole- binary gate MATCH at c_regions=215, differing_bytes=0, SHA-1 e173426c157384ebf1b6caf8c6fea18a85a14af9; promoted; make check green (regions=215 disagreements=0 result=AGREE, c_regions=215 MATCH, 223 tests). Workers: A 23, B 13, C 21 claims. New symbols: g_80122158/g_80122068/ g_8012277C/g_80122738 (gp-marked, worker C request). Override additions: 0x80104C38 maspsx=off (verified 1-byte DIFF with maspsx on at the loop back-edge, finding 17 family). gtemac.h GTE control map corrected after two workers' independent decodes and coordinator raw-word verification: the executable's control registers are the standard map UNshifted for 0..5 (rotation matrix, 0x80101CAC) and standard+7 from RBK onward (3 RBK .. 8 DQB); light matrix is 6..0, far colour 1..3, H 6, DQA 7, DQB 8. Cookbook finding 24's label for 3..5 was wrong; the numbers were always right. Added gte_ldH, gte_ldRT1RT2..gte_ldRT33; func_8001AE3C.c updated to the corrected RBK/GBK/BBK macros (re-verified MATCH); 0x80102FD4 and 0x80101CAC rewritten to macro form (re-verified MATCH). Recorded negatives: A 4 (cond-value-ifconv, alloc-scheduling, cc1-fold, strength-reduce+loop-rotate), B 7 (incl. exit-duplication, load-use-nop GTE alloc class, finding-4 sign-adjust trap), C 6 (incl. delay-slot-fill class, cc1-scheduler-bound). All deployed from src/.
This commit is contained in:
Christopher Williams
+47
-8
@@ -32,9 +32,11 @@
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* LIMITS. Only the operations listed below are covered, and only for the
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* register numbers observed here. The control-register numbering used by the
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* original is NOT the 0..31 "textbook" GTE control layout: this executable
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* writes DQB at $28, OFX/OFY at $24/$25, H at $26 and LR1LR2/LR3LG1/LG2LG3 at
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* $13/$14/$15, so the numbers below are the evidence, not a derivation. The
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* file is not an attempt to reconstruct Sony's gtemac.h.
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* writes DQB at $28, DQA at $27, OFX/OFY at $24/$25, H at $26, the far-colour
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* triple RFC/GFC/BFC at $21/$22/$23, and the light-direction triple
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* LR1LR2/LR3LG1/LG2LG3 at $13/$14/$15, so the numbers below are the evidence,
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* not a derivation. The file is not an attempt to reconstruct Sony's
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* gtemac.h.
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*/
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#ifndef SF3_GTEMAC_H
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@@ -61,17 +63,54 @@
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/* --- control registers (ctc2/cfc2) --------------------------------------- */
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/* --- control registers (ctc2/cfc2) --------------------------------------- */
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/* Rotation/translation matrix (UNSHIFTED standard map, 0x80101CAC: five
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* `ctc2`s from five loads). The executable uses the standard 0..5 numbers
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* here and standard+7 from RBK onward, so the 0x00-0x05 block is the only
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* unshifted control range. The four RT words hold the 3x3 rotation sorted
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* by the standard naming (RT1RT2 = row1col1,row1col2, ...):
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* $0 = RT1RT2 $1 = RT3RT21 $2 = RT22RT23
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* $3 = RT31RT32 $4 = RT33
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* $5 = TRX (TRY/TRZ unobserved; assumed from the standard order) */
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#define gte_ldRT1RT2(v) __asm__ volatile ("ctc2 %0,$0" : : "r"(v))
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#define gte_ldRT3RT21(v) __asm__ volatile ("ctc2 %0,$1" : : "r"(v))
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#define gte_ldRT22RT23(v) __asm__ volatile ("ctc2 %0,$2" : : "r"(v))
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#define gte_ldRT31RT32(v) __asm__ volatile ("ctc2 %0,$3" : : "r"(v))
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#define gte_ldRT33(v) __asm__ volatile ("ctc2 %0,$4" : : "r"(v))
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/* Rotation/light source and colour-matrix control words.
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* $13/$14/$15 = LR1LR2 / LR3LG1 / LG2LG3 (0x8001AE3C, three `ctc2`s)
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* The executable's control-register numbering is the standard map shifted
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* by +7 (all byte-proved): RBK/GBK/BBK at $13/$14/$15, the light-matrix
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* triple plus LB1LB2/LB3 at $16..$20, the far-colour triple RFC/GFC/BFC at
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* $21/$22/$23, OFX/OFY at $24/$25, H at $26, DQA at $27, DQB at $28. The
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* data-register space is the standard map unshifted (see above).
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* $13/$14/$15 = RBK / GBK / BBK (0x8001AE3C, three `ctc2`s)
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* $16/$17/$18 = LR1LR2 / LR3LG1 / LG2LG3 (0x80102FE4, with $19/$20 =
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* $19/$20 = LB1LB2 / LB3 LB1LB2/LB3 — same body)
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* $21/$22/$23 = RFC / GFC / BFC (0x80103B6C, each shifted left
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* by 4 before the write)
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* $24/$25 = OFX / OFY (0x80109778, after `sll ...,16`)
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* $26 = H (0x80103A94, `cfc2 v0,$26`)
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* $26 = H (0x80103A94 `cfc2 v0,$26`,
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* 0x80102FD4 `ctc2 a0,$26`)
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* $27 = DQA (0x80103B54, `ctc2 a0,$27`)
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* $28 = DQB (0x80103B60, `ctc2 a0,$28`) */
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#define gte_ldLR1LR2(v) __asm__ volatile ("ctc2 %0,$13" : : "r"(v))
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#define gte_ldLR3LG1(v) __asm__ volatile ("ctc2 %0,$14" : : "r"(v))
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#define gte_ldLG2LG3(v) __asm__ volatile ("ctc2 %0,$15" : : "r"(v))
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#define gte_ldRBK(v) __asm__ volatile ("ctc2 %0,$13" : : "r"(v))
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#define gte_ldGBK(v) __asm__ volatile ("ctc2 %0,$14" : : "r"(v))
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#define gte_ldBBK(v) __asm__ volatile ("ctc2 %0,$15" : : "r"(v))
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#define gte_ldLR1LR2(v) __asm__ volatile ("ctc2 %0,$16" : : "r"(v))
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#define gte_ldLR3LG1(v) __asm__ volatile ("ctc2 %0,$17" : : "r"(v))
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#define gte_ldLG2LG3(v) __asm__ volatile ("ctc2 %0,$18" : : "r"(v))
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#define gte_ldLB1LB2(v) __asm__ volatile ("ctc2 %0,$19" : : "r"(v))
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#define gte_ldLB3(v) __asm__ volatile ("ctc2 %0,$20" : : "r"(v))
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#define gte_ldRFC(v) __asm__ volatile ("ctc2 %0,$21" : : "r"(v))
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#define gte_ldGFC(v) __asm__ volatile ("ctc2 %0,$22" : : "r"(v))
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#define gte_ldBFC(v) __asm__ volatile ("ctc2 %0,$23" : : "r"(v))
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#define gte_ldOFX(v) __asm__ volatile ("ctc2 %0,$24" : : "r"(v))
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#define gte_ldOFY(v) __asm__ volatile ("ctc2 %0,$25" : : "r"(v))
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#define gte_ldH(v) __asm__ volatile ("ctc2 %0,$26" : : "r"(v))
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#define gte_stH(r) __asm__ volatile ("cfc2 %0,$26" : "=r"(r))
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#define gte_ldDQA(v) __asm__ volatile ("ctc2 %0,$27" : : "r"(v))
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#define gte_ldDQB(v) __asm__ volatile ("ctc2 %0,$28" : : "r"(v))
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/* --- commands ------------------------------------------------------------ */
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