From 6da840f3ab5cfde6e12a3b801f2833a13c8e64db Mon Sep 17 00:00:00 2001 From: Christopher Williams Date: Thu, 24 Sep 2026 18:15:57 -0400 Subject: [PATCH] =?UTF-8?q?phase12:=20recovery=20merge=209=20=E2=80=94=206?= =?UTF-8?q?35=20bodies=20/=20644=20regions=20(+33,=20past=20the=20cycle-1?= =?UTF-8?q?=20checkpoint)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All four workers stopped when the account ran out of credit. This commit recovers every row they had produced and verified but not yet reported, and it is the first thing done on resumption. RECOVERY AUDIT, because work that was produced but never claimed is INVISIBLE to the merge flow (charter rule 13): untracked src/ files produced this phase 11 distinct addresses claimed in ANY staging file 29 src/ files claimed by nothing (orphans) 0 claims whose source file is missing 0 One false alarm worth recording: my first pass globbed `.run/p12/w-*/claims.tsv` and reported `src/func_801008DC.c` as an orphan. It is claimed -- in `claims-altcc1.tsv`, which is a DELIBERATE separate pool because those rows need the `cc1bin` override. The audit tool was wrong, not the worker. A `src/`-vs-claims audit must glob EVERY claims file a charter defines, not just the default one, or it manufactures orphans. I re-verified ALL 29 claimed rows from fresh --work directories with `--symbols` (and `--cc1 gcc-2.8.1-psx/cc1` for the four `cc1bin` rows) BEFORE merging: **29 of 29 `differing_bytes=0 result=MATCH`, exit 0.** Then one `apply --skip-registered` over the combined input: 19 skipped as already merged, 10 added, 0 rejected. sf3_match gate c_regions=644 differing_bytes=0 result=MATCH sha1 e173426c157384ebf1b6caf8c6fea18a85a14af9 (unchanged) make check exit 0 extents-verify regions=644 disagreements=0 AGREE make worklist listed=984, excluded_already_registered=642 registry audit 644 rows, 635 distinct bodies, 0 missing, 4 carry cc1bin The 10 recovered rows, and they are the phase's best evidence that the dispatch re-cut worked: 0x8006D3B0 (192 B) and 0x8006AA88 (244 B) -- worker A, adjacency 0x8006D250 (172 B) and 0x8006D2FC (180 B) -- worker B, family/adjacency, sibling with a 5th arg 0x8002515C (60 B) and 0x800254B0 (60 B) -- worker D: BOTH twins of the registered 0x80025070, a THREE-member family, and twins of each other 0x80101C5C (32 B) and 0x80102FE4 (48 B) -- worker D, GTE class 0x80091490 (84 B) -- worker C, DEPENDENT, merged on my ruling (below) 0x801008DC (88 B) -- worker C, `cc1bin=gcc-2.8.1-psx`, 3 `jr $31` **RULING ON THE DEPENDENT CLAIM `0x80091490`.** Worker C flagged it rather than quietly merging it, correctly applying charter rule 2: its callee `0x80018284` is NOT reconstructed, and the 3-argument prototype is INFERRED from the call site (the tell is `move a1,zero` -- an integer 0, not a null pointer in v0). Ruling: MERGE, with the dependency recorded here and in the ledger. Reasoning: (i) rule 2 forbids verifying against a SUPERSET, and no superset was used; (ii) the whole-binary gate proves the bytes exact, so the call site's register setup is right; (iii) the residual risk is that a future `0x80018284` reconstruction disagrees about arity, and **that risk is caught by the gate the moment it happens** -- the row would stop matching and the cause would be visible. The alternative, holding a verified body, costs a body for a risk the gate already covers. **The worker who takes `0x80018284` must treat `0x80091490`'s prototype as a hypothesis to check.** Also recorded: `excluded_already_registered` still lags the registry by exactly 2 (642 vs 644). The lag did NOT grow when this merge added four negatives-derived rows, so it is not "negatives rows are counted elsewhere" -- it is a fixed pair of registry rows the counter never counts. Still open, still a diagnostic rather than a gate, still to be reconciled at the close with the full census. Phase position: 602 -> 635 bodies, +33. The cycle-1 checkpoint was +30. --- config/match_worklist.tsv | 1390 ++++++++++++++++++------------------- config/regions.tsv | 10 + src/func_8002515C.c | 38 + src/func_800254B0.c | 38 + src/func_8006AA88.c | 104 +++ src/func_8006B470.c | 77 ++ src/func_8006D250.c | 108 +++ src/func_8006D2FC.c | 100 +++ src/func_8006D3B0.c | 114 +++ src/func_80091490.c | 68 ++ src/func_801008DC.c | 92 +++ src/func_80101C5C.c | 52 ++ src/func_80102FE4.c | 48 ++ 13 files changed, 1542 insertions(+), 697 deletions(-) create mode 100644 src/func_8002515C.c create mode 100644 src/func_800254B0.c create mode 100644 src/func_8006AA88.c create mode 100644 src/func_8006B470.c create mode 100644 src/func_8006D250.c create mode 100644 src/func_8006D2FC.c create mode 100644 src/func_8006D3B0.c create mode 100644 src/func_80091490.c create mode 100644 src/func_801008DC.c create mode 100644 src/func_80101C5C.c create mode 100644 src/func_80102FE4.c diff --git a/config/match_worklist.tsv b/config/match_worklist.tsv index e8671c9..a5b53f5 100644 --- a/config/match_worklist.tsv +++ b/config/match_worklist.tsv @@ -299,703 +299,699 @@ 292 0x800BE780 0x800BE828 168 exact 2 frame 0 - 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1 -593 0x800735EC 0x8007374C 352 exact 2 frame 2 - 1 -594 0x8007EBEC 0x8007ED4C 352 exact 2 frame 1 - 1 -595 0x800ABA28 0x800ABB88 352 exact 2 frame 2 - 1 -596 0x800F6F70 0x800F70D0 352 exact 2 frame 4 - 1 -597 0x800F7FD8 0x800F8138 352 exact 2 frame 3 - 1 -598 0x8004702C 0x80047190 356 exact 2 frame 1 - 1 -599 0x800A9768 0x800A98CC 356 exact 2 frame 5 - 1 -600 0x800B5AF8 0x800B5C5C 356 exact 2 frame 1 - 1 -601 0x800272C8 0x80027430 360 exact 2 frame 10 - 1 -602 0x80065794 0x800658FC 360 exact 2 frame 2 - 1 -603 0x80101CDC 0x80101E44 360 exact 2 frame 11 - 1 -604 0x80106ED4 0x8010703C 360 exact 2 frame 5 - 1 -605 0x8003126C 0x800313D8 364 exact 2 frame 0 - 1 -606 0x80047DE0 0x80047F4C 364 exact 2 frame 3 - 1 -607 0x8009B638 0x8009B7A4 364 exact 2 frame 4 - 1 -608 0x80028844 0x800289B4 368 exact 2 frame 11 - 1 -609 0x8007DF34 0x8007E0A4 368 exact 2 frame 6 - 1 -610 0x80083878 0x800839E8 368 exact 2 frame 2 - 1 -611 0x8009CE58 0x8009CFC8 368 exact 2 frame 2 - 1 -612 0x80012B88 0x80012CFC 372 exact 2 frame 1 - 1 -613 0x800164EC 0x80016660 372 exact 2 frame 2 - 1 -614 0x80038BD4 0x80038D48 372 exact 2 frame 1 - 1 -615 0x8003D594 0x8003D708 372 exact 2 frame 4 - 1 -616 0x800ADC74 0x800ADDE8 372 exact 2 frame 1 - 1 -617 0x800BA8D4 0x800BAA48 372 exact 2 frame 0 - 1 -618 0x800F3E8C 0x800F4000 372 exact 2 frame 9 - 1 -619 0x8004780C 0x80047984 376 exact 2 frame 3 - 1 -620 0x8006EE44 0x8006EFBC 376 exact 2 frame 5 - 1 -621 0x800F7660 0x800F77D8 376 exact 2 frame 2 - 1 -622 0x800FFC3C 0x800FFDB4 376 exact 2 frame 3 - 1 -623 0x8002EF54 0x8002F0D0 380 exact 2 frame 2 - 1 -624 0x80034E50 0x80034FCC 380 exact 2 frame 2 - 1 -625 0x800B5924 0x800B5AA0 380 exact 2 frame 2 - 1 -626 0x800BD5E8 0x800BD764 380 exact 2 frame 4 - 1 -627 0x80038DD8 0x80038F58 384 exact 2 frame 5 - 1 -628 0x8003F010 0x8003F190 384 exact 2 frame 6 - 1 -629 0x800228D8 0x80022A60 392 exact 2 frame 5 - 1 -630 0x800B1114 0x800B129C 392 exact 2 frame 3 - 1 -631 0x800374F8 0x80037684 396 exact 2 frame 3 - 1 -632 0x8008D6E0 0x8008D86C 396 exact 2 frame 8 - 1 -633 0x800BF5A8 0x800BF734 396 exact 2 frame 1 - 1 -634 0x80026A9C 0x80026C2C 400 exact 2 frame 7 - 1 -635 0x80026C7C 0x80026E10 404 exact 2 frame 7 - 1 -636 0x80029118 0x800292AC 404 exact 2 frame 0 - 1 -637 0x80046884 0x80046A18 404 exact 2 frame 3 - 1 -638 0x80073B74 0x80073D08 404 exact 2 frame 10 - 1 -639 0x80079EEC 0x8007A080 404 exact 2 frame 2 - 1 -640 0x80096364 0x800964F8 404 exact 2 frame 8 - 1 -641 0x80109338 0x801094CC 404 exact 2 frame 5 - 1 -642 0x800162B4 0x8001644C 408 exact 2 frame 4 - 1 -643 0x800309CC 0x80030B64 408 exact 2 frame 3 - 1 -644 0x8004AAF0 0x8004AC88 408 exact 2 frame 3 - 1 -645 0x800A5D24 0x800A5EBC 408 exact 2 frame 2 - 1 -646 0x800C5AEC 0x800C5C84 408 exact 2 frame 1 - 1 -647 0x800199D0 0x80019B6C 412 exact 2 frame 4 - 1 -648 0x80025FE4 0x80026180 412 exact 2 frame 1 - 1 -649 0x8006606C 0x80066208 412 exact 2 frame 7 - 1 -650 0x800FA338 0x800FA4D4 412 exact 2 frame 10 - 1 -651 0x80109010 0x801091AC 412 exact 2 frame 3 - 1 -652 0x80051F50 0x800520F0 416 exact 2 frame 0 - 1 -653 0x8007F774 0x8007F914 416 exact 2 frame 1 - 1 -654 0x800A8700 0x800A88A0 416 exact 2 frame 2 - 1 -655 0x800BE828 0x800BE9C8 416 exact 2 frame 4 - 1 -656 0x80044610 0x800447B4 420 exact 2 frame 3 - 1 -657 0x80041A58 0x80041C00 424 exact 2 frame 8 - 1 -658 0x800AA10C 0x800AA2B4 424 exact 2 frame 1 - 1 -659 0x801027F8 0x801029A0 424 exact 2 frame 1 - 1 -660 0x8002497C 0x80024B28 428 exact 2 frame 5 - 1 -661 0x8002AAD8 0x8002AC84 428 exact 2 frame 9 - 1 -662 0x800489D8 0x80048B84 428 exact 2 frame 3 - 1 -663 0x800FFDB4 0x800FFF60 428 exact 2 frame 4 - 1 -664 0x8004E24C 0x8004E3FC 432 exact 2 frame 2 - 1 -665 0x800B0ECC 0x800B107C 432 exact 2 frame 0 - 1 -666 0x80108284 0x80108434 432 exact 2 frame 3 - 1 -667 0x8001AC10 0x8001ADC4 436 exact 2 frame 4 - 1 -668 0x800AA2F8 0x800AA4AC 436 exact 2 frame 2 - 1 -669 0x800231BC 0x80023374 440 exact 2 frame 6 - 1 -670 0x8002D828 0x8002D9E0 440 exact 2 frame 1 - 1 -671 0x80081174 0x8008132C 440 exact 2 frame 8 - 1 -672 0x8009D8E0 0x8009DA98 440 exact 2 frame 1 - 1 -673 0x80025B64 0x80025D20 444 exact 2 frame 7 - 1 -674 0x800559C4 0x80055B84 448 exact 2 frame 0 - 1 -675 0x800AD7E8 0x800AD9A8 448 exact 2 frame 3 - 1 -676 0x800AE9E0 0x800AEBA0 448 exact 2 frame 7 - 1 -677 0x8010A1C8 0x8010A388 448 exact 2 frame 6 - 1 -678 0x8002ACBC 0x8002AE80 452 exact 2 frame 12 - 1 -679 0x8002FE3C 0x80030000 452 exact 2 frame 3 - 1 -680 0x800839E8 0x80083BAC 452 exact 2 frame 2 - 1 -681 0x800BBE90 0x800BC054 452 exact 2 frame 0 - 1 -682 0x80018560 0x80018728 456 exact 2 frame 1 - 1 -683 0x80068D78 0x80068F40 456 exact 2 frame 10 - 1 -684 0x8006E1B0 0x8006E378 456 exact 2 frame 3 - 1 -685 0x80077088 0x80077250 456 exact 2 frame 7 - 1 -686 0x80030630 0x800307FC 460 exact 2 frame 2 - 1 -687 0x800590D8 0x800592A4 460 exact 2 frame 6 - 1 -688 0x800695D8 0x800697A4 460 exact 2 frame 4 - 1 -689 0x8008F114 0x8008F2E0 460 exact 2 frame 6 - 1 -690 0x80099E84 0x8009A050 460 exact 2 frame 1 - 1 -691 0x801095A8 0x80109774 460 exact 2 frame 4 - 1 -692 0x8002BA50 0x8002BC20 464 exact 2 frame 14 - 1 -693 0x8002E9F4 0x8002EBC4 464 exact 2 frame 6 - 1 -694 0x8003A7F8 0x8003A9C8 464 exact 2 frame 10 - 1 -695 0x800BBC1C 0x800BBDEC 464 exact 2 frame 0 - 1 -696 0x800C022C 0x800C03FC 464 exact 2 frame 3 - 1 -697 0x800F7B84 0x800F7D54 464 exact 2 frame 5 - 1 -698 0x8002D3F4 0x8002D5C8 468 exact 2 frame 11 - 1 -699 0x80047F4C 0x80048128 476 exact 2 frame 3 - 1 -700 0x80052ABC 0x80052C98 476 exact 2 frame 0 - 1 -701 0x80074394 0x80074570 476 exact 2 frame 12 - 1 -702 0x80078FD0 0x800791AC 476 exact 2 frame 7 - 1 -703 0x80101878 0x80101A54 476 exact 2 frame 4 - 1 -704 0x80044D78 0x80044F58 480 exact 2 frame 11 - 1 -705 0x8006496C 0x80064B4C 480 exact 2 frame 6 - 1 -706 0x80064B4C 0x80064D2C 480 exact 2 frame 4 - 1 -707 0x8006AB7C 0x8006AD5C 480 exact 2 frame 12 - 1 -708 0x800FBBA0 0x800FBD80 480 exact 2 frame 14 - 1 -709 0x80106CF4 0x80106ED4 480 exact 2 frame 9 - 1 -710 0x80059DF8 0x80059FDC 484 exact 2 frame 1 - 1 -711 0x80070270 0x80070454 484 exact 2 frame 2 - 1 -712 0x80052424 0x8005260C 488 exact 2 frame 7 - 1 -713 0x80069398 0x80069580 488 exact 2 frame 3 - 1 -714 0x800FA150 0x800FA338 488 exact 2 frame 21 - 1 -715 0x8003F7CC 0x8003F9B8 492 exact 2 frame 2 - 1 -716 0x80065980 0x80065B6C 492 exact 2 frame 1 - 1 -717 0x801078A4 0x80107A94 496 exact 2 frame 11 - 1 -718 0x80024C34 0x80024E28 500 exact 2 frame 3 - 1 -719 0x80064664 0x80064858 500 exact 2 frame 3 - 1 -720 0x800652A0 0x80065494 500 exact 2 frame 6 - 1 -721 0x800A4F8C 0x800A5180 500 exact 2 frame 0 - 1 -722 0x80016BD4 0x80016DCC 504 exact 2 frame 1 - 1 -723 0x8007ED8C 0x8007EF84 504 exact 2 frame 6 - 1 -724 0x80030000 0x800301FC 508 exact 2 frame 10 - 1 -725 0x80031CC0 0x80031EBC 508 exact 2 frame 7 - 1 -726 0x80014054 0x80014258 516 exact 2 frame 6 - 1 -727 0x800254EC 0x800256F0 516 exact 2 frame 5 - 1 -728 0x8007BA60 0x8007BC64 516 exact 2 frame 4 - 1 -729 0x8009AC28 0x8009AE2C 516 exact 2 frame 3 - 1 -730 0x800B0BE0 0x800B0DE4 516 exact 2 frame 8 - 1 -731 0x80067E70 0x80068078 520 exact 2 frame 5 - 1 -732 0x800150A0 0x800152AC 524 exact 2 frame 13 - 1 -733 0x80015DBC 0x80015FC8 524 exact 2 frame 5 - 1 -734 0x80043B80 0x80043D8C 524 exact 2 frame 5 - 1 -735 0x80098E18 0x80099024 524 exact 2 frame 13 - 1 -736 0x80038F58 0x80039168 528 exact 2 frame 3 - 1 -737 0x8007CFFC 0x8007D20C 528 exact 2 frame 3 - 1 -738 0x800A6C8C 0x800A6E9C 528 exact 2 frame 11 - 1 -739 0x80104720 0x80104930 528 exact 2 frame 2 - 1 -740 0x8004B438 0x8004B64C 532 exact 2 frame 3 - 1 -741 0x800697FC 0x80069A10 532 exact 2 frame 3 - 1 -742 0x800AD484 0x800AD698 532 exact 2 frame 5 - 1 -743 0x800295D4 0x800297F4 544 exact 2 frame 6 - 1 -744 0x8002D608 0x8002D828 544 exact 2 frame 2 - 1 -745 0x8009D47C 0x8009D69C 544 exact 2 frame 0 - 1 -746 0x8001778C 0x800179B8 556 exact 2 frame 4 - 1 -747 0x80059504 0x80059730 556 exact 2 frame 4 - 1 -748 0x80063900 0x80063B2C 556 exact 2 frame 10 - 1 -749 0x8003C590 0x8003C7C0 560 exact 2 frame 11 - 1 -750 0x8008A1D0 0x8008A400 560 exact 2 frame 3 - 1 -751 0x800BF734 0x800BF968 564 exact 2 frame 5 - 1 -752 0x800FB8EC 0x800FBB20 564 exact 2 frame 11 - 1 -753 0x8009D244 0x8009D47C 568 exact 2 frame 3 - 1 -754 0x800B6090 0x800B62C8 568 exact 2 frame 13 - 1 -755 0x8007F07C 0x8007F2B8 572 exact 2 frame 9 - 1 -756 0x80018728 0x8001896C 580 exact 2 frame 3 - 1 -757 0x80041DA0 0x80041FE4 580 exact 2 frame 6 - 1 -758 0x800BF968 0x800BFBAC 580 exact 2 frame 5 - 1 -759 0x8009AE2C 0x8009B074 584 exact 2 frame 0 - 1 -760 0x800B0940 0x800B0B88 584 exact 2 frame 7 - 1 -761 0x800B6894 0x800B6AE0 588 exact 2 frame 7 - 1 -762 0x80016704 0x80016954 592 exact 2 frame 4 - 1 -763 0x800A7E68 0x800A80B8 592 exact 2 frame 3 - 1 -764 0x800AFB6C 0x800AFDBC 592 exact 2 frame 2 - 1 -765 0x8002C930 0x8002CB84 596 exact 2 frame 23 - 1 -766 0x8006AE54 0x8006B0A8 596 exact 2 frame 0 - 1 -767 0x800283F4 0x8002864C 600 exact 2 frame 5 - 1 -768 0x8009736C 0x800975C4 600 exact 2 frame 10 - 1 -769 0x80050998 0x80050BF4 604 exact 2 frame 2 - 1 -770 0x80065E10 0x8006606C 604 exact 2 frame 4 - 1 -771 0x800C29D4 0x800C2C30 604 exact 2 frame 6 - 1 -772 0x800F5E44 0x800F60A4 608 exact 2 frame 5 - 1 -773 0x800B5CF8 0x800B5F5C 612 exact 2 frame 2 - 1 -774 0x8002BE6C 0x8002C0D4 616 exact 2 frame 13 - 1 -775 0x800571AC 0x80057418 620 exact 2 frame 2 - 1 -776 0x800B7264 0x800B74D0 620 exact 2 frame 10 - 1 -777 0x800FD834 0x800FDAA0 620 exact 2 frame 6 - 1 -778 0x8003F9B8 0x8003FC28 624 exact 2 frame 3 - 1 -779 0x80069128 0x80069398 624 exact 2 frame 2 - 1 -780 0x80073D08 0x80073F78 624 exact 2 frame 9 - 1 -781 0x800F4E40 0x800F50B0 624 exact 2 frame 5 - 1 -782 0x801051CC 0x8010543C 624 exact 2 frame 3 - 1 -783 0x80043554 0x800437CC 632 exact 2 frame 9 - 1 -784 0x80104930 0x80104BA8 632 exact 2 frame 3 - 1 -785 0x8009CFC8 0x8009D244 636 exact 2 frame 12 - 1 -786 0x80069A10 0x80069C90 640 exact 2 frame 4 - 1 -787 0x8008FA58 0x8008FCD8 640 exact 2 frame 5 - 1 -788 0x800A5EBC 0x800A613C 640 exact 2 frame 4 - 1 -789 0x80106154 0x801063D4 640 exact 2 frame 9 - 1 -790 0x80109F48 0x8010A1C8 640 exact 2 frame 11 - 1 -791 0x8010A444 0x8010A6C4 640 exact 2 frame 2 - 1 -792 0x800A30D4 0x800A3358 644 exact 2 frame 5 - 1 -793 0x8002AEAC 0x8002B138 652 exact 2 frame 30 - 1 -794 0x800943E0 0x80094670 656 exact 2 frame 1 - 1 -795 0x80072680 0x80072914 660 exact 2 frame 0 - 1 -796 0x8002E528 0x8002E7C4 668 exact 2 frame 9 - 1 -797 0x8006A6F0 0x8006A98C 668 exact 2 frame 0 - 1 -798 0x800FACE8 0x800FAF84 668 exact 2 frame 7 - 1 -799 0x80093768 0x80093A08 672 exact 2 frame 7 - 1 -800 0x800519A8 0x80051C4C 676 exact 2 frame 1 - 1 -801 0x800313D8 0x80031684 684 exact 2 frame 10 - 1 -802 0x800526F0 0x800529A0 688 exact 2 frame 0 - 1 -803 0x800F5B94 0x800F5E44 688 exact 2 frame 9 - 1 -804 0x8007DC4C 0x8007DF00 692 exact 2 frame 3 - 1 -805 0x800501DC 0x80050494 696 exact 2 frame 5 - 1 -806 0x800A3600 0x800A38B8 696 exact 2 frame 2 - 1 -807 0x800FF184 0x800FF43C 696 exact 2 frame 3 - 1 -808 0x80103544 0x801037FC 696 exact 2 frame 1 - 1 -809 0x800FA980 0x800FAC44 708 exact 2 frame 10 - 1 -810 0x801063D4 0x8010669C 712 exact 2 frame 9 - 1 -811 0x80074F1C 0x800751E8 716 exact 2 frame 8 - 1 -812 0x8006EFBC 0x8006F28C 720 exact 2 frame 2 - 1 -813 0x80084770 0x80084A48 728 exact 2 frame 7 - 1 -814 0x800FA688 0x800FA960 728 exact 2 frame 9 - 1 -815 0x8008A47C 0x8008A758 732 exact 2 frame 7 - 1 -816 0x8006C044 0x8006C324 736 exact 2 frame 1 - 1 -817 0x800916DC 0x800919BC 736 exact 2 frame 9 - 1 -818 0x80091D88 0x80092068 736 exact 2 frame 7 - 1 -819 0x800AB0EC 0x800AB3CC 736 exact 2 frame 1 - 1 -820 0x8007AD28 0x8007B00C 740 exact 2 frame 5 - 1 -821 0x80033ADC 0x80033DC8 748 exact 2 frame 5 - 1 -822 0x800BAED4 0x800BB1C4 752 exact 2 frame 4 - 1 -823 0x80093A84 0x80093D80 764 exact 2 frame 1 - 1 -824 0x80078B94 0x80078E94 768 exact 2 frame 6 - 1 -825 0x80051C4C 0x80051F50 772 exact 2 frame 2 - 1 -826 0x8009A904 0x8009AC08 772 exact 2 frame 2 - 1 -827 0x8004C400 0x8004C708 776 exact 2 frame 0 - 1 -828 0x80059AF0 0x80059DF8 776 exact 2 frame 9 - 1 -829 0x8009829C 0x800985A4 776 exact 2 frame 9 - 1 -830 0x8006D884 0x8006DB90 780 exact 2 frame 1 - 1 -831 0x80091A7C 0x80091D88 780 exact 2 frame 12 - 1 -832 0x800BFF20 0x800C022C 780 exact 2 frame 1 - 1 -833 0x80013D44 0x80014054 784 exact 2 frame 10 - 1 -834 0x8005D1B0 0x8005D4C4 788 exact 2 frame 2 - 1 -835 0x800748EC 0x80074C00 788 exact 2 frame 21 - 1 -836 0x80025198 0x800254B0 792 exact 2 frame 5 - 1 -837 0x80072048 0x80072360 792 exact 2 frame 12 - 1 -838 0x800830B4 0x800833CC 792 exact 2 frame 2 - 1 -839 0x80094670 0x80094988 792 exact 2 frame 8 - 1 -840 0x800FCC48 0x800FCF60 792 exact 2 frame 12 - 1 -841 0x8002B608 0x8002B924 796 exact 2 frame 3 - 1 -842 0x8007061C 0x80070938 796 exact 2 frame 10 - 1 -843 0x8008355C 0x80083878 796 exact 2 frame 7 - 1 -844 0x8006DB90 0x8006DEB4 804 exact 2 frame 3 - 1 -845 0x800292AC 0x800295D4 808 exact 2 frame 2 - 1 -846 0x8009CB28 0x8009CE58 816 exact 2 frame 6 - 1 -847 0x801042FC 0x80104630 820 exact 2 frame 18 - 1 -848 0x80052CAC 0x80052FF4 840 exact 2 frame 14 - 1 -849 0x80077250 0x8007759C 844 exact 2 frame 5 - 1 -850 0x800C54EC 0x800C583C 848 exact 2 frame 3 - 1 -851 0x80048684 0x800489D8 852 exact 2 frame 6 - 1 -852 0x800A98CC 0x800A9C24 856 exact 2 frame 14 - 1 -853 0x8006CC54 0x8006CFB0 860 exact 2 frame 4 - 1 -854 0x80059FDC 0x8005A33C 864 exact 2 frame 4 - 1 -855 0x80031684 0x800319F0 876 exact 2 frame 14 - 1 -856 0x80040884 0x80040BFC 888 exact 2 frame 4 - 1 -857 0x800897B8 0x80089B30 888 exact 2 frame 17 - 1 -858 0x8003C7C0 0x8003CB3C 892 exact 2 frame 9 - 1 -859 0x80089434 0x800897B8 900 exact 2 frame 20 - 1 -860 0x800AC2C4 0x800AC648 900 exact 2 frame 0 - 1 -861 0x800ABB88 0x800ABF10 904 exact 2 frame 1 - 1 -862 0x80017200 0x8001758C 908 exact 2 frame 6 - 1 -863 0x80048E70 0x800491FC 908 exact 2 frame 10 - 1 -864 0x8002EBC4 0x8002EF54 912 exact 2 frame 5 - 1 -865 0x80034ABC 0x80034E50 916 exact 2 frame 11 - 1 -866 0x80064230 0x800645CC 924 exact 2 frame 13 - 1 -867 0x80072DF4 0x80073190 924 exact 2 frame 10 - 1 -868 0x80090408 0x800907A4 924 exact 2 frame 12 - 1 -869 0x800564AC 0x80056854 936 exact 2 frame 11 - 1 -870 0x800ABF10 0x800AC2C4 948 exact 2 frame 4 - 1 -871 0x8006F2F4 0x8006F6BC 968 exact 2 frame 1 - 1 -872 0x8008EBFC 0x8008EFC4 968 exact 2 frame 9 - 1 -873 0x800B7524 0x800B78EC 968 exact 2 frame 4 - 1 -874 0x80047A14 0x80047DE0 972 exact 2 frame 9 - 1 -875 0x80033700 0x80033ADC 988 exact 2 frame 3 - 1 -876 0x800447B4 0x80044B90 988 exact 2 frame 12 - 1 -877 0x80088F38 0x80089314 988 exact 2 frame 11 - 1 -878 0x800AAC9C 0x800AB078 988 exact 2 frame 11 - 1 -879 0x80058608 0x800589E8 992 exact 2 frame 2 - 1 -880 0x80071C64 0x80072048 996 exact 2 frame 15 - 1 -881 0x8010128C 0x80101678 1004 exact 2 frame 6 - 1 -882 0x8009B074 0x8009B464 1008 exact 2 frame 0 - 1 -883 0x800B0550 0x800B0940 1008 exact 2 frame 11 - 1 -884 0x80037B98 0x80037F94 1020 exact 2 frame 9 - 1 -885 0x8007BD0C 0x8007C108 1020 exact 2 frame 10 - 1 -886 0x800C1A58 0x800C1E54 1020 exact 2 frame 8 - 1 -887 0x8010669C 0x80106AA8 1036 exact 2 frame 12 - 1 -888 0x8005CDA0 0x8005D1B0 1040 exact 2 frame 17 - 1 -889 0x80094F54 0x80095364 1040 exact 2 frame 9 - 1 -890 0x800331D4 0x800335E8 1044 exact 2 frame 7 - 1 -891 0x80055240 0x80055654 1044 exact 2 frame 6 - 1 -892 0x800868E8 0x80086CFC 1044 exact 2 frame 3 - 1 -893 0x800A2B04 0x800A2F20 1052 exact 2 frame 7 - 1 -894 0x800B6330 0x800B6754 1060 exact 2 frame 13 - 1 -895 0x8003F190 0x8003F5BC 1068 exact 2 frame 2 - 1 -896 0x80056854 0x80056C88 1076 exact 2 frame 20 - 1 -897 0x8003879C 0x80038BD4 1080 exact 2 frame 10 - 1 -898 0x80092460 0x80092898 1080 exact 2 frame 13 - 1 -899 0x800B2048 0x800B2488 1088 exact 2 frame 4 - 1 -900 0x80034638 0x80034A80 1096 exact 2 frame 7 - 1 -901 0x8009A4AC 0x8009A904 1112 exact 2 frame 6 - 1 -902 0x8005A8E8 0x8005AD44 1116 exact 2 frame 15 - 1 -903 0x8003EBAC 0x8003F010 1124 exact 2 frame 10 - 1 -904 0x800BCE20 0x800BD298 1144 exact 2 frame 13 - 1 -905 0x800C03FC 0x800C0874 1144 exact 2 frame 3 - 1 -906 0x800A38B8 0x800A3D34 1148 exact 2 frame 15 - 1 -907 0x800B8958 0x800B8DE4 1164 exact 2 frame 10 - 1 -908 0x800BAA48 0x800BAED4 1164 exact 2 frame 1 - 1 -909 0x800668F0 0x80066DA0 1200 exact 2 frame 15 - 1 -910 0x800A6FAC 0x800A745C 1200 exact 2 frame 20 - 1 -911 0x800B9C64 0x800BA114 1200 exact 2 frame 0 - 1 -912 0x8005E8B8 0x8005ED6C 1204 exact 2 frame 26 - 1 -913 0x80095364 0x80095820 1212 exact 2 frame 3 - 1 -914 0x800BC194 0x800BC658 1220 exact 2 frame 6 - 1 -915 0x8002B138 0x8002B608 1232 exact 2 frame 36 - 1 -916 0x8004D8A4 0x8004DD74 1232 exact 2 frame 6 - 1 -917 0x8004DD74 0x8004E24C 1240 exact 2 frame 7 - 1 -918 0x800F465C 0x800F4B54 1272 exact 2 frame 8 - 1 -919 0x800F70D0 0x800F75C8 1272 exact 2 frame 8 - 1 -920 0x80093E54 0x80094370 1308 exact 2 frame 15 - 1 -921 0x80056C88 0x800571AC 1316 exact 2 frame 4 - 1 -922 0x8007D718 0x8007DC40 1320 exact 2 frame 5 - 1 -923 0x800B78EC 0x800B7E14 1320 exact 2 frame 0 - 1 -924 0x80034FCC 0x800354F8 1324 exact 2 frame 13 - 1 -925 0x80066208 0x80066738 1328 exact 2 frame 7 - 1 -926 0x800C3C4C 0x800C417C 1328 exact 2 frame 10 - 1 -927 0x80054BC4 0x80055108 1348 exact 2 frame 4 - 1 -928 0x80086388 0x800868E8 1376 exact 2 frame 15 - 1 -929 0x8004ED90 0x8004F2F8 1384 exact 2 frame 11 - 1 -930 0x800855D4 0x80085B44 1392 exact 2 frame 2 - 1 -931 0x80064D2C 0x800652A0 1396 exact 2 frame 4 - 1 -932 0x8007E228 0x8007E7C0 1432 exact 2 frame 3 - 1 -933 0x8007B2A0 0x8007B83C 1436 exact 2 frame 5 - 1 -934 0x80095D74 0x80096324 1456 exact 2 frame 11 - 1 -935 0x800AEC48 0x800AF1FC 1460 exact 2 frame 14 - 1 -936 0x80094988 0x80094F54 1484 exact 2 frame 22 - 1 -937 0x800152AC 0x8001587C 1488 exact 2 frame 19 - 1 -938 0x8003CBE4 0x8003D224 1600 exact 2 frame 15 - 1 -939 0x8009B7A4 0x8009BDEC 1608 exact 2 frame 11 - 1 -940 0x80075228 0x8007587C 1620 exact 2 frame 15 - 1 -941 0x80099420 0x80099A94 1652 exact 2 frame 11 - 1 -942 0x80036390 0x80036A0C 1660 exact 2 frame 9 - 1 -943 0x8007A4FC 0x8007AB7C 1664 exact 2 frame 9 - 1 -944 0x80085CDC 0x80086388 1708 exact 2 frame 15 - 1 -945 0x8004CF0C 0x8004D5CC 1728 exact 2 frame 11 - 1 -946 0x800C356C 0x800C3C4C 1760 exact 2 frame 18 - 1 -947 0x80030B64 0x8003126C 1800 exact 2 frame 7 - 1 -948 0x80033F30 0x80034638 1800 exact 2 frame 0 - 1 -949 0x800BB2AC 0x800BB9FC 1872 exact 2 frame 5 - 1 -950 0x80043E98 0x80044610 1912 exact 2 frame 12 - 1 -951 0x8009E95C 0x8009F0E8 1932 exact 2 frame 10 - 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1 +956 0x8007C7CC 0x8007CFFC 2096 exact 2 frame 10 - 1 +957 0x80083C78 0x800844B8 2112 exact 2 frame 15 - 1 +958 0x800C417C 0x800C49BC 2112 exact 2 frame 6 - 1 +959 0x800985A4 0x80098E18 2164 exact 2 frame 49 - 1 +960 0x8004A278 0x8004AAF0 2168 exact 2 frame 12 - 1 +961 0x8002203C 0x800228D8 2204 exact 2 frame 4 - 1 +962 0x80050D48 0x80051628 2272 exact 2 frame 15 - 1 +963 0x80053064 0x80053954 2288 exact 2 frame 12 - 1 +964 0x80101EB0 0x801027CC 2332 exact 2 frame 12 - 1 +965 0x80055B84 0x800564AC 2344 exact 2 frame 17 - 1 +966 0x8001CE70 0x8001D7A0 2352 exact 2 frame 14 - 1 +967 0x8006C324 0x8006CC54 2352 exact 2 frame 19 - 1 +968 0x8008CCC0 0x8008D5F8 2360 exact 2 frame 11 - 1 +969 0x800C2054 0x800C29D4 2432 exact 2 frame 17 - 1 +970 0x80069C90 0x8006A654 2500 exact 2 frame 13 - 1 +971 0x800A5228 0x800A5C1C 2548 exact 2 frame 23 - 1 +972 0x8004F2F8 0x8004FE38 2880 exact 2 frame 21 - 1 +973 0x8003FD00 0x80040884 2948 exact 2 frame 26 - 1 +974 0x800975C4 0x8009829C 3288 exact 2 frame 71 - 1 +975 0x800142F4 0x80014FE8 3316 exact 2 frame 38 - 1 +976 0x800B8E60 0x800B9C64 3588 exact 2 frame 8 - 1 +977 0x800964F8 0x8009736C 3700 exact 2 frame 32 - 1 +978 0x80066E58 0x80067D34 3804 exact 2 frame 39 - 1 +979 0x80053954 0x80054AF8 4516 exact 2 frame 32 - 1 +980 0x8008132C 0x80082750 5156 exact 2 frame 34 - 1 +981 0x80086DFC 0x80088F38 8508 exact 2 frame 38 - 1 +982 0x8009F988 0x800A2684 11516 exact 2 frame 102 - 1 +983 0x80180808 0x8018080C 4 fallthrough 3 leaf 0 - 1 +984 0x801007E0 0x80100808 40 fallthrough 3 frame 1 - 1 # -# listed=988 -# excluded_already_registered=632 +# listed=984 +# excluded_already_registered=642 # excluded_bad_extent_start=8 # excluded_degenerate_body=252 # excluded_delay_slot_start=5 @@ -1004,6 +1000,6 @@ # excluded_low_confidence_grade=90 # excluded_named_exclusion=9 # excluded_no_extent=0 -# excluded_recorded_negative=160 +# excluded_recorded_negative=154 # excluded_restores_unsaved=11 # excluded_trapping_arith=48 diff --git a/config/regions.tsv b/config/regions.tsv index d93cd1d..ecd4166 100644 --- a/config/regions.tsv +++ b/config/regions.tsv @@ -87,6 +87,8 @@ 0x8002311C 0x800231BC src/func_8002311C.c 0x80024C14 0x80024C34 src/func_80024C14.c 0x80025070 0x800250AC src/func_80025070.c +0x8002515C 0x80025198 src/func_8002515C.c +0x800254B0 0x800254EC src/func_800254B0.c 0x800259A0 0x800259DC src/func_800259A0.c 0x80025A2C 0x80025ADC src/func_80025A2C.c 0x80025ADC 0x80025B64 src/func_80025ADC.c @@ -291,6 +293,7 @@ 0x800697C4 0x800697FC src/func_800697C4.c 0x8006A98C 0x8006AA10 src/func_8006A98C.c 0x8006AA10 0x8006AA88 src/func_8006AA10.c +0x8006AA88 0x8006AB7C src/func_8006AA88.c 0x8006AD5C 0x8006ADB0 src/func_8006AD5C.c 0x8006ADB0 0x8006AE04 src/func_8006ADB0.c 0x8006AE04 0x8006AE54 src/func_8006AE04.c @@ -314,6 +317,9 @@ 0x8006BC34 0x8006BC74 src/func_8006BC34.c 0x8006BC74 0x8006BF30 src/func_8006BC74.c 0x8006D1C4 0x8006D250 src/func_8006D1C4.c +0x8006D250 0x8006D2FC src/func_8006D250.c +0x8006D2FC 0x8006D3B0 src/func_8006D2FC.c +0x8006D3B0 0x8006D470 src/func_8006D3B0.c 0x8006EC94 0x8006ECD4 src/func_8006EC94.c 0x8006F28C 0x8006F2F4 src/func_8006F28C.c 0x8006F6BC 0x8006F6F4 src/func_8006F6BC.c @@ -398,6 +404,7 @@ 0x800912FC 0x8009132C src/func_800912FC.c 0x8009132C 0x80091370 src/func_8009132C.c 0x80091370 0x8009141C src/func_80091370.c +0x80091490 0x800914E4 src/func_80091490.c 0x800914E4 0x80091674 src/func_800914E4.c 0x80091674 0x800916DC src/func_80091674.c 0x80092068 0x80092088 src/func_80092068.c @@ -580,17 +587,20 @@ 0x80100038 0x801000A0 src/func_80100038.c maspsx=epilogue 0x80100318 0x80100334 src/func_80100318.c 0x80100740 0x801007E0 src/func_80100740.c +0x801008DC 0x80100934 src/func_801008DC.c cc1bin=gcc-2.8.1-psx 0x80100964 0x8010097C src/func_80100964.c 0x8010097C 0x80100998 src/func_8010097C.c 0x80101244 0x8010128C src/func_80101244.c 0x80101838 0x80101878 src/func_80101838.c 0x80101C2C 0x80101C54 src/func_80101C2C.c +0x80101C5C 0x80101C7C src/func_80101C5C.c 0x80101CAC 0x80101CDC src/func_80101CAC.c 0x801027CC 0x801027F8 src/func_801027CC.c 0x80102B10 0x80102B2C src/func_80102B10.c maspsx=off 0x80102B30 0x80102B5C src/func_80102B30.c maspsx=off 0x80102FA4 0x80102FD4 src/func_80102FA4.c 0x80102FD4 0x80102FE0 src/func_80102FD4.c +0x80102FE4 0x80103014 src/func_80102FE4.c 0x801032D4 0x80103320 src/func_801032D4.c 0x80103A94 0x80103AA0 src/func_80103A94.c 0x80103B54 0x80103B60 src/func_80103B54.c diff --git a/src/func_8002515C.c b/src/func_8002515C.c new file mode 100644 index 0000000..289827c --- /dev/null +++ b/src/func_8002515C.c @@ -0,0 +1,38 @@ +/* + * func_8002515C — 60 bytes at 0x8002515C..80025198 + * + * GOAL B ROW (worker D, Phase 12): recorded in + * with class `-`. A raw-word scan (cookbook 166/169) against every registered + * region of the same size found it is the registered `0x80025070` with EXACTLY + * TWO WORDS different, and both are JUMP TARGETS: + * + * word 6 j -> this row's else-arm call (0x80025088 in the parent) + * word 9 jal -> func_80025198 (func_800250AC in the parent) + * + * Every other word is identical, so the whole body is shared: read + * `*(int **)((char *)a0 + 0x20)`, and if it is non-null pass ITS `+0x20` word to + * the callee, otherwise pass 0. See `src/func_80025070.c` for the sibling's + * documentation. + * + * The other member of this family, `0x800254B0`, is the same body against + * `func_800254EC`; the registered parent plus these two make a three-member + * family, and the pool rows are one-attempt rows because the parent supplies the + * body (cookbook 125: the finder varies, the price does not). + * + * LIMITS: inherited from the parent. The struct field at +0x20 and the callee's + * three arguments are read off the emitted code; the callee is named for its + * address. whether either of the two arguments is really a pointer is not + * established — `(int)a0` is written because the parent does, and only the + * register placement is evidence. + */ +void func_80025198(int, int, int); + +int func_8002515C(int *a0, int a1) +{ + int *obj2 = *(int **)((char *)a0 + 0x20); + + if (obj2 == 0) + func_80025198((int)a0, 0, a1); + else + func_80025198((int)a0, *(int *)((char *)obj2 + 0x20), a1); +} diff --git a/src/func_800254B0.c b/src/func_800254B0.c new file mode 100644 index 0000000..fdde2ec --- /dev/null +++ b/src/func_800254B0.c @@ -0,0 +1,38 @@ +/* + * func_800254B0 — 60 bytes at 0x800254B0..800254EC + * + * GOAL B ROW (worker D, Phase 12): recorded in + * with class `-`. A raw-word scan (cookbook 166/169) against every registered + * region of the same size found it is the registered `0x80025070` with EXACTLY + * TWO WORDS different, and both are JUMP TARGETS: + * + * word 6 j -> this row's else-arm call (0x80025088 in the parent) + * word 9 jal -> func_800254EC (func_800250AC in the parent) + * + * Every other word is identical, so the whole body is shared: read + * `*(int **)((char *)a0 + 0x20)`, and if it is non-null pass ITS `+0x20` word to + * the callee, otherwise pass 0. See `src/func_80025070.c` for the sibling's + * documentation. + * + * The other member of this family, `0x800254B0`, is the same body against + * `func_800254EC`; the registered parent plus these two make a three-member + * family, and the pool rows are one-attempt rows because the parent supplies the + * body (cookbook 125: the finder varies, the price does not). + * + * LIMITS: inherited from the parent. The struct field at +0x20 and the callee's + * three arguments are read off the emitted code; the callee is named for its + * address. whether either of the two arguments is really a pointer is not + * established — `(int)a0` is written because the parent does, and only the + * register placement is evidence. + */ +void func_800254EC(int, int, int); + +int func_800254B0(int *a0, int a1) +{ + int *obj2 = *(int **)((char *)a0 + 0x20); + + if (obj2 == 0) + func_800254EC((int)a0, 0, a1); + else + func_800254EC((int)a0, *(int *)((char *)obj2 + 0x20), a1); +} diff --git a/src/func_8006AA88.c b/src/func_8006AA88.c new file mode 100644 index 0000000..ab9bea9 --- /dev/null +++ b/src/func_8006AA88.c @@ -0,0 +1,104 @@ +/* + * func_8006AA88 — 244 bytes at 0x8006AA88..0x8006AB7C + * + * Byte-identical reconstruction. A RECURSIVE two-phase body: it may recurse into + * a sub-object found at `p->+0x0c -> +0x184`, then, unless a bit is already set + * in `q`'s status word, asks func_8006AA10 which of two mutual-exclusion paths to + * take and records the choice in that same status word. + * + * The observed instructions are: + * addiu sp,sp,-32 / sw s0,16(sp) / move s0,a0 / sw ra,24(sp) / sw s1,20(sp) + * lw v0,12(s0) / nop / lw a0,388(v0) / nop + * beqz a0,second / move s1,a1 ; (delay — s1 is established on BOTH paths) + * first: + * lw a1,12(a0) / nop + * lw v0,260(a1) / nop / andi v0,v0,0x1000 + * beqz v0,after / nop + * jal func_8006AA88 ; RECURSIVE, with a0 = t, a1 = u in place + * nop + * after: + * jal func_80069A10 / move a0,s0 ; (delay) func_80069A10(p) + * second: + * lw v0,260(s1) / nop / andi v0,v0,0x800 + * bnez v0,epilogue / move a0,s0 ; (delay) + * jal func_8006AA10 / move a1,s1 ; (delay) func_8006AA10(p, q) + * andi v0,v0,0xff + * bnez v0,third / addiu a0,s1,128 ; (delay) a0 = (char *)q + 128 + * move a0,s0 / move a1,zero / jal func_8006A654 / li a2,1 + * move a0,s0 / move a1,zero / jal func_80069C90 / li a2,1 + * lw v0,260(s1) / j join / ori v0,v0,0x800 ; (delay) q->+0x104 |= 0x800 + * third: + * jal func_80068874 / move a1,zero ; (delay) + * move a1,zero + * lw v0,8(s0) / lw a2,12(s0) / lw a0,12(v0) + * jal func_800250AC / addiu a2,a2,128 ; (delay) + * lw v0,260(s1) / li v1,-2049 / and v0,v0,v1 + * join: + * sw v0,260(s1) ; q->+0x104 = v0 (shared by both arms) + * epilogue: + * lw ra,24(sp) / lw s1,20(sp) / lw s0,16(sp) / addiu sp,sp,32 / jr ra / nop + * + * FOUR things the bytes fix: + * + * 1. THE func_8006AA10 TEST IS MIRRORED. The original's fall-through arm is the + * one that calls func_8006A654 and func_80069C90 and ORs 0x800 into the status + * word; the func_80068874 arm is the BRANCH TARGET (`bnez v0,third`). Written + * in the natural polarity — `if (func_8006AA10(p, q) & 0xff) { 68874 arm } + * else { 654 arm }` — cc1 keeps the `then` arm inline, the body comes out 4 + * bytes LONG with the branch inverted (`beqz`), and the whole tail shifts. + * Writing the test NEGATED with the arms swapped lands it exactly + * (cookbook 28/100/132). + * 2. THE RECURSIVE CALL PASSES ITS OWN LIVE VALUES. `jal func_8006AA88` sets no + * argument register: `a0` already holds `t` and `a1` holds `u`, so the source + * is `func_8006AA88(t, u)` (cookbook 111/157/162). The prototype must be in + * scope — the function is its own callee. + * 3. THE SHARED STORE IS WHERE THE TWO ARMS JOIN. Both arms compute a status + * word and fall into ONE `sw v0,260(s1)`; the OR arm reaches it through + * `j join` with the `ori` in the delay slot, which is what makes the join a + * real source-level joint rather than a duplicated store. + * 4. `s1` IS ESTABLISHED IN THE FIRST BRANCH'S DELAY SLOT, so the second argument + * survives the recursive call and the two calls in the first arm — which is + * why the frame is 32 with `s0`, `s1` and `ra` and nothing else. + * + * LIMITS: every displacement, bit mask and the frame are read from the bytes. The + * record layout is modelled with `char *` chains because that is how the matched + * members of this translation unit express the same records; the field names and + * types are hypotheses. `func_8006AA10`'s declaration (`int (void *, void *)`) is + * taken from the existing corpus spelling, and the `& 0xff` on its result is + * written explicitly because the mask is in the bytes — whether the callee + * actually returns a byte-sized type is not established. The meanings of the + * 0x1000 and 0x800 bits are unknown; only their positions are evidence. + */ + +extern int func_8006AA10(void *, void *); + +void func_80069A10(char *); +void func_8006A654(char *, int, int); +void func_80069C90(char *, int, int); +void func_80068874(char *, int); +void func_800250AC(int, int, char *); +void func_8006AA88(char *, char *); + +void func_8006AA88(char *p, char *q) +{ + char *t = *(char **)(*(char **)(p + 12) + 388); + + if (t != 0) { + char *u = *(char **)(t + 12); + + if (*(int *)(u + 260) & 0x1000) + func_8006AA88(t, u); + func_80069A10(p); + } + if (!(*(int *)(q + 260) & 0x800)) { + if (!(func_8006AA10(p, q) & 0xff)) { + func_8006A654(p, 0, 1); + func_80069C90(p, 0, 1); + *(int *)(q + 260) |= 0x800; + } else { + func_80068874(q + 128, 0); + func_800250AC(*(int *)(*(int *)(p + 8) + 12), 0, (char *)(*(int *)(p + 12) + 128)); + *(int *)(q + 260) &= -2049; + } + } +} diff --git a/src/func_8006B470.c b/src/func_8006B470.c new file mode 100644 index 0000000..a81f005 --- /dev/null +++ b/src/func_8006B470.c @@ -0,0 +1,77 @@ +/* + * func_8006B470 — 84 bytes at 0x8006B470..0x8006B4C4 + * + * GOAL B ROW (worker D, Phase 12): recorded in `config/near_match_negatives.tsv` + * with class `-`, i.e. no mechanism at all. It is the third member of worker B's + * cluster (B matched `0x8006B328`; I matched `0x8006B398`), and reading the two + * neighbours' sources gave this body on the FIRST spelling. + * + * Byte-identical reconstruction: walk the gp-relative chain head D_80121E88 and + * call func_8006AB7C(p, n) for every object whose +0x160 field is NONZERO. + * + * The observed instructions are: + * lw a0,1360(gp) ; a0 = D_80121E88 (gp + 0x550) + * addiu sp,sp,-24 + * sw ra,20(sp) + * beqz a0,epilogue + * sw s0,16(sp) ; (delay slot) + * loop: + * lw a1,12(a0) ; n = *(char **)(p + 12) + * nop + * lw v0,352(a1) ; flag = *(int *)(n + 352) + * lw s0,396(a1) ; next = *(char **)(n + 396) + * beqz v0,advance ; if (flag == 0) skip the call + * nop + * jal func_8006AB7C ; called with a0 = p, a1 = n ALREADY IN PLACE + * nop + * advance: + * move a0,s0 ; p = next + * bnez a0,loop + * nop + * epilogue: + * lw ra,20(sp) / lw s0,16(sp) / addiu sp,sp,24 / jr ra / nop + * + * THREE things the bytes fix: + * + * 1. THE CALL PASSES ITS OWN LIVE POINTERS. The `jal` sets NO argument register: + * `a0` already holds the walk pointer and `a1` the inner object, so the source + * is `func_8006AB7C(p, n)`. Declaring the callee prototyped with two arguments + * is what pins them there (cookbook 111/157/162) — with an unprototyped callee + * the walk drifts to v0/v1 and the row stops matching. + * 2. THE CONDITION IS `flag != 0` AND THE CALL FALLS THROUGH. `beqz v0,advance` + * skips the call, so the call is on the FALL-THROUGH path — the natural + * spelling here, unlike its two siblings which need their tests inverted. + * 3. THE FRAME IS 24 WITH `ra` AND `s0` ONLY, AND `s0` EXISTS BECAUSE `next` IS + * LOADED BEFORE THE TEST. The successor is read whether or not the call + * happens, so it must survive the call in a callee-saved register. Loading it + * after the test would remove `s0` and the frame's 16(sp) slot. + * + * The `beqz a0,epilogue` entry guard plus the `bnez a0,loop` back edge is a plain + * `while (p != 0)` rotated by cc1 — the same shape as worker B's `0x8006B328`. + * + * LIMITS: every displacement, the gp offset and the frame arithmetic are read + * from the bytes. The chain is modelled as `char *` with byte/word fields because + * that is how the matched siblings express the same chain; the field types and + * names are hypotheses. `func_8006AB7C` is named for its address and its two + * arguments are evidenced by the argument registers being left in place. Nothing + * here establishes what the walk means. + */ + +extern char *D_80121E88; + +void func_8006AB7C(char *, char *); + +void func_8006B470(void) +{ + char *p = D_80121E88; + + while (p != 0) { + char *n = *(char **)(p + 12); + int flag = *(int *)(n + 352); + char *next = *(char **)(n + 396); + + if (flag != 0) + func_8006AB7C(p, n); + p = next; + } +} diff --git a/src/func_8006D250.c b/src/func_8006D250.c new file mode 100644 index 0000000..41e874e --- /dev/null +++ b/src/func_8006D250.c @@ -0,0 +1,108 @@ +/* + * func_8006D250 — 172 bytes at 0x8006D250..0x8006D2FC + * + * Hypothesis, not a claim about meaning: a request-builder. It fills a 64-byte record on its own + * stack from two optional 16-byte vectors, stamps a flags word, then tail-calls a function + * pointer with (the second parameter, &record). The two vector copies batch their loads (four + * `lw` then four `sw` each), which is the struct-assignment shape. + * + * Original words: + * 27BDFFA8 addiu sp,sp,-88 + * 00804821 move t1,a0 ; the callee is kept in t1 (a0 gets clobbered below) + * 00A04021 move t0,a1 ; the second parameter is kept in t0 (a1 is clobbered) + * 24020002 li v0,2 + * AFBF0050 sw ra,80(sp) + * 10C00009 beqz a2,0x8006D28C ; no first vector -> skip its copy + * AFA20014 sw v0,20(sp) ; (delay) rec[1] = 2 + * 8CC20000 lw v0,0(a2) ; (L) 4 loads ... + * 8CC30004 lw v1,4(a2) + * 8CC40008 lw a0,8(a2) + * 8CC5000C lw a1,12(a2) + * AFA20018 sw v0,24(sp) ; ... then 4 stores -> rec[2..5] = a2[0..3] + * AFA3001C sw v1,28(sp) + * AFA40020 sw a0,32(sp) + * AFA50024 sw a1,36(sp) + * 10E0000A beqz a3,0x8006D2B8 ; no second vector -> skip its copy + * 2402FFFE li v0,-2 ; (delay) the mask, FIRST materialisation + * 8CE20000 lw v0,0(a3) ; (L) 4 loads ... + * 8CE30004 lw v1,4(a3) + * 8CE40008 lw a0,8(a3) + * 8CE5000C lw a1,12(a3) + * AFA20028 sw v0,40(sp) ; ... then 4 stores -> rec[6..9] = a3[0..3] + * AFA3002C sw v1,44(sp) + * AFA40030 sw a0,48(sp) + * AFA50034 sw a1,52(sp) + * 2402FFFE li v0,-2 ; the SECOND materialisation of the same mask + * $L2: + * 01002021 move a0,t0 ; argument 0 = the saved second parameter + * 8FA30038 lw v1,56(sp) ; (L) v1 = rec[10] + * 27A50010 addiu a1,sp,16 ; argument 1 = &record + * 00621824 and v1,v1,v0 ; rec[10] &= -2 + * 0006102B sltu v0,zero,a2 ; (a2 != 0) + * 00621825 or v1,v1,v0 ; rec[10] |= (a2 != 0) + * 2402FFFD li v0,-3 + * 00621824 and v1,v1,v0 ; rec[10] &= -3 + * 0007102B sltu v0,zero,a3 ; (a3 != 0) + * 00021040 sll v0,v0,0x1 + * 00621825 or v1,v1,v0 ; rec[10] |= (a3 != 0) << 1 + * 0120F809 jalr t1 ; tail call: t1(a0,a1) + * AFA30038 sw v1,56(sp) ; (delay) rec[10] = v1 + * 8FBF0050 lw ra,80(sp) ; (END) + * 27BD0058 addiu sp,sp,88 + * 03E00008 jr ra + * 00000000 nop + * + * THREE BYTE-REQUIRED SPELLINGS, EACH MEASURED (3 spellings, 172/200/168/172): + * + * (1) THE VECTOR COPIES MUST BE STRUCT ASSIGNMENTS. Four separate element stores (`rec[2] = + * a2->v[0]; ...`) interleave load/store and cost FOUR load-delay `nop`s each: 200 bytes, + * +28. `*(struct V4 *)&rec[2] = *a2;` gives the original's four batched loads then four + * stores. Cookbook 76/96/102. + * + * (2) THE SECOND BOOLEAN MUST BE NAMED. `rec[10] |= (a3 != 0) << 1;` written inline becomes a + * BRANCH (`beqz a3` + `ori v0,v0,0x2` + a SECOND `sw` of rec[10]); only + * `b = (a3 != 0); rec[10] |= b << 1;` gives the original's `sltu`/`sll`/`or`. The FIRST + * boolean needs no help (`rec[10] |= (a2 != 0);` is already branchless) — cookbook 44/123's + * "name the boolean" direction, per-site rather than per-function. + * + * (3) THE MASK MUST BE A LITERAL, AND THAT IS WHAT FIXES THE REGISTER ALLOCATION. With the mask + * in a variable (`int f = -2; rec[10] &= f;`) GCC keeps f in `t0` ACROSS the two record + * copies: the row comes out 168 bytes, **one instruction SHORT**, and the allocation shifts + * (`fn`->t2, second parameter->t1, mask->t0) where the original has `fn`->t1, + * parameter->t0, mask->v0. Written as the literal `rec[10] &= -2;` the mask is + * REMATERIALISED once per path (`li v0,-2` in the `beqz a3` delay slot AND again inside the + * a3 block — two `li`s for one source expression), which is both the missing instruction and + * the reason `v0` stays free for it, leaving t0 and t1 for the two saved parameters. + * Diagnostic: the allocation of the two SAVED parameters moves together with the mask's + * register, so a "wrong register" residual on a saved parameter can be a constant-liveness + * problem somewhere else in the function. + * + * LIMITS: the function name, the callee (a call through t1, i.e. the first parameter), every + * record offset and the meaning of the record and its flags are read from the instruction shape; + * only the bytes are evidence. The local is modelled as `int rec[16]` because the frame (88 = + * 16 outgoing + 64 local + ra, rounded to 8) implies 64 bytes of local at sp+16..79 and `ra` at + * sp+80; the indices actually touched are 1, 2-5, 6-9 and 10. `struct V4` is a 16-byte/4-int + * vector type chosen for the copy shape, not a recovered declaration. The flags bits (0 = "first + * vector present", 1 = "second vector present") and the constant 2 stored at rec[1] are literal + * observations from the masks (-2 clears bit 0, -3 clears bit 1). + */ + +struct V4 { int v[4]; }; + +void func_8006D250(int (*fn)(), int a1, struct V4 *a2, struct V4 *a3) +{ + int rec[16]; + int b; + + rec[1] = 2; + if (a2 != 0) + *(struct V4 *)&rec[2] = *a2; + if (a3 != 0) + *(struct V4 *)&rec[6] = *a3; + rec[10] &= -2; + rec[10] |= (a2 != 0); + rec[10] &= -3; + b = (a3 != 0); + rec[10] |= b << 1; + fn(a1, rec); +} diff --git a/src/func_8006D2FC.c b/src/func_8006D2FC.c new file mode 100644 index 0000000..1f9097b --- /dev/null +++ b/src/func_8006D2FC.c @@ -0,0 +1,100 @@ +/* + * func_8006D2FC — 180 bytes at 0x8006D2FC..0x8006D3B0 + * + * Hypothesis, not a claim about meaning: the SIBLING of func_8006D250 (the row immediately + * before it in the image). Same request-builder shape — two optional 16-byte vector copies into + * a 64-byte stack record, a flags word, then a call through the function pointer — with three + * differences: the record's type tag at index 1 is 3 instead of 2, the record has a FIFTH + * incoming parameter which is stored at index 10, and the flags word is therefore at index 11 + * instead of 10. + * + * Original words: + * 27BDFFA8 addiu sp,sp,-88 + * 00805021 move t2,a0 ; the callee is kept in t2 (a0/a1 get clobbered below) + * 00A04821 move t1,a1 ; the second parameter is kept in t1 + * 8FA80068 lw t0,104(sp) ; t0 = the FIFTH incoming parameter (caller sp+16) + * 24020003 li v0,3 + * AFBF0050 sw ra,80(sp) + * 10C00009 beqz a2,0x8006D33C ; no first vector -> skip its copy + * AFA20014 sw v0,20(sp) ; (delay) rec[1] = 3 + * 8CC20000 lw v0,0(a2) ; (L) 4 loads ... + * 8CC30004 lw v1,4(a2) + * 8CC40008 lw a0,8(a2) + * 8CC5000C lw a1,12(a2) + * AFA20018 sw v0,24(sp) ; ... then 4 stores -> rec[2..5] = a2[0..3] + * AFA3001C sw v1,28(sp) + * AFA40020 sw a0,32(sp) + * AFA50024 sw a1,36(sp) + * 10E0000A beqz a3,0x8006D368 ; no second vector -> skip its copy + * 2402FFFE li v0,-2 ; (delay) the mask, FIRST materialisation + * 8CE20000 lw v0,0(a3) ; (L) 4 loads ... + * 8CE30004 lw v1,4(a3) + * 8CE40008 lw a0,8(a3) + * 8CE5000C lw a1,12(a3) + * AFA20028 sw v0,40(sp) ; ... then 4 stores -> rec[6..9] = a3[0..3] + * AFA3002C sw v1,44(sp) + * AFA40030 sw a0,48(sp) + * AFA50034 sw a1,52(sp) + * 2402FFFE li v0,-2 ; the SECOND materialisation of the same mask + * $L2: + * 01202021 move a0,t1 ; argument 0 = the saved second parameter + * 8FA3003C lw v1,60(sp) ; (L) v1 = rec[11] + * 27A50010 addiu a1,sp,16 ; argument 1 = &record + * AFA80038 sw t0,56(sp) ; (delay) rec[10] = the fifth parameter + * 00621824 and v1,v1,v0 ; rec[11] &= -2 + * 0006102B sltu v0,zero,a2 ; (a2 != 0) + * 00621825 or v1,v1,v0 ; rec[11] |= (a2 != 0) + * 2402FFFD li v0,-3 + * 00621824 and v1,v1,v0 ; rec[11] &= -3 + * 0007102B sltu v0,zero,a3 ; (a3 != 0) + * 00021040 sll v0,v0,0x1 + * 00621825 or v1,v1,v0 ; rec[11] |= (a3 != 0) << 1 + * 0140F809 jalr t2 ; tail call: t2(a0,a1) + * AFA3003C sw v1,60(sp) ; (delay) rec[11] = v1 + * 8FBF0050 lw ra,80(sp) ; (END) + * 27BD0058 addiu sp,sp,88 + * 03E00008 jr ra + * 00000000 nop + * + * THE FIVE PARAMETERS ARE READ OFF THE REGISTER AND STACK SET-UP, and the FIFTH is what shifts + * the flags word. `lw t0,104(sp)` at entry is the o32 fifth argument: this frame is 88 bytes, so + * the caller's outgoing-argument area starts at sp+88+16 = sp+104. The value is loaded ONCE at + * the top and kept in `t0` across both record copies, then stored at index 10 in the argument + * set-up delay slot — so the source stores it after the copies and the flags RMW works on index + * 11. The frame arithmetic is unchanged from func_8006D250 (88 = 16 outgoing + 64 local + ra). + * + * THE THREE BYTE-REQUIRED SPELLINGS ARE THE SIBLING'S, VERIFIED HERE AGAIN in one spelling each: + * the vector copies are STRUCT ASSIGNMENTS (four batched `lw` then four `sw`; element stores + * interleave and add four load-delay `nop`s each), the second boolean is a NAMED local + * (`b = (a3 != 0); rec[11] |= b << 1;` — written inline it becomes a branch plus a second + * `sw`), and the mask is the LITERAL `-2` so it is rematerialised once per path (`li v0,-2` + * twice) instead of being held in a register across the copies. + * + * LIMITS: the function name, the callee, every record offset, the tag value 3 and the meaning of + * the record and its flags are read from the instruction shape; only the bytes are evidence. The + * fifth parameter's TYPE is `int` because it is stored with a full `sw`; nothing establishes its + * meaning. The local is modelled as `int rec[16]` because the frame implies 64 bytes of local at + * sp+16..79 with `ra` at sp+80; the indices touched are 1, 2-5, 6-9, 10 and 11. `struct V4` is a + * 16-byte/4-int vector type chosen for the copy shape, not a recovered declaration. + */ + +struct V4 { int v[4]; }; + +void func_8006D2FC(int (*fn)(), int a1, struct V4 *a2, struct V4 *a3, int a5) +{ + int rec[16]; + int b; + + rec[1] = 3; + if (a2 != 0) + *(struct V4 *)&rec[2] = *a2; + if (a3 != 0) + *(struct V4 *)&rec[6] = *a3; + rec[10] = a5; + rec[11] &= -2; + rec[11] |= (a2 != 0); + rec[11] &= -3; + b = (a3 != 0); + rec[11] |= b << 1; + fn(a1, rec); +} diff --git a/src/func_8006D3B0.c b/src/func_8006D3B0.c new file mode 100644 index 0000000..0287b3f --- /dev/null +++ b/src/func_8006D3B0.c @@ -0,0 +1,114 @@ +/* + * func_8006D3B0 — 192 bytes at 0x8006D3B0..0x8006D470 + * + * Builds a 48-byte descriptor on the stack and hands it to a caller-supplied + * function pointer: `fn(a1, &desc)`. The descriptor carries a type word, up to + * two 4-word vectors copied in from optional pointers, one scalar taken from the + * FIFTH argument, and a packed flag word. + * + * The observed instructions are: + * addiu sp,sp,-0x58 + * move t2,a0 fn + * move t1,a1 a1 + * lw t0,0x68(sp) a4 — the FIFTH argument, see below + * li v0,4 + * sw ra,0x50(sp) + * beq a2,zero,skip1 \ + * _sw v0,0x14(sp) / desc.f4 = 4 (delay slot) + * lw v0,0(a2) / lw v1,4(a2) / lw a0,8(a2) / lw a1,12(a2) + * sw v0,0x18(sp) / sw v1,0x1c(sp) / sw a0,0x20(sp) / sw a1,0x24(sp) + * skip1: + * beq a3,zero,skip2 + * _li v0,-0x101 + * (the same four-and-four from a3 into 0x28..0x34) + * skip2: + * move a0,t1 \ + * lw v1,0x3c(sp) | desc.flags read-modify-write + * addiu a1,sp,0x10 / a1 = &desc + * sw t0,0x38(sp) desc.f28 = a4 + * and v1,v1,~0x100 / sltu v0,zero,a2 / sll v0,v0,8 / or v1,v1,v0 + * and v1,v1,~0x200 / sltu v0,zero,a3 / sll v0,v0,9 / or v1,v1,v0 + * li v0,1 + * sw v1,0x3c(sp) desc.flags = ... + * jalr t2 fn(a1, &desc) + * _sb v0,0x3c(sp) (delay slot) desc.type = 1 + * lw ra,0x50(sp) / addiu sp,sp,0x58 / jr ra / nop + * + * THE DESCRIPTOR LAYOUT (relative to the struct at sp+0x10, 48 bytes): + * +0x00 (unwritten) the field at sp+0x10 is never stored here + * +0x04 f4 = 4 + * +0x08 v1[4] copied from a2 when a2 != 0 + * +0x18 v2[4] copied from a3 when a3 != 0 + * +0x28 f28 = a4 + * +0x2c the flag word AND a byte "type" field in the same slot + * + * FOUR THINGS THE BYTES PIN DOWN, each of which cost a spelling: + * + * 1. THE FLAG WORD IS A BITFIELD, NOT MASK ARITHMETIC. It is both read-modified + * with `~0x100`/`~0x200` masks AND written with a single `sb` of 1 to the same + * address. That pair is only producible by `unsigned int type : 8; unsigned int + * f8 : 1; unsigned int f9 : 1;` — the 8-bit field is emitted as a byte store + * and the 1-bit fields make cc1 read the word, clear the bit and OR the new + * one in, preserving every other bit. Note the flag word is READ BEFORE IT IS + * EVER WRITTEN: the source leaves it uninitialised, and the read is real (it + * preserves the garbage in the other bits). That is a property of the + * original, not a reconstruction error. + * 2. THE COPIES ARE STRUCT ASSIGNMENTS, not element stores. `s.v1 = *a2;` gives + * the original's four loads then four stores; four `s.v1[i] = a2[i];` + * statements make maspsx insert a load-delay nop after every load and the row + * comes out 220 bytes instead of 192 (cookbook 76/102). + * 3. THE FRAME NEEDS A 16-BYTE UNREFERENCED ARRAY LOCAL. With the descriptor + * alone the frame is 72 and every descriptor offset is right, but the two + * epilogue instructions are 16 bytes off; `int pad[4];` (never referenced) + * reproduces the original's 88-byte frame exactly. cc1 homes an unreferenced + * ARRAY local but not an unreferenced scalar (cookbook 131, now its fourth + * independent instance). + * 4. THE SCALAR READ AT 0x68(sp) IS THE FIFTH ARGUMENT, NOT THE NINTH. With a + * 0x58 frame, the first stack argument sits at sp+0x68 — that is + * `callee_sp + frame + 16`, the o32 incoming-argument position. Declaring four + * extra unused parameters moves the load to sp+0x78 and is the ONLY remaining + * difference (1 differing byte). The function takes five arguments and four of + * them (the two vectors, a1 and a4) are all used. + * + * LIMITS: the struct/field names, the descriptor's meaning, the callee's + * signature and the flag bit meanings are hypotheses reconstructed from the + * disassembly. The uninitialised flag-word read and the unused 16-byte local are + * properties of the reconstruction that the original's bytes require; only the + * compiled bytes are evidence. + */ + +struct V4 { + int v[4]; +}; + +struct S { + int f0; /* +0x00 */ + int f4; /* +0x04 */ + struct V4 v1; /* +0x08 */ + struct V4 v2; /* +0x18 */ + int f28; /* +0x28 */ + unsigned int type : 8; /* +0x2c, byte-wide */ + unsigned int f8 : 1; /* +0x2c, bit 8 */ + unsigned int f9 : 1; /* +0x2c, bit 9 */ +}; + +void func_8006D3B0(void (*fn)(), int a1, struct V4 *a2, struct V4 *a3, int a4) +{ + struct S s; + int pad[4]; + + s.f4 = 4; + + if (a2 != 0) + s.v1 = *a2; + + if (a3 != 0) + s.v2 = *a3; + + s.f28 = a4; + s.f8 = a2 != 0; + s.f9 = a3 != 0; + s.type = 1; + + fn(a1, &s); +} diff --git a/src/func_80091490.c b/src/func_80091490.c new file mode 100644 index 0000000..8fc170a --- /dev/null +++ b/src/func_80091490.c @@ -0,0 +1,68 @@ +/* + * func_80091490 — 84 bytes at 0x80091490..0x800914E4 + * + * PHASE 12 WORKER C. **A DEPENDENT CLAIM (charter rule 2): the callee `func_80018284` is NOT + * yet reconstructed** — it is itself an unmatched row (`0x80018284`, 80 B, in worker C's + * partition, classed "struct-copy jr-slot shape"). Nothing here verifies against the callee's + * body: only the CALL SITE's register setup is reproduced, and the prototype below is + * INFERRED from that call site. If the callee's eventual reconstruction disagrees about how + * many arguments it takes or what the second one is, this declaration must be revisited. + * + * MATCH: candidate_bytes=84, differing_bytes=0, result=MATCH, exit 0 on the DEFAULT + * toolchain (gcc-2.7.2-psx). + * + * The observed instructions are: + * addiu sp,sp,-24 + * sw s0,16(sp) + * move s0,a1 s0 = a1 (the pointer must survive the call) + * move a1,zero arg2 = 0 + * sw ra,20(sp) + * jal 0x80018284 + * move a2,s0 (delay slot) arg3 = the original a1 + * bnez v0,0x800914D0 if (r != 0) goto epilogue (r stays in v0) + * nop + * move v0,zero the fall-through path returns 0 + * lw v1,20(s0) x = a1[5] + * lw a0,4(s0) y = a1[1] + * negu v1,v1 -x + * negu a0,a0 -y + * sw v1,4(s0) a1[1] = -x + * sw a0,20(s0) a1[5] = -y + * D0: lw ra,20(sp) + * lw s0,16(sp) + * addiu sp,sp,24 + * jr ra + * nop + * + * The two `lw`s are issued in the order 20(s0), 4(s0) and the two `sw`s in the MIRRORED order + * 4(s0), 20(s0) — so the source must READ both fields into locals before writing either, and + * the local for the field at +20 must be declared first. The earlier recorded spelling wrote + * the stores the other way round and reached the correct length with 2 differing bytes: the + * difference is purely which load lands in which register, i.e. the declaration order of the + * two locals. `move a1,zero` (rather than `move v0,zero`) is the tell that the second argument + * is the integer 0 and not a null pointer being passed in v0. + * + * LIMITS: the layout (+4 and +20 as words of the object a1 points at) and the meaning of the + * operation (negating and exchanging two fields, apparently a direction/velocity pair) are read + * off the instruction stream; there is no evidence for a struct declaration, so the body is + * written as explicit pointer arithmetic. The return type is `int` because the call's result is + * returned unchanged on one path. Only the compiled bytes are evidence. `D_80122154`-style + * symbol names are absent here, so nothing in this file depends on the gp registry. + */ + +extern int func_80018284(int a0, int a1, int *a2); + +int func_80091490(int a0, int *a1) +{ + int r = func_80018284(a0, 0, a1); + int x; + int y; + + if (r != 0) + return r; + x = a1[5]; + y = a1[1]; + a1[1] = -x; + a1[5] = -y; + return 0; +} diff --git a/src/func_801008DC.c b/src/func_801008DC.c new file mode 100644 index 0000000..dd7217d --- /dev/null +++ b/src/func_801008DC.c @@ -0,0 +1,92 @@ +/* + * func_801008DC — 88 bytes at 0x801008DC..0x80100934 + * + * PHASE 12 WORKER C. A THREE-exit search function, and the row that produced a new, + * REUSABLE lever for a residual class this partition keeps hitting (see LIMITS). + * + * MATCH: candidate_bytes=88, differing_bytes=0, result=MATCH, exit 0 under + * --cc1 tools/old-gcc/gcc-2.8.1-psx/cc1 + * The project default (gcc-2.7.2-psx) gives 88 bytes but 58 differing bytes on the same + * source: it merges the three `return`s into one shared epilogue. This row has THREE + * `jr $31`, so the `cc1bin` override is allowed by the gate AND required by the bytes. + * + * MECHANISM, measured: cc1 2.7.2 SHARES one return epilogue (materialising the return value + * before the branch and jumping to a single `j $31`); the original has one `j $31` per + * `return`. Census: 0 of 634 registered regions contain >= 2 `jr $31`; 12 negatives rows do. + * 14 flag sets on 2.7.2-psx all still give one exit; the cc1 BUILDS 2.8.0-psx / 2.8.1-psx / + * 2.91.66-psx / 2.95.2-psx emit one per return on this shape. (The generalisation is NOT + * established and must not be stated as one: the result is shape-dependent, and a separate + * probe of worker D's could not reproduce it. What is solid is the census and the row-level + * results like this one.) + * + * The observed instructions are: + * lw a1,28(a0) p = *(int **)((char *)a0 + 28) + * nop (load delay) + * bnez a1,0x801008F4 if (p == 0) return 0; + * lui v1,0x2044 (delay slot: the tag's high half, hoisted) + * jr ra + * move v0,zero + * F4: lw v0,0(a1) if (*p == 0x2044494D) + * ori v1,v1,0x494D return p; <- v0 = p in the delay slot + * beq v0,v1,0x80100924 + * move v0,a1 (delay slot: the return value's copy) + * lbu v0,7(a1) c = *(unsigned char *)((char *)p + 7) + * lbu a0,25(a0) d = *(unsigned char *)(a0 + 25) + * addiu v0,v0,-1 if (c - 1 < d) + * slt v0,v0,a0 + * bnez v0,0x8010092C return 0; + * sll v0,a0,0x2 (delay slot: d * 4) + * addu v0,a1,v0 p + d*4 + * lw v0,16(v0) return *(int *)(p + d*4 + 16) + * 24: jr ra return p; + * nop + * 2C: jr ra return 0; + * move v0,zero + * + * The tag word `0x2044494D` is "MID " as little-endian ASCII bytes (4D 49 44 20), which is + * what a Sony container id looks like; the value is evidence, the reading of it is a guess. + * + * LIMITS — and the LEVER, which is the interesting part of this file. + * This row's residual after the structure was solved was ONE differing byte: the operand + * order of the final `addu`. Original `addu v0,a1,v0` (0x00A21021); candidate + * `addu v0,v0,a1` (0x00451021). That is a POINTER-plus-INT, and — like + * `0x80050674`/`0x80050604`, whose only residual is the same class of operand order on an + * `addu` — re-spelling the addition does NOT move it: five forms were tried here + * (`(char *)p + 16 + d*4`, `(char *)p + (d*4 + 16)`, a named `off` variable, + * `((char *)p + d*4)` indexed with `[4]`, a reversed `(char *)p + 16` then `base + 16`) and + * all five give the same 1-byte residual. + * **What DOES move it: the pointer-plus must be BOUND TO A NAMED `char *` LOCAL, with the + * constant left outside as the load displacement** — + * base = (char *)p + *(unsigned char *)(a0 + 25) * 4; + * return (int *)*(int *)(base + 16); + * That flips the comparison to `addu v0,a1,v0` and the row is byte-exact. So the operand + * order of a commutative/pointer add here is controlled by a named binding, not by the + * expression's text order, and the `+ 16` must stay a displacement rather than being folded + * into the sum. This is the mirror of what worker C measured on `0x80050674`, where the same + * class resisted every spelling INCLUDING the named-local variants: the class is real and + * recurring, and this file is one worked instance of it. Note also that cookbook 42's claim + * that the operand order and the register allocation are COUPLED is false in this direction — + * here only the order moves. + * + * The rest of the limits: `a0` is typed `char *` because every access is a byte displacement + * from it; the layout (a pointer at +28, a byte at +25 and words at +0/+16 of the sub-object, + * a byte at +7 of the sub-object) is read off the instruction stream with no evidence for a + * struct declaration, so it is written as explicit pointer arithmetic. The return type is + * `int *` because two of the three exits return the sub-object pointer; the third returns a + * word from a table and is cast. Only the compiled bytes are evidence. + */ + +int *func_801008DC(char *a0) +{ + int *p = *(int **)(a0 + 28); + char *base; + + if (p == 0) + return 0; + if (*p == 0x2044494D) + return p; + if (*(unsigned char *)((char *)p + 7) - 1 < *(unsigned char *)(a0 + 25)) + return 0; + base = (char *)p + *(unsigned char *)(a0 + 25) * 4; + return (int *)*(int *)(base + 16); +} diff --git a/src/func_80101C5C.c b/src/func_80101C5C.c new file mode 100644 index 0000000..c0a000e --- /dev/null +++ b/src/func_80101C5C.c @@ -0,0 +1,52 @@ +/* + * func_80101C5C — 32 bytes at 0x80101C5C..0x80101C7C + * + * GOAL B ROW (worker D, Phase 12): recorded in + * `config/near_match_negatives.tsv` with class `-`. It is a **GTE class** row — + * the class the phase reopened with a known lever — and it matched on the FIRST + * spelling. + * + * Byte-identical reconstruction: copy the translation vector into the GTE's + * control registers $5/$6/$7 (TRX/TRY/TRZ) from `src[5..7]` (byte offsets + * +0x14/+0x18/+0x1c). + * + * The observed instructions are: + * lw t0,20(a0) / lw t1,24(a0) / lw t2,28(a0) ; ALL THREE LOADS FIRST + * ctc2 t0,$5 / ctc2 t1,$6 / ctc2 t2,$7 + * jr ra / nop + * + * TWO things the bytes fix: + * + * 1. THE LOADS ARE BATCHED, AND THAT IS A SOURCE FACT, NOT A SCHEDULE. Written + * as three bare `gte_ldTRx(src[n])` calls the operands are materialised inside + * each `__asm__ volatile`, cc1 emits `lw / #nop / ctc2` three times, and the + * region comes out 44 bytes instead of 32: the asm statements stop the loads + * from being hoisted. Binding the three values to REGISTER VARIABLES first + * (the idiom the neighbouring matched `src/func_80101CAC.c` uses) hoists all + * three loads above the first asm statement and reproduces the original + * exactly. Cookbook 160: a register binding is not inline assembly and needs + * no exemption. + * 2. THE REGISTERS ARE $8/$9/$10 — `t0`/`t1`/`t2` — which is what the bindings + * pin, and matches the neighbouring row's convention. + * + * LIMITS: the source pointer, the three displacements and the control-register + * numbers are read off the bytes; the macro names are the re-derived ones from + * `include/gtemac.h` (the numbering itself is cookbook 29's map, where $5/$6/$7 + * are the translation vector). Nothing here establishes what the values mean. + */ +#include "../include/gtemac.h" + +void func_80101C5C(int *src) +{ + register int t0 __asm__("$8"); + register int t1 __asm__("$9"); + register int t2 __asm__("$10"); + + t0 = src[5]; + t1 = src[6]; + t2 = src[7]; + + gte_ldTRX(t0); + gte_ldTRY(t1); + gte_ldTRZ(t2); +} diff --git a/src/func_80102FE4.c b/src/func_80102FE4.c new file mode 100644 index 0000000..223306d --- /dev/null +++ b/src/func_80102FE4.c @@ -0,0 +1,48 @@ +/* + * func_80102FE4 — 48 bytes at 0x80102FE4..0x80103014 + * + * GOAL B ROW (worker D, Phase 12): recorded in + * `config/near_match_negatives.tsv` with class `-`. GTE class; matched on the + * FIRST spelling with the same lever as its neighbour `0x80101C5C` (below). + * + * Byte-identical reconstruction: load the light-source colour matrix from + * `src[0..4]` into the GTE's control registers $16..$20 (LR1LR2, LR3LG1, + * LG2LG3, LB1LB2, LB3). + * + * The observed instructions are: + * lw t0,0(a0) / lw t1,4(a0) / lw t2,8(a0) / lw t3,12(a0) / lw t4,16(a0) + * ctc2 t0,$16 / ctc2 t1,$17 / ctc2 t2,$18 / ctc2 t3,$19 / ctc2 t4,$20 + * jr ra / nop + * + * All five loads are batched before the first `ctc2`, which is what the + * register-bound form produces: the bare macro form interleaves `lw / nop / + * ctc2` five times and is 68 bytes against the original's 48 (cookbook 160, + * and the idiom of the neighbouring registered `src/func_80101CAC.c`). + * + * LIMITS: as for `0x80101C5C` — displacements, the five register numbers and the + * source pointer are read from the bytes; `include/gtemac.h` supplies the macro + * names and cookbook 29 the register map. The initial source pointer is modelled + * as `int *` because only word loads are performed through it. + */ +#include "../include/gtemac.h" + +void func_80102FE4(int *src) +{ + register int t0 __asm__("$8"); + register int t1 __asm__("$9"); + register int t2 __asm__("$10"); + register int t3 __asm__("$11"); + register int t4 __asm__("$12"); + + t0 = src[0]; + t1 = src[1]; + t2 = src[2]; + t3 = src[3]; + t4 = src[4]; + + gte_ldLR1LR2(t0); + gte_ldLR3LG1(t1); + gte_ldLG2LG3(t2); + gte_ldLB1LB2(t3); + gte_ldLB3(t4); +}