src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c:func_80182F4C: score 29 (REG-caller; mine 81 ins, target 81) — not yet
  register pairs (mine -> target, count): t1->t0 x10, t0->a3 x6, a3->a0 x6, t4->t3 x5, a0->t6 x2, t6->t5 x2, t3->t2 x2, t2->t1 x2
  replace mine[0:3] target[0:3]
        0  lui	t1,0x0                         | lui	t0,0x0
        1  addiu	t1,t1,0                      | addiu	t0,t0,0
        2  li	t4,0xf800                       | li	t3,0xf800
  replace mine[5:8] target[5:8]
        5  sra	a0,a0,0x10                     | sra	t6,a0,0x10
        6  li	t0,0xfa00                       | li	a3,0xfa00
        7  andi	v0,t4,0xffff                  | andi	v0,t3,0xffff
  replace mine[10:12] target[10:12]
       10  andi	t6,v0,0x1ff                   | andi	t5,v0,0x1ff
       11  andi	v0,t0,0xffff                  | andi	v0,a3,0xffff
  replace mine[14:15] target[14:15]
       14  lhu	v1,2(t1)                       | lhu	v1,2(t0)
  replace mine[17:18] target[17:18]
       17  lhu	v1,4(t1)                       | lhu	v1,4(t0)
  replace mine[20:26] target[20:26]
       20  lw	a3,20(t1)                       | lw	a0,20(t0)
       21  lw	t3,24(t1)                       | lw	t2,24(t0)
       22  lw	t2,28(t1)                       | lw	t1,28(t0)
       23  lhu	v0,0(t1)                       | lhu	v0,0(t0)
       24  lw	v1,8(t1)                        | lw	v1,8(t0)
       25  subu	v0,t6,v0                      | subu	v0,t5,v0
  replace mine[35:36] target[35:36]
       35  addu	a3,a3,v1                      | addu	a0,a0,v1
  replace mine[40:42] target[40:42]
       40  li	t5,0xffff                       | li	t4,0xffff
       41  lhu	v1,0(a3)                       | lhu	v1,0(a0)
  replace mine[49:50] target[49:50]
       49  addu	v1,t3,v0                      | addu	v1,t2,v0
  replace mine[56:57] target[56:57]
       56  addu	v1,t2,v0                      | addu	v1,t1,v0
  replace mine[59:60] target[59:60]
       59  bne	v0,a0,8218 <func_80182F4C+0xf8> | bne	v0,t6,8218 <func_80182F4C+0xf8>
  replace mine[62:63] target[62:63]
       62  addiu	a3,a3,2                      | addiu	a0,a0,2
  replace mine[66:69] target[66:69]
       66  addu	a2,a2,t5                      | addu	a2,a2,t4
       67  addiu	t0,t0,128                    | addiu	a3,a3,128
       68  andi	v1,t0,0xffff                  | andi	v1,a3,0xffff
  replace mine[72:75] target[72:75]
       72  andi	v0,t0,0xffff                  | andi	v0,a3,0xffff
       73  addiu	t4,t4,128                    | addiu	t3,t3,128
       74  andi	v1,t4,0xffff                  | andi	v1,t3,0xffff
