src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.c:func_8012E364: score 25 (MIXED; mine 67 ins, target 67) — not yet
  register pairs (mine -> target, count): v0->v1 x9, a1->a2 x7, v1->a1 x4, v1->v0 x4, a2->a3 x3, v1->a0 x3, a3->t0 x2
  replace mine[0:2] target[0:2]
        0  move	a1,a0                         | move	a2,a0
        1  sh	zero,92(a1)                     | sh	zero,92(a2)
  replace mine[18:19] target[18:19]
       18  lw	v0,28(a1)                       | lw	v0,28(a2)
  replace mine[21:24] target[21:24]
       21  sw	v0,28(a1)                       | sw	v0,28(a2)
       22  mfhi	a3                            | mfhi	t0
       23  sra	v0,a3,0x5                      | sra	v0,t0,0x5
  replace mine[30:31] target[30:31]
       30  li	a2,4096                         | li	a3,4096
  replace mine[43:48] target[43:48]
       43  lui	v1,0x0                         | lui	a1,0x0
       44  lw	v1,0(v1)                        | lw	a1,0(a1)
       45  lw	a0,32(a1)                       | lw	a0,32(a2)
       46  lui	v0,0x0                         | lui	v1,0x0
       47  lw	v0,0(v0)                        | lw	v1,0(v1)
  replace mine[49:53] target[49:53]
       49  sw	a2,0(at)                        | sw	a3,0(at)
       50  subu	v0,v0,v1                      | subu	v1,v1,a1
       51  lhu	v1,44(a0)                      | lhu	v0,44(a0)
       52  addu	v0,v0,a2                      | addu	v1,v1,a3
  replace mine[54:60] target[54:60]
       54  sw	v0,0(at)                        | sw	v1,0(at)
       55  ori	v1,v1,0x10                     | ori	v0,v0,0x10
       56  sh	v1,44(a0)                       | sh	v0,44(a0)
       57  lw	v1,32(a1)                       | lw	a0,32(a2)
       58  bgez	v0,3778 <func_8012E364+0xf4>  | bgez	v1,3778 <func_8012E364+0xf4>
       59  nop                                | move	v0,v1
  replace mine[61:64] target[61:64]
       61  sh	v0,28(v1)                       | sh	v0,28(a0)
       62  sh	v0,24(v1)                       | sh	v0,24(a0)
       63  lw	v1,32(a1)                       | lw	v1,32(a2)
