From 02f0dd3c47e43e2ac913f0caabce9d81dbe0e8e8 Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 11 Sep 2026 03:10:54 -0600 Subject: [PATCH] =?UTF-8?q?phase-36:=20S104=20s104=5Fe24=20=E2=80=94=20fun?= =?UTF-8?q?c=5F80185B70=20banked=20at=200=20through=20the=20whole-object?= =?UTF-8?q?=20gate=20+=20propagated=20=E2=80=94=20e24=20sibling:=20an=20un?= =?UTF-8?q?marked=20do-while=20removed?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .run/P36/delever/calibration.json | 374 +++++++++++----------- .run/P36/delever/ledger.jsonl | 1 + src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c | 6 +- 3 files changed, 192 insertions(+), 189 deletions(-) diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index 94284bbd34..0d32c7b480 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,7 +1,7 @@ { - "head": "f823839e4", + "head": "41a2f9c24", "stamp": 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"build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.118, + "build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.157, + "build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.654, + "build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.089, + "build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.079 }, "ok": true, - "seconds": 15.3 + "seconds": 3.7 } diff --git a/.run/P36/delever/ledger.jsonl b/.run/P36/delever/ledger.jsonl index 744bff0416..ef0feed864 100644 --- a/.run/P36/delever/ledger.jsonl +++ b/.run/P36/delever/ledger.jsonl @@ -29476,3 +29476,4 @@ {"ts": "2026-09-11 03:08:59", "label": "s104_e24", "rung": "E", "calib": {"head": "902a30068", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c", "fn": "func_8017F694", "addr": 2149054100, "aliases": null, "header": false, "includers": 0, "nhash_before": "27972cd1f03c1db8ce89413c4309822c524c9db2", "nhash_after": "83c14d1ea423dd20ad871e78967d529d8d6de632", "source": ".run/P36/agents/ov_SC06_016__func_8017F694/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.179, "objects": ["build/src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.o"], "before_text": "void func_8017F694(s32 arg0) {\n /* Frame lever (cookbook \"frame-pad induction\"): the target's frame is\n 0x20 with $ra at 0x18, i.e. vars=8 with nothing $sp-addressed. A\n declared BLKmode local reserves its 8-byte slot at expand and -O2 DCE\n never reclaims it; `(void)&x` escapes the address with zero code and\n silences -Wunused. Without it: frame 0x18 / $ra at 0x10 (4 diffs). */\n SVec8_8017F694 unused;\n (void)&unused;\n\n if (D_8019F9FC != NULL) {\n if (*(s32 *)(*(s32 *)(arg0 + 0x20) + 0x4) < 0) {\n *(s32 *)((u8 *)D_8019F9FC + 0x4) |= 0x80000000;\n } else {\n u8 *ptr2 = (u8 *)D_8019F9FC;\n /* \u00a7194-A zero-byte fence at the HEAD of the else-arm block.\n Two jobs, both load-bearing:\n 1. reorg.c refuses to put an ASM insn in a delay slot, so the\n bgez's eager steal cannot take this arm's `lui 0x7FFF` --\n it falls back to the fall-through arm's `lui 0x80000000`,\n which is what the target's delay slot holds.\n 2. it pins the arm's first sched1 group, giving the target's\n lui / lw / ori / sh / and order.\n Drop it and the diff is 7 (stolen 0x7FFF lui + shuffled arm). */\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus10)\n *(s32 *)(ptr2 + 0x4) &= 0x7FFFFFFF;\n *(s16 *)(ptr2 + 0x10) = 0;\n *(u16 *)(ptr2 + 0x12) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x12);\n *(s16 *)(ptr2 + 0x14) = 0;\n /* four separate `lw 0x20($t0)` intervals in the target: each\n statement re-reads the pointer (\u00a7193-E), so never cache it. */\n *(SVec8_8017F694 *)(ptr2 + 0x8) = *(SVec8_8017F694 *)(*(s32 *)(arg0 + 0x20) + 0x8);\n *(SVec8_8017F694 *)(ptr2 + 0x18) = *(SVec8_8017F694 *)(*(s32 *)(arg0 + 0x20) + 0x18);\n func_800183E0((s32)(D_80188FAC + ((D_800B99DA & 7) << 5)));\n }\n }\n}\n", "after_text": "void func_8017F694(s32 arg0) {\n\n if (D_8019F9FC != NULL) {\n if (*(u32 *)(*(s32 *)(arg0 + 0x20) + 0x4) & 0x80000000) {\n *(s32 *)((u8 *)D_8019F9FC + 0x4) |= 0x80000000;\n } else {\n u8 *ptr2 = (u8 *)D_8019F9FC;\n *(s32 *)(ptr2 + 0x4) &= 0x7FFFFFFF;\n *(s16 *)(ptr2 + 0x10) = 0;\n *(u16 *)(ptr2 + 0x12) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x12);\n *(s16 *)(ptr2 + 0x14) = 0;\n *(SVec8_8017F694 *)(ptr2 + 0x8) = *(SVec8_8017F694 *)(*(s32 *)(arg0 + 0x20) + 0x8);\n *(SVec8_8017F694 *)(ptr2 + 0x18) = *(SVec8_8017F694 *)(*(s32 *)(arg0 + 0x20) + 0x18);\n func_800183E0((s32)(D_80188FAC + ((D_800B99DA & 7) << 5)));\n }\n }\n}\n"} {"ts": "2026-09-11 03:09:33", "label": "s104_e24", "rung": "E", "calib": {"head": "ae86c4962", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c", "fn": "func_80180E24", "addr": 2149060132, "aliases": null, "header": false, "includers": 0, "nhash_before": "8c7e93d4e2ab55fb67ee923708b9dd60d858f430", "nhash_after": "23c69cd89d9c9c855885f915e500f1f1155910c9", "source": ".run/P36/agents/ov_SC06_016__func_80180E24/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.135, "objects": ["build/src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.o"], "before_text": "void func_80180E24(void *a0)\n{\n void *s1;\n void *s2;\n void *s0;\n s32 t;\n s32 v0;\n s32 *p;\n s16 out[4];\n\n s1 = a0;\n s2 = *(void **)((u8 *)s1 + 0x2C); /* +0x2C: owner record */\n v0 = *(u16 *)((u8 *)s1 + 0x2); /* +0x02: state word */\n\n if (v0 == 0) {\n s0 = (u8 *)s1 + 0x24; /* +0x24: 4-word scratch */\n *(s32 *)(*(s32 *)((u8 *)s1 + 0x20) + 0x20) = (s32)&D_801890BC;\n *(u8 *)(*(s32 *)((u8 *)s1 + 0x20) + 0x27) = 0x43;\n\n /* one shared base for the 0x1A/0x18 pair (\u00a7193-E: naming it collapses\n * the two CSE intervals into the single `lw $v1,0x20($s1)` reload) */\n p = *(s32 **)((u8 *)s1 + 0x20);\n *(u16 *)((u8 *)p + 0x1A) = 0x2800;\n *(u16 *)((u8 *)p + 0x18) = 0x2800;\n\n func_80128EA8(*(s32 *)((u8 *)s1 + 0x20), (s32)s0, (s32)&D_801890C8);\n\n *(u16 *)((u8 *)s1 + 0x2) = *(u16 *)((u8 *)s1 + 0x2) + 1;\n func_80128ED8(*(s32 *)((u8 *)s1 + 0x20), (s32 *)s0);\n *(s32 *)((u8 *)s1 + 0x1C) = 0; /* +0x1C: frame timer */\n }\n\n t = *(s32 *)((u8 *)s1 + 0x1C) + 1;\n *(s32 *)((u8 *)s1 + 0x1C) = t;\n\n /* duplicated call+return in both arms; cross_jump merges the scheduled\n * common SUFFIX into the target's one shared block (\u00a7193-C / law 22) */\n if (t >= 0x16) {\n func_801292C8((u8 *)s1);\n return;\n }\n if (*(s16 *)((u8 *)s2 + 0x36) != *(s16 *)((u8 *)s1 + 0x30)) {\n func_801292C8((u8 *)s1);\n return;\n }\n\n if (t < 4) {\n v0 = (t * 5) << 9; /* 0xA00 per frame ramp */\n p = *(s32 **)((u8 *)s1 + 0x20);\n } else {\n p = *(s32 **)((u8 *)s1 + 0x20);\n v0 = 0x2800;\n }\n\n *(u16 *)((u8 *)p + 0x1A) = v0;\n *(u16 *)((u8 *)p + 0x18) = v0;\n __asm__ __volatile__(\"\"); /* \u00a7194-A / law 28: emit the sh // !FAKE: barrier \u2014 NEEDED COMPILE-ERROR (P36 rung B tus10)\n * pair FIRST in its block so the\n * next call's arg setup cannot\n * float above it (required --\n * removing it costs 6 ins) */\n\n func_8012F214((s32)s2, (s32)&D_801890D0, (s32)out);\n *(u16 *)((u8 *)s1 + 0x6) = out[0];\n *(u16 *)((u8 *)s1 + 0xA) = out[1];\n *(u16 *)((u8 *)s1 + 0xE) = out[2];\n\n *(u16 *)(*(s32 *)((u8 *)s1 + 0x20) + 0x2C) = 0xC040;\n}\n", "after_text": "void func_80180E24(void *a0)\n{\n void *s1;\n void *s2;\n void *s0;\n s32 t;\n s32 v0;\n s32 *p;\n s16 out[4];\n\n s1 = a0;\n s2 = *(void **)((u8 *)s1 + 0x2C); /* +0x2C: owner record */\n v0 = *(u16 *)((u8 *)s1 + 0x2); /* +0x02: state word */\n\n if (v0 == 0) {\n s0 = (u8 *)s1 + 0x24; /* +0x24: 4-word scratch */\n *(s32 *)(*(s32 *)((u8 *)s1 + 0x20) + 0x20) = (s32)&D_801890BC;\n *(u8 *)(*(s32 *)((u8 *)s1 + 0x20) + 0x27) = 0x43;\n\n /* one shared base for the 0x1A/0x18 pair (\u00a7193-E: naming it collapses\n * the two CSE intervals into the single `lw $v1,0x20($s1)` reload) */\n p = *(s32 **)((u8 *)s1 + 0x20);\n *(u16 *)((u8 *)p + 0x1A) = 0x2800;\n *(u16 *)((u8 *)p + 0x18) = 0x2800;\n\n func_80128EA8(*(s32 *)((u8 *)s1 + 0x20), (s32)s0, (s32)&D_801890C8);\n\n *(u16 *)((u8 *)s1 + 0x2) = *(u16 *)((u8 *)s1 + 0x2) + 1;\n func_80128ED8(*(s32 *)((u8 *)s1 + 0x20), (s32 *)s0);\n *(s32 *)((u8 *)s1 + 0x1C) = 0; /* +0x1C: frame timer */\n }\n\n t = *(s32 *)((u8 *)s1 + 0x1C) + 1;\n *(s32 *)((u8 *)s1 + 0x1C) = t;\n\n /* duplicated call+return in both arms; cross_jump merges the scheduled\n * common SUFFIX into the target's one shared block (\u00a7193-C / law 22) */\n if (t >= 0x16) {\n func_801292C8((u8 *)s1);\n return;\n }\n if (*(s16 *)((u8 *)s2 + 0x36) != *(s16 *)((u8 *)s1 + 0x30)) {\n func_801292C8((u8 *)s1);\n return;\n }\n\n if (t < 4) {\n v0 = (t * 5) << 9; /* 0xA00 per frame ramp */\n p = *(s32 **)((u8 *)s1 + 0x20);\n *(u16 *)((u8 *)p + 0x1A) = v0;\n *(u16 *)((u8 *)p + 0x18) = v0;\n } else {\n p = *(s32 **)((u8 *)s1 + 0x20);\n *(u16 *)((u8 *)p + 0x1A) = 0x2800;\n *(u16 *)((u8 *)p + 0x18) = 0x2800;\n }\n\n func_8012F214((s32)s2, (s32)&D_801890D0, (s32)out);\n *(u16 *)((u8 *)s1 + 0x6) = out[0];\n *(u16 *)((u8 *)s1 + 0xA) = out[1];\n *(u16 *)((u8 *)s1 + 0xE) = out[2];\n\n *(u16 *)(*(s32 *)((u8 *)s1 + 0x20) + 0x2C) = 0xC040;\n}\n"} {"ts": "2026-09-11 03:10:19", "label": "s104_e24", "rung": "E", "calib": {"head": "f823839e4", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_016/ov_SC06_016_jr_801816DC.c", "fn": "func_80181998", "addr": 2149063064, "aliases": null, "header": false, "includers": 0, "nhash_before": "b4d08651325f3ef01dfd2871b3d3525def268eb2", "nhash_after": "e57b49cd1f14485b5ba9dfd07a0054a562b1b58a", "source": ".run/P36/agents/ov_SC06_016__func_80180E24/scratch/sib_80181998.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.123, "objects": ["build/src/ov_SC06_016/ov_SC06_016_jr_801816DC.o"], "before_text": "void func_80181998(s32 param_1)\n{\n u16 state;\n s32 s2;\n s32 cnt;\n s32 p; /* the render object pointer, reloaded once per arm */\n s32 v; /* the 16-bit scale value stored to +0x1A / +0x18 */\n\n state = *(u16 *)(param_1 + 2); /* +0x02 state */\n s2 = *(s32 *)(param_1 + 0x2C); /* +0x2C owner */\n\n switch (state) {\n case 0: {\n s32 h = (s32)D_80189130;\n s32 obj = *(s32 *)(param_1 + 0x20);\n s32 s0 = param_1 + 0x24;\n *(s32 *)(obj + 0x20) = h;\n *(u32 *)(*(s32 *)(param_1 + 0x20) + 4) =\n *(u32 *)(*(s32 *)(param_1 + 0x20) + 4) | 0x58000000;\n *(u8 *)(*(s32 *)(param_1 + 0x20) + 0x27) = 0x42;\n {\n /* one CSE interval -> one lw feeding both sh (\u00a7193-E) */\n s32 q = *(s32 *)(param_1 + 0x20);\n *(u16 *)(q + 0x1A) = 0x3800;\n *(u16 *)(q + 0x18) = 0x3800;\n }\n func_80128EA8(*(s32 *)(param_1 + 0x20), s0, (s32)D_8018913C);\n *(u16 *)(param_1 + 2) = *(u16 *)(param_1 + 2) + 1;\n func_80128ED8(*(s32 *)(param_1 + 0x20), (s32 *)s0);\n *(s32 *)(param_1 + 0x1C) = 0; /* +0x1C frame counter */\n break;\n }\n case 1:\n break;\n default:\n return;\n }\n\n /* guard clause: the sw of the counter below sits in a branch delay slot,\n * so its statement dominates the if (\u00a7194-M) */\n if (*(s16 *)(s2 + 0x36) != *(s16 *)(param_1 + 0x30)) {\n func_801292C8((u8 *)param_1);\n return;\n }\n\n func_80128ED8(*(s32 *)(param_1 + 0x20), (s32 *)(param_1 + 0x24));\n cnt = *(s32 *)(param_1 + 0x1C) + 1;\n *(s32 *)(param_1 + 0x1C) = cnt;\n /* The reload of +0x20 is written INSIDE BOTH ARMS and, in the true arm,\n * BETWEEN the two halves of the *7<<8 chain. Both placements are\n * load-bearing: putting it last in each arm lets cross_jump merge the\n * common suffix (\u00a7193-C) and loses an instruction; putting it first\n * lets sched1 hoist it to the block top. Splitting the value into its\n * own local `v` (distinct from the counter `cnt`) is what puts the value\n * in $v0 and the pointer in $v1 (\u00a7186c: which allocator owns a pseudo\n * follows from where it is written). */\n if (cnt < 8) {\n v = cnt * 7;\n p = *(s32 *)(param_1 + 0x20);\n v = v << 8;\n } else {\n p = *(s32 *)(param_1 + 0x20);\n v = 0x3800;\n }\n do { *(u16 *)(p + 0x1A) = v; } while (0); // !FAKE: do-while \u2014 a LOOP-note scheduling barrier (sched.c:2058-2074; P36 R7)\n *(u16 *)(p + 0x18) = v;\n /* \u00a7194-A one-way fence: without it sched2 hoists func_80129350's two\n * argument copies above the pair of sh stores. */\n func_80129350(param_1, s2);\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x10) = 0;\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) = 0;\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x14) =\n *(u16 *)(*(s32 *)(s2 + 0x20) + 0x12);\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x2C) = 0xC040;\n}\n", "after_text": "void func_80181998(s32 param_1)\n{\n u16 state;\n s32 s2;\n s32 cnt;\n s32 p; /* the render object pointer, reloaded once per arm */\n s32 v; /* the 16-bit scale value stored to +0x1A / +0x18 */\n\n state = *(u16 *)(param_1 + 2); /* +0x02 state */\n s2 = *(s32 *)(param_1 + 0x2C); /* +0x2C owner */\n\n switch (state) {\n case 0: {\n s32 h = (s32)D_80189130;\n s32 obj = *(s32 *)(param_1 + 0x20);\n s32 s0 = param_1 + 0x24;\n *(s32 *)(obj + 0x20) = h;\n *(u32 *)(*(s32 *)(param_1 + 0x20) + 4) =\n *(u32 *)(*(s32 *)(param_1 + 0x20) + 4) | 0x58000000;\n *(u8 *)(*(s32 *)(param_1 + 0x20) + 0x27) = 0x42;\n {\n /* one CSE interval -> one lw feeding both sh (\u00a7193-E) */\n s32 q = *(s32 *)(param_1 + 0x20);\n *(u16 *)(q + 0x1A) = 0x3800;\n *(u16 *)(q + 0x18) = 0x3800;\n }\n func_80128EA8(*(s32 *)(param_1 + 0x20), s0, (s32)D_8018913C);\n *(u16 *)(param_1 + 2) = *(u16 *)(param_1 + 2) + 1;\n func_80128ED8(*(s32 *)(param_1 + 0x20), (s32 *)s0);\n *(s32 *)(param_1 + 0x1C) = 0; /* +0x1C frame counter */\n break;\n }\n case 1:\n break;\n default:\n return;\n }\n\n /* guard clause: the sw of the counter below sits in a branch delay slot,\n * so its statement dominates the if (\u00a7194-M) */\n if (*(s16 *)(s2 + 0x36) != *(s16 *)(param_1 + 0x30)) {\n func_801292C8((u8 *)param_1);\n return;\n }\n\n func_80128ED8(*(s32 *)(param_1 + 0x20), (s32 *)(param_1 + 0x24));\n cnt = *(s32 *)(param_1 + 0x1C) + 1;\n *(s32 *)(param_1 + 0x1C) = cnt;\n /* The reload of +0x20 is written INSIDE BOTH ARMS and, in the true arm,\n * BETWEEN the two halves of the *7<<8 chain. Both placements are\n * load-bearing: putting it last in each arm lets cross_jump merge the\n * common suffix (\u00a7193-C) and loses an instruction; putting it first\n * lets sched1 hoist it to the block top. Splitting the value into its\n * own local `v` (distinct from the counter `cnt`) is what puts the value\n * in $v0 and the pointer in $v1 (\u00a7186c: which allocator owns a pseudo\n * follows from where it is written). */\n if (cnt < 8) {\n v = cnt * 7;\n p = *(s32 *)(param_1 + 0x20);\n v = v << 8;\n *(u16 *)(p + 0x1A) = v;\n *(u16 *)(p + 0x18) = v;\n } else {\n p = *(s32 *)(param_1 + 0x20);\n *(u16 *)(p + 0x1A) = 0x3800;\n *(u16 *)(p + 0x18) = 0x3800;\n }\n func_80129350(param_1, s2);\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x10) = 0;\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) = 0;\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x14) =\n *(u16 *)(*(s32 *)(s2 + 0x20) + 0x12);\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x2C) = 0xC040;\n}\n"} +{"ts": "2026-09-11 03:10:52", "label": "s104_e24", "rung": "E", "calib": {"head": "41a2f9c24", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c", "fn": "func_80185B70", "addr": 2149079920, "aliases": null, "header": false, "includers": 0, "nhash_before": "3aaf812bf8aec6c72bc7d882fb8ad99879915449", "nhash_after": "cae470f8fd845c7a6efc8e9582423d8c4bbeb1c7", "source": ".run/P36/agents/ov_SC06_016__func_80180E24/scratch/sib2_a.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.367, "objects": ["build/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.o"], "before_text": "s32 func_80185B70(s32 a0) {\n s32 s2;\n\n s2 = func_80132EF4(a0, 0x4F);\n if (s2 == 0) {\n return 0;\n }\n\n *(s16 *)(s2 + 0xA) = *(u16 *)(s2 + 0xA) - 0x28;\n\n /* NOTE (this is the whole match, do not \"tidy\" it): each block MUST own its\n * own r/val/base locals. With one shared `r` across all three blocks, the\n * /32 block's remainder pseudo conflicts with the rand()-result pseudo, so\n * global.c's expand_preferences() cannot merge their preferences (it needs\n * a non-conflicting REG_DEAD copy). The result pseudo then has NO hard-reg\n * preference of its own, prune_preferences() puts $v1 into its\n * regs_someone_prefers set, and find_reg's pass 0 skips $v1 and lands the\n * value in $a0 instead of the target's $v1 (4 wrong instructions). */\n {\n s32 r, val, base;\n r = rand() % 28;\n base = *(s16 *)(s2 + 0x6);\n val = (rand() & 1) ? (base + r) : (base - r);\n *(s16 *)(s2 + 0x6) = val;\n }\n {\n s32 r, val, base;\n r = rand() % 32;\n base = *(s16 *)(s2 + 0xA);\n val = (rand() & 1) ? (base + r) : (base - r);\n *(s16 *)(s2 + 0xA) = val;\n }\n {\n s32 r, val, base;\n r = rand() % 28;\n base = *(s16 *)(s2 + 0xE);\n val = (rand() & 1) ? (base + r) : (base - r);\n *(s16 *)(s2 + 0xE) = val;\n }\n\n {\n s32 v0, v1;\n\n if (rand() & 1) {\n v1 = *(s32 *)(s2 + 0x20);\n v0 = -0x2000;\n *(s16 *)(v1 + 0x1C) = v0;\n } else {\n v1 = *(s32 *)(s2 + 0x20);\n v0 = 0x2000;\n *(s16 *)(v1 + 0x1C) = v0;\n }\n *(s16 *)(v1 + 0x1A) = v0;\n do { *(s16 *)(v1 + 0x18) = v0; } while (0);\n }\n\n /* Zero-byte scheduling fence (\u00a7190-C). Without it BOTH sched1 and sched2\n * independently hoist the call's `move $a0,$s3` + `li $a1,0x7F3` above the\n * two trailing `sh` stores (they feed the jal, so they carry the higher\n * INSN_PRIORITY), and reorg then fills the delay slot with `sh 0x18`\n * instead of the target's `addiu $a1`. -fno-schedule-insns{,2} alone does\n * not reproduce the target order -- only both together do, hence a real\n * barrier rather than a statement reorder. */\n ((s32 (*)())func_80185CEC)(a0, 0x7F3);\n return s2;\n}\n", "after_text": "s32 func_80185B70(s32 a0) {\n s32 s2;\n\n s2 = func_80132EF4(a0, 0x4F);\n if (s2 == 0) {\n return 0;\n }\n\n *(s16 *)(s2 + 0xA) = *(u16 *)(s2 + 0xA) - 0x28;\n\n /* NOTE (this is the whole match, do not \"tidy\" it): each block MUST own its\n * own r/val/base locals. With one shared `r` across all three blocks, the\n * /32 block's remainder pseudo conflicts with the rand()-result pseudo, so\n * global.c's expand_preferences() cannot merge their preferences (it needs\n * a non-conflicting REG_DEAD copy). The result pseudo then has NO hard-reg\n * preference of its own, prune_preferences() puts $v1 into its\n * regs_someone_prefers set, and find_reg's pass 0 skips $v1 and lands the\n * value in $a0 instead of the target's $v1 (4 wrong instructions). */\n {\n s32 r, val, base;\n r = rand() % 28;\n base = *(s16 *)(s2 + 0x6);\n val = (rand() & 1) ? (base + r) : (base - r);\n *(s16 *)(s2 + 0x6) = val;\n }\n {\n s32 r, val, base;\n r = rand() % 32;\n base = *(s16 *)(s2 + 0xA);\n val = (rand() & 1) ? (base + r) : (base - r);\n *(s16 *)(s2 + 0xA) = val;\n }\n {\n s32 r, val, base;\n r = rand() % 28;\n base = *(s16 *)(s2 + 0xE);\n val = (rand() & 1) ? (base + r) : (base - r);\n *(s16 *)(s2 + 0xE) = val;\n }\n\n {\n s32 v0, v1;\n\n if (rand() & 1) {\n v1 = *(s32 *)(s2 + 0x20);\n v0 = -0x2000;\n *(s16 *)(v1 + 0x1C) = v0;\n *(s16 *)(v1 + 0x1A) = v0;\n *(s16 *)(v1 + 0x18) = v0;\n } else {\n v1 = *(s32 *)(s2 + 0x20);\n v0 = 0x2000;\n *(s16 *)(v1 + 0x1C) = v0;\n *(s16 *)(v1 + 0x1A) = v0;\n *(s16 *)(v1 + 0x18) = v0;\n }\n }\n\n /* Zero-byte scheduling fence (\u00a7190-C). Without it BOTH sched1 and sched2\n * independently hoist the call's `move $a0,$s3` + `li $a1,0x7F3` above the\n * two trailing `sh` stores (they feed the jal, so they carry the higher\n * INSN_PRIORITY), and reorg then fills the delay slot with `sh 0x18`\n * instead of the target's `addiu $a1`. -fno-schedule-insns{,2} alone does\n * not reproduce the target order -- only both together do, hence a real\n * barrier rather than a statement reorder. */\n ((s32 (*)())func_80185CEC)(a0, 0x7F3);\n return s2;\n}\n"} diff --git a/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c b/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c index f793487129..40cd6add37 100644 --- a/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c +++ b/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c @@ -9275,13 +9275,15 @@ s32 func_80185B70(s32 a0) { v1 = *(s32 *)(s2 + 0x20); v0 = -0x2000; *(s16 *)(v1 + 0x1C) = v0; + *(s16 *)(v1 + 0x1A) = v0; + *(s16 *)(v1 + 0x18) = v0; } else { v1 = *(s32 *)(s2 + 0x20); v0 = 0x2000; *(s16 *)(v1 + 0x1C) = v0; + *(s16 *)(v1 + 0x1A) = v0; + *(s16 *)(v1 + 0x18) = v0; } - *(s16 *)(v1 + 0x1A) = v0; - do { *(s16 *)(v1 + 0x18) = v0; } while (0); } /* Zero-byte scheduling fence (ยง190-C). Without it BOTH sched1 and sched2