From 0a272b4ce4e10ee011a40f3ce4b41eb3843ce60c Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 11 Sep 2026 04:51:43 -0600 Subject: [PATCH] =?UTF-8?q?phase-36:=20S104=20s104=5Fe32=20=E2=80=94=20fun?= =?UTF-8?q?c=5F80184CA8=20banked=20at=200=20through=20the=20whole-object?= =?UTF-8?q?=20gate=20+=20propagated=20=E2=80=94=20e32=20sibling,=20the=20s?= =?UTF-8?q?ame=20cast?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .run/P36/delever/calibration.json | 348 +++++++++++----------- .run/P36/delever/ledger.jsonl | 1 + src/ov_SC03_105/ov_SC03_105_jr_80181C84.c | 18 +- 3 files changed, 181 insertions(+), 186 deletions(-) diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index e27dfe6fb..81e813fd9 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,5 +1,5 @@ { - "head": "35076c26a", + "head": "b6b1bbc1d", "stamp": "15956e4a96c4", "generated": "2026-09-11 04:51", "aliases": [ @@ -21,206 +21,206 @@ "main": { "objects": 85, "identical": 85, - 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As `<= 0 ? 4 : 3` the\n * shape is right but the result takes $v1; only the if/else lets it reuse the\n * dead compare's $v0. Polarity matters too: the DEFAULT (delay-slot) value is 3. */\n if (*(s16 *)(b58 + 6) <= 0) {\n *(u16 *)(s1 + 0x34) = 4;\n } else {\n *(u16 *)(s1 + 0x34) = 3;\n }\n func_8002D4C8(0xC2D, 0);\n }\n break;\n case 3:\n *(u16 *)(s1 + 0x102) = *(u16 *)(s1 + 0x102) + 0x20;\n if ((s16)*(u16 *)(s1 + 0x102) > 0x200) {\n *(u16 *)(s1 + 0x102) = 0x200;\n func_8013C9C4(D_8018AAA4);\n *(u16 *)(s1 + 0x34) = 5;\n *(s32 *)(s1 + 0x1C) = 0x40;\n func_8002D4C8(0xC06, 0);\n n = D_8018E88C[D_801BCBBC];\n for (i = 0; i < n; i++) {\n p = ((s32 (*)(void *, s16, s32))func_80183D38)((void *)s1, 0, 0);\n if (p != 0) {\n r = rand();\n q = 0x1C0 / n;\n /* LOAD-BEARING: load 0x6 BEFORE storing 0xA (they may alias, so gcc will\n * not hoist it afterwards), fold the +-0x40 into t6, and write the sum\n * back THROUGH t6 so it keeps t6's register instead of taking a new one. */\n tA = *(u16 *)(p + 0xA) - 0xE0;\n t6 = *(u16 *)(p + 0x6) + 0x40;\n *(u16 *)(p + 0xA) = tA;\n t6 = t6 + (i * q + r % q);\n *(u16 *)(p + 0x6) = t6;\n }\n }\n }\n break;\n case 4:\n *(u16 *)(s1 + 0x102) = *(u16 *)(s1 + 0x102) - 0x20;\n if ((s16)*(u16 *)(s1 + 0x102) < -0x200) {\n *(s16 *)(s1 + 0x102) = -0x200;\n func_8013C9C4(D_8018AAA4);\n *(u16 *)(s1 + 0x34) = 6;\n *(s32 *)(s1 + 0x1C) = 0x40;\n func_8002D4C8(0xC06, 0);\n n = D_8018E88C[D_801BCBBC];\n for (i = 0; i < n; i++) {\n p = ((s32 (*)(void *, s16, s32))func_80183D38)((void *)s1, 0, 0);\n if (p != 0) {\n r = rand();\n q = 0x1C0 / n;\n /* LOAD-BEARING: load 0x6 BEFORE storing 0xA (they may alias, so gcc will\n * not hoist it afterwards), fold the +-0x40 into t6, and write the sum\n * back THROUGH t6 so it keeps t6's register instead of taking a new one. */\n tA = *(u16 *)(p + 0xA) - 0xE0;\n t6 = *(u16 *)(p + 0x6) - 0x40;\n *(u16 *)(p + 0xA) = tA;\n t6 = t6 - (i * q + r % q);\n *(u16 *)(p + 0x6) = t6;\n }\n }\n }\n break;\n case 5:\n case 6:\n if (func_8012BEE8(s1) != 0) {\n *(u16 *)(s1 + 0x34) = *(u16 *)(s1 + 0x34) + 2;\n }\n break;\n case 7:\n *(u16 *)(s1 + 0x102) = *(u16 *)(s1 + 0x102) - 0x20;\n if ((s16)*(u16 *)(s1 + 0x102) < 0) {\n goto lShared;\n }\n break;\n case 8:\n *(u16 *)(s1 + 0x102) = *(u16 *)(s1 + 0x102) + 0x20;\n if ((s16)*(u16 *)(s1 + 0x102) <= 0) {\n break;\n }\n lShared:\n /* LOAD-BEARING: a SEPARATE temp from case 0's t34 (sharing one kills case 0's coalesce),\n * and the 0x34 load must HEAD the block -- it is a branch target, so reorg cannot\n * speculate a load into case 8's blez delay slot, which is why the target has a nop. */\n t34b = *(u16 *)(s1 + 0x34) + 1;\n *(s32 *)(s1 + 0x1C) = 0x10;\n *(u16 *)(s1 + 0x102) = 0;\n *(s32 *)(s1 + 0xE0) = *(s32 *)(s1 + 0xE0) | 0x10;\n *(u16 *)(s1 + 0x34) = t34b;\n break;\n case 9:\n case 10:\n if (func_8012BEE8(s1) != 0) {\n func_801843DC(s1);\n *(s32 *)(s1 + 0x1C) = 0x10;\n *(u16 *)(s1 + 0x34) = *(u16 *)(s1 + 0x34) + 1;\n }\n break;\n case 11:\n if (func_8012BEE8(s1) == 0) {\n return;\n }\n func_80183F0C((void *)s1);\n *(s32 *)(s1 + 0x4) = 0xFFF80000;\n *(s32 *)(s1 + 0x8) = 0xFE5E0000;\n *(s32 *)(s1 + 0xC) = 0xFE380000;\n *(s32 *)(s1 + 0x58) = ((s32)D_8018E288 | 0x40000000) | 0x20000000;\n return;\n }\n func_80183DA0(s1);\n func_801834A4(s1);\n func_801839A4(s1, 0x30);\n if (func_8018233C(s1) == 1) {\n func_801843DC(s1);\n *(s32 *)(s1 + 0xE0) = *(s32 *)(s1 + 0xE0) | 0x10;\n }\n}\n", "after_text": "void func_80181C84(s32 a0)\n{\n /* LOAD-BEARING (P36 S104 e32, replacing the $s2/$v1 pins): case 7 and case 8 each carry their\n * OWN copy of the 0x34/0x1C/0x102/0xE0 tail (no shared label) -- the extra references raise the\n * entity's allocno_compare priority above `i` (global.c:594-607), so the entity takes $s1 and `i`\n * $s2; post-reload cross-jump (jump.c:2371) re-merges the two tails, so the bytes keep one copy.\n * `q` is declared inside each `if (p != 0)` block: a q shared by the two div loops is a global\n * allocno that conflicts with the unused-remainder pseudo of `0x1C0 / n` in $v1; a per-block q is\n * local and takes $v1 itself. */\n s32 s1;\n Local_80181C84 local;\n u8 *b58;\n u16 tE;\n u16 t34;\n u16 t34b;\n s32 i;\n s32 n;\n s32 r;\n s32 p;\n s32 tA;\n s32 t6;\n\n s1 = a0;\n /* LOAD-BEARING: `u8 *` base + *(s16 *)(b58 + 6), the TU:5099/7196 idiom -- this is what\n * parks &D_80126B58 in $s0 across the whole switch (prologue la, two `lh 0x6($s0)`). */\n b58 = (u8 *)&D_80126B58;\n\n switch (*(u16 *)(s1 + 0x34)) {\n case 0:\n *(s32 *)(s1 + 0x1C) = 0x40;\n /* LOAD-BEARING: read 0x34 into a temp BEFORE the 0xE0 read-modify-write, store it after.\n * Written inline, the lhu sinks below the lw and the +1 lands in the wrong register. */\n t34 = *(u16 *)(s1 + 0x34) + 1;\n *(s32 *)(s1 + 0xE0) = *(s32 *)(s1 + 0xE0) & ~0x10;\n *(u16 *)(s1 + 0x34) = t34;\n case 1:\n if (func_8012BEE8(s1) == 0) {\n return;\n }\n *(s16 *)(s1 + 0xA) = -0x102;\n *(s16 *)(s1 + 0xE) = -0x1C8;\n *(s32 *)(s1 + 0x1C) = 0x20;\n *(u16 *)(s1 + 0x6) = 0;\n *(s32 *)(s1 + 0x58) = ((s32)D_8018E2B8 | 0x40000000) | 0x20000000;\n *(u16 *)(s1 + 0x34) = *(u16 *)(s1 + 0x34) + 1;\n func_80184604(*(s16 *)(b58 + 6) > 0 ? 4 : 6);\n local.f0 = *(u16 *)(s1 + 0x6);\n local.f1 = *(u16 *)(s1 + 0xA);\n tE = *(u16 *)(s1 + 0xE);\n local.f3 = 0x170;\n local.f4 = 0x8000;\n local.f5 = 0;\n local.f6 = 0x7FFF;\n local.f7 = 0x80;\n local.f2 = tE;\n i = 0;\n do {\n local.f8 = i << 10;\n func_8012C51C(&local, s1);\n i++;\n } while (i < 4);\n break;\n case 2:\n if (func_8012BEE8(s1) != 0) {\n func_8018364C((void *)s1);\n /* LOAD-BEARING: the duplicated store (\u00a7224), not a ternary. As `<= 0 ? 4 : 3` the\n * shape is right but the result takes $v1; only the if/else lets it reuse the\n * dead compare's $v0. Polarity matters too: the DEFAULT (delay-slot) value is 3. */\n if (*(s16 *)(b58 + 6) <= 0) {\n *(u16 *)(s1 + 0x34) = 4;\n } else {\n *(u16 *)(s1 + 0x34) = 3;\n }\n func_8002D4C8(0xC2D, 0);\n }\n break;\n case 3:\n *(u16 *)(s1 + 0x102) = *(u16 *)(s1 + 0x102) + 0x20;\n if ((s16)*(u16 *)(s1 + 0x102) > 0x200) {\n *(u16 *)(s1 + 0x102) = 0x200;\n func_8013C9C4(D_8018AAA4);\n *(u16 *)(s1 + 0x34) = 5;\n *(s32 *)(s1 + 0x1C) = 0x40;\n func_8002D4C8(0xC06, 0);\n n = D_8018E88C[D_801BCBBC];\n for (i = 0; i < n; i++) {\n p = ((s32 (*)(void *, s16, s32))func_80183D38)((void *)s1, 0, 0);\n if (p != 0) {\n s32 q;\n r = rand();\n q = 0x1C0 / n;\n /* LOAD-BEARING: load 0x6 BEFORE storing 0xA (they may alias, so gcc will\n * not hoist it afterwards), fold the +-0x40 into t6, and write the sum\n * back THROUGH t6 so it keeps t6's register instead of taking a new one. */\n tA = *(u16 *)(p + 0xA) - 0xE0;\n t6 = *(u16 *)(p + 0x6) + 0x40;\n *(u16 *)(p + 0xA) = tA;\n t6 = t6 + (i * q + r % q);\n *(u16 *)(p + 0x6) = t6;\n }\n }\n }\n break;\n case 4:\n *(u16 *)(s1 + 0x102) = *(u16 *)(s1 + 0x102) - 0x20;\n if ((s16)*(u16 *)(s1 + 0x102) < -0x200) {\n *(s16 *)(s1 + 0x102) = -0x200;\n func_8013C9C4(D_8018AAA4);\n *(u16 *)(s1 + 0x34) = 6;\n *(s32 *)(s1 + 0x1C) = 0x40;\n func_8002D4C8(0xC06, 0);\n n = D_8018E88C[D_801BCBBC];\n for (i = 0; i < n; i++) {\n p = ((s32 (*)(void *, s16, s32))func_80183D38)((void *)s1, 0, 0);\n if (p != 0) {\n s32 q;\n r = rand();\n q = 0x1C0 / n;\n /* LOAD-BEARING: load 0x6 BEFORE storing 0xA (they may alias, so gcc will\n * not hoist it afterwards), fold the +-0x40 into t6, and write the sum\n * back THROUGH t6 so it keeps t6's register instead of taking a new one. */\n tA = *(u16 *)(p + 0xA) - 0xE0;\n t6 = *(u16 *)(p + 0x6) - 0x40;\n *(u16 *)(p + 0xA) = tA;\n t6 = t6 - (i * q + r % q);\n *(u16 *)(p + 0x6) = t6;\n }\n }\n }\n break;\n case 5:\n case 6:\n if (func_8012BEE8(s1) != 0) {\n *(u16 *)(s1 + 0x34) = *(u16 *)(s1 + 0x34) + 2;\n }\n break;\n case 7:\n *(u16 *)(s1 + 0x102) = *(u16 *)(s1 + 0x102) - 0x20;\n if ((s16)*(u16 *)(s1 + 0x102) < 0) {\n t34b = *(u16 *)(s1 + 0x34) + 1;\n *(s32 *)(s1 + 0x1C) = 0x10;\n *(u16 *)(s1 + 0x102) = 0;\n *(s32 *)(s1 + 0xE0) = *(s32 *)(s1 + 0xE0) | 0x10;\n *(u16 *)(s1 + 0x34) = t34b;\n }\n break;\n case 8:\n *(u16 *)(s1 + 0x102) = *(u16 *)(s1 + 0x102) + 0x20;\n if ((s16)*(u16 *)(s1 + 0x102) > 0) {\n t34b = *(u16 *)(s1 + 0x34) + 1;\n *(s32 *)(s1 + 0x1C) = 0x10;\n *(u16 *)(s1 + 0x102) = 0;\n *(s32 *)(s1 + 0xE0) = *(s32 *)(s1 + 0xE0) | 0x10;\n *(u16 *)(s1 + 0x34) = t34b;\n }\n break;\n case 9:\n case 10:\n if (func_8012BEE8(s1) != 0) {\n func_801843DC(s1);\n *(s32 *)(s1 + 0x1C) = 0x10;\n *(u16 *)(s1 + 0x34) = *(u16 *)(s1 + 0x34) + 1;\n }\n break;\n case 11:\n if (func_8012BEE8(s1) == 0) {\n return;\n }\n func_80183F0C((void *)s1);\n *(s32 *)(s1 + 0x4) = 0xFFF80000;\n *(s32 *)(s1 + 0x8) = 0xFE5E0000;\n *(s32 *)(s1 + 0xC) = 0xFE380000;\n *(s32 *)(s1 + 0x58) = ((s32)D_8018E288 | 0x40000000) | 0x20000000;\n return;\n }\n func_80183DA0(s1);\n func_801834A4(s1);\n func_801839A4(s1, 0x30);\n if (func_8018233C(s1) == 1) {\n func_801843DC(s1);\n *(s32 *)(s1 + 0xE0) = *(s32 *)(s1 + 0xE0) | 0x10;\n }\n}\n"} {"ts": "2026-09-11 04:51:08", "label": "s104_e32", "rung": "E", "calib": {"head": "ae63eded3", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_105/ov_SC03_105_jr_80181C84.c", "fn": "func_80183DA0", "addr": 2149072288, "aliases": null, "header": false, "includers": 0, "nhash_before": "abe28a8a2560e366822a77bc8239d3aaa36454f5", "nhash_after": "232532d954dab04338179cb15b00264a2bb1c158", "source": ".run/P36/agents/ov_SC03_105__func_80183DA0/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.108, "objects": ["build/src/ov_SC03_105/ov_SC03_105_jr_80181C84.o"], "before_text": "void func_80183DA0(s32 a0) {\n SVec_80183DA0 pos;\n SVec_80183DA0 out;\n s32 val;\n register s32 lvl __asm__(\"$17\"); // !FAKE: pin $17 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n s32 sv;\n s32 n;\n s32 t;\n s32 r;\n\n val = 0x7F;\n pos.vx = *(s16 *)(a0 + 0x6);\n pos.vy = *(s16 *)(a0 + 0xA);\n pos.vz = *(s16 *)(a0 + 0xE);\n ((void (*)(void *, void *))func_8012EFB8)(&pos, &out);\n lvl = 7;\n\n if (out.vx >= 0) {\n if (out.vx >= 0x140) {\n val = 0;\n goto tail;\n }\n } else {\n if (-out.vx >= 0x140) {\n goto zero;\n }\n }\n\n sv = (s16)val;\n if (out.vx >= 0) {\n val = sv - out.vx * 0x7F / 0x140;\n } else {\n val = sv - -out.vx * 0x7F / 0x140;\n }\n goto tail;\n\nzero:\n val = 0;\n\ntail:\n t = out.vx;\n n = lvl + t / 0x14;\n lvl = n;\n __asm__ __volatile__(\"\" : \"=r\"(n) : \"0\"(n)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus10)\n if ((s16)n < 0) {\n lvl = 0;\n } else if ((s16)n >= 0x10) {\n lvl = 0xF;\n }\n r = (lvl << 8) | 0x3000;\n func_8002D4C8(0x730, (val | r) & 0xFFFF);\n}\n", "after_text": "void func_80183DA0(s32 a0) {\n SVec_80183DA0 pos;\n SVec_80183DA0 out;\n s32 val;\n s32 sv;\n s16 lvl;\n\n val = 0x7F;\n lvl = 7;\n pos.vx = *(s16 *)(a0 + 0x6);\n pos.vy = *(s16 *)(a0 + 0xA);\n pos.vz = *(s16 *)(a0 + 0xE);\n ((void (*)(void *, void *))func_8012EFB8)(&pos, &out);\n\n if (out.vx >= 0 ? out.vx < 0x140 : -out.vx < 0x140) {\n sv = (s16)val;\n if (out.vx >= 0) {\n val = sv - out.vx * 0x7F / 0x140;\n } else {\n val = sv - -out.vx * 0x7F / 0x140;\n }\n } else {\n val = 0;\n }\n\n lvl += out.vx / 0x14;\n if (lvl < 0) {\n lvl = 0;\n } else if (lvl >= 0x10) {\n lvl = 0xF;\n }\n func_8002D4C8(0x730, (u16)(val | ((lvl << 8) | 0x3000)));\n}\n"} {"ts": "2026-09-11 04:51:25", "label": "s104_e32", "rung": "E", "calib": {"head": "35076c26a", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_105/ov_SC03_105_jr_80181C84.c", "fn": "func_8018574C", "addr": 2149078860, "aliases": null, "header": false, "includers": 0, "nhash_before": "4db6fe851a3b449c868a5295e883f701891ebe4e", "nhash_after": "9206465ff43e249c29f032e5e86a0c44c90a7def", "source": ".run/P36/agents/ov_SC03_105__func_8018574C/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.104, "objects": ["build/src/ov_SC03_105/ov_SC03_105_jr_80181C84.o"], "before_text": "void func_8018574C(void *a0) {\n register s32 s0 __asm__(\"$16\") = (s32)a0; // !FAKE: pin $16 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n s32 rnd;\n s32 t;\n s32 base;\n s32 rem;\n s32 result;\n s16 tmp[3];\n u8 aux[8];\n\n rnd = rand();\n t = *(s16 *)(s0 + 0xC);\n base = *(s16 *)(s0 + 0x14);\n __asm__(\"\" : \"=r\"(t) : \"0\"(t), \"r\"(base)); // !FAKE: launder \u2014 REFUSED launder with 2 inputs (P36 rung B tus10)\n rem = rnd % (t >> 7);\n if (rand() & 1) {\n result = base + rem;\n } else {\n result = base - rem;\n }\n tmp[0] = result;\n tmp[1] = *(u16 *)(s0 + 0x16) + *(u16 *)(s0 + 0x1E);\n tmp[2] = *(u16 *)(s0 + 0x18);\n func_8012F214(*(s32 *)(s0 + 0x20), (s32)tmp, (s32)aux);\n func_8017E5C8((s32)aux);\n}\n", "after_text": "void func_8018574C(void *a0) {\n s32 s0 = (s32)a0;\n s32 rnd;\n s32 t;\n s32 base;\n s32 rem;\n s32 result;\n s16 tmp[3];\n u8 aux[8];\n\n rnd = rand();\n t = *(s16 *)(s0 + 0xC);\n base = *(s16 *)(s0 + 0x14);\n /* `(s16)t >> 7` (P36 S104 e32): the cast at the shift keeps the target's lh + sra,7;\n `t >> 7` lets combine fold the load's sign extension into lhu + sll,16 + sra,23. */\n rem = rnd % ((s16)t >> 7);\n if (rand() & 1) {\n result = base + rem;\n } else {\n result = base - rem;\n }\n tmp[0] = result;\n tmp[1] = *(u16 *)(s0 + 0x16) + *(u16 *)(s0 + 0x1E);\n tmp[2] = *(u16 *)(s0 + 0x18);\n func_8012F214(*(s32 *)(s0 + 0x20), (s32)tmp, (s32)aux);\n func_8017E5C8((s32)aux);\n}\n"} +{"ts": "2026-09-11 04:51:42", "label": "s104_e32", "rung": "E", "calib": {"head": "b6b1bbc1d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_105/ov_SC03_105_jr_80181C84.c", "fn": "func_80184CA8", "addr": 2149076136, "aliases": null, "header": false, "includers": 0, "nhash_before": "c2965c1a2bf1830f587a072222355bb1b4f29546", "nhash_after": "26871f5045e56d49361d410849fa3b64894fb7c5", "source": ".run/P36/agents/ov_SC03_105__func_8018574C/scratch/cca8_final.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.105, "objects": ["build/src/ov_SC03_105/ov_SC03_105_jr_80181C84.o"], "before_text": "void func_80184CA8(s32 a0) {\n s32 v0;\n s16 *s1;\n s32 s3;\n u16 flag;\n s32 counter;\n /* K&R house style: all locals at the top. gcc-2.7.2 assigns stack slots in\n DECLARATION order (cookbook item 6), so buf[8] must be declared BEFORE\n tmp[4] to land at sp+0x10 with tmp at sp+0x20 -- even though tmp's arm\n runs first at runtime. */\n s16 buf[8];\n s16 tmp[4];\n s32 t;\n s16 u;\n s32 rnd;\n s32 base;\n s32 rem;\n s32 result;\n\n s3 = a0 + 0x20; /* $s3 = a0 + 0x20 */\n v0 = *(s32 *)(a0 + 0x54);\n s1 = *(s16 **)(a0 + 0x50);\n if (v0 == 0) { /* target: bnez v0 SKIPS the call */\n v0 = func_80185628(a0 + 0x34, (s32)s1);\n *(s16 *)(a0 + 0x28) = v0;\n }\n\n flag = *(u16 *)(a0 + 2);\n *(s16 *)(a0 + 0x34) = s1[0];\n *(s16 *)(a0 + 0x36) = s1[1];\n *(s16 *)(a0 + 0x38) = s1[2];\n\n /* flag != 0 first: writing the arms the other way round flips which side\n falls through and corrupts every branch downstream. */\n if (flag != 0) {\n counter = *(s32 *)(a0 + 0x1C);\n if (counter != 0) {\n *(s32 *)(a0 + 0x1C) = counter - 1;\n } else {\n v0 = func_80185680((void *)s3, (void *)(a0 + 0x48));\n if (v0 == 1) {\n rnd = rand();\n t = *(s16 *)(a0 + 0x2C);\n base = *(s16 *)(a0 + 0x34);\n /* Two levers in ONE zero-byte asm.\n (1) combine expands sign_extend(lh) into ashift/ashiftrt and\n merges it with the outer >>7, so the natural spelling\n always emits lhu+sll,16+sra,23 (3 ins). The re-tie breaks\n the i2->i3 chain, leaving the target's lh + sra,7 (2 ins).\n (2) naming `base` as an extra INPUT makes the 0x34 load a\n predecessor of the fence, so sched1 must place it before\n the fence -- i.e. into the lh 0x2C load-delay slot, which\n is exactly where the target has `lh $s1,0x34($s0)`.\n Without it that slot is a nop and the function is 116 ins. */\n __asm__(\"\" : \"=r\"(t) : \"0\"(t), \"r\"(base)); // !FAKE: launder \u2014 REFUSED launder with 2 inputs (P36 rung B tus10)\n rem = rnd % (t >> 7);\n if (rand() & 1) {\n result = base + rem;\n } else {\n result = base - rem;\n }\n tmp[0] = result; /* sp+0x20 */\n tmp[1] = *(u16 *)(s3 + 0x16) + *(u16 *)(s3 + 0x1E); /* sp+0x22 */\n tmp[2] = *(u16 *)(s3 + 0x18); /* sp+0x24 */\n func_8017E5C8((s32)tmp);\n func_80185218((void *)a0);\n } else {\n /* `u` MUST be declared s16, not s32 (width dial, cookbook\n \u00a7194-B): the 16-bit local keeps the shift result in $v0 and\n sends the negation to $v1; an s32 local swaps the pair. */\n u = (s16)(*(u16 *)(a0 + 0x2C)) >> 9;\n buf[2] = -u; /* sp+0x14 */\n buf[3] = u; /* sp+0x16 */\n u = (s16)(*(u16 *)(a0 + 0x2E)) >> 9;\n buf[4] = -u; /* sp+0x18 */\n buf[5] = u; /* sp+0x1A */\n u = (s16)(*(u16 *)(a0 + 0x30)) >> 9;\n buf[6] = -u; /* sp+0x1C */\n buf[7] = u; /* sp+0x1E */\n func_80185380(a0, (s32)&buf[0], 0x30); /* a1 = sp+0x10 */\n func_80185810(s3);\n }\n }\n } else {\n *(s16 *)(a0 + 2) = flag + 1;\n *(s32 *)(a0 + 0x1C) = rand() % 4;\n }\n}\n", "after_text": "void func_80184CA8(s32 a0) {\n s32 v0;\n s16 *s1;\n s32 s3;\n u16 flag;\n s32 counter;\n /* K&R house style: all locals at the top. gcc-2.7.2 assigns stack slots in\n DECLARATION order (cookbook item 6), so buf[8] must be declared BEFORE\n tmp[4] to land at sp+0x10 with tmp at sp+0x20 -- even though tmp's arm\n runs first at runtime. */\n s16 buf[8];\n s16 tmp[4];\n s32 t;\n s16 u;\n s32 rnd;\n s32 base;\n s32 rem;\n s32 result;\n\n s3 = a0 + 0x20; /* $s3 = a0 + 0x20 */\n v0 = *(s32 *)(a0 + 0x54);\n s1 = *(s16 **)(a0 + 0x50);\n if (v0 == 0) { /* target: bnez v0 SKIPS the call */\n v0 = func_80185628(a0 + 0x34, (s32)s1);\n *(s16 *)(a0 + 0x28) = v0;\n }\n\n flag = *(u16 *)(a0 + 2);\n *(s16 *)(a0 + 0x34) = s1[0];\n *(s16 *)(a0 + 0x36) = s1[1];\n *(s16 *)(a0 + 0x38) = s1[2];\n\n /* flag != 0 first: writing the arms the other way round flips which side\n falls through and corrupts every branch downstream. */\n if (flag != 0) {\n counter = *(s32 *)(a0 + 0x1C);\n if (counter != 0) {\n *(s32 *)(a0 + 0x1C) = counter - 1;\n } else {\n v0 = func_80185680((void *)s3, (void *)(a0 + 0x48));\n if (v0 == 1) {\n rnd = rand();\n t = *(s16 *)(a0 + 0x2C);\n base = *(s16 *)(a0 + 0x34);\n /* `(s16)t >> 7`, not `t >> 7` (P36 S104 e32, replacing a 2-input launder):\n with the cast at the shift, c-typeck's short_shift re-extends the value and\n cse folds that pair into the `lh`, leaving the target's lh + sra,7; written\n `t >> 7`, combine merges the load's sign extension with the shift into\n lhu + sll,16 + sra,23. The 0x34 load then fills the lh delay slot by itself. */\n rem = rnd % ((s16)t >> 7);\n if (rand() & 1) {\n result = base + rem;\n } else {\n result = base - rem;\n }\n tmp[0] = result; /* sp+0x20 */\n tmp[1] = *(u16 *)(s3 + 0x16) + *(u16 *)(s3 + 0x1E); /* sp+0x22 */\n tmp[2] = *(u16 *)(s3 + 0x18); /* sp+0x24 */\n func_8017E5C8((s32)tmp);\n func_80185218((void *)a0);\n } else {\n /* `u` MUST be declared s16, not s32 (width dial, cookbook\n \u00a7194-B): the 16-bit local keeps the shift result in $v0 and\n sends the negation to $v1; an s32 local swaps the pair. */\n u = (s16)(*(u16 *)(a0 + 0x2C)) >> 9;\n buf[2] = -u; /* sp+0x14 */\n buf[3] = u; /* sp+0x16 */\n u = (s16)(*(u16 *)(a0 + 0x2E)) >> 9;\n buf[4] = -u; /* sp+0x18 */\n buf[5] = u; /* sp+0x1A */\n u = (s16)(*(u16 *)(a0 + 0x30)) >> 9;\n buf[6] = -u; /* sp+0x1C */\n buf[7] = u; /* sp+0x1E */\n func_80185380(a0, (s32)&buf[0], 0x30); /* a1 = sp+0x10 */\n func_80185810(s3);\n }\n }\n } else {\n *(s16 *)(a0 + 2) = flag + 1;\n *(s32 *)(a0 + 0x1C) = rand() % 4;\n }\n}\n"} diff --git a/src/ov_SC03_105/ov_SC03_105_jr_80181C84.c b/src/ov_SC03_105/ov_SC03_105_jr_80181C84.c index e50831373..4533c520d 100644 --- a/src/ov_SC03_105/ov_SC03_105_jr_80181C84.c +++ b/src/ov_SC03_105/ov_SC03_105_jr_80181C84.c @@ -4852,18 +4852,12 @@ void func_80184CA8(s32 a0) { rnd = rand(); t = *(s16 *)(a0 + 0x2C); base = *(s16 *)(a0 + 0x34); - /* Two levers in ONE zero-byte asm. - (1) combine expands sign_extend(lh) into ashift/ashiftrt and - merges it with the outer >>7, so the natural spelling - always emits lhu+sll,16+sra,23 (3 ins). The re-tie breaks - the i2->i3 chain, leaving the target's lh + sra,7 (2 ins). - (2) naming `base` as an extra INPUT makes the 0x34 load a - predecessor of the fence, so sched1 must place it before - the fence -- i.e. into the lh 0x2C load-delay slot, which - is exactly where the target has `lh $s1,0x34($s0)`. - Without it that slot is a nop and the function is 116 ins. */ - __asm__("" : "=r"(t) : "0"(t), "r"(base)); // !FAKE: launder — REFUSED launder with 2 inputs (P36 rung B tus10) - rem = rnd % (t >> 7); + /* `(s16)t >> 7`, not `t >> 7` (P36 S104 e32, replacing a 2-input launder): + with the cast at the shift, c-typeck's short_shift re-extends the value and + cse folds that pair into the `lh`, leaving the target's lh + sra,7; written + `t >> 7`, combine merges the load's sign extension with the shift into + lhu + sll,16 + sra,23. The 0x34 load then fills the lh delay slot by itself. */ + rem = rnd % ((s16)t >> 7); if (rand() & 1) { result = base + rem; } else {