From 0c9a78bc8ebb653f683b6060238045207b7712bd Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 2 Oct 2026 18:35:00 -0600 Subject: [PATCH] T7.1.c3: gte_consolidate batch c3b2: 395 files consolidated, oracle IDENTICAL --- .run/P36/delever/calibration.json | 304 ++++++++--------- .run/P36/delever/ledger.jsonl | 395 ++++++++++++++++++++++ .run/P36/gte/canonical.json | 216 ++++++------ src/md_MAIN_019/md_MAIN_019.c | 30 +- src/ov_MAIN_012/ov_MAIN_012_jr_80131340.c | 9 +- src/ov_SC01_000/ov_SC01_000_jr_8012ACE0.c | 9 +- src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c | 7 - src/ov_SC01_001/ov_SC01_001_jr_8012ACE0.c | 9 +- src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c | 7 - src/ov_SC01_004/ov_SC01_004_jr_8012ACE0.c | 9 +- src/ov_SC01_005/ov_SC01_005_jr_8012ACE0.c | 9 +- src/ov_SC01_008/ov_SC01_008_jr_8012ACE0.c | 9 +- src/ov_SC01_009/ov_SC01_009_jr_8012ACE0.c | 9 +- src/ov_SC01_074/ov_SC01_074_jr_8012ACE0.c | 9 +- src/ov_SC01_077/ov_SC01_077_jr_8012ACE0.c | 9 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src/ov_SC05_017/ov_SC05_017_jr_801380E0.c | 7 +- src/ov_SC05_017/ov_SC05_017_jr_8013C98C.c | 4 +- src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.c | 7 - src/ov_SC05_018/ov_SC05_018_jr_8012ACE0.c | 9 +- src/ov_SC05_018/ov_SC05_018_jr_801380E0.c | 7 +- src/ov_SC05_018/ov_SC05_018_jr_8013C98C.c | 4 +- src/ov_SC05_019/ov_SC05_019_jr_801380E0.c | 5 - src/ov_SC05_019/ov_SC05_019_jr_8017D5C0.c | 7 - src/ov_SC06_000/ov_SC06_000_jr_8012ACE0.c | 9 +- src/ov_SC06_000/ov_SC06_000_jr_801380E0.c | 7 +- src/ov_SC06_000/ov_SC06_000_jr_8013C98C.c | 4 +- src/ov_SC06_006/ov_SC06_006_jr_8012ACE0.c | 9 +- src/ov_SC06_006/ov_SC06_006_jr_801380E0.c | 7 +- src/ov_SC06_006/ov_SC06_006_jr_8013C98C.c | 4 +- src/ov_SC06_006/ov_SC06_006_jr_8017BEBC.c | 7 - src/ov_SC06_008/ov_SC06_008_jr_8012ACE0.c | 9 +- src/ov_SC06_008/ov_SC06_008_jr_801380E0.c | 7 +- src/ov_SC06_008/ov_SC06_008_jr_8013C98C.c | 4 +- src/ov_SC06_008/ov_SC06_008_jr_8017C294.c | 12 - src/ov_SC06_010/ov_SC06_010_jr_8012ACE0.c | 9 +- src/ov_SC06_010/ov_SC06_010_jr_801380E0.c | 7 +- src/ov_SC06_010/ov_SC06_010_jr_8013C98C.c | 4 +- src/ov_SC06_011/ov_SC06_011_jr_8012ACE0.c | 9 +- src/ov_SC06_011/ov_SC06_011_jr_801380E0.c | 7 +- src/ov_SC06_011/ov_SC06_011_jr_8013C98C.c | 4 +- src/ov_SC06_011/ov_SC06_011_jr_8017BEBC.c | 7 - src/ov_SC06_013/ov_SC06_013_jr_8012ACE0.c | 9 +- src/ov_SC06_013/ov_SC06_013_jr_801380E0.c | 7 +- src/ov_SC06_013/ov_SC06_013_jr_8013C98C.c | 4 +- src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c | 7 - src/ov_SC06_014/ov_SC06_014_jr_8012ACE0.c | 9 +- src/ov_SC06_014/ov_SC06_014_jr_801380E0.c | 7 +- src/ov_SC06_014/ov_SC06_014_jr_8013C98C.c | 4 +- src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c | 7 - src/ov_SC06_015/ov_SC06_015_jr_8012ACE0.c | 9 +- src/ov_SC06_015/ov_SC06_015_jr_801380E0.c | 7 +- src/ov_SC06_015/ov_SC06_015_jr_8013C98C.c | 4 +- src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c | 7 - src/ov_SC06_016/ov_SC06_016_jr_8012ACE0.c | 9 +- src/ov_SC06_016/ov_SC06_016_jr_801380E0.c | 7 +- src/ov_SC06_016/ov_SC06_016_jr_8013C98C.c | 4 +- src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c | 7 - src/ov_SC06_018/ov_SC06_018_jr_8012ACE0.c | 9 +- src/ov_SC06_018/ov_SC06_018_jr_801380E0.c | 7 +- src/ov_SC06_018/ov_SC06_018_jr_8013C98C.c | 4 +- src/ov_SC06_020/ov_SC06_020_jr_8012ACE0.c | 9 +- src/ov_SC06_020/ov_SC06_020_jr_801380E0.c | 7 +- src/ov_SC06_020/ov_SC06_020_jr_8013C98C.c | 4 +- src/ov_SC06_022/ov_SC06_022_jr_8012ACE0.c | 9 +- src/ov_SC06_022/ov_SC06_022_jr_801380E0.c | 7 +- src/ov_SC06_022/ov_SC06_022_jr_8013C98C.c | 4 +- src/ov_SC06_022/ov_SC06_022_jr_8017BEBC.c | 7 - src/ov_SC06_024/ov_SC06_024_jr_8012ACE0.c | 9 +- src/ov_SC06_024/ov_SC06_024_jr_801380E0.c | 7 +- src/ov_SC06_024/ov_SC06_024_jr_8013C98C.c | 4 +- src/ov_SC06_024/ov_SC06_024_jr_8017BEBC.c | 7 - src/ov_SC06_025/ov_SC06_025_jr_8012ACE0.c | 9 +- src/ov_SC06_025/ov_SC06_025_jr_801380E0.c | 7 +- src/ov_SC06_025/ov_SC06_025_jr_8013C98C.c | 4 +- src/ov_SC06_025/ov_SC06_025_jr_8017BEBC.c | 7 - src/ov_SC06_025/ov_SC06_025_jr_8017EEC4.c | 17 +- src/ov_SC06_027/ov_SC06_027_jr_8012ACE0.c | 9 +- src/ov_SC06_027/ov_SC06_027_jr_801380E0.c | 7 +- src/ov_SC06_027/ov_SC06_027_jr_8013C98C.c | 4 +- src/ov_SC06_027/ov_SC06_027_jr_8017BEBC.c | 73 +--- src/ov_SC06_029/ov_SC06_029_jr_8012ACE0.c | 9 +- src/ov_SC06_029/ov_SC06_029_jr_801380E0.c | 7 +- src/ov_SC06_029/ov_SC06_029_jr_8013C98C.c | 4 +- src/ov_SC06_029/ov_SC06_029_jr_8017C954.c | 9 +- src/ov_SC06_029/ov_SC06_029_jr_801898CC.c | 83 +---- src/ov_SC06_030/ov_SC06_030_jr_8012ACE0.c | 9 +- src/ov_SC06_030/ov_SC06_030_jr_801380E0.c | 7 +- src/ov_SC06_030/ov_SC06_030_jr_8013C98C.c | 4 +- src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.c | 7 - src/ov_SC06_032/ov_SC06_032_jr_8012ACE0.c | 9 +- src/ov_SC06_032/ov_SC06_032_jr_801380E0.c | 7 +- src/ov_SC06_032/ov_SC06_032_jr_8013C98C.c | 4 +- src/ov_SC06_033/ov_SC06_033_jr_8012ACE0.c | 9 +- src/ov_SC06_033/ov_SC06_033_jr_801380E0.c | 7 +- src/ov_SC06_033/ov_SC06_033_jr_8013C98C.c | 4 +- src/ov_SC07_000/ov_SC07_000_jr_8012ACE0.c | 9 +- src/ov_SC07_000/ov_SC07_000_jr_801380E0.c | 7 +- src/ov_SC07_000/ov_SC07_000_jr_8013C98C.c | 4 +- src/ov_SC07_001/ov_SC07_001_jr_8012ACE0.c | 9 +- src/ov_SC07_001/ov_SC07_001_jr_801380E0.c | 7 +- src/ov_SC07_001/ov_SC07_001_jr_8013C98C.c | 4 +- src/ov_SC07_001/ov_SC07_001_jr_8017BEBC.c | 73 +--- src/ov_SC07_002/ov_SC07_002_jr_8012ACE0.c | 9 +- src/ov_SC07_002/ov_SC07_002_jr_801380E0.c | 7 +- src/ov_SC07_002/ov_SC07_002_jr_8013C98C.c | 4 +- src/ov_SC07_002/ov_SC07_002_jr_8017C8D0.c | 73 +--- src/ov_SC07_006/ov_SC07_006_jr_80131340.c | 9 +- src/ov_SC07_006/ov_SC07_006_jr_801380E0.c | 7 +- src/ov_SC07_006/ov_SC07_006_jr_8013C98C.c | 4 +- src/ov_SC07_006/ov_SC07_006_jr_8017BEBC.c | 7 - src/ov_SC07_007/ov_SC07_007_jr_80131340.c | 9 +- src/ov_SC07_007/ov_SC07_007_jr_801380E0.c | 7 +- src/ov_SC07_007/ov_SC07_007_jr_8013C98C.c | 4 +- src/ov_SC07_007/ov_SC07_007_jr_8017BEBC.c | 7 - src/ov_SC07_008/ov_SC07_008_jr_8012ACE0.c | 9 +- src/ov_SC07_008/ov_SC07_008_jr_801380E0.c | 7 +- src/ov_SC07_008/ov_SC07_008_jr_8013C98C.c | 4 +- src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c | 7 - src/ov_SC07_009/ov_SC07_009_jr_8012ACE0.c | 9 +- src/ov_SC07_009/ov_SC07_009_jr_801380E0.c | 7 +- src/ov_SC07_009/ov_SC07_009_jr_8013C98C.c | 4 +- src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c | 7 - src/ov_SC07_010/ov_SC07_010_jr_80131340.c | 9 +- src/ov_SC07_010/ov_SC07_010_jr_801380E0.c | 7 +- src/ov_SC07_010/ov_SC07_010_o2b.c | 4 +- src/ov_SC07_011/ov_SC07_011_jr_80131340.c | 9 +- src/ov_SC07_011/ov_SC07_011_jr_801380E0.c | 7 +- src/ov_SC07_011/ov_SC07_011_jr_8013C98C.c | 4 +- src/ov_SC07_011/ov_SC07_011_jr_8017BEBC.c | 7 - src/shared/ov/func_8012BFA8.h | 9 +- src/shared/ov/func_8012EF34.h | 2 +- src/shared/ov/func_8012EF70.h | 7 +- src/shared/ov/func_80133CD4__de6ea26c.h | 9 +- src/shared/ov/func_8013D9B0__4b66f7ea.h | 4 +- src/shared/ov/func_8013E064.h | 9 +- src/shared/ov/func_8013E0FC.h | 9 +- src/shared/ov/func_8013E194.h | 9 +- src/shared/ov/func_8013E2C4.h | 9 +- 398 files changed, 1099 insertions(+), 3403 deletions(-) diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index 80fd03b4d2..ee0f9a20ab 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,7 +1,7 @@ { - "head": "8c3937da22", + "head": "e672acfa6d", "stamp": "588cbf38c6e4", - "generated": "2026-10-02 18:30", + "generated": "2026-10-02 18:32", "aliases": [ "main", "md_SC07_004", @@ -21,176 +21,176 @@ "main": { "objects": 85, "identical": 85, - "seconds": 10.391999999999998, - "mean_s": 0.122 + "seconds": 8.636000000000003, + "mean_s": 0.102 }, "md_SC07_004": { "objects": 1, "identical": 1, - "seconds": 0.689, - "mean_s": 0.689 + "seconds": 0.612, + "mean_s": 0.612 }, "ov_SC03_015": { "objects": 32, "identical": 32, - "seconds": 6.799000000000002, - "mean_s": 0.212 + "seconds": 6.078999999999999, + "mean_s": 0.19 }, "ov_SC04_011": { "objects": 28, "identical": 28, - "seconds": 5.675000000000001, - "mean_s": 0.203 + "seconds": 5.280999999999999, + "mean_s": 0.189 } }, "per_object_seconds": { - "build/src/800.o": 1.016, - "build/src/800_b.o": 0.15, - "build/src/800_b_2.o": 0.487, - "build/src/800_b_o0a.o": 0.072, - "build/src/800_c.o": 0.344, - "build/src/800b2.o": 0.081, - "build/src/apicard1.o": 0.077, - "build/src/apicard2.o": 0.078, - "build/src/apicard3.o": 0.074, - "build/src/apicard4.o": 0.221, - "build/src/apicard5.o": 0.129, - "build/src/apicard6.o": 0.072, - "build/src/apicard7.o": 0.199, - "build/src/boot.o": 0.219, - "build/src/gap.o": 0.201, - "build/src/libapi1.o": 0.211, - "build/src/libapi2.o": 0.201, - "build/src/libc2_1.o": 0.199, - "build/src/libc2_2.o": 0.194, - "build/src/libcd1.o": 0.215, - "build/src/libcd2.o": 0.19, - "build/src/libetc.o": 0.199, - "build/src/libgpu.o": 0.14, - "build/src/libgpu2.o": 0.154, - "build/src/libgs1.o": 0.103, - "build/src/libgs2.o": 0.087, - "build/src/libgs3.o": 0.082, - "build/src/libgs4.o": 0.087, - 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"action": "call", "name": "gte_lwc2x3_sqr_e416"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:33:55", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c", "fn": null, "addr": null, "aliases": null, "header": false, "sites": [], "compiles": 1, "seconds": 0.14544963836669922, "record": {"deleted": 1, "renamed_defs": 0, "use_renames": 0, "direct_calls": 0, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [{"name": "gte_stsxy3_f4", "l0": 2684, "action": "deleted", "canonical": "gte_stsxy3_f4"}], "direct": [], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:33:55", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC07_009/ov_SC07_009_jr_8012ACE0.c", "fn": null, "addr": null, "aliases": null, "header": false, "sites": [], "compiles": 1, "seconds": 0.4196789264678955, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 2408, "action": "call", "name": "gte_lwc2x3_sqr_e416"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:33:55", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c", "fn": null, "addr": null, "aliases": null, "header": false, "sites": [], "compiles": 1, "seconds": 0.18111109733581543, "record": {"deleted": 1, "renamed_defs": 0, "use_renames": 0, "direct_calls": 0, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [{"name": "gte_stsxy3_f4", "l0": 3293, "action": "deleted", "canonical": "gte_stsxy3_f4"}], "direct": [], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:33:55", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC07_010/ov_SC07_010_jr_80131340.c", "fn": null, "addr": null, "aliases": null, "header": false, "sites": [], "compiles": 1, "seconds": 0.21317362785339355, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 1599, "action": "call", "name": "gte_lwc2x3_sqr_e416"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:33:55", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC07_011/ov_SC07_011_jr_80131340.c", "fn": null, "addr": null, "aliases": null, "header": false, "sites": [], "compiles": 1, "seconds": 0.20341873168945312, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], 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true, "sites": [], "compiles": 3, "seconds": 0.34107065200805664, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 2, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 52, "action": "call", "name": "gte_mtc2_lwc2x2_1fc7"}, {"line": 54, "action": "call", "name": "gte_move_swc2_e610"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:33:55", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/shared/ov/func_8012BFA8.h", "fn": null, "addr": null, "aliases": null, "header": true, "sites": [], "compiles": 141, "seconds": 65.28078603744507, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 12, "action": "call", "name": "gte_lwc2x3_sqr_e416"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:34:00", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/shared/ov/func_8012EF34.h", "fn": null, "addr": null, "aliases": null, "header": true, "sites": [], "compiles": 141, "seconds": 66.08468794822693, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 10, "action": "call", "name": "gte_stsz"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:34:04", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/shared/ov/func_8012EF70.h", "fn": null, "addr": null, "aliases": null, "header": true, "sites": [], "compiles": 141, "seconds": 56.906054973602295, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, 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"seconds": 20.525766611099243, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 12, "action": "call", "name": "gte_lwc2x3_sqr_b502"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:34:09", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/shared/ov/func_8013E0FC.h", "fn": null, "addr": null, "aliases": null, "header": true, "sites": [], "compiles": 141, "seconds": 20.56452775001526, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 12, "action": "call", "name": "gte_lwc2x3_sqr_b502"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:34:11", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/shared/ov/func_8013E194.h", "fn": null, "addr": null, "aliases": null, "header": true, "sites": [], "compiles": 141, "seconds": 17.658052444458008, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 12, "action": "call", "name": "gte_lwc2x3_sqr_b502"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:34:12", "label": "c3b2", "rung": "gte", "calib": {"head": "e672acfa6d", "stamp": "588cbf38c6e4"}, "tu": "src/shared/ov/func_8013E2C4.h", "fn": null, "addr": null, "aliases": null, "header": true, "sites": [], "compiles": 141, "seconds": 17.635914087295532, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 12, "action": "call", "name": "gte_lwc2x3_sqr_e416"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} diff --git a/.run/P36/gte/canonical.json b/.run/P36/gte/canonical.json index 6031b4c0bd..bd6220e710 100644 --- a/.run/P36/gte/canonical.json +++ b/.run/P36/gte/canonical.json @@ -1,5 +1,5 @@ { - "generated": "2026-10-02 18:31", + "generated": "2026-10-02 18:33", "canonical": { "08008ce80c008de810008ee8|0|1": { "name": "gte_stsxy3_f3", @@ -8,11 +8,11 @@ "clob": [ "memory" ], - "defs": 80, - "files": 80, + "defs": 72, + "files": 72, "synthesized": false, "names": { - "gte_stsxy3_f4": 81, + "gte_stsxy3_f4": 73, "gte_stsxy3_f3": 1 }, "sony": true, @@ -54,7 +54,7 @@ "files": 0, "synthesized": false, "names": { - "gte_SetRotMatrix_m": 4, + "gte_SetRotMatrix_m": 3, "gte_SetRotMatrix": 1 }, "sony": true, @@ -62,7 +62,7 @@ "nout": 0, "tmpl": "lw $12, 0( %0 );lw $13, 4( %0 );ctc2 $12, $0;ctc2 $13, $1;lw $12, 8( %0 );lw $13, 12( %0 );lw $14, 16( %0 );ctc2 $12, $2;ctc2 $13, $3;ctc2 $14, $4", "outs_first": false, - "inline": 15 + "inline": 13 }, "14008c8c18008d8c0028cc481c008e8c0030cd480038ce48|0|1": { "name": "gte_SetTransMatrix", @@ -87,44 +87,6 @@ "outs_first": false, "inline": 12 }, - "000080c8040081c8|0|1": { - "name": "gte_ldv0", - "params": "(r0)", - "body": "__asm__ volatile (\n \"lwc2 $0, 0( %0 );\"\n \"lwc2 $1, 4( %0 )\"\n :\n : \"r\"( r0 ) )", - "clob": [], - "defs": 0, - "files": 0, - "synthesized": false, - "names": { - "gte_ldv0_m": 2, - "gte_ldv0": 1 - }, - "sony": true, - "nin": 1, - "nout": 0, - "tmpl": "lwc2 $0, 0( %0 );lwc2 $1, 4( %0 )", - "outs_first": false, - "inline": 3 - }, - "00000000000000001260484a|0|0": { - "name": "gte_rtv0", - "params": "()", - "body": "__asm__ __volatile__(\n \"nop\\n\"\n \"nop\\n\"\n \"mvmva 1, 0, 0, 3, 0\\n\" )", - "clob": [], - "defs": 0, - "files": 0, - "synthesized": false, - "names": { - "gte_rtv0_m": 2, - "gte_rtv0": 1 - }, - "sony": true, - "nin": 0, - "nout": 0, - "tmpl": "nop\\nnop\\nmvmva 1, 0, 0, 3, 0\\n", - "outs_first": false, - "inline": 2 - }, "00008c8c04008d8c0000cc480008cd4808008c8c0c008d8c10008e8c0010cc480018cd480020ce4814008c8c18008d8c0028cc481c008e8c0030cd480038ce48|0|1": { "name": "gte_SetRotTransMatrix", "params": "(r0)", @@ -195,6 +157,25 @@ "outs_first": false, "inline": 3 }, + "000080c8040081c8|0|1": { + "name": "gte_ldv0", + "params": "(r0)", + "body": "__asm__ volatile (\n \"lwc2 $0, 0( %0 );\"\n \"lwc2 $1, 4( %0 )\"\n :\n : \"r\"( r0 ) )", + "clob": [], + "defs": 0, + "files": 0, + "synthesized": false, + "names": { + "gte_ldv0": 1, + "gte_ldv0_m": 1 + }, + "sony": true, + "nin": 1, + "nout": 0, + "tmpl": "lwc2 $0, 0( %0 );lwc2 $1, 4( %0 )", + "outs_first": false, + "inline": 1 + }, "000000000000000012e0494a|0|0": { "name": "gte_rtir", "params": "()", @@ -232,6 +213,24 @@ "outs_first": false, "inline": 1 }, + "00000000000000001260484a|0|0": { + "name": "gte_rtv0", + "params": "()", + "body": "__asm__ __volatile__(\n \"nop\\n\"\n \"nop\\n\"\n \"mvmva 1, 0, 0, 3, 0\\n\" )", + "clob": [], + "defs": 0, + "files": 0, + "synthesized": false, + "names": { + "gte_rtv0": 1, + "gte_rtv0_m": 1 + }, + "sony": true, + "nin": 0, + "nout": 0, + "tmpl": "nop\\nnop\\nmvmva 1, 0, 0, 3, 0\\n", + "outs_first": false + }, "00f84c480000000000008cac|0|1": { "name": "gte_stflg", "params": "(r0)", @@ -305,8 +304,7 @@ "nin": 1, "nout": 1, "tmpl": "cfc2 %0, $31; nop; sw %0, 0(%1)", - "outs_first": true, - "inline": 1 + "outs_first": true }, "00000000000000002900684a|0|0": { "name": "gte_dpcl", @@ -396,8 +394,7 @@ "nin": 1, "nout": 0, "tmpl": "lwc2 $9, 0(%0)\\n\\tlwc2 $10, 4(%0)\\n\\tlwc2 $11, 8(%0)", - "outs_first": false, - "inline": 1 + "outs_first": false }, "01008d8000008c80006c0d0000640c0002640c0025608d0102008d8000008c4800088d48|0|1": { "name": "gte_ldlvl_alt", @@ -508,7 +505,7 @@ "nout": 0, "tmpl": "lwc2 $9, 0($sp)\\nlwc2 $10, 4($sp)\\nlwc2 $11, 8($sp)\\nnop\\nnop\\nsqr 0\\n", "outs_first": false, - "inline": 11 + "inline": 1 }, "000089c804008ac808008bc800000000000000002804a84a|0|1": { "name": "gte_lwc2x3_sqr_b502", @@ -554,7 +551,7 @@ "nout": 0, "tmpl": "lwc2 $9, 0(%0)\\nlwc2 $10, 4(%0)\\nlwc2 $11, 8(%0)\\nnop\\nnop\\nsqr 0\\n", "outs_first": false, - "inline": 141 + "inline": 139 }, "000089c804008ac808008bc800000000000000002804a04a000099e804009ae808009be8|0|1": { "name": "gte_lwc2x3_sqr_swc2x3_c9fc", @@ -577,7 +574,7 @@ "nout": 0, "tmpl": "lwc2 $9, 0( %0 );lwc2 $10, 4( %0 );lwc2 $11, 8( %0 );nop;nop;sqr 0;swc2 $25, 0( %0 );swc2 $26, 4( %0 );swc2 $27, 8( %0 )", "outs_first": false, - "inline": 2 + "inline": 1 }, "00004c8c04004d8c0000cc480008cd4808004c8c0c004d8c10004e8c0010cc480018cd480020ce481000a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a00480c4800500d4800580e4800004ca406004da40c004ea41200a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a0200422400480c4800500d4800580e4800004ca406004da40c004ea41400a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a0400422400480c4800500d4800580e4800004ca406004da40c004ea4|1|1": { "name": "gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d", @@ -600,7 +597,7 @@ "nout": 1, "tmpl": "lw $12, 0(%0);lw $13, 4(%0);ctc2 $12, $0;ctc2 $13, $1;lw $12, 8(%0);lw $13, 12(%0);lw $14, 16(%0);ctc2 $12, $2;ctc2 $13, $3;ctc2 $14, $4;addiu $2, $sp, 0x10;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0(%0);sh $13, 6(%0);sh $14, 12(%0);addiu $2, $sp, 0x12;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;addiu $2, %0, 0x2;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0($2);sh $13, 6($2);sh $14, 12($2);addiu $2, $sp, 0x14;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;addiu %0, %0, 4;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0(%0);sh $13, 6(%0);sh $14, 12(%0)", "outs_first": true, - "inline": 17 + "inline": 12 }, "00008c8c04008d8c0000cc480008cd4808008c8c0c008d8c10008e8c0010cc480018cd480020ce480000ac940600ad940c00ae9400488c4800508d4800588e48000000000000000012e0494a00480c4800500d4800580e4800008ca406008da40c008ea43200a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a1200a22700480c4800500d4800580e4800004ca406004da40c004ea43400a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a1400a22700480c4800500d4800580e4800004ca406004da40c004ea4|0|2": { "name": "gte_lwx2_ctc2x2_lwx3_ctc2x3_3eb0", @@ -621,8 +618,7 @@ "nin": 2, "nout": 0, "tmpl": "lw $12, 0(%0);lw $13, 4(%0);ctc2 $12, $0;ctc2 $13, $1;lw $12, 8(%0);lw $13, 12(%0);lw $14, 16(%0);ctc2 $12, $2;ctc2 $13, $3;ctc2 $14, $4;lhu $12, 0(%1);lhu $13, 6(%1);lhu $14, 12(%1);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0(%0);sh $13, 6(%0);sh $14, 12(%0);addiu $2, $sp, 50;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;addiu $2, $sp, 18;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0($2);sh $13, 6($2);sh $14, 12($2);addiu $2, $sp, 52;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;addiu $2, $sp, 20;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0($2);sh $13, 6($2);sh $14, 12($2)", - "outs_first": false, - "inline": 1 + "outs_first": false }, "0000828c0400838c0000c2480008c3480800828c0c00838c1000988c0010c2480018c3480020d8481400828c1800838c0028c2481c00988c0030c3480038d848|3|1": { "name": "gte_lwx2_ctc2x2_lwx3_ctc2x3_42e3", @@ -639,8 +635,7 @@ "nin": 1, "nout": 3, "tmpl": "lw %0, 0(%3);lw %1, 4(%3);ctc2 %0, $0;ctc2 %1, $1;lw %0, 8(%3);lw %1, 12(%3);lw %2, 16(%3);ctc2 %0, $2;ctc2 %1, $3;ctc2 %2, $4;lw %0, 20(%3);lw %1, 24(%3);ctc2 %0, $5;lw %2, 28(%3);ctc2 %1, $6;ctc2 %2, $7", - "outs_first": true, - "inline": 1 + "outs_first": true }, "00008c8c04008d8c0000cc480008cd4808008c8c0c008d8c10008e8c0010cc480018cd480020ce481000a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a00480c4800500d4800580e4800008ca406008da40c008ea41200a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a0200822400480c4800500d4800580e4800004ca406004da40c004ea41400a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a0400822400480c4800500d4800580e4800004ca406004da40c004ea4|0|1": { "name": "gte_lwx2_ctc2x2_lwx3_ctc2x3_8b56", @@ -662,8 +657,7 @@ "nin": 1, "nout": 0, "tmpl": "lw $12, 0(%0);lw $13, 4(%0);ctc2 $12, $0;ctc2 $13, $1;lw $12, 8(%0);lw $13, 12(%0);lw $14, 16(%0);ctc2 $12, $2;ctc2 $13, $3;ctc2 $14, $4;addiu $2, $sp, 16;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0(%0);sh $13, 6(%0);sh $14, 12(%0);addiu $2, $sp, 18;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;addiu $2, %0, 2;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0($2);sh $13, 6($2);sh $14, 12($2);addiu $2, $sp, 20;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;addiu $2, %0, 4;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0($2);sh $13, 6($2);sh $14, 12($2)", - "outs_first": false, - "inline": 3 + "outs_first": false }, "00008c8c04008d8c0000cc480008cd4808008c8c0c008d8c10008e8c0010cc480018cd480020ce483000a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a00480c4800500d4800580e4800008ca406008da40c008ea43200a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a1200a22700480c4800500d4800580e4800004ca406004da40c004ea43400a22700004c9406004d940c004e9400488c4800508d4800588e48000000000000000012e0494a1400a22700480c4800500d4800580e4800004ca406004da40c004ea4|0|1": { "name": "gte_lwx2_ctc2x2_lwx3_ctc2x3_b751", @@ -686,8 +680,7 @@ "nin": 1, "nout": 0, "tmpl": "lw $12, 0(%0);lw $13, 4(%0);ctc2 $12, $0;ctc2 $13, $1;lw $12, 8(%0);lw $13, 12(%0);lw $14, 16(%0);ctc2 $12, $2;ctc2 $13, $3;ctc2 $14, $4;addiu $2, $sp, 0x30;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0(%0);sh $13, 6(%0);sh $14, 12(%0);addiu $2, $sp, 0x32;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;addiu $2, $sp, 0x12;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0($2);sh $13, 6($2);sh $14, 12($2);addiu $2, $sp, 0x34;lhu $12, 0($2);lhu $13, 6($2);lhu $14, 12($2);mtc2 $12, $9;mtc2 $13, $10;mtc2 $14, $11;nop;nop;mvmva 1, 0, 3, 3, 0;addiu $2, $sp, 0x14;mfc2 $12, $9;mfc2 $13, $10;mfc2 $14, $11;sh $12, 0($2);sh $13, 6($2);sh $14, 12($2);", - "outs_first": false, - "inline": 1 + "outs_first": false }, "00008c8c04008d8c0000cc480008cd4808008c8c0c008d8c10008e8c0010cc480018cd480020ce480000a0c80400a1c800000000000000001260484a0000d9e80400dae80800dbe8|0|0": { "name": "gte_lwx2_ctc2x2_lwx3_ctc2x3_fc24", @@ -709,8 +702,7 @@ "nin": 0, "nout": 0, "tmpl": ".set\\tnoreorder\\nlw $12, 0($4)\\nlw $13, 4($4)\\nctc2 $12, $0\\nctc2 $13, $1\\nlw $12, 8($4)\\nlw $13, 12($4)\\nlw $14, 16($4)\\nctc2 $12, $2\\nctc2 $13, $3\\nctc2 $14, $4\\nlwc2 $0, 0($5)\\nlwc2 $1, 4($5)\\nnop\\nnop\\nmvmva 1, 0, 0, 3, 0\\nswc2 $25, 0($6)\\nswc2 $26, 4($6)\\nswc2 $27, 8($6)\\n.set\\treorder\\n", - "outs_first": false, - "inline": 1 + "outs_first": false }, "2160800000009de9|0|1": { "name": "gte_move_swc2_e610", @@ -731,7 +723,7 @@ "nout": 0, "tmpl": "move $12, %0\\n\\tswc2 $29, 0($12)", "outs_first": false, - "inline": 134 + "inline": 107 }, "00408048000086c80000bcc8|0|2": { "name": "gte_mtc2_lwc2x2_1fc7", @@ -751,7 +743,7 @@ "nout": 0, "tmpl": "mtc2 $0, $8\\n\\tlwc2 $6, 0(%0)\\n\\tlwc2 $28, 0(%1)", "outs_first": false, - "inline": 134 + "inline": 107 }, "00008c9406008d940c008e9400488c4800508d4800588e48000000000000000012e0494a00480c4800500d4800580e4800008ca406008da40c008ea4|0|1": { "name": "gte_mulcol", @@ -898,8 +890,7 @@ "nin": 0, "nout": 0, "tmpl": "nop\\n\\tnop\\n\\tsqr 0", - "outs_first": false, - "inline": 1 + "outs_first": false }, "00009de8|0|1": { "name": "gte_stORGB", @@ -959,8 +950,7 @@ "nin": 1, "nout": 0, "tmpl": "swc2 $8, 0( %0 )", - "outs_first": false, - "inline": 2 + "outs_first": false }, "000099e804009ae808009be8|0|1": { "name": "gte_stlvnl", @@ -1347,7 +1337,7 @@ "nout": 0, "tmpl": "swc2 $25, 0($sp)\\nswc2 $26, 4($sp)\\nswc2 $27, 8($sp)\\n", "outs_first": false, - "inline": 11 + "inline": 1 } }, "variants": { @@ -1385,8 +1375,8 @@ "memory" ], "fewer": [], - "defs": 3, - "files": 3, + "defs": 2, + "files": 2, "inline": 12, "params": "(r0)", "body": "__asm__ __volatile__(\n \"lw $12, 0(%0)\\n\"\n \"lw $13, 4(%0)\\n\"\n \"ctc2 $12, $0\\n\"\n \"ctc2 $13, $1\\n\"\n \"lw $12, 8(%0)\\n\"\n \"lw $13, 12(%0)\\n\"\n \"lw $14, 16(%0)\\n\"\n \"ctc2 $12, $2\\n\"\n \"ctc2 $13, $3\\n\"\n \"ctc2 $14, $4\\n\"\n : : \"r\"(r0) : \"$12\", \"$13\", \"$14\", \"memory\")", @@ -1417,46 +1407,6 @@ "marker": "// !FAKE: gte variant gte_SetTransMatrix_m \u2014 clobbers +memory vs `gte_SetTransMatrix` (a scheduling steer); pass: P36 T5 GTE consolidation (per-TU definitions; moved to this header 3.39 T7.1); instrument: tools/gte_consolidate.py --header", "pass_": "P36 T5 GTE consolidation (per-TU definitions; moved to this header 3.39 T7.1)" }, - "000080c8040081c8|0|1|memory": { - "name": "gte_ldv0_m", - "of": "gte_ldv0", - "key": "000080c8040081c8|0|1", - "clob": [ - "memory" - ], - "extra": [ - "memory" - ], - "fewer": [], - "defs": 1, - "files": 1, - "inline": 1, - "params": "(p)", - "body": "__asm__ __volatile__(\n \"lwc2 $0, 0(%0)\\n\"\n \"lwc2 $1, 4(%0)\\n\"\n : : \"r\"(p) : \"memory\")", - "source": "header", - "marker": "// !FAKE: gte variant gte_ldv0_m \u2014 clobbers +memory vs `gte_ldv0` (a scheduling steer); pass: P36 T5 GTE consolidation (per-TU definitions; moved to this header 3.39 T7.1); instrument: tools/gte_consolidate.py --header", - "pass_": "P36 T5 GTE consolidation (per-TU definitions; moved to this header 3.39 T7.1)" - }, - "00000000000000001260484a|0|0|memory": { - "name": "gte_rtv0_m", - "of": "gte_rtv0", - "key": "00000000000000001260484a|0|0", - "clob": [ - "memory" - ], - "extra": [ - "memory" - ], - "fewer": [], - "defs": 1, - "files": 1, - "inline": 133, - "params": "()", - "body": "__asm__ __volatile__(\n \"nop\\n\"\n \"nop\\n\"\n \"mvmva 1, 0, 0, 3, 0\\n\"\n : : : \"memory\")", - "source": "header", - "marker": "// !FAKE: gte variant gte_rtv0_m \u2014 clobbers +memory vs `gte_rtv0` (a scheduling steer); pass: P36 T5 GTE consolidation (per-TU definitions; moved to this header 3.39 T7.1); instrument: tools/gte_consolidate.py --header", - "pass_": "P36 T5 GTE consolidation (per-TU definitions; moved to this header 3.39 T7.1)" - }, "00008c8c04008d8c0000cc480008cd4808008c8c0c008d8c10008e8c0010cc480018cd480020ce4814008c8c18008d8c0028cc481c008e8c0030cd480038ce48|0|1|$12|$13|$14|memory": { "name": "gte_SetRotTransMatrix_m", "of": "gte_SetRotTransMatrix", @@ -1526,6 +1476,26 @@ "marker": "// !FAKE: gte variant gte_ldclmv_m \u2014 clobbers +memory vs `gte_ldclmv` (a scheduling steer); pass: 3.39 T7.1 inline GTE statements (exact clobbers); instrument: tools/gte_consolidate.py --header", "pass_": "3.39 T7.1 inline GTE statements (exact clobbers)" }, + "000080c8040081c8|0|1|memory": { + "name": "gte_ldv0_m", + "of": "gte_ldv0", + "key": "000080c8040081c8|0|1", + "clob": [ + "memory" + ], + "extra": [ + "memory" + ], + "fewer": [], + "defs": 0, + "files": 0, + "inline": 1, + "params": "(p)", + "body": "__asm__ __volatile__(\n \"lwc2 $0, 0(%0)\\n\"\n \"lwc2 $1, 4(%0)\\n\"\n : : \"r\"(p) : \"memory\")", + "source": "header", + "marker": "// !FAKE: gte variant gte_ldv0_m \u2014 clobbers +memory vs `gte_ldv0` (a scheduling steer); pass: P36 T5 GTE consolidation (per-TU definitions; moved to this header 3.39 T7.1); instrument: tools/gte_consolidate.py --header", + "pass_": "3.39 T7.1 inline GTE statements (exact clobbers)" + }, "000000000000000012e0494a|0|0|memory": { "name": "gte_rtir_m", "of": "gte_rtir", @@ -1566,6 +1536,26 @@ "marker": "// !FAKE: gte variant gte_rtps_m \u2014 clobbers +memory vs `gte_rtps` (a scheduling steer); pass: 3.39 T7.1 inline GTE statements (exact clobbers); instrument: tools/gte_consolidate.py --header", "pass_": "3.39 T7.1 inline GTE statements (exact clobbers)" }, + "00000000000000001260484a|0|0|memory": { + "name": "gte_rtv0_m", + "of": "gte_rtv0", + "key": "00000000000000001260484a|0|0", + "clob": [ + "memory" + ], + "extra": [ + "memory" + ], + "fewer": [], + "defs": 0, + "files": 0, + "inline": 133, + "params": "()", + "body": "__asm__ __volatile__(\n \"nop\\n\"\n \"nop\\n\"\n \"mvmva 1, 0, 0, 3, 0\\n\"\n : : : \"memory\")", + "source": "header", + "marker": "// !FAKE: gte variant gte_rtv0_m \u2014 clobbers +memory vs `gte_rtv0` (a scheduling steer); pass: P36 T5 GTE consolidation (per-TU definitions; moved to this header 3.39 T7.1); instrument: tools/gte_consolidate.py --header", + "pass_": "3.39 T7.1 inline GTE statements (exact clobbers)" + }, "00f84c480000000000008cac|0|1|$12": { "name": "gte_stflg_v845d", "of": "gte_stflg", @@ -1597,8 +1587,8 @@ "clob": [ "memory" ], - "defs": 80, - "files": 80, + "defs": 72, + "files": 72, "variant": false, "marker": null }, diff --git a/src/md_MAIN_019/md_MAIN_019.c b/src/md_MAIN_019/md_MAIN_019.c index 0ab8be7542..8e1adea0e8 100644 --- a/src/md_MAIN_019/md_MAIN_019.c +++ b/src/md_MAIN_019/md_MAIN_019.c @@ -292,30 +292,6 @@ extern u8 D_800CC5B0[]; extern u8 D_800CC638[]; -#define gte_rt(p) \ - __asm__ volatile ( \ - "lhu $12, 0( %0 );" \ - "lhu $13, 6( %0 );" \ - "lhu $14, 12( %0 );" \ - "mtc2 $12, $9;" \ - "mtc2 $13, $10;" \ - "mtc2 $14, $11;" \ - "nop;" \ - "nop;" \ - "mvmva 1, 0, 3, 3, 0" \ - : \ - : "r"( p ) \ - : "$12", "$13", "$14", "memory"); \ - __asm__ volatile ( \ - "mfc2 $12, $9;" \ - "mfc2 $13, $10;" \ - "mfc2 $14, $11;" \ - "sh $12, 0( %0 );" \ - "sh $13, 6( %0 );" \ - "sh $14, 12( %0 )" \ - : \ - : "r"( p ) \ - : "$12", "$13", "$14", "memory") void func_800CB578(void *arg0) { u16 pos[4]; @@ -332,9 +308,9 @@ void func_800CB578(void *arg0) { func_80013F3C(&mat); RotMatrixZ(CAST_SIGN(s16, (u8 *)arg0, 0x64), &mat); gte_SetRotMatrix(obj + 0x34); - gte_rt((s32)&mat); - gte_rt((s32)&mat + 2); - gte_rt((s32)&mat + 4); + gte_rt_alt2((s32)&mat); + gte_rt_alt2((s32)&mat + 2); + gte_rt_alt2((s32)&mat + 4); mat.t[0] = *(s32 *)(obj + 0x48); mat.t[1] = *(s32 *)(obj + 0x4C); mat.t[2] = *(s32 *)(obj + 0x50); diff --git a/src/ov_MAIN_012/ov_MAIN_012_jr_80131340.c b/src/ov_MAIN_012/ov_MAIN_012_jr_80131340.c index 3640ae3f83..b0b6fbe843 100644 --- a/src/ov_MAIN_012/ov_MAIN_012_jr_80131340.c +++ b/src/ov_MAIN_012/ov_MAIN_012_jr_80131340.c @@ -1643,14 +1643,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017E924) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017E924); gte_stlvnl(D_8017E928); pc0 = D_8017E924; diff --git a/src/ov_SC01_000/ov_SC01_000_jr_8012ACE0.c b/src/ov_SC01_000/ov_SC01_000_jr_8012ACE0.c index df74b06e51..8cfda8b30f 100644 --- a/src/ov_SC01_000/ov_SC01_000_jr_8012ACE0.c +++ b/src/ov_SC01_000/ov_SC01_000_jr_8012ACE0.c @@ -2403,14 +2403,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F1AC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F1AC); gte_stlvnl(D_8017F1B0); pc0 = D_8017F1AC; diff --git a/src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c b/src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c index ad9ee18944..72e7913935 100644 --- a/src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c +++ b/src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c @@ -2666,13 +2666,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC01_001/ov_SC01_001_jr_8012ACE0.c b/src/ov_SC01_001/ov_SC01_001_jr_8012ACE0.c index 9ec919065b..1194a5c6cc 100644 --- a/src/ov_SC01_001/ov_SC01_001_jr_8012ACE0.c +++ b/src/ov_SC01_001/ov_SC01_001_jr_8012ACE0.c @@ -2403,14 +2403,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80183DFC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80183DFC); gte_stlvnl(D_80183E00); pc0 = D_80183DFC; diff --git a/src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c b/src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c index 95980860b3..3688f8a825 100644 --- a/src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c +++ b/src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c @@ -2683,13 +2683,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC01_004/ov_SC01_004_jr_8012ACE0.c b/src/ov_SC01_004/ov_SC01_004_jr_8012ACE0.c index 30af014bfe..092d7c273b 100644 --- a/src/ov_SC01_004/ov_SC01_004_jr_8012ACE0.c +++ b/src/ov_SC01_004/ov_SC01_004_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F7C0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F7C0); gte_stlvnl(D_8017F7C4); pc0 = D_8017F7C0; diff --git a/src/ov_SC01_005/ov_SC01_005_jr_8012ACE0.c b/src/ov_SC01_005/ov_SC01_005_jr_8012ACE0.c index c9126989ce..4cfe509430 100644 --- a/src/ov_SC01_005/ov_SC01_005_jr_8012ACE0.c +++ b/src/ov_SC01_005/ov_SC01_005_jr_8012ACE0.c @@ -2396,14 +2396,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182954) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182954); gte_stlvnl(D_80182958); pc0 = D_80182954; diff --git a/src/ov_SC01_008/ov_SC01_008_jr_8012ACE0.c b/src/ov_SC01_008/ov_SC01_008_jr_8012ACE0.c index 5e4d0d8ef2..c46a1a1b48 100644 --- a/src/ov_SC01_008/ov_SC01_008_jr_8012ACE0.c +++ b/src/ov_SC01_008/ov_SC01_008_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017FD34) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017FD34); gte_stlvnl(D_8017FD38); pc0 = D_8017FD34; diff --git a/src/ov_SC01_009/ov_SC01_009_jr_8012ACE0.c b/src/ov_SC01_009/ov_SC01_009_jr_8012ACE0.c index bc5e8736d3..37111ad816 100644 --- a/src/ov_SC01_009/ov_SC01_009_jr_8012ACE0.c +++ b/src/ov_SC01_009/ov_SC01_009_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182F1C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182F1C); gte_stlvnl(D_80182F20); pc0 = D_80182F1C; diff --git a/src/ov_SC01_074/ov_SC01_074_jr_8012ACE0.c b/src/ov_SC01_074/ov_SC01_074_jr_8012ACE0.c index 4be0b07411..15aab43a7e 100644 --- a/src/ov_SC01_074/ov_SC01_074_jr_8012ACE0.c +++ b/src/ov_SC01_074/ov_SC01_074_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017EB9C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017EB9C); gte_stlvnl(D_8017EBA0); pc0 = D_8017EB9C; diff --git a/src/ov_SC01_077/ov_SC01_077_jr_8012ACE0.c b/src/ov_SC01_077/ov_SC01_077_jr_8012ACE0.c index f3afecc75d..e470f2adca 100644 --- a/src/ov_SC01_077/ov_SC01_077_jr_8012ACE0.c +++ b/src/ov_SC01_077/ov_SC01_077_jr_8012ACE0.c @@ -2800,14 +2800,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801870C0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801870C0); gte_stlvnl(D_801870C4); pc0 = D_801870C0; diff --git a/src/ov_SC01_080/ov_SC01_080_jr_8012ACE0.c b/src/ov_SC01_080/ov_SC01_080_jr_8012ACE0.c index 838963de64..47a56f1684 100644 --- a/src/ov_SC01_080/ov_SC01_080_jr_8012ACE0.c +++ b/src/ov_SC01_080/ov_SC01_080_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80183AFC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80183AFC); gte_stlvnl(D_80183B00); pc0 = D_80183AFC; diff --git a/src/ov_SC01_084/ov_SC01_084_jr_8012ACE0.c b/src/ov_SC01_084/ov_SC01_084_jr_8012ACE0.c index 7746fa714c..da2b40c984 100644 --- a/src/ov_SC01_084/ov_SC01_084_jr_8012ACE0.c +++ b/src/ov_SC01_084/ov_SC01_084_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80186DF0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80186DF0); gte_stlvnl(D_80186DF4); pc0 = D_80186DF0; diff --git a/src/ov_SC01_084/ov_SC01_084_jr_8017CA80.c b/src/ov_SC01_084/ov_SC01_084_jr_8017CA80.c index 3272637a21..70e43faff8 100644 --- a/src/ov_SC01_084/ov_SC01_084_jr_8017CA80.c +++ b/src/ov_SC01_084/ov_SC01_084_jr_8017CA80.c @@ -2692,13 +2692,6 @@ extern void func_8017C7C4(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC02_000/ov_SC02_000_jr_8012ACE0.c b/src/ov_SC02_000/ov_SC02_000_jr_8012ACE0.c index 7c096ff1a8..30f7b64775 100644 --- a/src/ov_SC02_000/ov_SC02_000_jr_8012ACE0.c +++ b/src/ov_SC02_000/ov_SC02_000_jr_8012ACE0.c @@ -2401,14 +2401,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018B1A0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018B1A0); gte_stlvnl(D_8018B1A4); pc0 = D_8018B1A0; diff --git a/src/ov_SC02_004/ov_SC02_004_jr_8012ACE0.c b/src/ov_SC02_004/ov_SC02_004_jr_8012ACE0.c index 056b772dbd..754e728bdf 100644 --- a/src/ov_SC02_004/ov_SC02_004_jr_8012ACE0.c +++ b/src/ov_SC02_004/ov_SC02_004_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017E280) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017E280); gte_stlvnl(D_8017E284); pc0 = D_8017E280; diff --git a/src/ov_SC02_005/ov_SC02_005_jr_8012ACE0.c b/src/ov_SC02_005/ov_SC02_005_jr_8012ACE0.c index 549bc46108..49031553cc 100644 --- a/src/ov_SC02_005/ov_SC02_005_jr_8012ACE0.c +++ b/src/ov_SC02_005/ov_SC02_005_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80190E84) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80190E84); gte_stlvnl(D_80190E88); pc0 = D_80190E84; diff --git a/src/ov_SC02_005/ov_SC02_005_jr_80185E80.c b/src/ov_SC02_005/ov_SC02_005_jr_80185E80.c index 2124a76944..e3b37d6563 100644 --- a/src/ov_SC02_005/ov_SC02_005_jr_80185E80.c +++ b/src/ov_SC02_005/ov_SC02_005_jr_80185E80.c @@ -3181,13 +3181,7 @@ void func_8018A4C4(s32 a0) * live at offset 0x34+0x14/0x18/0x1c inside the object pointed to by * a0's field 0x20. Written as raw asm: the target's .s marks these ctc2 * lines "handwritten instruction" (not a normal codegen mnemonic). */ - __asm__ __volatile__( - "lw $12, 20(%0)\n" - "lw $13, 24(%0)\n" - "ctc2 $12, $5\n" - "lw $14, 28(%0)\n" - "ctc2 $13, $6\n" - "ctc2 $14, $7\n" : : "r"((u8 *)*(s32 *)(a0 + 0x20) + 0x34) : "$12", "$13", "$14" ); + gte_SetTransMatrix((u8 *)*(s32 *)(a0 + 0x20) + 0x34); for (i = 0; i < 8; i++) { s0 = func_8012913C(0xC); diff --git a/src/ov_SC02_011/ov_SC02_011_jr_8012ACE0.c b/src/ov_SC02_011/ov_SC02_011_jr_8012ACE0.c index cb83cd592d..80156b1eb2 100644 --- a/src/ov_SC02_011/ov_SC02_011_jr_8012ACE0.c +++ b/src/ov_SC02_011/ov_SC02_011_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801912D4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801912D4); gte_stlvnl(D_801912D8); pc0 = D_801912D4; diff --git a/src/ov_SC02_011/ov_SC02_011_jr_80188E3C.c b/src/ov_SC02_011/ov_SC02_011_jr_80188E3C.c index 0c7b80a640..2465dd2ebd 100644 --- a/src/ov_SC02_011/ov_SC02_011_jr_80188E3C.c +++ b/src/ov_SC02_011/ov_SC02_011_jr_80188E3C.c @@ -2062,71 +2062,7 @@ void func_8018B60C(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC02_015/ov_SC02_015_jr_8012ACE0.c b/src/ov_SC02_015/ov_SC02_015_jr_8012ACE0.c index dcceacc567..1605c17962 100644 --- a/src/ov_SC02_015/ov_SC02_015_jr_8012ACE0.c +++ b/src/ov_SC02_015/ov_SC02_015_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017E7E8) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017E7E8); gte_stlvnl(D_8017E7EC); pc0 = D_8017E7E8; diff --git a/src/ov_SC02_015/ov_SC02_015_jr_8017AE2C.c b/src/ov_SC02_015/ov_SC02_015_jr_8017AE2C.c index 65c4e02c50..b68579fbb2 100644 --- a/src/ov_SC02_015/ov_SC02_015_jr_8017AE2C.c +++ b/src/ov_SC02_015/ov_SC02_015_jr_8017AE2C.c @@ -3413,13 +3413,6 @@ void func_8017C18C(s32 a0) { #include "../shared/ov/func_8017C230.h" -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) #include "../shared/ov/func_8017C294__t67f11bf2.h" diff --git a/src/ov_SC02_016/ov_SC02_016_jr_8012ACE0.c b/src/ov_SC02_016/ov_SC02_016_jr_8012ACE0.c index 1905c29307..45630723cf 100644 --- a/src/ov_SC02_016/ov_SC02_016_jr_8012ACE0.c +++ b/src/ov_SC02_016/ov_SC02_016_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80184A20) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80184A20); gte_stlvnl(D_80184A24); pc0 = D_80184A20; diff --git a/src/ov_SC02_016/ov_SC02_016_jr_801810C8.c b/src/ov_SC02_016/ov_SC02_016_jr_801810C8.c index 9eea107890..020a34a07f 100644 --- a/src/ov_SC02_016/ov_SC02_016_jr_801810C8.c +++ b/src/ov_SC02_016/ov_SC02_016_jr_801810C8.c @@ -4044,11 +4044,6 @@ extern int D_801B481C; /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_801829D8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, @@ -4094,15 +4089,15 @@ void func_801829D8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, { int t = f->vy - 0x10; f->vy = t + (r & 0x1f); } gte_ldv0(c); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(r0_00); gte_ldv0(f); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(r0_00 + 1); gte_ldv0(d); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) r0 = r0_00 + 2; gte_stsv(r0); @@ -4111,7 +4106,7 @@ void func_801829D8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, d->vx = d->vx - (f->pad & r); gte_ldv0(d); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) pSVar6 = r0_00 + 3; gte_stsv(pSVar6); @@ -4119,7 +4114,7 @@ void func_801829D8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, func_80017714(r0_00); gte_ldv0(e); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(r0); *e = *f; @@ -4127,7 +4122,7 @@ void func_801829D8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, e->vx = e->vx + (f->pad & r); gte_ldv0(e); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(pSVar6); r0_00->vz = ((u16 *)b)[2]; diff --git a/src/ov_SC02_017/ov_SC02_017_jr_8012ACE0.c b/src/ov_SC02_017/ov_SC02_017_jr_8012ACE0.c index f5a7b28f8a..8dce59975d 100644 --- a/src/ov_SC02_017/ov_SC02_017_jr_8012ACE0.c +++ b/src/ov_SC02_017/ov_SC02_017_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018AA78) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018AA78); gte_stlvnl(D_8018AA7C); pc0 = D_8018AA78; diff --git a/src/ov_SC02_017/ov_SC02_017_jr_80186C64.c b/src/ov_SC02_017/ov_SC02_017_jr_80186C64.c index 26a5b7aee3..34c558c014 100644 --- a/src/ov_SC02_017/ov_SC02_017_jr_80186C64.c +++ b/src/ov_SC02_017/ov_SC02_017_jr_80186C64.c @@ -5326,71 +5326,7 @@ void func_80189908(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC02_021/ov_SC02_021_jr_8012ACE0.c b/src/ov_SC02_021/ov_SC02_021_jr_8012ACE0.c index 95059bbd06..c5a2c68b07 100644 --- a/src/ov_SC02_021/ov_SC02_021_jr_8012ACE0.c +++ b/src/ov_SC02_021/ov_SC02_021_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018006C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018006C); gte_stlvnl(D_80180070); pc0 = D_8018006C; diff --git a/src/ov_SC02_021/ov_SC02_021_jr_8017C294.c b/src/ov_SC02_021/ov_SC02_021_jr_8017C294.c index 7540f5d5e0..b919d3f1e2 100644 --- a/src/ov_SC02_021/ov_SC02_021_jr_8017C294.c +++ b/src/ov_SC02_021/ov_SC02_021_jr_8017C294.c @@ -2693,13 +2693,6 @@ extern void func_8017C230(int a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC02_026/ov_SC02_026_jr_8012ACE0.c b/src/ov_SC02_026/ov_SC02_026_jr_8012ACE0.c index 752b2ad280..927ec175ad 100644 --- a/src/ov_SC02_026/ov_SC02_026_jr_8012ACE0.c +++ b/src/ov_SC02_026/ov_SC02_026_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801866C0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801866C0); gte_stlvnl(D_801866C4); pc0 = D_801866C0; diff --git a/src/ov_SC02_027/ov_SC02_027_jr_8012ACE0.c b/src/ov_SC02_027/ov_SC02_027_jr_8012ACE0.c index 73e952bd26..f241e2f55b 100644 --- a/src/ov_SC02_027/ov_SC02_027_jr_8012ACE0.c +++ b/src/ov_SC02_027/ov_SC02_027_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018B7E4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018B7E4); gte_stlvnl(D_8018B7E8); pc0 = D_8018B7E4; diff --git a/src/ov_SC02_027/ov_SC02_027_jr_8017D898.c b/src/ov_SC02_027/ov_SC02_027_jr_8017D898.c index ca18300b25..f687274bc1 100644 --- a/src/ov_SC02_027/ov_SC02_027_jr_8017D898.c +++ b/src/ov_SC02_027/ov_SC02_027_jr_8017D898.c @@ -2689,13 +2689,6 @@ extern void func_8017D5DC(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC02_028/ov_SC02_028_jr_8012ACE0.c b/src/ov_SC02_028/ov_SC02_028_jr_8012ACE0.c index 1faad00845..c0f43ae811 100644 --- a/src/ov_SC02_028/ov_SC02_028_jr_8012ACE0.c +++ b/src/ov_SC02_028/ov_SC02_028_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018B9E8) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018B9E8); gte_stlvnl(D_8018B9EC); pc0 = D_8018B9E8; diff --git a/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c b/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c index 77423c7ddb..3a7d1d702b 100644 --- a/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c +++ b/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c @@ -2689,13 +2689,6 @@ extern void func_8017D5DC(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC02_031/ov_SC02_031_jr_8012ACE0.c b/src/ov_SC02_031/ov_SC02_031_jr_8012ACE0.c index 4845a1ddea..0ff657cb33 100644 --- a/src/ov_SC02_031/ov_SC02_031_jr_8012ACE0.c +++ b/src/ov_SC02_031/ov_SC02_031_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80185214) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80185214); gte_stlvnl(D_80185218); pc0 = D_80185214; diff --git a/src/ov_SC02_031/ov_SC02_031_jr_8017AE2C.c b/src/ov_SC02_031/ov_SC02_031_jr_8017AE2C.c index 1b9f8efc7f..24d3adc7cd 100644 --- a/src/ov_SC02_031/ov_SC02_031_jr_8017AE2C.c +++ b/src/ov_SC02_031/ov_SC02_031_jr_8017AE2C.c @@ -7951,14 +7951,7 @@ void func_80183DC0(void *a0) { * in src/ov_SC03_099/ov_SC03_099_jr_8012ACE0.c:2737. */ { s32 *p = &d.vx; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(p) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(p); gte_stlvnl(p); } diff --git a/src/ov_SC02_035/ov_SC02_035_jr_8012ACE0.c b/src/ov_SC02_035/ov_SC02_035_jr_8012ACE0.c index f2f62d2239..41fafe808a 100644 --- a/src/ov_SC02_035/ov_SC02_035_jr_8012ACE0.c +++ b/src/ov_SC02_035/ov_SC02_035_jr_8012ACE0.c @@ -2404,14 +2404,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80184A74) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80184A74); gte_stlvnl(D_80184A78); pc0 = D_80184A74; diff --git a/src/ov_SC02_035/ov_SC02_035_jr_8017BEBC.c b/src/ov_SC02_035/ov_SC02_035_jr_8017BEBC.c index 32943f7123..e8bd4dac5f 100644 --- a/src/ov_SC02_035/ov_SC02_035_jr_8017BEBC.c +++ b/src/ov_SC02_035/ov_SC02_035_jr_8017BEBC.c @@ -2678,13 +2678,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC02_037/ov_SC02_037_jr_80131340.c b/src/ov_SC02_037/ov_SC02_037_jr_80131340.c index 92be8780e9..df03442ca5 100644 --- a/src/ov_SC02_037/ov_SC02_037_jr_80131340.c +++ b/src/ov_SC02_037/ov_SC02_037_jr_80131340.c @@ -1644,14 +1644,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801841B0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801841B0); gte_stlvnl(D_801841B4); pc0 = D_801841B0; diff --git a/src/ov_SC02_039/ov_SC02_039_jr_8012ACE0.c b/src/ov_SC02_039/ov_SC02_039_jr_8012ACE0.c index 8185ea4b1b..89b23fd7fe 100644 --- a/src/ov_SC02_039/ov_SC02_039_jr_8012ACE0.c +++ b/src/ov_SC02_039/ov_SC02_039_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F6A0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F6A0); gte_stlvnl(D_8017F6A4); pc0 = D_8017F6A0; diff --git a/src/ov_SC02_041/ov_SC02_041_jr_8012ACE0.c b/src/ov_SC02_041/ov_SC02_041_jr_8012ACE0.c index d1c7e383f2..5b1ef6f4dd 100644 --- a/src/ov_SC02_041/ov_SC02_041_jr_8012ACE0.c +++ b/src/ov_SC02_041/ov_SC02_041_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80185370) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80185370); gte_stlvnl(D_80185374); pc0 = D_80185370; diff --git a/src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c b/src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c index 7c1a7c0bfd..7bf7dac98e 100644 --- a/src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c +++ b/src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c @@ -2679,13 +2679,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_001/ov_SC03_001_jr_8012ACE0.c b/src/ov_SC03_001/ov_SC03_001_jr_8012ACE0.c index 5b18595543..c94dc6d7d5 100644 --- a/src/ov_SC03_001/ov_SC03_001_jr_8012ACE0.c +++ b/src/ov_SC03_001/ov_SC03_001_jr_8012ACE0.c @@ -2403,14 +2403,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018DAB0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018DAB0); gte_stlvnl(D_8018DAB4); pc0 = D_8018DAB0; diff --git a/src/ov_SC03_001/ov_SC03_001_jr_8013C98C.c b/src/ov_SC03_001/ov_SC03_001_jr_8013C98C.c index f7bf45720d..fa7f9e2039 100644 --- a/src/ov_SC03_001/ov_SC03_001_jr_8013C98C.c +++ b/src/ov_SC03_001/ov_SC03_001_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c b/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c index 46869df06d..69cc896bef 100644 --- a/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c +++ b/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c @@ -3650,13 +3650,6 @@ extern void func_80146C3C(); // K&R: ? of 1 args (P37 rung D t4_D23) #include "../shared/ov/func_8017C6AC.h" -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) #include "../shared/ov/func_8017C710__t3f3d6beb.h" diff --git a/src/ov_SC03_002/ov_SC03_002_jr_8012ACE0.c b/src/ov_SC03_002/ov_SC03_002_jr_8012ACE0.c index 1c445a404b..0d1c807046 100644 --- a/src/ov_SC03_002/ov_SC03_002_jr_8012ACE0.c +++ b/src/ov_SC03_002/ov_SC03_002_jr_8012ACE0.c @@ -2407,14 +2407,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80185AA0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80185AA0); gte_stlvnl(D_80185AA4); pc0 = D_80185AA0; diff --git a/src/ov_SC03_002/ov_SC03_002_jr_8013C98C.c b/src/ov_SC03_002/ov_SC03_002_jr_8013C98C.c index b25ee1cb0e..0c3cfc152b 100644 --- a/src/ov_SC03_002/ov_SC03_002_jr_8013C98C.c +++ b/src/ov_SC03_002/ov_SC03_002_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_003/ov_SC03_003_jr_8012ACE0.c b/src/ov_SC03_003/ov_SC03_003_jr_8012ACE0.c index ae12a31095..134375986b 100644 --- a/src/ov_SC03_003/ov_SC03_003_jr_8012ACE0.c +++ b/src/ov_SC03_003/ov_SC03_003_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F868) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F868); gte_stlvnl(D_8017F86C); pc0 = D_8017F868; diff --git a/src/ov_SC03_003/ov_SC03_003_jr_8013C98C.c b/src/ov_SC03_003/ov_SC03_003_jr_8013C98C.c index 564cc6100e..0df9847197 100644 --- a/src/ov_SC03_003/ov_SC03_003_jr_8013C98C.c +++ b/src/ov_SC03_003/ov_SC03_003_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_006/ov_SC03_006_jr_8012ACE0.c b/src/ov_SC03_006/ov_SC03_006_jr_8012ACE0.c index be5fbb99b1..9d5beb93fc 100644 --- a/src/ov_SC03_006/ov_SC03_006_jr_8012ACE0.c +++ b/src/ov_SC03_006/ov_SC03_006_jr_8012ACE0.c @@ -2407,14 +2407,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018CB84) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018CB84); gte_stlvnl(D_8018CB88); pc0 = D_8018CB84; diff --git a/src/ov_SC03_006/ov_SC03_006_jr_8013C98C.c b/src/ov_SC03_006/ov_SC03_006_jr_8013C98C.c index 01511064cb..630469abc1 100644 --- a/src/ov_SC03_006/ov_SC03_006_jr_8013C98C.c +++ b/src/ov_SC03_006/ov_SC03_006_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_007/ov_SC03_007_jr_8012ACE0.c b/src/ov_SC03_007/ov_SC03_007_jr_8012ACE0.c index b1cdd2ea70..09d639b0b3 100644 --- a/src/ov_SC03_007/ov_SC03_007_jr_8012ACE0.c +++ b/src/ov_SC03_007/ov_SC03_007_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018797C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018797C); gte_stlvnl(D_80187980); pc0 = D_8018797C; diff --git a/src/ov_SC03_007/ov_SC03_007_jr_8013C98C.c b/src/ov_SC03_007/ov_SC03_007_jr_8013C98C.c index 3ac1fd7d7b..cd686d73f4 100644 --- a/src/ov_SC03_007/ov_SC03_007_jr_8013C98C.c +++ b/src/ov_SC03_007/ov_SC03_007_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_010/ov_SC03_010_jr_8012ACE0.c b/src/ov_SC03_010/ov_SC03_010_jr_8012ACE0.c index 707e52f706..74d2257cde 100644 --- a/src/ov_SC03_010/ov_SC03_010_jr_8012ACE0.c +++ b/src/ov_SC03_010/ov_SC03_010_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018049C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018049C); gte_stlvnl(D_801804A0); pc0 = D_8018049C; diff --git a/src/ov_SC03_010/ov_SC03_010_jr_8013C98C.c b/src/ov_SC03_010/ov_SC03_010_jr_8013C98C.c index 0e155e4451..6196d286d9 100644 --- a/src/ov_SC03_010/ov_SC03_010_jr_8013C98C.c +++ b/src/ov_SC03_010/ov_SC03_010_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_010/ov_SC03_010_jr_8017C730.c b/src/ov_SC03_010/ov_SC03_010_jr_8017C730.c index f3baf2286c..62ebe2595b 100644 --- a/src/ov_SC03_010/ov_SC03_010_jr_8017C730.c +++ b/src/ov_SC03_010/ov_SC03_010_jr_8017C730.c @@ -2847,13 +2847,6 @@ extern void func_8017C214(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -4002,71 +3995,7 @@ void func_8017F214(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC03_011/ov_SC03_011_jr_8012ACE0.c b/src/ov_SC03_011/ov_SC03_011_jr_8012ACE0.c index ad8f536b7c..fef070f135 100644 --- a/src/ov_SC03_011/ov_SC03_011_jr_8012ACE0.c +++ b/src/ov_SC03_011/ov_SC03_011_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018180C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018180C); gte_stlvnl(D_80181810); pc0 = D_8018180C; diff --git a/src/ov_SC03_011/ov_SC03_011_jr_8013C98C.c b/src/ov_SC03_011/ov_SC03_011_jr_8013C98C.c index 86a8d9c5fb..aa922e8190 100644 --- a/src/ov_SC03_011/ov_SC03_011_jr_8013C98C.c +++ b/src/ov_SC03_011/ov_SC03_011_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_012/ov_SC03_012_jr_8012ACE0.c b/src/ov_SC03_012/ov_SC03_012_jr_8012ACE0.c index 1afa92b495..3394c49b40 100644 --- a/src/ov_SC03_012/ov_SC03_012_jr_8012ACE0.c +++ b/src/ov_SC03_012/ov_SC03_012_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017E6EC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017E6EC); gte_stlvnl(D_8017E6F0); pc0 = D_8017E6EC; diff --git a/src/ov_SC03_012/ov_SC03_012_jr_8013C98C.c b/src/ov_SC03_012/ov_SC03_012_jr_8013C98C.c index e6d7296c79..c2ed3ced1f 100644 --- a/src/ov_SC03_012/ov_SC03_012_jr_8013C98C.c +++ b/src/ov_SC03_012/ov_SC03_012_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_013/ov_SC03_013_jr_8012ACE0.c b/src/ov_SC03_013/ov_SC03_013_jr_8012ACE0.c index 1061f9026d..84afafba4f 100644 --- a/src/ov_SC03_013/ov_SC03_013_jr_8012ACE0.c +++ b/src/ov_SC03_013/ov_SC03_013_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801814D4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801814D4); gte_stlvnl(D_801814D8); pc0 = D_801814D4; diff --git a/src/ov_SC03_013/ov_SC03_013_jr_8013C98C.c b/src/ov_SC03_013/ov_SC03_013_jr_8013C98C.c index 85d77bcda0..ffe567d4ee 100644 --- a/src/ov_SC03_013/ov_SC03_013_jr_8013C98C.c +++ b/src/ov_SC03_013/ov_SC03_013_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_013/ov_SC03_013_jr_8017C730.c b/src/ov_SC03_013/ov_SC03_013_jr_8017C730.c index 18cfabacbf..d9ebdd520a 100644 --- a/src/ov_SC03_013/ov_SC03_013_jr_8017C730.c +++ b/src/ov_SC03_013/ov_SC03_013_jr_8017C730.c @@ -2686,13 +2686,6 @@ extern void func_8017C214(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_013/ov_SC03_013_jr_8017FAA8.c b/src/ov_SC03_013/ov_SC03_013_jr_8017FAA8.c index 5fbcfa4c90..179e676569 100644 --- a/src/ov_SC03_013/ov_SC03_013_jr_8017FAA8.c +++ b/src/ov_SC03_013/ov_SC03_013_jr_8017FAA8.c @@ -3075,71 +3075,7 @@ void func_8017FFE8(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC03_014/ov_SC03_014_jr_8012ACE0.c b/src/ov_SC03_014/ov_SC03_014_jr_8012ACE0.c index ff71e250b8..43c9cfe404 100644 --- a/src/ov_SC03_014/ov_SC03_014_jr_8012ACE0.c +++ b/src/ov_SC03_014/ov_SC03_014_jr_8012ACE0.c @@ -2403,14 +2403,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018BB10) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018BB10); gte_stlvnl(D_8018BB14); pc0 = D_8018BB10; diff --git a/src/ov_SC03_014/ov_SC03_014_jr_8013C98C.c b/src/ov_SC03_014/ov_SC03_014_jr_8013C98C.c index 01c19d7adb..a30b425d38 100644 --- a/src/ov_SC03_014/ov_SC03_014_jr_8013C98C.c +++ b/src/ov_SC03_014/ov_SC03_014_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.c b/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.c index 7b0569a671..a5145a7d47 100644 --- a/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.c +++ b/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.c @@ -3448,11 +3448,6 @@ extern PW8017C290 D_8018EF70[]; /* GTE VARIANT `gte_rtv0tr_m`: memory beyond Sony's `gte_rtv0tr` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rtv0tr_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8017C290(int a, s16 *b, SVECTOR_8017C290 *c, SVECTOR_8017C290 *d, diff --git a/src/ov_SC03_023/ov_SC03_023_jr_8012ACE0.c b/src/ov_SC03_023/ov_SC03_023_jr_8012ACE0.c index 6cc9930b9e..585113a2b8 100644 --- a/src/ov_SC03_023/ov_SC03_023_jr_8012ACE0.c +++ b/src/ov_SC03_023/ov_SC03_023_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F48C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F48C); gte_stlvnl(D_8017F490); pc0 = D_8017F48C; diff --git a/src/ov_SC03_023/ov_SC03_023_jr_8013C98C.c b/src/ov_SC03_023/ov_SC03_023_jr_8013C98C.c index 0d6a4034cf..1a6592424b 100644 --- a/src/ov_SC03_023/ov_SC03_023_jr_8013C98C.c +++ b/src/ov_SC03_023/ov_SC03_023_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_024/ov_SC03_024_jr_8012ACE0.c b/src/ov_SC03_024/ov_SC03_024_jr_8012ACE0.c index cdfa91da79..84c2753805 100644 --- a/src/ov_SC03_024/ov_SC03_024_jr_8012ACE0.c +++ b/src/ov_SC03_024/ov_SC03_024_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801874B0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801874B0); gte_stlvnl(D_801874B4); pc0 = D_801874B0; diff --git a/src/ov_SC03_024/ov_SC03_024_jr_8013C98C.c b/src/ov_SC03_024/ov_SC03_024_jr_8013C98C.c index 2c73035b6e..9277b4749e 100644 --- a/src/ov_SC03_024/ov_SC03_024_jr_8013C98C.c +++ b/src/ov_SC03_024/ov_SC03_024_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_028/ov_SC03_028_jr_8012ACE0.c b/src/ov_SC03_028/ov_SC03_028_jr_8012ACE0.c index 25f8116c5d..308abcfb41 100644 --- a/src/ov_SC03_028/ov_SC03_028_jr_8012ACE0.c +++ b/src/ov_SC03_028/ov_SC03_028_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018BF7C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018BF7C); gte_stlvnl(D_8018BF80); pc0 = D_8018BF7C; diff --git a/src/ov_SC03_028/ov_SC03_028_jr_8013C98C.c b/src/ov_SC03_028/ov_SC03_028_jr_8013C98C.c index c56e672b4f..d4737796e2 100644 --- a/src/ov_SC03_028/ov_SC03_028_jr_8013C98C.c +++ b/src/ov_SC03_028/ov_SC03_028_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_029/ov_SC03_029_jr_8012ACE0.c b/src/ov_SC03_029/ov_SC03_029_jr_8012ACE0.c index ea5aee7fe1..3c19e388d9 100644 --- a/src/ov_SC03_029/ov_SC03_029_jr_8012ACE0.c +++ b/src/ov_SC03_029/ov_SC03_029_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80187DB4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80187DB4); gte_stlvnl(D_80187DB8); pc0 = D_80187DB4; diff --git a/src/ov_SC03_029/ov_SC03_029_jr_8013C98C.c b/src/ov_SC03_029/ov_SC03_029_jr_8013C98C.c index c4a67b0101..079c6ae771 100644 --- a/src/ov_SC03_029/ov_SC03_029_jr_8013C98C.c +++ b/src/ov_SC03_029/ov_SC03_029_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_029/ov_SC03_029_jr_80186A34.c b/src/ov_SC03_029/ov_SC03_029_jr_80186A34.c index 1990e54385..734448001a 100644 --- a/src/ov_SC03_029/ov_SC03_029_jr_80186A34.c +++ b/src/ov_SC03_029/ov_SC03_029_jr_80186A34.c @@ -3605,71 +3605,7 @@ void func_80187318(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC03_030/ov_SC03_030_jr_8012ACE0.c b/src/ov_SC03_030/ov_SC03_030_jr_8012ACE0.c index fbd6fa8318..2683ba57c0 100644 --- a/src/ov_SC03_030/ov_SC03_030_jr_8012ACE0.c +++ b/src/ov_SC03_030/ov_SC03_030_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801823F0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801823F0); gte_stlvnl(D_801823F4); pc0 = D_801823F0; diff --git a/src/ov_SC03_030/ov_SC03_030_jr_8013C98C.c b/src/ov_SC03_030/ov_SC03_030_jr_8013C98C.c index cc0e7bad4d..6e6ed1a26c 100644 --- a/src/ov_SC03_030/ov_SC03_030_jr_8013C98C.c +++ b/src/ov_SC03_030/ov_SC03_030_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_031/ov_SC03_031_jr_8012ACE0.c b/src/ov_SC03_031/ov_SC03_031_jr_8012ACE0.c index 12962e8efc..042f7ee28c 100644 --- a/src/ov_SC03_031/ov_SC03_031_jr_8012ACE0.c +++ b/src/ov_SC03_031/ov_SC03_031_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018290C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018290C); gte_stlvnl(D_80182910); pc0 = D_8018290C; diff --git a/src/ov_SC03_031/ov_SC03_031_jr_8013C98C.c b/src/ov_SC03_031/ov_SC03_031_jr_8013C98C.c index 78fef6db59..6e309e825f 100644 --- a/src/ov_SC03_031/ov_SC03_031_jr_8013C98C.c +++ b/src/ov_SC03_031/ov_SC03_031_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_031/ov_SC03_031_jr_8017DB5C.c b/src/ov_SC03_031/ov_SC03_031_jr_8017DB5C.c index c581d49071..089a00a74d 100644 --- a/src/ov_SC03_031/ov_SC03_031_jr_8017DB5C.c +++ b/src/ov_SC03_031/ov_SC03_031_jr_8017DB5C.c @@ -3637,23 +3637,8 @@ void func_8017F95C(s32 a0) { mat = *(Mat32 *)&D_800AE620; RotMatrixX(-0x300, &mat); - __asm__ __volatile__( - "lw $12, 0(%0)\n" - "lw $13, 4(%0)\n" - "ctc2 $12, $0\n" - "ctc2 $13, $1\n" - "lw $12, 8(%0)\n" - "lw $13, 12(%0)\n" - "lw $14, 16(%0)\n" - "ctc2 $12, $2\n" - "ctc2 $13, $3\n" - "ctc2 $14, $4\n" : : "r"(&mat) : "$12", "$13", "$14" ); - __asm__ __volatile__( - "lwc2 $0, 0(%0)\n" - "lwc2 $1, 4(%0)\n" - "nop\n" - "nop\n" - "mvmva 1, 0, 0, 3, 0\n" : : "r"(&D_8018618C) ); + gte_SetRotMatrix(&mat); + gte_ldv0(&D_8018618C); gte_rtv0(); gte_stsv(buf); ((Unkstruct_800B5CB8 *)a0)->unk6 += buf[0]; diff --git a/src/ov_SC03_089/ov_SC03_089_jr_8012ACE0.c b/src/ov_SC03_089/ov_SC03_089_jr_8012ACE0.c index 7f255a492d..7fb3de293c 100644 --- a/src/ov_SC03_089/ov_SC03_089_jr_8012ACE0.c +++ b/src/ov_SC03_089/ov_SC03_089_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80189C08) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80189C08); gte_stlvnl(D_80189C0C); pc0 = D_80189C08; diff --git a/src/ov_SC03_089/ov_SC03_089_jr_8013C98C.c b/src/ov_SC03_089/ov_SC03_089_jr_8013C98C.c index c065b74a86..cf89a2fa47 100644 --- a/src/ov_SC03_089/ov_SC03_089_jr_8013C98C.c +++ b/src/ov_SC03_089/ov_SC03_089_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c b/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c index 1132243a32..2265f73122 100644 --- a/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c +++ b/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c @@ -2686,13 +2686,6 @@ extern void func_8017C7C4(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_090/ov_SC03_090_jr_8012ACE0.c b/src/ov_SC03_090/ov_SC03_090_jr_8012ACE0.c index ecb0b35e91..cd0b0df7da 100644 --- a/src/ov_SC03_090/ov_SC03_090_jr_8012ACE0.c +++ b/src/ov_SC03_090/ov_SC03_090_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018C02C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018C02C); gte_stlvnl(D_8018C030); pc0 = D_8018C02C; diff --git a/src/ov_SC03_090/ov_SC03_090_jr_8013C98C.c b/src/ov_SC03_090/ov_SC03_090_jr_8013C98C.c index 125ae9fdf1..757a3ea9ff 100644 --- a/src/ov_SC03_090/ov_SC03_090_jr_8013C98C.c +++ b/src/ov_SC03_090/ov_SC03_090_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c b/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c index 6b81ad6a08..1ac25dbfd2 100644 --- a/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c +++ b/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c @@ -2683,13 +2683,6 @@ extern void func_8017C7C4(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_091/ov_SC03_091_jr_8012ACE0.c b/src/ov_SC03_091/ov_SC03_091_jr_8012ACE0.c index bb0340f37c..899a4e115f 100644 --- a/src/ov_SC03_091/ov_SC03_091_jr_8012ACE0.c +++ b/src/ov_SC03_091/ov_SC03_091_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018CED4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018CED4); gte_stlvnl(D_8018CED8); pc0 = D_8018CED4; diff --git a/src/ov_SC03_091/ov_SC03_091_jr_8013C98C.c b/src/ov_SC03_091/ov_SC03_091_jr_8013C98C.c index 7629cbda74..cf83859a42 100644 --- a/src/ov_SC03_091/ov_SC03_091_jr_8013C98C.c +++ b/src/ov_SC03_091/ov_SC03_091_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_091/ov_SC03_091_jr_8017D898.c b/src/ov_SC03_091/ov_SC03_091_jr_8017D898.c index 56d4fa8710..7c6bc5976e 100644 --- a/src/ov_SC03_091/ov_SC03_091_jr_8017D898.c +++ b/src/ov_SC03_091/ov_SC03_091_jr_8017D898.c @@ -2703,13 +2703,6 @@ extern void func_8017D5DC(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_092/ov_SC03_092_jr_8012ACE0.c b/src/ov_SC03_092/ov_SC03_092_jr_8012ACE0.c index fe7c47d7f3..c1e4d05059 100644 --- a/src/ov_SC03_092/ov_SC03_092_jr_8012ACE0.c +++ b/src/ov_SC03_092/ov_SC03_092_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801852A4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801852A4); gte_stlvnl(D_801852A8); pc0 = D_801852A4; diff --git a/src/ov_SC03_092/ov_SC03_092_jr_8013C98C.c b/src/ov_SC03_092/ov_SC03_092_jr_8013C98C.c index 20be0262c3..3e92718f36 100644 --- a/src/ov_SC03_092/ov_SC03_092_jr_8013C98C.c +++ b/src/ov_SC03_092/ov_SC03_092_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_093/ov_SC03_093_jr_8012ACE0.c b/src/ov_SC03_093/ov_SC03_093_jr_8012ACE0.c index 75a7b0aad8..d3a5268fb5 100644 --- a/src/ov_SC03_093/ov_SC03_093_jr_8012ACE0.c +++ b/src/ov_SC03_093/ov_SC03_093_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018647C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018647C); gte_stlvnl(D_80186480); pc0 = D_8018647C; diff --git a/src/ov_SC03_093/ov_SC03_093_jr_8013C98C.c b/src/ov_SC03_093/ov_SC03_093_jr_8013C98C.c index 54aa79b8b0..4bbabf5d33 100644 --- a/src/ov_SC03_093/ov_SC03_093_jr_8013C98C.c +++ b/src/ov_SC03_093/ov_SC03_093_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_093/ov_SC03_093_jr_8017D898.c b/src/ov_SC03_093/ov_SC03_093_jr_8017D898.c index 85e16ca76c..debaeeac12 100644 --- a/src/ov_SC03_093/ov_SC03_093_jr_8017D898.c +++ b/src/ov_SC03_093/ov_SC03_093_jr_8017D898.c @@ -2686,13 +2686,6 @@ extern void func_8017D5DC(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_094/ov_SC03_094_jr_8012ACE0.c b/src/ov_SC03_094/ov_SC03_094_jr_8012ACE0.c index 19a12aa0af..58219ce4cb 100644 --- a/src/ov_SC03_094/ov_SC03_094_jr_8012ACE0.c +++ b/src/ov_SC03_094/ov_SC03_094_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80187E78) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80187E78); gte_stlvnl(D_80187E7C); pc0 = D_80187E78; diff --git a/src/ov_SC03_094/ov_SC03_094_jr_8013C98C.c b/src/ov_SC03_094/ov_SC03_094_jr_8013C98C.c index 35ee145130..c27d94b6c7 100644 --- a/src/ov_SC03_094/ov_SC03_094_jr_8013C98C.c +++ b/src/ov_SC03_094/ov_SC03_094_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_094/ov_SC03_094_jr_8017BEBC.c b/src/ov_SC03_094/ov_SC03_094_jr_8017BEBC.c index e22c3b65bc..20d9e30714 100644 --- a/src/ov_SC03_094/ov_SC03_094_jr_8017BEBC.c +++ b/src/ov_SC03_094/ov_SC03_094_jr_8017BEBC.c @@ -2674,13 +2674,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_095/ov_SC03_095_jr_8012ACE0.c b/src/ov_SC03_095/ov_SC03_095_jr_8012ACE0.c index 541afbe830..f2eba2abb8 100644 --- a/src/ov_SC03_095/ov_SC03_095_jr_8012ACE0.c +++ b/src/ov_SC03_095/ov_SC03_095_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801814D8) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801814D8); gte_stlvnl(D_801814DC); pc0 = D_801814D8; diff --git a/src/ov_SC03_095/ov_SC03_095_jr_8013C98C.c b/src/ov_SC03_095/ov_SC03_095_jr_8013C98C.c index e58c7616f7..37b513c3e8 100644 --- a/src/ov_SC03_095/ov_SC03_095_jr_8013C98C.c +++ b/src/ov_SC03_095/ov_SC03_095_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_095/ov_SC03_095_jr_8017BEBC.c b/src/ov_SC03_095/ov_SC03_095_jr_8017BEBC.c index ce88fc486d..0d68175338 100644 --- a/src/ov_SC03_095/ov_SC03_095_jr_8017BEBC.c +++ b/src/ov_SC03_095/ov_SC03_095_jr_8017BEBC.c @@ -2677,13 +2677,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_096/ov_SC03_096_jr_8012ACE0.c b/src/ov_SC03_096/ov_SC03_096_jr_8012ACE0.c index 8854b1f686..69a135d828 100644 --- a/src/ov_SC03_096/ov_SC03_096_jr_8012ACE0.c +++ b/src/ov_SC03_096/ov_SC03_096_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80181058) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80181058); gte_stlvnl(D_8018105C); pc0 = D_80181058; diff --git a/src/ov_SC03_096/ov_SC03_096_jr_8013C98C.c b/src/ov_SC03_096/ov_SC03_096_jr_8013C98C.c index 41f4815c4a..bb8db08442 100644 --- a/src/ov_SC03_096/ov_SC03_096_jr_8013C98C.c +++ b/src/ov_SC03_096/ov_SC03_096_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_096/ov_SC03_096_jr_8017BEBC.c b/src/ov_SC03_096/ov_SC03_096_jr_8017BEBC.c index 5372922a90..7fa3d7dac7 100644 --- a/src/ov_SC03_096/ov_SC03_096_jr_8017BEBC.c +++ b/src/ov_SC03_096/ov_SC03_096_jr_8017BEBC.c @@ -2677,13 +2677,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_097/ov_SC03_097_jr_8012ACE0.c b/src/ov_SC03_097/ov_SC03_097_jr_8012ACE0.c index 65e1df2804..f0a70943a7 100644 --- a/src/ov_SC03_097/ov_SC03_097_jr_8012ACE0.c +++ b/src/ov_SC03_097/ov_SC03_097_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80186438) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80186438); gte_stlvnl(D_8018643C); pc0 = D_80186438; diff --git a/src/ov_SC03_097/ov_SC03_097_jr_8013C98C.c b/src/ov_SC03_097/ov_SC03_097_jr_8013C98C.c index e2d4fa3fc7..e1f8b77c07 100644 --- a/src/ov_SC03_097/ov_SC03_097_jr_8013C98C.c +++ b/src/ov_SC03_097/ov_SC03_097_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c b/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c index 14f3ad3a06..791bc0b738 100644 --- a/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c +++ b/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c @@ -2685,13 +2685,6 @@ extern void func_8017D5DC(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_098/ov_SC03_098_jr_8012ACE0.c b/src/ov_SC03_098/ov_SC03_098_jr_8012ACE0.c index b8b9081f09..7214166143 100644 --- a/src/ov_SC03_098/ov_SC03_098_jr_8012ACE0.c +++ b/src/ov_SC03_098/ov_SC03_098_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801858C4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801858C4); gte_stlvnl(D_801858C8); pc0 = D_801858C4; diff --git a/src/ov_SC03_098/ov_SC03_098_jr_8013C98C.c b/src/ov_SC03_098/ov_SC03_098_jr_8013C98C.c index d05ac2cf39..417af8f835 100644 --- a/src/ov_SC03_098/ov_SC03_098_jr_8013C98C.c +++ b/src/ov_SC03_098/ov_SC03_098_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_098/ov_SC03_098_jr_8017D898.c b/src/ov_SC03_098/ov_SC03_098_jr_8017D898.c index 99d1e61fe3..a979d5c1aa 100644 --- a/src/ov_SC03_098/ov_SC03_098_jr_8017D898.c +++ b/src/ov_SC03_098/ov_SC03_098_jr_8017D898.c @@ -2687,13 +2687,6 @@ extern void func_8017D5DC(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_099/ov_SC03_099_jr_8012ACE0.c b/src/ov_SC03_099/ov_SC03_099_jr_8012ACE0.c index 445f3f5e49..b8251b00ea 100644 --- a/src/ov_SC03_099/ov_SC03_099_jr_8012ACE0.c +++ b/src/ov_SC03_099/ov_SC03_099_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801839C4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801839C4); gte_stlvnl(D_801839C8); pc0 = D_801839C4; diff --git a/src/ov_SC03_099/ov_SC03_099_jr_8013C98C.c b/src/ov_SC03_099/ov_SC03_099_jr_8013C98C.c index a7b630f430..2c24cbf618 100644 --- a/src/ov_SC03_099/ov_SC03_099_jr_8013C98C.c +++ b/src/ov_SC03_099/ov_SC03_099_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_099/ov_SC03_099_jr_8017BEBC.c b/src/ov_SC03_099/ov_SC03_099_jr_8017BEBC.c index 65c4b89472..18f2305704 100644 --- a/src/ov_SC03_099/ov_SC03_099_jr_8017BEBC.c +++ b/src/ov_SC03_099/ov_SC03_099_jr_8017BEBC.c @@ -2679,13 +2679,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_100/ov_SC03_100_jr_8012ACE0.c b/src/ov_SC03_100/ov_SC03_100_jr_8012ACE0.c index 445e25d6ba..8400594807 100644 --- a/src/ov_SC03_100/ov_SC03_100_jr_8012ACE0.c +++ b/src/ov_SC03_100/ov_SC03_100_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80184E90) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80184E90); gte_stlvnl(D_80184E94); pc0 = D_80184E90; diff --git a/src/ov_SC03_100/ov_SC03_100_jr_8013C98C.c b/src/ov_SC03_100/ov_SC03_100_jr_8013C98C.c index 514bba1ac1..bb41c270ae 100644 --- a/src/ov_SC03_100/ov_SC03_100_jr_8013C98C.c +++ b/src/ov_SC03_100/ov_SC03_100_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_100/ov_SC03_100_jr_8017D898.c b/src/ov_SC03_100/ov_SC03_100_jr_8017D898.c index 0313788e3f..beab615198 100644 --- a/src/ov_SC03_100/ov_SC03_100_jr_8017D898.c +++ b/src/ov_SC03_100/ov_SC03_100_jr_8017D898.c @@ -2687,13 +2687,6 @@ extern void func_8017D5DC(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_101/ov_SC03_101_jr_8012ACE0.c b/src/ov_SC03_101/ov_SC03_101_jr_8012ACE0.c index 41a5dd2f5c..08ee1ebf3d 100644 --- a/src/ov_SC03_101/ov_SC03_101_jr_8012ACE0.c +++ b/src/ov_SC03_101/ov_SC03_101_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80183E6C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80183E6C); gte_stlvnl(D_80183E70); pc0 = D_80183E6C; diff --git a/src/ov_SC03_101/ov_SC03_101_jr_8013C98C.c b/src/ov_SC03_101/ov_SC03_101_jr_8013C98C.c index 50f7fb08dc..9f0043ec1a 100644 --- a/src/ov_SC03_101/ov_SC03_101_jr_8013C98C.c +++ b/src/ov_SC03_101/ov_SC03_101_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c b/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c index 9d15139205..2b1f7e3f0b 100644 --- a/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c +++ b/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c @@ -2687,13 +2687,6 @@ extern void func_8017C7C4(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_102/ov_SC03_102_jr_8012ACE0.c b/src/ov_SC03_102/ov_SC03_102_jr_8012ACE0.c index 2e9a9e0252..414bf697ff 100644 --- a/src/ov_SC03_102/ov_SC03_102_jr_8012ACE0.c +++ b/src/ov_SC03_102/ov_SC03_102_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80186724) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80186724); gte_stlvnl(D_80186728); pc0 = D_80186724; diff --git a/src/ov_SC03_102/ov_SC03_102_jr_8013C98C.c b/src/ov_SC03_102/ov_SC03_102_jr_8013C98C.c index 80e3e878aa..aa2252efae 100644 --- a/src/ov_SC03_102/ov_SC03_102_jr_8013C98C.c +++ b/src/ov_SC03_102/ov_SC03_102_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_103/ov_SC03_103_jr_8012ACE0.c b/src/ov_SC03_103/ov_SC03_103_jr_8012ACE0.c index 26bcfb139a..30c1c46409 100644 --- a/src/ov_SC03_103/ov_SC03_103_jr_8012ACE0.c +++ b/src/ov_SC03_103/ov_SC03_103_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801846D4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801846D4); gte_stlvnl(D_801846D8); pc0 = D_801846D4; diff --git a/src/ov_SC03_103/ov_SC03_103_jr_8013C98C.c b/src/ov_SC03_103/ov_SC03_103_jr_8013C98C.c index 07c7417f67..b91b3675f4 100644 --- a/src/ov_SC03_103/ov_SC03_103_jr_8013C98C.c +++ b/src/ov_SC03_103/ov_SC03_103_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_103/ov_SC03_103_jr_8017C294.c b/src/ov_SC03_103/ov_SC03_103_jr_8017C294.c index 6bd849f8e5..98dbc55b40 100644 --- a/src/ov_SC03_103/ov_SC03_103_jr_8017C294.c +++ b/src/ov_SC03_103/ov_SC03_103_jr_8017C294.c @@ -2689,13 +2689,6 @@ extern void func_8017C230(int a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_104/ov_SC03_104_jr_8012ACE0.c b/src/ov_SC03_104/ov_SC03_104_jr_8012ACE0.c index 16bba457ed..dd9239973b 100644 --- a/src/ov_SC03_104/ov_SC03_104_jr_8012ACE0.c +++ b/src/ov_SC03_104/ov_SC03_104_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018B264) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018B264); gte_stlvnl(D_8018B268); pc0 = D_8018B264; diff --git a/src/ov_SC03_104/ov_SC03_104_jr_8013C98C.c b/src/ov_SC03_104/ov_SC03_104_jr_8013C98C.c index 5d94351bdd..90239ec0d1 100644 --- a/src/ov_SC03_104/ov_SC03_104_jr_8013C98C.c +++ b/src/ov_SC03_104/ov_SC03_104_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c b/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c index 1b07e7842b..5833c756c8 100644 --- a/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c +++ b/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c @@ -2694,13 +2694,6 @@ extern void func_8017C7C4(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_105/ov_SC03_105_jr_8012ACE0.c b/src/ov_SC03_105/ov_SC03_105_jr_8012ACE0.c index 41a387ecbe..58254c4f88 100644 --- a/src/ov_SC03_105/ov_SC03_105_jr_8012ACE0.c +++ b/src/ov_SC03_105/ov_SC03_105_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018A8EC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018A8EC); gte_stlvnl(D_8018A8F0); pc0 = D_8018A8EC; diff --git a/src/ov_SC03_105/ov_SC03_105_jr_8013C98C.c b/src/ov_SC03_105/ov_SC03_105_jr_8013C98C.c index 815f86d0d7..217ca31a29 100644 --- a/src/ov_SC03_105/ov_SC03_105_jr_8013C98C.c +++ b/src/ov_SC03_105/ov_SC03_105_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.c b/src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.c index 6a85403a2c..46c9d67f9b 100644 --- a/src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.c +++ b/src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.c @@ -2696,13 +2696,6 @@ extern void func_8017C114(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_107/ov_SC03_107_jr_80131340.c b/src/ov_SC03_107/ov_SC03_107_jr_80131340.c index ea76bfbf82..7c30d4737f 100644 --- a/src/ov_SC03_107/ov_SC03_107_jr_80131340.c +++ b/src/ov_SC03_107/ov_SC03_107_jr_80131340.c @@ -1645,14 +1645,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182A4C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182A4C); gte_stlvnl(D_80182A50); pc0 = D_80182A4C; diff --git a/src/ov_SC03_107/ov_SC03_107_jr_8013C98C.c b/src/ov_SC03_107/ov_SC03_107_jr_8013C98C.c index b347729462..787e798c79 100644 --- a/src/ov_SC03_107/ov_SC03_107_jr_8013C98C.c +++ b/src/ov_SC03_107/ov_SC03_107_jr_8013C98C.c @@ -1443,9 +1443,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_108/ov_SC03_108_jr_8012ACE0.c b/src/ov_SC03_108/ov_SC03_108_jr_8012ACE0.c index a48a835fe2..579108dfcc 100644 --- a/src/ov_SC03_108/ov_SC03_108_jr_8012ACE0.c +++ b/src/ov_SC03_108/ov_SC03_108_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80181244) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80181244); gte_stlvnl(D_80181248); pc0 = D_80181244; diff --git a/src/ov_SC03_108/ov_SC03_108_jr_8013C98C.c b/src/ov_SC03_108/ov_SC03_108_jr_8013C98C.c index 1c29b47413..53a79a3a96 100644 --- a/src/ov_SC03_108/ov_SC03_108_jr_8013C98C.c +++ b/src/ov_SC03_108/ov_SC03_108_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_108/ov_SC03_108_jr_8017BEBC.c b/src/ov_SC03_108/ov_SC03_108_jr_8017BEBC.c index 00ef42e916..8f7ece784a 100644 --- a/src/ov_SC03_108/ov_SC03_108_jr_8017BEBC.c +++ b/src/ov_SC03_108/ov_SC03_108_jr_8017BEBC.c @@ -2691,13 +2691,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -3916,71 +3909,7 @@ void func_8017EC04(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC03_109/ov_SC03_109_jr_8012ACE0.c b/src/ov_SC03_109/ov_SC03_109_jr_8012ACE0.c index 4b058de868..d5293b7722 100644 --- a/src/ov_SC03_109/ov_SC03_109_jr_8012ACE0.c +++ b/src/ov_SC03_109/ov_SC03_109_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017E8F0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017E8F0); gte_stlvnl(D_8017E8F4); pc0 = D_8017E8F0; diff --git a/src/ov_SC03_109/ov_SC03_109_jr_8013C98C.c b/src/ov_SC03_109/ov_SC03_109_jr_8013C98C.c index 7fb571a961..192c5fc714 100644 --- a/src/ov_SC03_109/ov_SC03_109_jr_8013C98C.c +++ b/src/ov_SC03_109/ov_SC03_109_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_109/ov_SC03_109_jr_8017C180.c b/src/ov_SC03_109/ov_SC03_109_jr_8017C180.c index 325b92953c..a332546d66 100644 --- a/src/ov_SC03_109/ov_SC03_109_jr_8017C180.c +++ b/src/ov_SC03_109/ov_SC03_109_jr_8017C180.c @@ -2684,13 +2684,6 @@ extern void func_8017C0E4(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_110/ov_SC03_110_jr_8012ACE0.c b/src/ov_SC03_110/ov_SC03_110_jr_8012ACE0.c index 599962b5b1..953c72d869 100644 --- a/src/ov_SC03_110/ov_SC03_110_jr_8012ACE0.c +++ b/src/ov_SC03_110/ov_SC03_110_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182310) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182310); gte_stlvnl(D_80182314); pc0 = D_80182310; diff --git a/src/ov_SC03_110/ov_SC03_110_jr_8013C98C.c b/src/ov_SC03_110/ov_SC03_110_jr_8013C98C.c index 9ca5d74167..351396f4b4 100644 --- a/src/ov_SC03_110/ov_SC03_110_jr_8013C98C.c +++ b/src/ov_SC03_110/ov_SC03_110_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_110/ov_SC03_110_jr_8017D898.c b/src/ov_SC03_110/ov_SC03_110_jr_8017D898.c index b2b7e05660..012e9ea44b 100644 --- a/src/ov_SC03_110/ov_SC03_110_jr_8017D898.c +++ b/src/ov_SC03_110/ov_SC03_110_jr_8017D898.c @@ -2692,13 +2692,6 @@ extern void func_8017D5DC(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_111/ov_SC03_111_jr_8012ACE0.c b/src/ov_SC03_111/ov_SC03_111_jr_8012ACE0.c index b75c1f6100..00da6d9764 100644 --- a/src/ov_SC03_111/ov_SC03_111_jr_8012ACE0.c +++ b/src/ov_SC03_111/ov_SC03_111_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80184EC4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80184EC4); gte_stlvnl(D_80184EC8); pc0 = D_80184EC4; diff --git a/src/ov_SC03_111/ov_SC03_111_jr_8013C98C.c b/src/ov_SC03_111/ov_SC03_111_jr_8013C98C.c index 7fa7efce64..887357c398 100644 --- a/src/ov_SC03_111/ov_SC03_111_jr_8013C98C.c +++ b/src/ov_SC03_111/ov_SC03_111_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_111/ov_SC03_111_jr_8017EC58.c b/src/ov_SC03_111/ov_SC03_111_jr_8017EC58.c index 1ace0e5be9..4774544257 100644 --- a/src/ov_SC03_111/ov_SC03_111_jr_8017EC58.c +++ b/src/ov_SC03_111/ov_SC03_111_jr_8017EC58.c @@ -4054,71 +4054,7 @@ void func_80181838(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC03_112/ov_SC03_112_jr_8012ACE0.c b/src/ov_SC03_112/ov_SC03_112_jr_8012ACE0.c index f49a14ed93..d1156acf1c 100644 --- a/src/ov_SC03_112/ov_SC03_112_jr_8012ACE0.c +++ b/src/ov_SC03_112/ov_SC03_112_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80185CCC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80185CCC); gte_stlvnl(D_80185CD0); pc0 = D_80185CCC; diff --git a/src/ov_SC03_112/ov_SC03_112_jr_8013C98C.c b/src/ov_SC03_112/ov_SC03_112_jr_8013C98C.c index 83307feb32..265edb3bae 100644 --- a/src/ov_SC03_112/ov_SC03_112_jr_8013C98C.c +++ b/src/ov_SC03_112/ov_SC03_112_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_112/ov_SC03_112_jr_8017C294.c b/src/ov_SC03_112/ov_SC03_112_jr_8017C294.c index 81d0221ed6..c8333968e0 100644 --- a/src/ov_SC03_112/ov_SC03_112_jr_8017C294.c +++ b/src/ov_SC03_112/ov_SC03_112_jr_8017C294.c @@ -2697,13 +2697,6 @@ extern void func_8017C230(int a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -4145,71 +4138,7 @@ void func_8017F598(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC03_112/ov_SC03_112_jr_80183AE0.c b/src/ov_SC03_112/ov_SC03_112_jr_80183AE0.c index 4107fb0c37..f260e66990 100644 --- a/src/ov_SC03_112/ov_SC03_112_jr_80183AE0.c +++ b/src/ov_SC03_112/ov_SC03_112_jr_80183AE0.c @@ -2919,27 +2919,7 @@ extern s32 func_80047948(s32 a0); extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012C218(void *a0); /* GTE VARIANT `gte_SetRotMatrix_m`: memory beyond Sony's `gte_SetRotMatrix` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_SetRotMatrix_m(r0) __asm__ __volatile__( \ - "lw $12, 0(%0)\n" \ - "lw $13, 4(%0)\n" \ - "ctc2 $12, $0\n" \ - "ctc2 $13, $1\n" \ - "lw $12, 8(%0)\n" \ - "lw $13, 12(%0)\n" \ - "lw $14, 16(%0)\n" \ - "ctc2 $12, $2\n" \ - "ctc2 $13, $3\n" \ - "ctc2 $14, $4\n" \ - : : "r"(r0) : "$12", "$13", "$14", "memory") /* GTE VARIANT `gte_SetTransMatrix_m`: memory beyond Sony's `gte_SetTransMatrix` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_SetTransMatrix_m(r0) __asm__ __volatile__( \ - "lw $12, 20(%0)\n" \ - "lw $13, 24(%0)\n" \ - "ctc2 $12, $5\n" \ - "lw $14, 28(%0)\n" \ - "ctc2 $13, $6\n" \ - "ctc2 $14, $7\n" \ - : : "r"(r0) : "$12", "$13", "$14", "memory") void func_80183EA0(s32 a0) { diff --git a/src/ov_SC03_113/ov_SC03_113_jr_8012ACE0.c b/src/ov_SC03_113/ov_SC03_113_jr_8012ACE0.c index 5080eb6704..aaffddc14d 100644 --- a/src/ov_SC03_113/ov_SC03_113_jr_8012ACE0.c +++ b/src/ov_SC03_113/ov_SC03_113_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018337C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018337C); gte_stlvnl(D_80183380); pc0 = D_8018337C; diff --git a/src/ov_SC03_113/ov_SC03_113_jr_8013C98C.c b/src/ov_SC03_113/ov_SC03_113_jr_8013C98C.c index 87f70811aa..e9ef7a24dc 100644 --- a/src/ov_SC03_113/ov_SC03_113_jr_8013C98C.c +++ b/src/ov_SC03_113/ov_SC03_113_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_113/ov_SC03_113_jr_8017C294.c b/src/ov_SC03_113/ov_SC03_113_jr_8017C294.c index 78b6902079..777a5c400f 100644 --- a/src/ov_SC03_113/ov_SC03_113_jr_8017C294.c +++ b/src/ov_SC03_113/ov_SC03_113_jr_8017C294.c @@ -2685,13 +2685,6 @@ extern void func_8017C230(int a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_114/ov_SC03_114_jr_8012ACE0.c b/src/ov_SC03_114/ov_SC03_114_jr_8012ACE0.c index fcaff81cd3..6aaf3c962e 100644 --- a/src/ov_SC03_114/ov_SC03_114_jr_8012ACE0.c +++ b/src/ov_SC03_114/ov_SC03_114_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017EFE4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017EFE4); gte_stlvnl(D_8017EFE8); pc0 = D_8017EFE4; diff --git a/src/ov_SC03_114/ov_SC03_114_jr_8013C98C.c b/src/ov_SC03_114/ov_SC03_114_jr_8013C98C.c index 9f00f35d86..042ff889e3 100644 --- a/src/ov_SC03_114/ov_SC03_114_jr_8013C98C.c +++ b/src/ov_SC03_114/ov_SC03_114_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_114/ov_SC03_114_jr_8017BEBC.c b/src/ov_SC03_114/ov_SC03_114_jr_8017BEBC.c index 3114008ed1..c7290bb0a9 100644 --- a/src/ov_SC03_114/ov_SC03_114_jr_8017BEBC.c +++ b/src/ov_SC03_114/ov_SC03_114_jr_8017BEBC.c @@ -2691,13 +2691,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_115/ov_SC03_115_jr_8012ACE0.c b/src/ov_SC03_115/ov_SC03_115_jr_8012ACE0.c index 038518d239..e5d364b49b 100644 --- a/src/ov_SC03_115/ov_SC03_115_jr_8012ACE0.c +++ b/src/ov_SC03_115/ov_SC03_115_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80180A50) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80180A50); gte_stlvnl(D_80180A54); pc0 = D_80180A50; diff --git a/src/ov_SC03_115/ov_SC03_115_jr_8013C98C.c b/src/ov_SC03_115/ov_SC03_115_jr_8013C98C.c index b02bd48955..d920a3ab25 100644 --- a/src/ov_SC03_115/ov_SC03_115_jr_8013C98C.c +++ b/src/ov_SC03_115/ov_SC03_115_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_116/ov_SC03_116_jr_8012ACE0.c b/src/ov_SC03_116/ov_SC03_116_jr_8012ACE0.c index 3e4496a241..d3c2c3e94c 100644 --- a/src/ov_SC03_116/ov_SC03_116_jr_8012ACE0.c +++ b/src/ov_SC03_116/ov_SC03_116_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182E54) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182E54); gte_stlvnl(D_80182E58); pc0 = D_80182E54; diff --git a/src/ov_SC03_116/ov_SC03_116_jr_8013C98C.c b/src/ov_SC03_116/ov_SC03_116_jr_8013C98C.c index aca3d7bb4b..4ae378b2d5 100644 --- a/src/ov_SC03_116/ov_SC03_116_jr_8013C98C.c +++ b/src/ov_SC03_116/ov_SC03_116_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_117/ov_SC03_117_jr_8012ACE0.c b/src/ov_SC03_117/ov_SC03_117_jr_8012ACE0.c index 31fbd112d2..abe7adee0f 100644 --- a/src/ov_SC03_117/ov_SC03_117_jr_8012ACE0.c +++ b/src/ov_SC03_117/ov_SC03_117_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80184E60) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80184E60); gte_stlvnl(D_80184E64); pc0 = D_80184E60; diff --git a/src/ov_SC03_117/ov_SC03_117_jr_8013C98C.c b/src/ov_SC03_117/ov_SC03_117_jr_8013C98C.c index 31650e7e46..732368977c 100644 --- a/src/ov_SC03_117/ov_SC03_117_jr_8013C98C.c +++ b/src/ov_SC03_117/ov_SC03_117_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_118/ov_SC03_118_jr_8012ACE0.c b/src/ov_SC03_118/ov_SC03_118_jr_8012ACE0.c index 117f28343b..62e2b568d5 100644 --- a/src/ov_SC03_118/ov_SC03_118_jr_8012ACE0.c +++ b/src/ov_SC03_118/ov_SC03_118_jr_8012ACE0.c @@ -2154,14 +2154,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80189F0C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80189F0C); gte_stlvnl(D_80189F10); pc0 = D_80189F0C; diff --git a/src/ov_SC03_118/ov_SC03_118_jr_8013C98C.c b/src/ov_SC03_118/ov_SC03_118_jr_8013C98C.c index bb3fcaef18..c1b218de1f 100644 --- a/src/ov_SC03_118/ov_SC03_118_jr_8013C98C.c +++ b/src/ov_SC03_118/ov_SC03_118_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_118/ov_SC03_118_jr_801863CC.c b/src/ov_SC03_118/ov_SC03_118_jr_801863CC.c index 5b6c230920..dec67b6035 100644 --- a/src/ov_SC03_118/ov_SC03_118_jr_801863CC.c +++ b/src/ov_SC03_118/ov_SC03_118_jr_801863CC.c @@ -3200,28 +3200,8 @@ extern void RotTransSV(void *a0, void *a1, void *a2); extern s32 func_8012CEB0(s32 a0, s32 a1, s32 a2); /* GTE VARIANT `gte_SetRotMatrix_m`: memory beyond Sony's `gte_SetRotMatrix` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_SetRotMatrix_m(r0) __asm__ __volatile__( \ - "lw $12, 0(%0)\n" \ - "lw $13, 4(%0)\n" \ - "ctc2 $12, $0\n" \ - "ctc2 $13, $1\n" \ - "lw $12, 8(%0)\n" \ - "lw $13, 12(%0)\n" \ - "lw $14, 16(%0)\n" \ - "ctc2 $12, $2\n" \ - "ctc2 $13, $3\n" \ - "ctc2 $14, $4\n" \ - : : "r"(r0) : "$12", "$13", "$14", "memory") /* GTE VARIANT `gte_SetTransMatrix_m`: memory beyond Sony's `gte_SetTransMatrix` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_SetTransMatrix_m(r0) __asm__ __volatile__( \ - "lw $12, 20(%0)\n" \ - "lw $13, 24(%0)\n" \ - "ctc2 $12, $5\n" \ - "lw $14, 28(%0)\n" \ - "ctc2 $13, $6\n" \ - "ctc2 $14, $7\n" \ - : : "r"(r0) : "$12", "$13", "$14", "memory") void func_80186B78(s32 a0) { diff --git a/src/ov_SC03_121/ov_SC03_121_jr_8012ACE0.c b/src/ov_SC03_121/ov_SC03_121_jr_8012ACE0.c index 179e3889e4..69022021fb 100644 --- a/src/ov_SC03_121/ov_SC03_121_jr_8012ACE0.c +++ b/src/ov_SC03_121/ov_SC03_121_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182728) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182728); gte_stlvnl(D_8018272C); pc0 = D_80182728; diff --git a/src/ov_SC03_121/ov_SC03_121_jr_8013C98C.c b/src/ov_SC03_121/ov_SC03_121_jr_8013C98C.c index 287b9a46e1..53fa931564 100644 --- a/src/ov_SC03_121/ov_SC03_121_jr_8013C98C.c +++ b/src/ov_SC03_121/ov_SC03_121_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_121/ov_SC03_121_jr_8017BEBC.c b/src/ov_SC03_121/ov_SC03_121_jr_8017BEBC.c index efd6e655e7..a32260353a 100644 --- a/src/ov_SC03_121/ov_SC03_121_jr_8017BEBC.c +++ b/src/ov_SC03_121/ov_SC03_121_jr_8017BEBC.c @@ -2691,13 +2691,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC03_124/ov_SC03_124_jr_8012ACE0.c b/src/ov_SC03_124/ov_SC03_124_jr_8012ACE0.c index e79508cead..56f8e12fb1 100644 --- a/src/ov_SC03_124/ov_SC03_124_jr_8012ACE0.c +++ b/src/ov_SC03_124/ov_SC03_124_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018B154) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018B154); gte_stlvnl(D_8018B158); pc0 = D_8018B154; diff --git a/src/ov_SC03_124/ov_SC03_124_jr_8013C98C.c b/src/ov_SC03_124/ov_SC03_124_jr_8013C98C.c index b859da3ef8..ffa2dae8ea 100644 --- a/src/ov_SC03_124/ov_SC03_124_jr_8013C98C.c +++ b/src/ov_SC03_124/ov_SC03_124_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c b/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c index 340a6754f0..260b2615dd 100644 --- a/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c +++ b/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c @@ -3627,13 +3627,6 @@ extern void func_80146C3C(); // K&R: ? of 1 args (P37 rung D t4_D22) #include "../shared/ov/func_8017C6AC.h" -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) #include "../shared/ov/func_8017C710__t3f3d6beb.h" diff --git a/src/ov_SC03_125/ov_SC03_125_jr_8012ACE0.c b/src/ov_SC03_125/ov_SC03_125_jr_8012ACE0.c index f963b14704..333f5dccd9 100644 --- a/src/ov_SC03_125/ov_SC03_125_jr_8012ACE0.c +++ b/src/ov_SC03_125/ov_SC03_125_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80184324) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80184324); gte_stlvnl(D_80184328); pc0 = D_80184324; diff --git a/src/ov_SC03_125/ov_SC03_125_jr_8013C98C.c b/src/ov_SC03_125/ov_SC03_125_jr_8013C98C.c index d0f8a570bf..13adf30e13 100644 --- a/src/ov_SC03_125/ov_SC03_125_jr_8013C98C.c +++ b/src/ov_SC03_125/ov_SC03_125_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_126/ov_SC03_126_jr_801380E0.c b/src/ov_SC03_126/ov_SC03_126_jr_801380E0.c index 92fc27253c..9c74e7001f 100644 --- a/src/ov_SC03_126/ov_SC03_126_jr_801380E0.c +++ b/src/ov_SC03_126/ov_SC03_126_jr_801380E0.c @@ -871,11 +871,6 @@ extern s16 D_800D45F4[]; /* src0 (flat: [2*i]=x, [2*i+1]=y) */ extern u8 D_8017F948[]; /* sign table, alt (when a1 < 0xC00) */ -#define gte_mvmva0() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") #include "../shared/ov/func_8013AD38__49b61a70.h" diff --git a/src/ov_SC03_126/ov_SC03_126_jr_8017D5C0.c b/src/ov_SC03_126/ov_SC03_126_jr_8017D5C0.c index 3b5f7f5321..0261abf5e7 100644 --- a/src/ov_SC03_126/ov_SC03_126_jr_8017D5C0.c +++ b/src/ov_SC03_126/ov_SC03_126_jr_8017D5C0.c @@ -2703,13 +2703,6 @@ extern void func_8017C688(s32 a0, s32 a1); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC04_000/ov_SC04_000_jr_8012ACE0.c b/src/ov_SC04_000/ov_SC04_000_jr_8012ACE0.c index 68c479e10b..506a8f9e91 100644 --- a/src/ov_SC04_000/ov_SC04_000_jr_8012ACE0.c +++ b/src/ov_SC04_000/ov_SC04_000_jr_8012ACE0.c @@ -2407,14 +2407,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80183828) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80183828); gte_stlvnl(D_8018382C); pc0 = D_80183828; diff --git a/src/ov_SC04_000/ov_SC04_000_jr_8013C98C.c b/src/ov_SC04_000/ov_SC04_000_jr_8013C98C.c index 0d41eb7d5a..4944259fe1 100644 --- a/src/ov_SC04_000/ov_SC04_000_jr_8013C98C.c +++ b/src/ov_SC04_000/ov_SC04_000_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_000/ov_SC04_000_jr_801818E8.c b/src/ov_SC04_000/ov_SC04_000_jr_801818E8.c index 0e37dc1959..0cf3d1b800 100644 --- a/src/ov_SC04_000/ov_SC04_000_jr_801818E8.c +++ b/src/ov_SC04_000/ov_SC04_000_jr_801818E8.c @@ -2990,19 +2990,8 @@ short *a0; data[0] = a0[3] - a0[68]; data[1] = 0; data[2] = a0[7] - a0[70]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return (data[0] + data[2]) <= 0x18FFFF; } diff --git a/src/ov_SC04_002/ov_SC04_002_jr_8012ACE0.c b/src/ov_SC04_002/ov_SC04_002_jr_8012ACE0.c index 9ed690d0c0..1633bf3236 100644 --- a/src/ov_SC04_002/ov_SC04_002_jr_8012ACE0.c +++ b/src/ov_SC04_002/ov_SC04_002_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80188994) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80188994); gte_stlvnl(D_80188998); pc0 = D_80188994; diff --git a/src/ov_SC04_002/ov_SC04_002_jr_8013C98C.c b/src/ov_SC04_002/ov_SC04_002_jr_8013C98C.c index 74ecfc45a5..61bba31179 100644 --- a/src/ov_SC04_002/ov_SC04_002_jr_8013C98C.c +++ b/src/ov_SC04_002/ov_SC04_002_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_003/ov_SC04_003_jr_8012ACE0.c b/src/ov_SC04_003/ov_SC04_003_jr_8012ACE0.c index 4c575983ec..2a03eb7e26 100644 --- a/src/ov_SC04_003/ov_SC04_003_jr_8012ACE0.c +++ b/src/ov_SC04_003/ov_SC04_003_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182730) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182730); gte_stlvnl(D_80182734); pc0 = D_80182730; diff --git a/src/ov_SC04_003/ov_SC04_003_jr_8013C98C.c b/src/ov_SC04_003/ov_SC04_003_jr_8013C98C.c index 1fca53e693..344511173f 100644 --- a/src/ov_SC04_003/ov_SC04_003_jr_8013C98C.c +++ b/src/ov_SC04_003/ov_SC04_003_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c b/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c index 94e2050505..ec5ca32c95 100644 --- a/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c +++ b/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c @@ -2689,13 +2689,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC04_004/ov_SC04_004_jr_8012ACE0.c b/src/ov_SC04_004/ov_SC04_004_jr_8012ACE0.c index f9066ad88b..d96f8046ba 100644 --- a/src/ov_SC04_004/ov_SC04_004_jr_8012ACE0.c +++ b/src/ov_SC04_004/ov_SC04_004_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80184C64) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80184C64); gte_stlvnl(D_80184C68); pc0 = D_80184C64; diff --git a/src/ov_SC04_004/ov_SC04_004_jr_8013C98C.c b/src/ov_SC04_004/ov_SC04_004_jr_8013C98C.c index 7252d7804b..371b7c0214 100644 --- a/src/ov_SC04_004/ov_SC04_004_jr_8013C98C.c +++ b/src/ov_SC04_004/ov_SC04_004_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_005/ov_SC04_005_jr_8012ACE0.c b/src/ov_SC04_005/ov_SC04_005_jr_8012ACE0.c index 4e5257f8b7..421e2d13b0 100644 --- a/src/ov_SC04_005/ov_SC04_005_jr_8012ACE0.c +++ b/src/ov_SC04_005/ov_SC04_005_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80188098) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80188098); gte_stlvnl(D_8018809C); pc0 = D_80188098; diff --git a/src/ov_SC04_005/ov_SC04_005_jr_801380E0.c b/src/ov_SC04_005/ov_SC04_005_jr_801380E0.c index e88116e423..efd940f7a6 100644 --- a/src/ov_SC04_005/ov_SC04_005_jr_801380E0.c +++ b/src/ov_SC04_005/ov_SC04_005_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_801881C4[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_005/ov_SC04_005_jr_8013C98C.c b/src/ov_SC04_005/ov_SC04_005_jr_8013C98C.c index 0517be804d..af9f970a41 100644 --- a/src/ov_SC04_005/ov_SC04_005_jr_8013C98C.c +++ b/src/ov_SC04_005/ov_SC04_005_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_006/ov_SC04_006_jr_8012ACE0.c b/src/ov_SC04_006/ov_SC04_006_jr_8012ACE0.c index 506844cd1e..bd91c7cfa5 100644 --- a/src/ov_SC04_006/ov_SC04_006_jr_8012ACE0.c +++ b/src/ov_SC04_006/ov_SC04_006_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80180178) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80180178); gte_stlvnl(D_8018017C); pc0 = D_80180178; diff --git a/src/ov_SC04_006/ov_SC04_006_jr_801380E0.c b/src/ov_SC04_006/ov_SC04_006_jr_801380E0.c index de6fc021b7..904e7b8cd6 100644 --- a/src/ov_SC04_006/ov_SC04_006_jr_801380E0.c +++ b/src/ov_SC04_006/ov_SC04_006_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_801802A4[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_006/ov_SC04_006_jr_8013C98C.c b/src/ov_SC04_006/ov_SC04_006_jr_8013C98C.c index 30bceeec84..9dbb75b2b7 100644 --- a/src/ov_SC04_006/ov_SC04_006_jr_8013C98C.c +++ b/src/ov_SC04_006/ov_SC04_006_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_007/ov_SC04_007_jr_8012ACE0.c b/src/ov_SC04_007/ov_SC04_007_jr_8012ACE0.c index b1c845963d..69b9e76db3 100644 --- a/src/ov_SC04_007/ov_SC04_007_jr_8012ACE0.c +++ b/src/ov_SC04_007/ov_SC04_007_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80186130) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80186130); gte_stlvnl(D_80186134); pc0 = D_80186130; diff --git a/src/ov_SC04_007/ov_SC04_007_jr_801380E0.c b/src/ov_SC04_007/ov_SC04_007_jr_801380E0.c index 4aa0a08b7a..f322daa473 100644 --- a/src/ov_SC04_007/ov_SC04_007_jr_801380E0.c +++ b/src/ov_SC04_007/ov_SC04_007_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8018625C[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_007/ov_SC04_007_jr_8013C98C.c b/src/ov_SC04_007/ov_SC04_007_jr_8013C98C.c index 60337a3c40..a670510d54 100644 --- a/src/ov_SC04_007/ov_SC04_007_jr_8013C98C.c +++ b/src/ov_SC04_007/ov_SC04_007_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_008/ov_SC04_008_jr_8012ACE0.c b/src/ov_SC04_008/ov_SC04_008_jr_8012ACE0.c index 03992e35ae..3e4ce1f3f5 100644 --- a/src/ov_SC04_008/ov_SC04_008_jr_8012ACE0.c +++ b/src/ov_SC04_008/ov_SC04_008_jr_8012ACE0.c @@ -1883,14 +1883,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F068) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F068); gte_stlvnl(D_8017F06C); pc0 = D_8017F068; diff --git a/src/ov_SC04_008/ov_SC04_008_jr_801380E0.c b/src/ov_SC04_008/ov_SC04_008_jr_801380E0.c index bd7d73de53..c41810c1bb 100644 --- a/src/ov_SC04_008/ov_SC04_008_jr_801380E0.c +++ b/src/ov_SC04_008/ov_SC04_008_jr_801380E0.c @@ -871,11 +871,6 @@ extern s16 D_800D45F4[]; /* src0 (flat: [2*i]=x, [2*i+1]=y) */ extern u8 D_8017F194[]; /* sign table, alt (when a1 < 0xC00) */ -#define gte_mvmva0() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") #include "../shared/ov/func_8013AD38__06daa24e.h" diff --git a/src/ov_SC04_008/ov_SC04_008_jr_8013C98C.c b/src/ov_SC04_008/ov_SC04_008_jr_8013C98C.c index 9bd6c3e189..da3ba04909 100644 --- a/src/ov_SC04_008/ov_SC04_008_jr_8013C98C.c +++ b/src/ov_SC04_008/ov_SC04_008_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_008/ov_SC04_008_jr_8017AE2C.c b/src/ov_SC04_008/ov_SC04_008_jr_8017AE2C.c index 762d9952f5..7918b7a621 100644 --- a/src/ov_SC04_008/ov_SC04_008_jr_8017AE2C.c +++ b/src/ov_SC04_008/ov_SC04_008_jr_8017AE2C.c @@ -3297,13 +3297,6 @@ extern void (*D_801824A4[])(void); #include "../shared/ov/func_8017BEB4.h" -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) #include "../shared/ov/func_8017BEBC__t67f11bf2.h" diff --git a/src/ov_SC04_009/ov_SC04_009_jr_8012ACE0.c b/src/ov_SC04_009/ov_SC04_009_jr_8012ACE0.c index 0da1e84d3e..4bd3352fc5 100644 --- a/src/ov_SC04_009/ov_SC04_009_jr_8012ACE0.c +++ b/src/ov_SC04_009/ov_SC04_009_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F094) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F094); gte_stlvnl(D_8017F098); pc0 = D_8017F094; diff --git a/src/ov_SC04_009/ov_SC04_009_jr_801380E0.c b/src/ov_SC04_009/ov_SC04_009_jr_801380E0.c index e5b3b18c66..ee099b6e5e 100644 --- a/src/ov_SC04_009/ov_SC04_009_jr_801380E0.c +++ b/src/ov_SC04_009/ov_SC04_009_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8017F1C0[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_009/ov_SC04_009_jr_8013C98C.c b/src/ov_SC04_009/ov_SC04_009_jr_8013C98C.c index 77d3a718ab..dbe01c625d 100644 --- a/src/ov_SC04_009/ov_SC04_009_jr_8013C98C.c +++ b/src/ov_SC04_009/ov_SC04_009_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_009/ov_SC04_009_jr_8017BEBC.c b/src/ov_SC04_009/ov_SC04_009_jr_8017BEBC.c index 6b1acd78cf..7d213018b2 100644 --- a/src/ov_SC04_009/ov_SC04_009_jr_8017BEBC.c +++ b/src/ov_SC04_009/ov_SC04_009_jr_8017BEBC.c @@ -2689,13 +2689,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC04_010/ov_SC04_010_jr_8012ACE0.c b/src/ov_SC04_010/ov_SC04_010_jr_8012ACE0.c index 2702fc935c..91c79a4681 100644 --- a/src/ov_SC04_010/ov_SC04_010_jr_8012ACE0.c +++ b/src/ov_SC04_010/ov_SC04_010_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017E740) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017E740); gte_stlvnl(D_8017E744); pc0 = D_8017E740; diff --git a/src/ov_SC04_010/ov_SC04_010_jr_801380E0.c b/src/ov_SC04_010/ov_SC04_010_jr_801380E0.c index 8580634ad8..7b9f7462bd 100644 --- a/src/ov_SC04_010/ov_SC04_010_jr_801380E0.c +++ b/src/ov_SC04_010/ov_SC04_010_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8017E86C[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_010/ov_SC04_010_jr_8013C98C.c b/src/ov_SC04_010/ov_SC04_010_jr_8013C98C.c index ca3785b29d..3d81e504fe 100644 --- a/src/ov_SC04_010/ov_SC04_010_jr_8013C98C.c +++ b/src/ov_SC04_010/ov_SC04_010_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_010/ov_SC04_010_jr_8017BEBC.c b/src/ov_SC04_010/ov_SC04_010_jr_8017BEBC.c index 1230b8a5de..4f3d3f6c95 100644 --- a/src/ov_SC04_010/ov_SC04_010_jr_8017BEBC.c +++ b/src/ov_SC04_010/ov_SC04_010_jr_8017BEBC.c @@ -2688,13 +2688,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.c b/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.c index b33824c038..f4c84c2f0c 100644 --- a/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.c +++ b/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801909D0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801909D0); gte_stlvnl(D_801909D4); pc0 = D_801909D0; diff --git a/src/ov_SC04_011/ov_SC04_011_jr_801380E0.c b/src/ov_SC04_011/ov_SC04_011_jr_801380E0.c index bcdb6e0e26..4eaf9cc0d8 100644 --- a/src/ov_SC04_011/ov_SC04_011_jr_801380E0.c +++ b/src/ov_SC04_011/ov_SC04_011_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80190AFC[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.c b/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.c index 6c3cc2cd70..23acef807b 100644 --- a/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.c +++ b/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_012/ov_SC04_012_jr_8012ACE0.c b/src/ov_SC04_012/ov_SC04_012_jr_8012ACE0.c index 16656bb664..c28482847b 100644 --- a/src/ov_SC04_012/ov_SC04_012_jr_8012ACE0.c +++ b/src/ov_SC04_012/ov_SC04_012_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017EBA4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017EBA4); gte_stlvnl(D_8017EBA8); pc0 = D_8017EBA4; diff --git a/src/ov_SC04_012/ov_SC04_012_jr_801380E0.c b/src/ov_SC04_012/ov_SC04_012_jr_801380E0.c index 0bc444dfaa..e8ef6aa631 100644 --- a/src/ov_SC04_012/ov_SC04_012_jr_801380E0.c +++ b/src/ov_SC04_012/ov_SC04_012_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8017ECD0[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_012/ov_SC04_012_jr_8013C98C.c b/src/ov_SC04_012/ov_SC04_012_jr_8013C98C.c index fff23f7d03..6b59a78bc0 100644 --- a/src/ov_SC04_012/ov_SC04_012_jr_8013C98C.c +++ b/src/ov_SC04_012/ov_SC04_012_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_012/ov_SC04_012_jr_8017AE2C.c b/src/ov_SC04_012/ov_SC04_012_jr_8017AE2C.c index 7a739a5e9c..b2fa8877ac 100644 --- a/src/ov_SC04_012/ov_SC04_012_jr_8017AE2C.c +++ b/src/ov_SC04_012/ov_SC04_012_jr_8017AE2C.c @@ -3295,13 +3295,6 @@ void func_8017BE60(void *a0) { #include "../shared/ov/func_8017BEB4.h" -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) #include "../shared/ov/func_8017BEBC__t67f11bf2.h" diff --git a/src/ov_SC04_015/ov_SC04_015_jr_8012ACE0.c b/src/ov_SC04_015/ov_SC04_015_jr_8012ACE0.c index 0ded2a1da5..4288a6e825 100644 --- a/src/ov_SC04_015/ov_SC04_015_jr_8012ACE0.c +++ b/src/ov_SC04_015/ov_SC04_015_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80184ADC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80184ADC); gte_stlvnl(D_80184AE0); pc0 = D_80184ADC; diff --git a/src/ov_SC04_015/ov_SC04_015_jr_801380E0.c b/src/ov_SC04_015/ov_SC04_015_jr_801380E0.c index 99233c4fee..f752e4c523 100644 --- a/src/ov_SC04_015/ov_SC04_015_jr_801380E0.c +++ b/src/ov_SC04_015/ov_SC04_015_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80184C08[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_015/ov_SC04_015_jr_8013C98C.c b/src/ov_SC04_015/ov_SC04_015_jr_8013C98C.c index 41d33dd2b7..45c39c976c 100644 --- a/src/ov_SC04_015/ov_SC04_015_jr_8013C98C.c +++ b/src/ov_SC04_015/ov_SC04_015_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_016/ov_SC04_016_jr_8012ACE0.c b/src/ov_SC04_016/ov_SC04_016_jr_8012ACE0.c index fa194d461c..71e1bf519c 100644 --- a/src/ov_SC04_016/ov_SC04_016_jr_8012ACE0.c +++ b/src/ov_SC04_016/ov_SC04_016_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801805A0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801805A0); gte_stlvnl(D_801805A4); pc0 = D_801805A0; diff --git a/src/ov_SC04_016/ov_SC04_016_jr_801380E0.c b/src/ov_SC04_016/ov_SC04_016_jr_801380E0.c index 9827d7281b..32385a1991 100644 --- a/src/ov_SC04_016/ov_SC04_016_jr_801380E0.c +++ b/src/ov_SC04_016/ov_SC04_016_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_801806CC[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_016/ov_SC04_016_jr_8013C98C.c b/src/ov_SC04_016/ov_SC04_016_jr_8013C98C.c index d5d554c9d9..9803f879f9 100644 --- a/src/ov_SC04_016/ov_SC04_016_jr_8013C98C.c +++ b/src/ov_SC04_016/ov_SC04_016_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_016/ov_SC04_016_jr_8017BEBC.c b/src/ov_SC04_016/ov_SC04_016_jr_8017BEBC.c index e0dd4a85e2..1bacce309c 100644 --- a/src/ov_SC04_016/ov_SC04_016_jr_8017BEBC.c +++ b/src/ov_SC04_016/ov_SC04_016_jr_8017BEBC.c @@ -2691,13 +2691,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC04_018/ov_SC04_018_jr_8012ACE0.c b/src/ov_SC04_018/ov_SC04_018_jr_8012ACE0.c index 1a4786dc52..556c8f752a 100644 --- a/src/ov_SC04_018/ov_SC04_018_jr_8012ACE0.c +++ b/src/ov_SC04_018/ov_SC04_018_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018D7B8) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018D7B8); gte_stlvnl(D_8018D7BC); pc0 = D_8018D7B8; diff --git a/src/ov_SC04_018/ov_SC04_018_jr_801380E0.c b/src/ov_SC04_018/ov_SC04_018_jr_801380E0.c index 6e03ddc5fd..d1d4101e41 100644 --- a/src/ov_SC04_018/ov_SC04_018_jr_801380E0.c +++ b/src/ov_SC04_018/ov_SC04_018_jr_801380E0.c @@ -1005,11 +1005,6 @@ extern u8 D_8018D8E4[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1031,7 +1026,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_018/ov_SC04_018_jr_8013C98C.c b/src/ov_SC04_018/ov_SC04_018_jr_8013C98C.c index cda6aad811..716edbe650 100644 --- a/src/ov_SC04_018/ov_SC04_018_jr_8013C98C.c +++ b/src/ov_SC04_018/ov_SC04_018_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_018/ov_SC04_018_jr_8017AE2C.c b/src/ov_SC04_018/ov_SC04_018_jr_8017AE2C.c index 166e83c824..3b6cc4b569 100644 --- a/src/ov_SC04_018/ov_SC04_018_jr_8017AE2C.c +++ b/src/ov_SC04_018/ov_SC04_018_jr_8017AE2C.c @@ -3638,13 +3638,6 @@ extern void func_80146C3C(); // K&R: ? of 1 args (P37 rung D t4_D22) #include "../shared/ov/func_8017C6AC.h" -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) #include "../shared/ov/func_8017C710__t3f3d6beb.h" diff --git a/src/ov_SC04_020/ov_SC04_020_jr_8012ACE0.c b/src/ov_SC04_020/ov_SC04_020_jr_8012ACE0.c index 59fb7b141d..6a941eb12f 100644 --- a/src/ov_SC04_020/ov_SC04_020_jr_8012ACE0.c +++ b/src/ov_SC04_020/ov_SC04_020_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801838F0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801838F0); gte_stlvnl(D_801838F4); pc0 = D_801838F0; diff --git a/src/ov_SC04_020/ov_SC04_020_jr_801380E0.c b/src/ov_SC04_020/ov_SC04_020_jr_801380E0.c index 4513466488..0d80642fc6 100644 --- a/src/ov_SC04_020/ov_SC04_020_jr_801380E0.c +++ b/src/ov_SC04_020/ov_SC04_020_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80183A1C[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC04_020/ov_SC04_020_jr_8013C98C.c b/src/ov_SC04_020/ov_SC04_020_jr_8013C98C.c index 93f5156788..b13f18f468 100644 --- a/src/ov_SC04_020/ov_SC04_020_jr_8013C98C.c +++ b/src/ov_SC04_020/ov_SC04_020_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC04_021/ov_SC04_021_jr_801380E0.c b/src/ov_SC04_021/ov_SC04_021_jr_801380E0.c index 92fc27253c..9c74e7001f 100644 --- a/src/ov_SC04_021/ov_SC04_021_jr_801380E0.c +++ b/src/ov_SC04_021/ov_SC04_021_jr_801380E0.c @@ -871,11 +871,6 @@ extern s16 D_800D45F4[]; /* src0 (flat: [2*i]=x, [2*i+1]=y) */ extern u8 D_8017F948[]; /* sign table, alt (when a1 < 0xC00) */ -#define gte_mvmva0() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") #include "../shared/ov/func_8013AD38__49b61a70.h" diff --git a/src/ov_SC04_021/ov_SC04_021_jr_8017D5C0.c b/src/ov_SC04_021/ov_SC04_021_jr_8017D5C0.c index a7d005bf97..4f6eda3706 100644 --- a/src/ov_SC04_021/ov_SC04_021_jr_8017D5C0.c +++ b/src/ov_SC04_021/ov_SC04_021_jr_8017D5C0.c @@ -2703,13 +2703,6 @@ extern void func_8017C688(s32 a0, s32 a1); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC05_000/ov_SC05_000_jr_8012ACE0.c b/src/ov_SC05_000/ov_SC05_000_jr_8012ACE0.c index 2bf580106a..47ebc3eaca 100644 --- a/src/ov_SC05_000/ov_SC05_000_jr_8012ACE0.c +++ b/src/ov_SC05_000/ov_SC05_000_jr_8012ACE0.c @@ -2407,14 +2407,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017E830) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017E830); gte_stlvnl(D_8017E834); pc0 = D_8017E830; diff --git a/src/ov_SC05_000/ov_SC05_000_jr_801380E0.c b/src/ov_SC05_000/ov_SC05_000_jr_801380E0.c index 193e34bfc9..df4d99c416 100644 --- a/src/ov_SC05_000/ov_SC05_000_jr_801380E0.c +++ b/src/ov_SC05_000/ov_SC05_000_jr_801380E0.c @@ -1005,11 +1005,6 @@ extern u8 D_8017E95C[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1031,7 +1026,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_000/ov_SC05_000_jr_8013C98C.c b/src/ov_SC05_000/ov_SC05_000_jr_8013C98C.c index de70dfd452..3a3ab79a2b 100644 --- a/src/ov_SC05_000/ov_SC05_000_jr_8013C98C.c +++ b/src/ov_SC05_000/ov_SC05_000_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_001/ov_SC05_001_jr_8012ACE0.c b/src/ov_SC05_001/ov_SC05_001_jr_8012ACE0.c index dc9da24c3b..fece106c94 100644 --- a/src/ov_SC05_001/ov_SC05_001_jr_8012ACE0.c +++ b/src/ov_SC05_001/ov_SC05_001_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018600C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018600C); gte_stlvnl(D_80186010); pc0 = D_8018600C; diff --git a/src/ov_SC05_001/ov_SC05_001_jr_801380E0.c b/src/ov_SC05_001/ov_SC05_001_jr_801380E0.c index 201aed7514..1f5f382ddb 100644 --- a/src/ov_SC05_001/ov_SC05_001_jr_801380E0.c +++ b/src/ov_SC05_001/ov_SC05_001_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80186138[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_001/ov_SC05_001_jr_8013C98C.c b/src/ov_SC05_001/ov_SC05_001_jr_8013C98C.c index 868ad89120..4ec5f3e8bc 100644 --- a/src/ov_SC05_001/ov_SC05_001_jr_8013C98C.c +++ b/src/ov_SC05_001/ov_SC05_001_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_002/ov_SC05_002_jr_8012ACE0.c b/src/ov_SC05_002/ov_SC05_002_jr_8012ACE0.c index 1cb7a2a9d5..19501d6426 100644 --- a/src/ov_SC05_002/ov_SC05_002_jr_8012ACE0.c +++ b/src/ov_SC05_002/ov_SC05_002_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801807CC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801807CC); gte_stlvnl(D_801807D0); pc0 = D_801807CC; diff --git a/src/ov_SC05_002/ov_SC05_002_jr_801380E0.c b/src/ov_SC05_002/ov_SC05_002_jr_801380E0.c index 164a780ace..26bc3e95a4 100644 --- a/src/ov_SC05_002/ov_SC05_002_jr_801380E0.c +++ b/src/ov_SC05_002/ov_SC05_002_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_801808F8[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_002/ov_SC05_002_jr_8013C98C.c b/src/ov_SC05_002/ov_SC05_002_jr_8013C98C.c index 7462506d73..fa6d0ff953 100644 --- a/src/ov_SC05_002/ov_SC05_002_jr_8013C98C.c +++ b/src/ov_SC05_002/ov_SC05_002_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_002/ov_SC05_002_jr_8017BEBC.c b/src/ov_SC05_002/ov_SC05_002_jr_8017BEBC.c index 7313acd00a..92704e808e 100644 --- a/src/ov_SC05_002/ov_SC05_002_jr_8017BEBC.c +++ b/src/ov_SC05_002/ov_SC05_002_jr_8017BEBC.c @@ -2690,13 +2690,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC05_003/ov_SC05_003_jr_8012ACE0.c b/src/ov_SC05_003/ov_SC05_003_jr_8012ACE0.c index bab638cd95..75e2207c78 100644 --- a/src/ov_SC05_003/ov_SC05_003_jr_8012ACE0.c +++ b/src/ov_SC05_003/ov_SC05_003_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182B04) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182B04); gte_stlvnl(D_80182B08); pc0 = D_80182B04; diff --git a/src/ov_SC05_003/ov_SC05_003_jr_801380E0.c b/src/ov_SC05_003/ov_SC05_003_jr_801380E0.c index 01a4133828..6f68c5e255 100644 --- a/src/ov_SC05_003/ov_SC05_003_jr_801380E0.c +++ b/src/ov_SC05_003/ov_SC05_003_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80182C30[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_003/ov_SC05_003_jr_8013C98C.c b/src/ov_SC05_003/ov_SC05_003_jr_8013C98C.c index 36cbe3d2da..a00b3d1b0c 100644 --- a/src/ov_SC05_003/ov_SC05_003_jr_8013C98C.c +++ b/src/ov_SC05_003/ov_SC05_003_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c b/src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c index 9c748d4897..ed05b5e94a 100644 --- a/src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c +++ b/src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c @@ -2687,13 +2687,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -5641,19 +5634,7 @@ s32 func_80181720(void *arg0) { v.vz = (s16)D_80126B66 - raw[2]; /* gte SQR on the XZ difference vector (in place) */ - __asm__ volatile ( - "lwc2 $9, 0( %0 );" - "lwc2 $10, 4( %0 );" - "lwc2 $11, 8( %0 );" - "nop;" - "nop;" - "sqr 0;" - "swc2 $25, 0( %0 );" - "swc2 $26, 4( %0 );" - "swc2 $27, 8( %0 )" - : - : "r"(&v) - : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_swc2x3_c9fc(&v); if (r * r <= v.vx + v.vz) { return 0; diff --git a/src/ov_SC05_004/ov_SC05_004_jr_8012ACE0.c b/src/ov_SC05_004/ov_SC05_004_jr_8012ACE0.c index 86cce6d1ec..4e0fb94e5d 100644 --- a/src/ov_SC05_004/ov_SC05_004_jr_8012ACE0.c +++ b/src/ov_SC05_004/ov_SC05_004_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80181C10) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80181C10); gte_stlvnl(D_80181C14); pc0 = D_80181C10; diff --git a/src/ov_SC05_004/ov_SC05_004_jr_801380E0.c b/src/ov_SC05_004/ov_SC05_004_jr_801380E0.c index bd3cdd2184..9ab832b94b 100644 --- a/src/ov_SC05_004/ov_SC05_004_jr_801380E0.c +++ b/src/ov_SC05_004/ov_SC05_004_jr_801380E0.c @@ -1007,11 +1007,6 @@ extern u8 D_80181D3C[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1033,7 +1028,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_004/ov_SC05_004_jr_8013C98C.c b/src/ov_SC05_004/ov_SC05_004_jr_8013C98C.c index 1bdd1a4927..93d9cbd3b4 100644 --- a/src/ov_SC05_004/ov_SC05_004_jr_8013C98C.c +++ b/src/ov_SC05_004/ov_SC05_004_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_005/ov_SC05_005_jr_8012ACE0.c b/src/ov_SC05_005/ov_SC05_005_jr_8012ACE0.c index 158fe3cb26..4ff9cf9f5e 100644 --- a/src/ov_SC05_005/ov_SC05_005_jr_8012ACE0.c +++ b/src/ov_SC05_005/ov_SC05_005_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801829E4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801829E4); gte_stlvnl(D_801829E8); pc0 = D_801829E4; diff --git a/src/ov_SC05_005/ov_SC05_005_jr_801380E0.c b/src/ov_SC05_005/ov_SC05_005_jr_801380E0.c index 789181c8a7..7cc3d4169c 100644 --- a/src/ov_SC05_005/ov_SC05_005_jr_801380E0.c +++ b/src/ov_SC05_005/ov_SC05_005_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80182B10[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_005/ov_SC05_005_jr_8013C98C.c b/src/ov_SC05_005/ov_SC05_005_jr_8013C98C.c index 84d9531d40..d2b1452a6a 100644 --- a/src/ov_SC05_005/ov_SC05_005_jr_8013C98C.c +++ b/src/ov_SC05_005/ov_SC05_005_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_006/ov_SC05_006_jr_8012ACE0.c b/src/ov_SC05_006/ov_SC05_006_jr_8012ACE0.c index 86900fd526..17cb729f06 100644 --- a/src/ov_SC05_006/ov_SC05_006_jr_8012ACE0.c +++ b/src/ov_SC05_006/ov_SC05_006_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017FA04) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017FA04); gte_stlvnl(D_8017FA08); pc0 = D_8017FA04; diff --git a/src/ov_SC05_006/ov_SC05_006_jr_801380E0.c b/src/ov_SC05_006/ov_SC05_006_jr_801380E0.c index 20b24edfd5..95db30ccaf 100644 --- a/src/ov_SC05_006/ov_SC05_006_jr_801380E0.c +++ b/src/ov_SC05_006/ov_SC05_006_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8017FB30[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_006/ov_SC05_006_jr_8013C98C.c b/src/ov_SC05_006/ov_SC05_006_jr_8013C98C.c index f26ff1af46..af46edc42b 100644 --- a/src/ov_SC05_006/ov_SC05_006_jr_8013C98C.c +++ b/src/ov_SC05_006/ov_SC05_006_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_007/ov_SC05_007_jr_8012ACE0.c b/src/ov_SC05_007/ov_SC05_007_jr_8012ACE0.c index 4f8072277d..539e7ffc10 100644 --- a/src/ov_SC05_007/ov_SC05_007_jr_8012ACE0.c +++ b/src/ov_SC05_007/ov_SC05_007_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80181000) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80181000); gte_stlvnl(D_80181004); pc0 = D_80181000; diff --git a/src/ov_SC05_007/ov_SC05_007_jr_801380E0.c b/src/ov_SC05_007/ov_SC05_007_jr_801380E0.c index 306b61c6a7..fe9826aeb4 100644 --- a/src/ov_SC05_007/ov_SC05_007_jr_801380E0.c +++ b/src/ov_SC05_007/ov_SC05_007_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8018112C[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_007/ov_SC05_007_jr_8013C98C.c b/src/ov_SC05_007/ov_SC05_007_jr_8013C98C.c index 9a5639ae44..b36f728007 100644 --- a/src/ov_SC05_007/ov_SC05_007_jr_8013C98C.c +++ b/src/ov_SC05_007/ov_SC05_007_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c b/src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c index 0f5ca581e2..8dc2a142b2 100644 --- a/src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c +++ b/src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c @@ -2686,13 +2686,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC05_008/ov_SC05_008_jr_8012ACE0.c b/src/ov_SC05_008/ov_SC05_008_jr_8012ACE0.c index 7e921763f2..0f73a96406 100644 --- a/src/ov_SC05_008/ov_SC05_008_jr_8012ACE0.c +++ b/src/ov_SC05_008/ov_SC05_008_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182F58) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182F58); gte_stlvnl(D_80182F5C); pc0 = D_80182F58; diff --git a/src/ov_SC05_008/ov_SC05_008_jr_801380E0.c b/src/ov_SC05_008/ov_SC05_008_jr_801380E0.c index c0e3837765..0bde56b469 100644 --- a/src/ov_SC05_008/ov_SC05_008_jr_801380E0.c +++ b/src/ov_SC05_008/ov_SC05_008_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80183084[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_008/ov_SC05_008_jr_8013C98C.c b/src/ov_SC05_008/ov_SC05_008_jr_8013C98C.c index 6eaf2720d5..bff7b893b8 100644 --- a/src/ov_SC05_008/ov_SC05_008_jr_8013C98C.c +++ b/src/ov_SC05_008/ov_SC05_008_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_008/ov_SC05_008_jr_8017AE2C.c b/src/ov_SC05_008/ov_SC05_008_jr_8017AE2C.c index ffce6ea69d..9b3a393a0b 100644 --- a/src/ov_SC05_008/ov_SC05_008_jr_8017AE2C.c +++ b/src/ov_SC05_008/ov_SC05_008_jr_8017AE2C.c @@ -3298,13 +3298,6 @@ void func_8017BE60(void *a0) { #include "../shared/ov/func_8017BEB4.h" -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) #include "../shared/ov/func_8017BEBC__t67f11bf2.h" diff --git a/src/ov_SC05_009/ov_SC05_009_jr_8012ACE0.c b/src/ov_SC05_009/ov_SC05_009_jr_8012ACE0.c index 80c666e66d..56dd758e13 100644 --- a/src/ov_SC05_009/ov_SC05_009_jr_8012ACE0.c +++ b/src/ov_SC05_009/ov_SC05_009_jr_8012ACE0.c @@ -1883,14 +1883,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F068) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F068); gte_stlvnl(D_8017F06C); pc0 = D_8017F068; diff --git a/src/ov_SC05_009/ov_SC05_009_jr_801380E0.c b/src/ov_SC05_009/ov_SC05_009_jr_801380E0.c index 32198b747c..eba46f7314 100644 --- a/src/ov_SC05_009/ov_SC05_009_jr_801380E0.c +++ b/src/ov_SC05_009/ov_SC05_009_jr_801380E0.c @@ -871,11 +871,6 @@ extern s16 D_800D45F4[]; /* src0 (flat: [2*i]=x, [2*i+1]=y) */ extern u8 D_8017F194[]; /* sign table, alt (when a1 < 0xC00) */ -#define gte_mvmva0() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") #include "../shared/ov/func_8013AD38__06daa24e.h" diff --git a/src/ov_SC05_009/ov_SC05_009_jr_8013C98C.c b/src/ov_SC05_009/ov_SC05_009_jr_8013C98C.c index 3ade9730a5..4466fc9070 100644 --- a/src/ov_SC05_009/ov_SC05_009_jr_8013C98C.c +++ b/src/ov_SC05_009/ov_SC05_009_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_009/ov_SC05_009_jr_8017BEBC.c b/src/ov_SC05_009/ov_SC05_009_jr_8017BEBC.c index 14b4f32050..3c319dbf2f 100644 --- a/src/ov_SC05_009/ov_SC05_009_jr_8017BEBC.c +++ b/src/ov_SC05_009/ov_SC05_009_jr_8017BEBC.c @@ -2686,13 +2686,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC05_010/ov_SC05_010_jr_8012ACE0.c b/src/ov_SC05_010/ov_SC05_010_jr_8012ACE0.c index 3222efaa8e..bac702a6cc 100644 --- a/src/ov_SC05_010/ov_SC05_010_jr_8012ACE0.c +++ b/src/ov_SC05_010/ov_SC05_010_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80188F44) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80188F44); gte_stlvnl(D_80188F48); pc0 = D_80188F44; diff --git a/src/ov_SC05_010/ov_SC05_010_jr_801380E0.c b/src/ov_SC05_010/ov_SC05_010_jr_801380E0.c index 9c39d79c4f..8802c56f0b 100644 --- a/src/ov_SC05_010/ov_SC05_010_jr_801380E0.c +++ b/src/ov_SC05_010/ov_SC05_010_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80189070[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_010/ov_SC05_010_jr_8013C98C.c b/src/ov_SC05_010/ov_SC05_010_jr_8013C98C.c index 3cb7db846e..80b062cbe6 100644 --- a/src/ov_SC05_010/ov_SC05_010_jr_8013C98C.c +++ b/src/ov_SC05_010/ov_SC05_010_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.c b/src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.c index 92f6c15623..23e17f393e 100644 --- a/src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.c +++ b/src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.c @@ -2692,13 +2692,6 @@ extern void func_8017C114(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC05_010/ov_SC05_010_jr_8018473C.c b/src/ov_SC05_010/ov_SC05_010_jr_8018473C.c index fbd47805fc..8831023330 100644 --- a/src/ov_SC05_010/ov_SC05_010_jr_8018473C.c +++ b/src/ov_SC05_010/ov_SC05_010_jr_8018473C.c @@ -3201,14 +3201,7 @@ void func_8018505C(void *a0) { * in src/ov_SC03_099/ov_SC03_099_jr_8012ACE0.c:2737. */ { s32 *p = &d.vx; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(p) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(p); gte_stlvnl(p); } diff --git a/src/ov_SC05_011/ov_SC05_011_jr_8012ACE0.c b/src/ov_SC05_011/ov_SC05_011_jr_8012ACE0.c index 17c1e1179f..62c1e94267 100644 --- a/src/ov_SC05_011/ov_SC05_011_jr_8012ACE0.c +++ b/src/ov_SC05_011/ov_SC05_011_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017E2BC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017E2BC); gte_stlvnl(D_8017E2C0); pc0 = D_8017E2BC; diff --git a/src/ov_SC05_011/ov_SC05_011_jr_801380E0.c b/src/ov_SC05_011/ov_SC05_011_jr_801380E0.c index 0eb92a90bd..112b95b69f 100644 --- a/src/ov_SC05_011/ov_SC05_011_jr_801380E0.c +++ b/src/ov_SC05_011/ov_SC05_011_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8017E3E8[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_011/ov_SC05_011_jr_8013C98C.c b/src/ov_SC05_011/ov_SC05_011_jr_8013C98C.c index 5c77e426d5..693032828e 100644 --- a/src/ov_SC05_011/ov_SC05_011_jr_8013C98C.c +++ b/src/ov_SC05_011/ov_SC05_011_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_011/ov_SC05_011_jr_8017BEBC.c b/src/ov_SC05_011/ov_SC05_011_jr_8017BEBC.c index 3fef31326e..33bebab419 100644 --- a/src/ov_SC05_011/ov_SC05_011_jr_8017BEBC.c +++ b/src/ov_SC05_011/ov_SC05_011_jr_8017BEBC.c @@ -2691,13 +2691,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC05_017/ov_SC05_017_jr_8012ACE0.c b/src/ov_SC05_017/ov_SC05_017_jr_8012ACE0.c index b2bdf7b89c..36b4be7b5f 100644 --- a/src/ov_SC05_017/ov_SC05_017_jr_8012ACE0.c +++ b/src/ov_SC05_017/ov_SC05_017_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018D77C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018D77C); gte_stlvnl(D_8018D780); pc0 = D_8018D77C; diff --git a/src/ov_SC05_017/ov_SC05_017_jr_801380E0.c b/src/ov_SC05_017/ov_SC05_017_jr_801380E0.c index d326b5809b..e0dc474d4e 100644 --- a/src/ov_SC05_017/ov_SC05_017_jr_801380E0.c +++ b/src/ov_SC05_017/ov_SC05_017_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8018D8A8[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_017/ov_SC05_017_jr_8013C98C.c b/src/ov_SC05_017/ov_SC05_017_jr_8013C98C.c index 29ffaf82c7..16de9288c7 100644 --- a/src/ov_SC05_017/ov_SC05_017_jr_8013C98C.c +++ b/src/ov_SC05_017/ov_SC05_017_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.c b/src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.c index 1ca0cdae07..c7eae945bf 100644 --- a/src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.c +++ b/src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.c @@ -3632,13 +3632,6 @@ extern void func_80146C3C(); // K&R: ? of 1 args (P37 rung D t4_D22) #include "../shared/ov/func_8017C6AC.h" -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) #include "../shared/ov/func_8017C710__t3f3d6beb.h" diff --git a/src/ov_SC05_018/ov_SC05_018_jr_8012ACE0.c b/src/ov_SC05_018/ov_SC05_018_jr_8012ACE0.c index 8171160984..2e842e0fba 100644 --- a/src/ov_SC05_018/ov_SC05_018_jr_8012ACE0.c +++ b/src/ov_SC05_018/ov_SC05_018_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80186ED8) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80186ED8); gte_stlvnl(D_80186EDC); pc0 = D_80186ED8; diff --git a/src/ov_SC05_018/ov_SC05_018_jr_801380E0.c b/src/ov_SC05_018/ov_SC05_018_jr_801380E0.c index d702f8e75a..649788fb2c 100644 --- a/src/ov_SC05_018/ov_SC05_018_jr_801380E0.c +++ b/src/ov_SC05_018/ov_SC05_018_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80187004[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC05_018/ov_SC05_018_jr_8013C98C.c b/src/ov_SC05_018/ov_SC05_018_jr_8013C98C.c index 28bfd11d41..f3d370e2c1 100644 --- a/src/ov_SC05_018/ov_SC05_018_jr_8013C98C.c +++ b/src/ov_SC05_018/ov_SC05_018_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC05_019/ov_SC05_019_jr_801380E0.c b/src/ov_SC05_019/ov_SC05_019_jr_801380E0.c index 92fc27253c..9c74e7001f 100644 --- a/src/ov_SC05_019/ov_SC05_019_jr_801380E0.c +++ b/src/ov_SC05_019/ov_SC05_019_jr_801380E0.c @@ -871,11 +871,6 @@ extern s16 D_800D45F4[]; /* src0 (flat: [2*i]=x, [2*i+1]=y) */ extern u8 D_8017F948[]; /* sign table, alt (when a1 < 0xC00) */ -#define gte_mvmva0() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") #include "../shared/ov/func_8013AD38__49b61a70.h" diff --git a/src/ov_SC05_019/ov_SC05_019_jr_8017D5C0.c b/src/ov_SC05_019/ov_SC05_019_jr_8017D5C0.c index 0df77b9c8d..2a0224c7a6 100644 --- a/src/ov_SC05_019/ov_SC05_019_jr_8017D5C0.c +++ b/src/ov_SC05_019/ov_SC05_019_jr_8017D5C0.c @@ -2703,13 +2703,6 @@ extern void func_8017C688(s32 a0, s32 a1); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_000/ov_SC06_000_jr_8012ACE0.c b/src/ov_SC06_000/ov_SC06_000_jr_8012ACE0.c index 0c577dac08..6be5dbf0c6 100644 --- a/src/ov_SC06_000/ov_SC06_000_jr_8012ACE0.c +++ b/src/ov_SC06_000/ov_SC06_000_jr_8012ACE0.c @@ -2407,14 +2407,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018882C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018882C); gte_stlvnl(D_80188830); pc0 = D_8018882C; diff --git a/src/ov_SC06_000/ov_SC06_000_jr_801380E0.c b/src/ov_SC06_000/ov_SC06_000_jr_801380E0.c index c304d60a21..5965c13280 100644 --- a/src/ov_SC06_000/ov_SC06_000_jr_801380E0.c +++ b/src/ov_SC06_000/ov_SC06_000_jr_801380E0.c @@ -1008,11 +1008,6 @@ extern u8 D_80188958[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1034,7 +1029,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_000/ov_SC06_000_jr_8013C98C.c b/src/ov_SC06_000/ov_SC06_000_jr_8013C98C.c index 19a3ba6438..5680e13458 100644 --- a/src/ov_SC06_000/ov_SC06_000_jr_8013C98C.c +++ b/src/ov_SC06_000/ov_SC06_000_jr_8013C98C.c @@ -1496,9 +1496,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_006/ov_SC06_006_jr_8012ACE0.c b/src/ov_SC06_006/ov_SC06_006_jr_8012ACE0.c index d7690c7637..01585f0f22 100644 --- a/src/ov_SC06_006/ov_SC06_006_jr_8012ACE0.c +++ b/src/ov_SC06_006/ov_SC06_006_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182350) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182350); gte_stlvnl(D_80182354); pc0 = D_80182350; diff --git a/src/ov_SC06_006/ov_SC06_006_jr_801380E0.c b/src/ov_SC06_006/ov_SC06_006_jr_801380E0.c index fa938bb484..5bcad3e692 100644 --- a/src/ov_SC06_006/ov_SC06_006_jr_801380E0.c +++ b/src/ov_SC06_006/ov_SC06_006_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8018247C[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_006/ov_SC06_006_jr_8013C98C.c b/src/ov_SC06_006/ov_SC06_006_jr_8013C98C.c index 249496f56b..0db7260d31 100644 --- a/src/ov_SC06_006/ov_SC06_006_jr_8013C98C.c +++ b/src/ov_SC06_006/ov_SC06_006_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_006/ov_SC06_006_jr_8017BEBC.c b/src/ov_SC06_006/ov_SC06_006_jr_8017BEBC.c index 90ac39e00f..d3323b0f68 100644 --- a/src/ov_SC06_006/ov_SC06_006_jr_8017BEBC.c +++ b/src/ov_SC06_006/ov_SC06_006_jr_8017BEBC.c @@ -2689,13 +2689,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_008/ov_SC06_008_jr_8012ACE0.c b/src/ov_SC06_008/ov_SC06_008_jr_8012ACE0.c index 4b10a292ca..4dc1d7a659 100644 --- a/src/ov_SC06_008/ov_SC06_008_jr_8012ACE0.c +++ b/src/ov_SC06_008/ov_SC06_008_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80185DB8) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80185DB8); gte_stlvnl(D_80185DBC); pc0 = D_80185DB8; diff --git a/src/ov_SC06_008/ov_SC06_008_jr_801380E0.c b/src/ov_SC06_008/ov_SC06_008_jr_801380E0.c index 9a2da87ded..75191ce2a8 100644 --- a/src/ov_SC06_008/ov_SC06_008_jr_801380E0.c +++ b/src/ov_SC06_008/ov_SC06_008_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80185EE4[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_008/ov_SC06_008_jr_8013C98C.c b/src/ov_SC06_008/ov_SC06_008_jr_8013C98C.c index 0bb9282061..7456c6cda2 100644 --- a/src/ov_SC06_008/ov_SC06_008_jr_8013C98C.c +++ b/src/ov_SC06_008/ov_SC06_008_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_008/ov_SC06_008_jr_8017C294.c b/src/ov_SC06_008/ov_SC06_008_jr_8017C294.c index fd60fe17cd..11f54d1b7d 100644 --- a/src/ov_SC06_008/ov_SC06_008_jr_8017C294.c +++ b/src/ov_SC06_008/ov_SC06_008_jr_8017C294.c @@ -2692,13 +2692,6 @@ extern void func_8017C230(int a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -3641,11 +3634,6 @@ extern int D_801AA030; /* GTE VARIANT `gte_rtv0tr_m`: memory beyond Sony's `gte_rtv0tr` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rtv0tr_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8017E830(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, diff --git a/src/ov_SC06_010/ov_SC06_010_jr_8012ACE0.c b/src/ov_SC06_010/ov_SC06_010_jr_8012ACE0.c index 1891522bdb..0018df5af4 100644 --- a/src/ov_SC06_010/ov_SC06_010_jr_8012ACE0.c +++ b/src/ov_SC06_010/ov_SC06_010_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80186F94) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80186F94); gte_stlvnl(D_80186F98); pc0 = D_80186F94; diff --git a/src/ov_SC06_010/ov_SC06_010_jr_801380E0.c b/src/ov_SC06_010/ov_SC06_010_jr_801380E0.c index fd49832cce..d687e4eca8 100644 --- a/src/ov_SC06_010/ov_SC06_010_jr_801380E0.c +++ b/src/ov_SC06_010/ov_SC06_010_jr_801380E0.c @@ -1007,11 +1007,6 @@ extern u8 D_801870C0[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1033,7 +1028,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_010/ov_SC06_010_jr_8013C98C.c b/src/ov_SC06_010/ov_SC06_010_jr_8013C98C.c index 7958af721e..cbf58bea11 100644 --- a/src/ov_SC06_010/ov_SC06_010_jr_8013C98C.c +++ b/src/ov_SC06_010/ov_SC06_010_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_011/ov_SC06_011_jr_8012ACE0.c b/src/ov_SC06_011/ov_SC06_011_jr_8012ACE0.c index 14288d152e..9c3409c63f 100644 --- a/src/ov_SC06_011/ov_SC06_011_jr_8012ACE0.c +++ b/src/ov_SC06_011/ov_SC06_011_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801809F4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801809F4); gte_stlvnl(D_801809F8); pc0 = D_801809F4; diff --git a/src/ov_SC06_011/ov_SC06_011_jr_801380E0.c b/src/ov_SC06_011/ov_SC06_011_jr_801380E0.c index 92baa1402b..b4a18c3bc0 100644 --- a/src/ov_SC06_011/ov_SC06_011_jr_801380E0.c +++ b/src/ov_SC06_011/ov_SC06_011_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80180B20[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_011/ov_SC06_011_jr_8013C98C.c b/src/ov_SC06_011/ov_SC06_011_jr_8013C98C.c index 01c18cccc6..cdb3c6d8be 100644 --- a/src/ov_SC06_011/ov_SC06_011_jr_8013C98C.c +++ b/src/ov_SC06_011/ov_SC06_011_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_011/ov_SC06_011_jr_8017BEBC.c b/src/ov_SC06_011/ov_SC06_011_jr_8017BEBC.c index ddc2eb3638..f5a979a203 100644 --- a/src/ov_SC06_011/ov_SC06_011_jr_8017BEBC.c +++ b/src/ov_SC06_011/ov_SC06_011_jr_8017BEBC.c @@ -2691,13 +2691,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_013/ov_SC06_013_jr_8012ACE0.c b/src/ov_SC06_013/ov_SC06_013_jr_8012ACE0.c index db23113375..11e3f6e855 100644 --- a/src/ov_SC06_013/ov_SC06_013_jr_8012ACE0.c +++ b/src/ov_SC06_013/ov_SC06_013_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F170) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F170); gte_stlvnl(D_8017F174); pc0 = D_8017F170; diff --git a/src/ov_SC06_013/ov_SC06_013_jr_801380E0.c b/src/ov_SC06_013/ov_SC06_013_jr_801380E0.c index 9144614c2b..26e29b87c1 100644 --- a/src/ov_SC06_013/ov_SC06_013_jr_801380E0.c +++ b/src/ov_SC06_013/ov_SC06_013_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8017F29C[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_013/ov_SC06_013_jr_8013C98C.c b/src/ov_SC06_013/ov_SC06_013_jr_8013C98C.c index 4223f423df..ec4eef6005 100644 --- a/src/ov_SC06_013/ov_SC06_013_jr_8013C98C.c +++ b/src/ov_SC06_013/ov_SC06_013_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c b/src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c index 65c05cbe96..05615ada8f 100644 --- a/src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c +++ b/src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c @@ -2689,13 +2689,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_014/ov_SC06_014_jr_8012ACE0.c b/src/ov_SC06_014/ov_SC06_014_jr_8012ACE0.c index 39b60fd4c2..6f19cb6081 100644 --- a/src/ov_SC06_014/ov_SC06_014_jr_8012ACE0.c +++ b/src/ov_SC06_014/ov_SC06_014_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801804D4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801804D4); gte_stlvnl(D_801804D8); pc0 = D_801804D4; diff --git a/src/ov_SC06_014/ov_SC06_014_jr_801380E0.c b/src/ov_SC06_014/ov_SC06_014_jr_801380E0.c index 2711fd948b..03db3f4a4d 100644 --- a/src/ov_SC06_014/ov_SC06_014_jr_801380E0.c +++ b/src/ov_SC06_014/ov_SC06_014_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80180600[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_014/ov_SC06_014_jr_8013C98C.c b/src/ov_SC06_014/ov_SC06_014_jr_8013C98C.c index 36a7f3e65e..f77bc4cd26 100644 --- a/src/ov_SC06_014/ov_SC06_014_jr_8013C98C.c +++ b/src/ov_SC06_014/ov_SC06_014_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c b/src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c index 35a1bedf82..1bd6956230 100644 --- a/src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c +++ b/src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c @@ -2689,13 +2689,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_015/ov_SC06_015_jr_8012ACE0.c b/src/ov_SC06_015/ov_SC06_015_jr_8012ACE0.c index 34cd569694..18293f0a6f 100644 --- a/src/ov_SC06_015/ov_SC06_015_jr_8012ACE0.c +++ b/src/ov_SC06_015/ov_SC06_015_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F02C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F02C); gte_stlvnl(D_8017F030); pc0 = D_8017F02C; diff --git a/src/ov_SC06_015/ov_SC06_015_jr_801380E0.c b/src/ov_SC06_015/ov_SC06_015_jr_801380E0.c index 76d0a81ad3..63a9059a2a 100644 --- a/src/ov_SC06_015/ov_SC06_015_jr_801380E0.c +++ b/src/ov_SC06_015/ov_SC06_015_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8017F158[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_015/ov_SC06_015_jr_8013C98C.c b/src/ov_SC06_015/ov_SC06_015_jr_8013C98C.c index 0bb3edbd37..592f2f881e 100644 --- a/src/ov_SC06_015/ov_SC06_015_jr_8013C98C.c +++ b/src/ov_SC06_015/ov_SC06_015_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c b/src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c index 58dd49b3ba..9cdfb4df0c 100644 --- a/src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c +++ b/src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c @@ -2680,13 +2680,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_016/ov_SC06_016_jr_8012ACE0.c b/src/ov_SC06_016/ov_SC06_016_jr_8012ACE0.c index 748f45c6ce..dbd6a0e035 100644 --- a/src/ov_SC06_016/ov_SC06_016_jr_8012ACE0.c +++ b/src/ov_SC06_016/ov_SC06_016_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018543C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018543C); gte_stlvnl(D_80185440); pc0 = D_8018543C; diff --git a/src/ov_SC06_016/ov_SC06_016_jr_801380E0.c b/src/ov_SC06_016/ov_SC06_016_jr_801380E0.c index 057db51ae0..b033ce750b 100644 --- a/src/ov_SC06_016/ov_SC06_016_jr_801380E0.c +++ b/src/ov_SC06_016/ov_SC06_016_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80185568[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_016/ov_SC06_016_jr_8013C98C.c b/src/ov_SC06_016/ov_SC06_016_jr_8013C98C.c index bbe572891f..d48cbb5216 100644 --- a/src/ov_SC06_016/ov_SC06_016_jr_8013C98C.c +++ b/src/ov_SC06_016/ov_SC06_016_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c b/src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c index 039ef8a1cf..68ac08e7de 100644 --- a/src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c +++ b/src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c @@ -2691,13 +2691,6 @@ extern void func_8017C114(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_018/ov_SC06_018_jr_8012ACE0.c b/src/ov_SC06_018/ov_SC06_018_jr_8012ACE0.c index 9e8779be71..d0ac3840a1 100644 --- a/src/ov_SC06_018/ov_SC06_018_jr_8012ACE0.c +++ b/src/ov_SC06_018/ov_SC06_018_jr_8012ACE0.c @@ -2408,14 +2408,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80193B78) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80193B78); gte_stlvnl(D_80193B7C); pc0 = D_80193B78; diff --git a/src/ov_SC06_018/ov_SC06_018_jr_801380E0.c b/src/ov_SC06_018/ov_SC06_018_jr_801380E0.c index 5d782ffee8..dee9cd1f17 100644 --- a/src/ov_SC06_018/ov_SC06_018_jr_801380E0.c +++ b/src/ov_SC06_018/ov_SC06_018_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80193CA4[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_018/ov_SC06_018_jr_8013C98C.c b/src/ov_SC06_018/ov_SC06_018_jr_8013C98C.c index 53326f2d89..eba88522d3 100644 --- a/src/ov_SC06_018/ov_SC06_018_jr_8013C98C.c +++ b/src/ov_SC06_018/ov_SC06_018_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_020/ov_SC06_020_jr_8012ACE0.c b/src/ov_SC06_020/ov_SC06_020_jr_8012ACE0.c index 831df4966e..6b0bc4320c 100644 --- a/src/ov_SC06_020/ov_SC06_020_jr_8012ACE0.c +++ b/src/ov_SC06_020/ov_SC06_020_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80185600) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80185600); gte_stlvnl(D_80185604); pc0 = D_80185600; diff --git a/src/ov_SC06_020/ov_SC06_020_jr_801380E0.c b/src/ov_SC06_020/ov_SC06_020_jr_801380E0.c index 3537d252cb..89844288c5 100644 --- a/src/ov_SC06_020/ov_SC06_020_jr_801380E0.c +++ b/src/ov_SC06_020/ov_SC06_020_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8018572C[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_020/ov_SC06_020_jr_8013C98C.c b/src/ov_SC06_020/ov_SC06_020_jr_8013C98C.c index 70834bdbfd..f4e5d0c6d8 100644 --- a/src/ov_SC06_020/ov_SC06_020_jr_8013C98C.c +++ b/src/ov_SC06_020/ov_SC06_020_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_022/ov_SC06_022_jr_8012ACE0.c b/src/ov_SC06_022/ov_SC06_022_jr_8012ACE0.c index a81d8317fd..4c725c4fec 100644 --- a/src/ov_SC06_022/ov_SC06_022_jr_8012ACE0.c +++ b/src/ov_SC06_022/ov_SC06_022_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018D8BC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018D8BC); gte_stlvnl(D_8018D8C0); pc0 = D_8018D8BC; diff --git a/src/ov_SC06_022/ov_SC06_022_jr_801380E0.c b/src/ov_SC06_022/ov_SC06_022_jr_801380E0.c index 711dcb1467..a823df80cf 100644 --- a/src/ov_SC06_022/ov_SC06_022_jr_801380E0.c +++ b/src/ov_SC06_022/ov_SC06_022_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8018D9E8[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_022/ov_SC06_022_jr_8013C98C.c b/src/ov_SC06_022/ov_SC06_022_jr_8013C98C.c index c47a6179be..5ecc81af0d 100644 --- a/src/ov_SC06_022/ov_SC06_022_jr_8013C98C.c +++ b/src/ov_SC06_022/ov_SC06_022_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_022/ov_SC06_022_jr_8017BEBC.c b/src/ov_SC06_022/ov_SC06_022_jr_8017BEBC.c index f77793842d..5b31e0e3de 100644 --- a/src/ov_SC06_022/ov_SC06_022_jr_8017BEBC.c +++ b/src/ov_SC06_022/ov_SC06_022_jr_8017BEBC.c @@ -2683,13 +2683,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_024/ov_SC06_024_jr_8012ACE0.c b/src/ov_SC06_024/ov_SC06_024_jr_8012ACE0.c index 315bec93ca..2b2ea3d60c 100644 --- a/src/ov_SC06_024/ov_SC06_024_jr_8012ACE0.c +++ b/src/ov_SC06_024/ov_SC06_024_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018FD94) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018FD94); gte_stlvnl(D_8018FD98); pc0 = D_8018FD94; diff --git a/src/ov_SC06_024/ov_SC06_024_jr_801380E0.c b/src/ov_SC06_024/ov_SC06_024_jr_801380E0.c index 92462ff5a4..5d58a383d2 100644 --- a/src/ov_SC06_024/ov_SC06_024_jr_801380E0.c +++ b/src/ov_SC06_024/ov_SC06_024_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8018FEC0[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_024/ov_SC06_024_jr_8013C98C.c b/src/ov_SC06_024/ov_SC06_024_jr_8013C98C.c index a4e06ac0ed..0ab6d02171 100644 --- a/src/ov_SC06_024/ov_SC06_024_jr_8013C98C.c +++ b/src/ov_SC06_024/ov_SC06_024_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_024/ov_SC06_024_jr_8017BEBC.c b/src/ov_SC06_024/ov_SC06_024_jr_8017BEBC.c index a281931c50..f1936b476a 100644 --- a/src/ov_SC06_024/ov_SC06_024_jr_8017BEBC.c +++ b/src/ov_SC06_024/ov_SC06_024_jr_8017BEBC.c @@ -2682,13 +2682,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_025/ov_SC06_025_jr_8012ACE0.c b/src/ov_SC06_025/ov_SC06_025_jr_8012ACE0.c index 766f80452d..c8a13bbc06 100644 --- a/src/ov_SC06_025/ov_SC06_025_jr_8012ACE0.c +++ b/src/ov_SC06_025/ov_SC06_025_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80185238) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80185238); gte_stlvnl(D_8018523C); pc0 = D_80185238; diff --git a/src/ov_SC06_025/ov_SC06_025_jr_801380E0.c b/src/ov_SC06_025/ov_SC06_025_jr_801380E0.c index a395e93448..6b69bd624e 100644 --- a/src/ov_SC06_025/ov_SC06_025_jr_801380E0.c +++ b/src/ov_SC06_025/ov_SC06_025_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80185364[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_025/ov_SC06_025_jr_8013C98C.c b/src/ov_SC06_025/ov_SC06_025_jr_8013C98C.c index d46c1e448a..da2624a9f8 100644 --- a/src/ov_SC06_025/ov_SC06_025_jr_8013C98C.c +++ b/src/ov_SC06_025/ov_SC06_025_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_025/ov_SC06_025_jr_8017BEBC.c b/src/ov_SC06_025/ov_SC06_025_jr_8017BEBC.c index 064eb9ee5a..f8ce9765d8 100644 --- a/src/ov_SC06_025/ov_SC06_025_jr_8017BEBC.c +++ b/src/ov_SC06_025/ov_SC06_025_jr_8017BEBC.c @@ -2689,13 +2689,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_025/ov_SC06_025_jr_8017EEC4.c b/src/ov_SC06_025/ov_SC06_025_jr_8017EEC4.c index d58f4cd88a..4b2b2674db 100644 --- a/src/ov_SC06_025/ov_SC06_025_jr_8017EEC4.c +++ b/src/ov_SC06_025/ov_SC06_025_jr_8017EEC4.c @@ -6637,11 +6637,6 @@ extern int D_801B2114; /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_80183ED8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, @@ -6687,15 +6682,15 @@ void func_80183ED8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, { int t = f->vy - 0x10; f->vy = t + (r & 0x1f); } gte_ldv0(c); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(r0_00); gte_ldv0(f); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(r0_00 + 1); gte_ldv0(d); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) r0 = r0_00 + 2; gte_stsv(r0); @@ -6704,7 +6699,7 @@ void func_80183ED8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, d->vx = d->vx - (f->pad & r); gte_ldv0(d); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) pSVar6 = r0_00 + 3; gte_stsv(pSVar6); @@ -6712,7 +6707,7 @@ void func_80183ED8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, func_80017714(r0_00); gte_ldv0(e); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(r0); *e = *f; @@ -6720,7 +6715,7 @@ void func_80183ED8(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, e->vx = e->vx + (f->pad & r); gte_ldv0(e); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(pSVar6); r0_00->vz = ((u16 *)b)[2]; diff --git a/src/ov_SC06_027/ov_SC06_027_jr_8012ACE0.c b/src/ov_SC06_027/ov_SC06_027_jr_8012ACE0.c index 712e81501d..e8517daab5 100644 --- a/src/ov_SC06_027/ov_SC06_027_jr_8012ACE0.c +++ b/src/ov_SC06_027/ov_SC06_027_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017E578) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017E578); gte_stlvnl(D_8017E57C); pc0 = D_8017E578; diff --git a/src/ov_SC06_027/ov_SC06_027_jr_801380E0.c b/src/ov_SC06_027/ov_SC06_027_jr_801380E0.c index b213d06127..d387eed700 100644 --- a/src/ov_SC06_027/ov_SC06_027_jr_801380E0.c +++ b/src/ov_SC06_027/ov_SC06_027_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8017E6A4[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_027/ov_SC06_027_jr_8013C98C.c b/src/ov_SC06_027/ov_SC06_027_jr_8013C98C.c index 8d9607b2e9..1123958a78 100644 --- a/src/ov_SC06_027/ov_SC06_027_jr_8013C98C.c +++ b/src/ov_SC06_027/ov_SC06_027_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_027/ov_SC06_027_jr_8017BEBC.c b/src/ov_SC06_027/ov_SC06_027_jr_8017BEBC.c index fdb36c698f..9070bf0492 100644 --- a/src/ov_SC06_027/ov_SC06_027_jr_8017BEBC.c +++ b/src/ov_SC06_027/ov_SC06_027_jr_8017BEBC.c @@ -2692,13 +2692,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -3340,71 +3333,7 @@ void func_8017DADC(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC06_029/ov_SC06_029_jr_8012ACE0.c b/src/ov_SC06_029/ov_SC06_029_jr_8012ACE0.c index 39a80606b6..8c5cef08b6 100644 --- a/src/ov_SC06_029/ov_SC06_029_jr_8012ACE0.c +++ b/src/ov_SC06_029/ov_SC06_029_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018CB0C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018CB0C); gte_stlvnl(D_8018CB10); pc0 = D_8018CB0C; diff --git a/src/ov_SC06_029/ov_SC06_029_jr_801380E0.c b/src/ov_SC06_029/ov_SC06_029_jr_801380E0.c index 2cd496e1bc..e36ff542fe 100644 --- a/src/ov_SC06_029/ov_SC06_029_jr_801380E0.c +++ b/src/ov_SC06_029/ov_SC06_029_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8018CC38[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_029/ov_SC06_029_jr_8013C98C.c b/src/ov_SC06_029/ov_SC06_029_jr_8013C98C.c index 3d25de9fb8..0b395ba81d 100644 --- a/src/ov_SC06_029/ov_SC06_029_jr_8013C98C.c +++ b/src/ov_SC06_029/ov_SC06_029_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_029/ov_SC06_029_jr_8017C954.c b/src/ov_SC06_029/ov_SC06_029_jr_8017C954.c index 58b2355e12..1ebdcd9196 100644 --- a/src/ov_SC06_029/ov_SC06_029_jr_8017C954.c +++ b/src/ov_SC06_029/ov_SC06_029_jr_8017C954.c @@ -6866,14 +6866,7 @@ void func_801838BC(short *param_1, short *param_2) Y = 0x7F; v[2] = param_1[2] - *(s16 *)&D_80126B66; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(v) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(v); gte_stlvnl(v); t = v[0] + v[2] - 0x4000; diff --git a/src/ov_SC06_029/ov_SC06_029_jr_801898CC.c b/src/ov_SC06_029/ov_SC06_029_jr_801898CC.c index d25bd4d376..4a219d0b26 100644 --- a/src/ov_SC06_029/ov_SC06_029_jr_801898CC.c +++ b/src/ov_SC06_029/ov_SC06_029_jr_801898CC.c @@ -4031,71 +4031,7 @@ void func_8018AA60(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } @@ -4910,11 +4846,6 @@ extern int D_801E1ED4; /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8018BA5C(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, @@ -4960,15 +4891,15 @@ void func_8018BA5C(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, { int t = f->vy - 0x10; f->vy = t + (r & 0x1f); } gte_ldv0(c); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(r0_00); gte_ldv0(f); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(r0_00 + 1); gte_ldv0(d); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) r0 = r0_00 + 2; gte_stsv(r0); @@ -4977,7 +4908,7 @@ void func_8018BA5C(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, d->vx = d->vx - (f->pad & r); gte_ldv0(d); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) pSVar6 = r0_00 + 3; gte_stsv(pSVar6); @@ -4985,7 +4916,7 @@ void func_8018BA5C(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, func_80017714(r0_00); gte_ldv0(e); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(r0); *e = *f; @@ -4993,7 +4924,7 @@ void func_8018BA5C(int a, s16 *b, SVECTOR_8017E6D8 *c, SVECTOR_8017E6D8 *d, e->vx = e->vx + (f->pad & r); gte_ldv0(e); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stsv(pSVar6); r0_00->vz = ((u16 *)b)[2]; diff --git a/src/ov_SC06_030/ov_SC06_030_jr_8012ACE0.c b/src/ov_SC06_030/ov_SC06_030_jr_8012ACE0.c index 20a3329fed..26158e1ad3 100644 --- a/src/ov_SC06_030/ov_SC06_030_jr_8012ACE0.c +++ b/src/ov_SC06_030/ov_SC06_030_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801823FC) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801823FC); gte_stlvnl(D_80182400); pc0 = D_801823FC; diff --git a/src/ov_SC06_030/ov_SC06_030_jr_801380E0.c b/src/ov_SC06_030/ov_SC06_030_jr_801380E0.c index e3e136e789..ee985da889 100644 --- a/src/ov_SC06_030/ov_SC06_030_jr_801380E0.c +++ b/src/ov_SC06_030/ov_SC06_030_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80182528[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_030/ov_SC06_030_jr_8013C98C.c b/src/ov_SC06_030/ov_SC06_030_jr_8013C98C.c index 6c8d9c92f5..aadd24f2d1 100644 --- a/src/ov_SC06_030/ov_SC06_030_jr_8013C98C.c +++ b/src/ov_SC06_030/ov_SC06_030_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.c b/src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.c index 6063a1da35..baaede3ae1 100644 --- a/src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.c +++ b/src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.c @@ -2688,13 +2688,6 @@ extern void func_8017C114(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC06_032/ov_SC06_032_jr_8012ACE0.c b/src/ov_SC06_032/ov_SC06_032_jr_8012ACE0.c index 90c7a348a0..a36a91451e 100644 --- a/src/ov_SC06_032/ov_SC06_032_jr_8012ACE0.c +++ b/src/ov_SC06_032/ov_SC06_032_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801938C8) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801938C8); gte_stlvnl(D_801938CC); pc0 = D_801938C8; diff --git a/src/ov_SC06_032/ov_SC06_032_jr_801380E0.c b/src/ov_SC06_032/ov_SC06_032_jr_801380E0.c index 35a930a435..561697d799 100644 --- a/src/ov_SC06_032/ov_SC06_032_jr_801380E0.c +++ b/src/ov_SC06_032/ov_SC06_032_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_801939F4[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_032/ov_SC06_032_jr_8013C98C.c b/src/ov_SC06_032/ov_SC06_032_jr_8013C98C.c index af2317b95a..4e48be4e07 100644 --- a/src/ov_SC06_032/ov_SC06_032_jr_8013C98C.c +++ b/src/ov_SC06_032/ov_SC06_032_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC06_033/ov_SC06_033_jr_8012ACE0.c b/src/ov_SC06_033/ov_SC06_033_jr_8012ACE0.c index 944ae1ab94..687d5dd27a 100644 --- a/src/ov_SC06_033/ov_SC06_033_jr_8012ACE0.c +++ b/src/ov_SC06_033/ov_SC06_033_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80191DD8) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80191DD8); gte_stlvnl(D_80191DDC); pc0 = D_80191DD8; diff --git a/src/ov_SC06_033/ov_SC06_033_jr_801380E0.c b/src/ov_SC06_033/ov_SC06_033_jr_801380E0.c index ded6935dae..3479249c75 100644 --- a/src/ov_SC06_033/ov_SC06_033_jr_801380E0.c +++ b/src/ov_SC06_033/ov_SC06_033_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80191F04[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC06_033/ov_SC06_033_jr_8013C98C.c b/src/ov_SC06_033/ov_SC06_033_jr_8013C98C.c index 2f55f153a1..38a9ddf586 100644 --- a/src/ov_SC06_033/ov_SC06_033_jr_8013C98C.c +++ b/src/ov_SC06_033/ov_SC06_033_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC07_000/ov_SC07_000_jr_8012ACE0.c b/src/ov_SC07_000/ov_SC07_000_jr_8012ACE0.c index 38f1cb3ec6..b22fb660ea 100644 --- a/src/ov_SC07_000/ov_SC07_000_jr_8012ACE0.c +++ b/src/ov_SC07_000/ov_SC07_000_jr_8012ACE0.c @@ -2407,14 +2407,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182C20) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182C20); gte_stlvnl(D_80182C24); pc0 = D_80182C20; diff --git a/src/ov_SC07_000/ov_SC07_000_jr_801380E0.c b/src/ov_SC07_000/ov_SC07_000_jr_801380E0.c index be681a2afa..b230fd5b56 100644 --- a/src/ov_SC07_000/ov_SC07_000_jr_801380E0.c +++ b/src/ov_SC07_000/ov_SC07_000_jr_801380E0.c @@ -1005,11 +1005,6 @@ extern u8 D_80182D4C[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1031,7 +1026,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC07_000/ov_SC07_000_jr_8013C98C.c b/src/ov_SC07_000/ov_SC07_000_jr_8013C98C.c index 70af8e4b71..aa88dd85a6 100644 --- a/src/ov_SC07_000/ov_SC07_000_jr_8013C98C.c +++ b/src/ov_SC07_000/ov_SC07_000_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC07_001/ov_SC07_001_jr_8012ACE0.c b/src/ov_SC07_001/ov_SC07_001_jr_8012ACE0.c index 210d30071b..596bb1be22 100644 --- a/src/ov_SC07_001/ov_SC07_001_jr_8012ACE0.c +++ b/src/ov_SC07_001/ov_SC07_001_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80181AD0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80181AD0); gte_stlvnl(D_80181AD4); pc0 = D_80181AD0; diff --git a/src/ov_SC07_001/ov_SC07_001_jr_801380E0.c b/src/ov_SC07_001/ov_SC07_001_jr_801380E0.c index b09705a8c6..c43e1da4e1 100644 --- a/src/ov_SC07_001/ov_SC07_001_jr_801380E0.c +++ b/src/ov_SC07_001/ov_SC07_001_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80181BFC[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC07_001/ov_SC07_001_jr_8013C98C.c b/src/ov_SC07_001/ov_SC07_001_jr_8013C98C.c index 5850027c22..e752f7650e 100644 --- a/src/ov_SC07_001/ov_SC07_001_jr_8013C98C.c +++ b/src/ov_SC07_001/ov_SC07_001_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC07_001/ov_SC07_001_jr_8017BEBC.c b/src/ov_SC07_001/ov_SC07_001_jr_8017BEBC.c index 1e552866b7..ccd34f5d50 100644 --- a/src/ov_SC07_001/ov_SC07_001_jr_8017BEBC.c +++ b/src/ov_SC07_001/ov_SC07_001_jr_8017BEBC.c @@ -2692,13 +2692,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -4830,71 +4823,7 @@ void func_80181034(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC07_002/ov_SC07_002_jr_8012ACE0.c b/src/ov_SC07_002/ov_SC07_002_jr_8012ACE0.c index ef8970eb19..17222981fb 100644 --- a/src/ov_SC07_002/ov_SC07_002_jr_8012ACE0.c +++ b/src/ov_SC07_002/ov_SC07_002_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80186D8C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80186D8C); gte_stlvnl(D_80186D90); pc0 = D_80186D8C; diff --git a/src/ov_SC07_002/ov_SC07_002_jr_801380E0.c b/src/ov_SC07_002/ov_SC07_002_jr_801380E0.c index 18af41e30b..227dae1efe 100644 --- a/src/ov_SC07_002/ov_SC07_002_jr_801380E0.c +++ b/src/ov_SC07_002/ov_SC07_002_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_80186EB8[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC07_002/ov_SC07_002_jr_8013C98C.c b/src/ov_SC07_002/ov_SC07_002_jr_8013C98C.c index 8fd763a76a..7c85594711 100644 --- a/src/ov_SC07_002/ov_SC07_002_jr_8013C98C.c +++ b/src/ov_SC07_002/ov_SC07_002_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC07_002/ov_SC07_002_jr_8017C8D0.c b/src/ov_SC07_002/ov_SC07_002_jr_8017C8D0.c index da00f88e7d..ef2dc89298 100644 --- a/src/ov_SC07_002/ov_SC07_002_jr_8017C8D0.c +++ b/src/ov_SC07_002/ov_SC07_002_jr_8017C8D0.c @@ -2695,13 +2695,6 @@ extern void func_8017C114(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -8170,71 +8163,7 @@ void func_801856E8(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC07_006/ov_SC07_006_jr_80131340.c b/src/ov_SC07_006/ov_SC07_006_jr_80131340.c index b72784369a..078ffaf32e 100644 --- a/src/ov_SC07_006/ov_SC07_006_jr_80131340.c +++ b/src/ov_SC07_006/ov_SC07_006_jr_80131340.c @@ -1594,14 +1594,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8018A9B0) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8018A9B0); gte_stlvnl(D_8018A9B4); pc0 = D_8018A9B0; diff --git a/src/ov_SC07_006/ov_SC07_006_jr_801380E0.c b/src/ov_SC07_006/ov_SC07_006_jr_801380E0.c index 34d737e876..651afa8f6c 100644 --- a/src/ov_SC07_006/ov_SC07_006_jr_801380E0.c +++ b/src/ov_SC07_006/ov_SC07_006_jr_801380E0.c @@ -1297,11 +1297,6 @@ extern void func_8013AF20(u32 *param_1, u16 *param_2, u16 *param_3, u8 *param_4) /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) { @@ -1324,7 +1319,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) { vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair *)out2)[i].x = res[0]; ((Pair *)out2)[i].y = res[1]; diff --git a/src/ov_SC07_006/ov_SC07_006_jr_8013C98C.c b/src/ov_SC07_006/ov_SC07_006_jr_8013C98C.c index a67f13d73d..71b8b26eca 100644 --- a/src/ov_SC07_006/ov_SC07_006_jr_8013C98C.c +++ b/src/ov_SC07_006/ov_SC07_006_jr_8013C98C.c @@ -1391,9 +1391,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC07_006/ov_SC07_006_jr_8017BEBC.c b/src/ov_SC07_006/ov_SC07_006_jr_8017BEBC.c index dbd26d9d5d..e63a91de16 100644 --- a/src/ov_SC07_006/ov_SC07_006_jr_8017BEBC.c +++ b/src/ov_SC07_006/ov_SC07_006_jr_8017BEBC.c @@ -3203,13 +3203,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC07_007/ov_SC07_007_jr_80131340.c b/src/ov_SC07_007/ov_SC07_007_jr_80131340.c index 3500033527..55edd218fd 100644 --- a/src/ov_SC07_007/ov_SC07_007_jr_80131340.c +++ b/src/ov_SC07_007/ov_SC07_007_jr_80131340.c @@ -1591,14 +1591,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_801834D4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_801834D4); gte_stlvnl(D_801834D8); pc0 = D_801834D4; diff --git a/src/ov_SC07_007/ov_SC07_007_jr_801380E0.c b/src/ov_SC07_007/ov_SC07_007_jr_801380E0.c index 99fa1de8c3..b96ae403b8 100644 --- a/src/ov_SC07_007/ov_SC07_007_jr_801380E0.c +++ b/src/ov_SC07_007/ov_SC07_007_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern void func_8013AF20(u32 *param_1, u16 *param_2, u16 *param_3, u8 *param_4) /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) { @@ -1031,7 +1026,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) { vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair *)out2)[i].x = res[0]; ((Pair *)out2)[i].y = res[1]; diff --git a/src/ov_SC07_007/ov_SC07_007_jr_8013C98C.c b/src/ov_SC07_007/ov_SC07_007_jr_8013C98C.c index 3bc35e1ed1..316a670742 100644 --- a/src/ov_SC07_007/ov_SC07_007_jr_8013C98C.c +++ b/src/ov_SC07_007/ov_SC07_007_jr_8013C98C.c @@ -1391,9 +1391,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC07_007/ov_SC07_007_jr_8017BEBC.c b/src/ov_SC07_007/ov_SC07_007_jr_8017BEBC.c index 40bac983a1..a37c4e5d72 100644 --- a/src/ov_SC07_007/ov_SC07_007_jr_8017BEBC.c +++ b/src/ov_SC07_007/ov_SC07_007_jr_8017BEBC.c @@ -3196,13 +3196,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC07_008/ov_SC07_008_jr_8012ACE0.c b/src/ov_SC07_008/ov_SC07_008_jr_8012ACE0.c index ac49d19d1c..f000f6e107 100644 --- a/src/ov_SC07_008/ov_SC07_008_jr_8012ACE0.c +++ b/src/ov_SC07_008/ov_SC07_008_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017D8A4) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017D8A4); gte_stlvnl(D_8017D8A8); pc0 = D_8017D8A4; diff --git a/src/ov_SC07_008/ov_SC07_008_jr_801380E0.c b/src/ov_SC07_008/ov_SC07_008_jr_801380E0.c index 49d1690ee8..bf0949c37b 100644 --- a/src/ov_SC07_008/ov_SC07_008_jr_801380E0.c +++ b/src/ov_SC07_008/ov_SC07_008_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8017D9D0[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC07_008/ov_SC07_008_jr_8013C98C.c b/src/ov_SC07_008/ov_SC07_008_jr_8013C98C.c index 107e6aaea5..6358c85203 100644 --- a/src/ov_SC07_008/ov_SC07_008_jr_8013C98C.c +++ b/src/ov_SC07_008/ov_SC07_008_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c b/src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c index 138bce76f7..5e37c6646f 100644 --- a/src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c +++ b/src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c @@ -2681,13 +2681,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/ov_SC07_009/ov_SC07_009_jr_8012ACE0.c b/src/ov_SC07_009/ov_SC07_009_jr_8012ACE0.c index 4f2d82ca34..91a95840d6 100644 --- a/src/ov_SC07_009/ov_SC07_009_jr_8012ACE0.c +++ b/src/ov_SC07_009/ov_SC07_009_jr_8012ACE0.c @@ -2405,14 +2405,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017E348) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017E348); gte_stlvnl(D_8017E34C); pc0 = D_8017E348; diff --git a/src/ov_SC07_009/ov_SC07_009_jr_801380E0.c b/src/ov_SC07_009/ov_SC07_009_jr_801380E0.c index dd84965d60..abac2638dc 100644 --- a/src/ov_SC07_009/ov_SC07_009_jr_801380E0.c +++ b/src/ov_SC07_009/ov_SC07_009_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern u8 D_8017E474[]; /* sign table, alt (when a1 < 0xC00) */ /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) @@ -1030,7 +1025,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair_8013AD38 *)out2)[i].x = res[0]; ((Pair_8013AD38 *)out2)[i].y = res[1]; diff --git a/src/ov_SC07_009/ov_SC07_009_jr_8013C98C.c b/src/ov_SC07_009/ov_SC07_009_jr_8013C98C.c index e378d27447..1e64cdaf9b 100644 --- a/src/ov_SC07_009/ov_SC07_009_jr_8013C98C.c +++ b/src/ov_SC07_009/ov_SC07_009_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c b/src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c index c6bf2396d6..7bfe5af3df 100644 --- a/src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c +++ b/src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c @@ -3290,13 +3290,6 @@ void func_8017BE60(void *a0) { #include "../shared/ov/func_8017BEB4.h" -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) #include "../shared/ov/func_8017BEBC__t67f11bf2.h" diff --git a/src/ov_SC07_010/ov_SC07_010_jr_80131340.c b/src/ov_SC07_010/ov_SC07_010_jr_80131340.c index b7861ff0cc..1a37c112a5 100644 --- a/src/ov_SC07_010/ov_SC07_010_jr_80131340.c +++ b/src/ov_SC07_010/ov_SC07_010_jr_80131340.c @@ -1596,14 +1596,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_80182564) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_80182564); gte_stlvnl(D_80182568); pc0 = D_80182564; diff --git a/src/ov_SC07_010/ov_SC07_010_jr_801380E0.c b/src/ov_SC07_010/ov_SC07_010_jr_801380E0.c index 91ec6e509c..67debcd489 100644 --- a/src/ov_SC07_010/ov_SC07_010_jr_801380E0.c +++ b/src/ov_SC07_010/ov_SC07_010_jr_801380E0.c @@ -1007,11 +1007,6 @@ void func_8013A378(void) { /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) { @@ -1034,7 +1029,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) { vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair *)out2)[i].x = res[0]; ((Pair *)out2)[i].y = res[1]; diff --git a/src/ov_SC07_010/ov_SC07_010_o2b.c b/src/ov_SC07_010/ov_SC07_010_o2b.c index 5ef9a8b5c2..8a6ad53f79 100644 --- a/src/ov_SC07_010/ov_SC07_010_o2b.c +++ b/src/ov_SC07_010/ov_SC07_010_o2b.c @@ -711,9 +711,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC07_011/ov_SC07_011_jr_80131340.c b/src/ov_SC07_011/ov_SC07_011_jr_80131340.c index e0e2d0a6a6..f23247509a 100644 --- a/src/ov_SC07_011/ov_SC07_011_jr_80131340.c +++ b/src/ov_SC07_011/ov_SC07_011_jr_80131340.c @@ -1591,14 +1591,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017EC24) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017EC24); gte_stlvnl(D_8017EC28); pc0 = D_8017EC24; diff --git a/src/ov_SC07_011/ov_SC07_011_jr_801380E0.c b/src/ov_SC07_011/ov_SC07_011_jr_801380E0.c index a560bf4ffd..f343b20646 100644 --- a/src/ov_SC07_011/ov_SC07_011_jr_801380E0.c +++ b/src/ov_SC07_011/ov_SC07_011_jr_801380E0.c @@ -1004,11 +1004,6 @@ extern void func_8013AF20(u32 *param_1, u16 *param_2, u16 *param_3, u8 *param_4) /* GTE VARIANT `gte_rt_m`: memory beyond Sony's `gte_rt` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rt_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 0, 0\n" \ - : : : "memory") void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) { @@ -1031,7 +1026,7 @@ void func_8013AD38(void *flag, s32 a1, void *out2, void *out3) { vec[0] = D_800D45F4[2 * i] + (((D_800D466C[2 * i] - D_800D45F4[2 * i]) * ((s16)a1)) >> 12); vec[1] = D_800D45F4[2 * i + 1] + (((D_800D466C[2 * i + 1] - D_800D45F4[2 * i + 1]) * ((s16)a1)) >> 12); gte_ldv0(vec); - gte_rt_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) + gte_rtv0tr_m(); // !FAKE: gte via gte_rt_m — memory beyond Sony's `gte_rt` (P36 T5 gte2) gte_stlvnl(res); ((Pair *)out2)[i].x = res[0]; ((Pair *)out2)[i].y = res[1]; diff --git a/src/ov_SC07_011/ov_SC07_011_jr_8013C98C.c b/src/ov_SC07_011/ov_SC07_011_jr_8013C98C.c index d0a97186c0..28d0453af3 100644 --- a/src/ov_SC07_011/ov_SC07_011_jr_8013C98C.c +++ b/src/ov_SC07_011/ov_SC07_011_jr_8013C98C.c @@ -1392,9 +1392,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC07_011/ov_SC07_011_jr_8017BEBC.c b/src/ov_SC07_011/ov_SC07_011_jr_8017BEBC.c index 912859f19d..ad9a85d3b2 100644 --- a/src/ov_SC07_011/ov_SC07_011_jr_8017BEBC.c +++ b/src/ov_SC07_011/ov_SC07_011_jr_8017BEBC.c @@ -3196,13 +3196,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) diff --git a/src/shared/ov/func_8012BFA8.h b/src/shared/ov/func_8012BFA8.h index fb9893b3f3..b2ac65bf50 100644 --- a/src/shared/ov/func_8012BFA8.h +++ b/src/shared/ov/func_8012BFA8.h @@ -9,14 +9,7 @@ int func_8012BFA8(short *a0) { in[0] = D_80126CAC - a0[3]; in[1] = D_80126CAE - a0[5]; in[2] = D_80126CB0 - a0[7]; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(&in[0]) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(&in[0]); { int *pout = &out[0]; gte_stlvnl(pout); diff --git a/src/shared/ov/func_8012EF34.h b/src/shared/ov/func_8012EF34.h index 1d5a662476..ba7b917a2f 100644 --- a/src/shared/ov/func_8012EF34.h +++ b/src/shared/ov/func_8012EF34.h @@ -7,7 +7,7 @@ void func_8012EF34(s32 a0, s32 a1) { func_8012EFB8(a0); { register s32 *p __asm__("$3") = &sp10; // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B headers1) - __asm__ __volatile__("swc2 $19, 0(%0)" : : "r"(p) : "memory"); + gte_stsz(p); } v1 = sp10; *(s16 *)(a1 + 4) = v1; diff --git a/src/shared/ov/func_8012EF70.h b/src/shared/ov/func_8012EF70.h index a78cf441ee..1508a3bac2 100644 --- a/src/shared/ov/func_8012EF70.h +++ b/src/shared/ov/func_8012EF70.h @@ -7,12 +7,7 @@ void func_8012EF70(s32 a0, s32 a1) { func_8012EFB8(a0); { register s32 *p __asm__("$3") = &sp10; // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B headers1) - __asm__ __volatile__( - "mfc2 $12, $19\n" - "nop\n" - "sra $12, $12, 2\n" - "sw $12, 0(%0)\n" - : : "r"(p) : "memory", "$12"); + gte_stszotz(p); } v1 = sp10; *(s16 *)(a1 + 4) = v1; diff --git a/src/shared/ov/func_80133CD4__de6ea26c.h b/src/shared/ov/func_80133CD4__de6ea26c.h index 3c80b37ffb..d7f27eb031 100644 --- a/src/shared/ov/func_80133CD4__de6ea26c.h +++ b/src/shared/ov/func_80133CD4__de6ea26c.h @@ -79,14 +79,7 @@ s32 func_80133CD4(arg0, cmd, base, arr) } s1var = -ret; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(D_8017F81C) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(D_8017F81C); gte_stlvnl(D_8017F820); pc0 = D_8017F81C; diff --git a/src/shared/ov/func_8013D9B0__4b66f7ea.h b/src/shared/ov/func_8013D9B0__4b66f7ea.h index aa5d77528f..42f0fa505c 100644 --- a/src/shared/ov/func_8013D9B0__4b66f7ea.h +++ b/src/shared/ov/func_8013D9B0__4b66f7ea.h @@ -49,9 +49,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/shared/ov/func_8013E064.h b/src/shared/ov/func_8013E064.h index 0446774fca..607c9f9ec8 100644 --- a/src/shared/ov/func_8013E064.h +++ b/src/shared/ov/func_8013E064.h @@ -9,14 +9,7 @@ int func_8013E064(s16 *a0, s16 *a1) { d[2] = a0[5] - a1[5]; { s32 *pd = &d[0]; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 1\n" - : : "r"(pd) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_b502(pd); } { s32 *pq = &sq[0]; diff --git a/src/shared/ov/func_8013E0FC.h b/src/shared/ov/func_8013E0FC.h index 9dce7b0ee6..820a5159a7 100644 --- a/src/shared/ov/func_8013E0FC.h +++ b/src/shared/ov/func_8013E0FC.h @@ -9,14 +9,7 @@ int func_8013E0FC(s16 *a0, s16 *a1) { d[2] = a0[5] - a1[2]; { s32 *pd = &d[0]; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 1\n" - : : "r"(pd) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_b502(pd); } { s32 *pq = &sq[0]; diff --git a/src/shared/ov/func_8013E194.h b/src/shared/ov/func_8013E194.h index 0b99b204ed..07e27f8b0c 100644 --- a/src/shared/ov/func_8013E194.h +++ b/src/shared/ov/func_8013E194.h @@ -9,14 +9,7 @@ int func_8013E194(s16 *a0, s16 *a1) { d[2] = a0[2] - a1[2]; { s32 *pd = &d[0]; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 1\n" - : : "r"(pd) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_b502(pd); } { s32 *pq = &sq[0]; diff --git a/src/shared/ov/func_8013E2C4.h b/src/shared/ov/func_8013E2C4.h index b4bb791ed2..82f38b0c4f 100644 --- a/src/shared/ov/func_8013E2C4.h +++ b/src/shared/ov/func_8013E2C4.h @@ -9,14 +9,7 @@ int func_8013E2C4(short *a0) { in[0] = D_80126CAC - a0[0]; in[1] = D_80126CAE - a0[1]; in[2] = D_80126CB0 - a0[2]; - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(&in[0]) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(&in[0]); { int *pout = &out[0]; gte_stlvnl(pout);