diff --git a/config/overlays.mk b/config/overlays.mk index d11345f2a2..4b7a0f0699 100644 --- a/config/overlays.mk +++ b/config/overlays.mk @@ -55,12 +55,13 @@ ov_SC01_005_ELF := $(ov_SC01_005_OUT).elf ov_SC01_005_MAPFILE := $(ov_SC01_005_OUT).map ov_SC01_005_LD_SCRIPT := $(ov_SC01_005_OUT).ld ov_SC01_005_SPLAT_YAML := config/splat.ov_SC01_005.yaml -ov_SC01_005_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_005.o,ov_SC01_005_jr_8012ACE0.o,tail2.data.o,ov_SC01_005_jr_80135888.o,tail3.data.o,ov_SC01_005_jr_80135A4C.o,tail4.data.o,ov_SC01_005_jr_80135D20.o,tail5.data.o,ov_SC01_005_jr_801380E0.o,ov_SC01_005_o0c.o,tail6.data.o,ov_SC01_005_jr_8013F350.o,tail7.data.o,ov_SC01_005_jr_8013FFD8.o,tail8.data.o,ov_SC01_005_jr_80140608.o,tail9.data.o,ov_SC01_005_jr_8015444C.o,tail10.data.o,ov_SC01_005_jr_80154C24.o,ov_SC01_005_jr_801588CC.o,tail11.data.o,ov_SC01_005_jr_80159C84.o,tail12.data.o,ov_SC01_005_jr_8015A3C8.o,tail13.data.o,ov_SC01_005_jr_8015AE2C.o,tail14.data.o,ov_SC01_005_jr_8015C32C.o,tail15.data.o,ov_SC01_005_jr_8016AB6C.o,tail16.data.o,ov_SC01_005_jr_80171B4C.o,ov_SC01_005_jr_801734BC.o,tail17.data.o,ov_SC01_005_jr_801789AC.o,ov_SC01_005_jr_80178D40.o,tail18.data.o,ov_SC01_005_jr_8017A4AC.o,tail19.data.o,ov_SC01_005_jr_8017AE2C.o,ov_SC01_005_jr_8017C340.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC01_005_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_005.o,ov_SC01_005_jr_8012ACE0.o,tail2.data.o,ov_SC01_005_jr_80135888.o,tail3.data.o,ov_SC01_005_jr_80135A4C.o,tail4.data.o,ov_SC01_005_jr_80135D20.o,tail5.data.o,ov_SC01_005_jr_801380E0.o,ov_SC01_005_o0c.o,tail6.data.o,ov_SC01_005_jr_8013F350.o,tail7.data.o,ov_SC01_005_jr_8013FFD8.o,tail8.data.o,ov_SC01_005_jr_80140608.o,tail9.data.o,ov_SC01_005_jr_8015444C.o,ov_SC01_005_jr_80154C24.o,ov_SC01_005_jr_801588CC.o,tail10.data.o,ov_SC01_005_jr_80159C84.o,tail11.data.o,ov_SC01_005_jr_8015A3C8.o,tail12.data.o,ov_SC01_005_jr_8015AE2C.o,tail13.data.o,ov_SC01_005_jr_8015C32C.o,tail14.data.o,ov_SC01_005_jr_8016AB6C.o,tail15.data.o,ov_SC01_005_jr_80171B4C.o,ov_SC01_005_jr_801734BC.o,tail16.data.o,ov_SC01_005_jr_801789AC.o,ov_SC01_005_jr_80178D40.o,tail17.data.o,ov_SC01_005_jr_8017A4AC.o,tail18.data.o,ov_SC01_005_jr_8017AE2C.o,ov_SC01_005_jr_8017C340.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC01_005/ov_SC01_005.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC01_005/ov_SC01_005_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC01_005/ov_SC01_005_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC01_005/ov_SC01_005_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_005/ov_SC01_005_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC01_005/ov_SC01_005_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC01_005/ov_SC01_005_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC01_005/ov_SC01_005_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC01_005/ov_SC01_005_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -89,12 +90,13 @@ ov_SC01_006_ELF := $(ov_SC01_006_OUT).elf ov_SC01_006_MAPFILE := $(ov_SC01_006_OUT).map ov_SC01_006_LD_SCRIPT := $(ov_SC01_006_OUT).ld ov_SC01_006_SPLAT_YAML := config/splat.ov_SC01_006.yaml -ov_SC01_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_006.o,ov_SC01_006_jr_8012ACE0.o,tail2.data.o,ov_SC01_006_jr_80135888.o,tail3.data.o,ov_SC01_006_jr_80135A4C.o,tail4.data.o,ov_SC01_006_jr_80135D20.o,tail5.data.o,ov_SC01_006_jr_801380E0.o,ov_SC01_006_o0c.o,tail6.data.o,ov_SC01_006_jr_8013F350.o,tail7.data.o,ov_SC01_006_jr_8013FFD8.o,tail8.data.o,ov_SC01_006_jr_80140608.o,tail9.data.o,ov_SC01_006_jr_8015444C.o,tail10.data.o,ov_SC01_006_jr_80154C24.o,ov_SC01_006_jr_801588CC.o,tail11.data.o,ov_SC01_006_jr_80159C84.o,tail12.data.o,ov_SC01_006_jr_8015A3C8.o,tail13.data.o,ov_SC01_006_jr_8015AE2C.o,tail14.data.o,ov_SC01_006_jr_8015C32C.o,tail15.data.o,ov_SC01_006_jr_8016AB6C.o,tail16.data.o,ov_SC01_006_jr_80171B4C.o,ov_SC01_006_jr_801734BC.o,tail17.data.o,ov_SC01_006_jr_801789AC.o,ov_SC01_006_jr_80178D40.o,tail18.data.o,ov_SC01_006_jr_8017A4AC.o,tail19.data.o,ov_SC01_006_jr_8017AE2C.o,ov_SC01_006_jr_8017C340.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC01_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_006.o,ov_SC01_006_jr_8012ACE0.o,tail2.data.o,ov_SC01_006_jr_80135888.o,tail3.data.o,ov_SC01_006_jr_80135A4C.o,tail4.data.o,ov_SC01_006_jr_80135D20.o,tail5.data.o,ov_SC01_006_jr_801380E0.o,ov_SC01_006_o0c.o,tail6.data.o,ov_SC01_006_jr_8013F350.o,tail7.data.o,ov_SC01_006_jr_8013FFD8.o,tail8.data.o,ov_SC01_006_jr_80140608.o,tail9.data.o,ov_SC01_006_jr_8015444C.o,ov_SC01_006_jr_80154C24.o,ov_SC01_006_jr_801588CC.o,tail10.data.o,ov_SC01_006_jr_80159C84.o,tail11.data.o,ov_SC01_006_jr_8015A3C8.o,tail12.data.o,ov_SC01_006_jr_8015AE2C.o,tail13.data.o,ov_SC01_006_jr_8015C32C.o,tail14.data.o,ov_SC01_006_jr_8016AB6C.o,tail15.data.o,ov_SC01_006_jr_80171B4C.o,ov_SC01_006_jr_801734BC.o,tail16.data.o,ov_SC01_006_jr_801789AC.o,ov_SC01_006_jr_80178D40.o,tail17.data.o,ov_SC01_006_jr_8017A4AC.o,tail18.data.o,ov_SC01_006_jr_8017AE2C.o,ov_SC01_006_jr_8017C340.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC01_006/ov_SC01_006.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC01_006/ov_SC01_006_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC01_006/ov_SC01_006_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC01_006/ov_SC01_006_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_006/ov_SC01_006_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC01_006/ov_SC01_006_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC01_006/ov_SC01_006_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC01_006/ov_SC01_006_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC01_006/ov_SC01_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -123,12 +125,13 @@ ov_SC03_001_ELF := $(ov_SC03_001_OUT).elf ov_SC03_001_MAPFILE := $(ov_SC03_001_OUT).map ov_SC03_001_LD_SCRIPT := $(ov_SC03_001_OUT).ld ov_SC03_001_SPLAT_YAML := config/splat.ov_SC03_001.yaml -ov_SC03_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_001.o,ov_SC03_001_jr_8012ACE0.o,tail2.data.o,ov_SC03_001_jr_80135888.o,tail3.data.o,ov_SC03_001_jr_80135A4C.o,tail4.data.o,ov_SC03_001_jr_80135D20.o,tail5.data.o,ov_SC03_001_jr_801380E0.o,ov_SC03_001_o0c.o,tail6.data.o,ov_SC03_001_jr_8013F350.o,tail7.data.o,ov_SC03_001_jr_8013FFD8.o,tail8.data.o,ov_SC03_001_jr_80140608.o,tail9.data.o,ov_SC03_001_jr_8015444C.o,tail10.data.o,ov_SC03_001_jr_80154C24.o,ov_SC03_001_jr_801588CC.o,tail11.data.o,ov_SC03_001_jr_80159C84.o,tail12.data.o,ov_SC03_001_jr_8015A3C8.o,tail13.data.o,ov_SC03_001_jr_8015AE2C.o,tail14.data.o,ov_SC03_001_jr_8015C32C.o,tail15.data.o,ov_SC03_001_jr_8016AB6C.o,tail16.data.o,ov_SC03_001_jr_80171B4C.o,ov_SC03_001_jr_801734BC.o,tail17.data.o,ov_SC03_001_jr_801789AC.o,ov_SC03_001_jr_80178D40.o,tail18.data.o,ov_SC03_001_jr_8017A4AC.o,tail19.data.o,ov_SC03_001_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_001.o,ov_SC03_001_jr_8012ACE0.o,tail2.data.o,ov_SC03_001_jr_80135888.o,tail3.data.o,ov_SC03_001_jr_80135A4C.o,tail4.data.o,ov_SC03_001_jr_80135D20.o,tail5.data.o,ov_SC03_001_jr_801380E0.o,ov_SC03_001_o0c.o,tail6.data.o,ov_SC03_001_jr_8013F350.o,tail7.data.o,ov_SC03_001_jr_8013FFD8.o,tail8.data.o,ov_SC03_001_jr_80140608.o,tail9.data.o,ov_SC03_001_jr_8015444C.o,ov_SC03_001_jr_80154C24.o,ov_SC03_001_jr_801588CC.o,tail10.data.o,ov_SC03_001_jr_80159C84.o,tail11.data.o,ov_SC03_001_jr_8015A3C8.o,tail12.data.o,ov_SC03_001_jr_8015AE2C.o,tail13.data.o,ov_SC03_001_jr_8015C32C.o,tail14.data.o,ov_SC03_001_jr_8016AB6C.o,tail15.data.o,ov_SC03_001_jr_80171B4C.o,ov_SC03_001_jr_801734BC.o,tail16.data.o,ov_SC03_001_jr_801789AC.o,ov_SC03_001_jr_80178D40.o,tail17.data.o,ov_SC03_001_jr_8017A4AC.o,tail18.data.o,ov_SC03_001_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_001/ov_SC03_001.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_001/ov_SC03_001_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_001/ov_SC03_001_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_001/ov_SC03_001_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_001/ov_SC03_001_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_001/ov_SC03_001_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_001/ov_SC03_001_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_001/ov_SC03_001_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_001/ov_SC03_001_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -158,12 +161,13 @@ ov_SC01_000_ELF := $(ov_SC01_000_OUT).elf ov_SC01_000_MAPFILE := $(ov_SC01_000_OUT).map ov_SC01_000_LD_SCRIPT := $(ov_SC01_000_OUT).ld ov_SC01_000_SPLAT_YAML := config/splat.ov_SC01_000.yaml -ov_SC01_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_000.o,ov_SC01_000_jr_8012ACE0.o,tail2.data.o,ov_SC01_000_jr_80135888.o,tail3.data.o,ov_SC01_000_jr_80135A4C.o,tail4.data.o,ov_SC01_000_jr_80135D20.o,tail5.data.o,ov_SC01_000_jr_801380E0.o,ov_SC01_000_o0c.o,tail6.data.o,ov_SC01_000_jr_8013F350.o,tail7.data.o,ov_SC01_000_jr_8013FFD8.o,tail8.data.o,ov_SC01_000_jr_80140608.o,tail9.data.o,ov_SC01_000_jr_8015444C.o,tail10.data.o,ov_SC01_000_jr_80154C24.o,ov_SC01_000_jr_801588CC.o,tail11.data.o,ov_SC01_000_jr_80159C84.o,tail12.data.o,ov_SC01_000_jr_8015A3C8.o,tail13.data.o,ov_SC01_000_jr_8015AE2C.o,tail14.data.o,ov_SC01_000_jr_8015C32C.o,tail15.data.o,ov_SC01_000_jr_8016AB6C.o,tail16.data.o,ov_SC01_000_jr_80171B4C.o,ov_SC01_000_jr_801734BC.o,tail17.data.o,ov_SC01_000_jr_801789AC.o,ov_SC01_000_jr_80178D40.o,tail18.data.o,ov_SC01_000_jr_8017A4AC.o,tail19.data.o,ov_SC01_000_jr_8017AE2C.o,ov_SC01_000_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC01_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_000.o,ov_SC01_000_jr_8012ACE0.o,tail2.data.o,ov_SC01_000_jr_80135888.o,tail3.data.o,ov_SC01_000_jr_80135A4C.o,tail4.data.o,ov_SC01_000_jr_80135D20.o,tail5.data.o,ov_SC01_000_jr_801380E0.o,ov_SC01_000_o0c.o,tail6.data.o,ov_SC01_000_jr_8013F350.o,tail7.data.o,ov_SC01_000_jr_8013FFD8.o,tail8.data.o,ov_SC01_000_jr_80140608.o,tail9.data.o,ov_SC01_000_jr_8015444C.o,ov_SC01_000_jr_80154C24.o,ov_SC01_000_jr_801588CC.o,tail10.data.o,ov_SC01_000_jr_80159C84.o,tail11.data.o,ov_SC01_000_jr_8015A3C8.o,tail12.data.o,ov_SC01_000_jr_8015AE2C.o,tail13.data.o,ov_SC01_000_jr_8015C32C.o,tail14.data.o,ov_SC01_000_jr_8016AB6C.o,tail15.data.o,ov_SC01_000_jr_80171B4C.o,ov_SC01_000_jr_801734BC.o,tail16.data.o,ov_SC01_000_jr_801789AC.o,ov_SC01_000_jr_80178D40.o,tail17.data.o,ov_SC01_000_jr_8017A4AC.o,tail18.data.o,ov_SC01_000_jr_8017AE2C.o,ov_SC01_000_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC01_000/ov_SC01_000.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC01_000/ov_SC01_000_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC01_000/ov_SC01_000_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC01_000/ov_SC01_000_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_000/ov_SC01_000_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC01_000/ov_SC01_000_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC01_000/ov_SC01_000_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC01_000/ov_SC01_000_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC01_000/ov_SC01_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -192,12 +196,13 @@ ov_SC01_001_ELF := $(ov_SC01_001_OUT).elf ov_SC01_001_MAPFILE := $(ov_SC01_001_OUT).map ov_SC01_001_LD_SCRIPT := $(ov_SC01_001_OUT).ld ov_SC01_001_SPLAT_YAML := config/splat.ov_SC01_001.yaml -ov_SC01_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_001.o,ov_SC01_001_jr_8012ACE0.o,tail2.data.o,ov_SC01_001_jr_80135888.o,tail3.data.o,ov_SC01_001_jr_80135A4C.o,tail4.data.o,ov_SC01_001_jr_80135D20.o,tail5.data.o,ov_SC01_001_jr_801380E0.o,ov_SC01_001_o0c.o,tail6.data.o,ov_SC01_001_jr_8013F350.o,tail7.data.o,ov_SC01_001_jr_8013FFD8.o,tail8.data.o,ov_SC01_001_jr_80140608.o,tail9.data.o,ov_SC01_001_jr_8015444C.o,tail10.data.o,ov_SC01_001_jr_80154C24.o,ov_SC01_001_jr_801588CC.o,tail11.data.o,ov_SC01_001_jr_80159C84.o,tail12.data.o,ov_SC01_001_jr_8015A3C8.o,tail13.data.o,ov_SC01_001_jr_8015AE2C.o,tail14.data.o,ov_SC01_001_jr_8015C32C.o,tail15.data.o,ov_SC01_001_jr_8016AB6C.o,tail16.data.o,ov_SC01_001_jr_80171B4C.o,ov_SC01_001_jr_801734BC.o,tail17.data.o,ov_SC01_001_jr_801789AC.o,ov_SC01_001_jr_80178D40.o,tail18.data.o,ov_SC01_001_jr_8017A4AC.o,tail19.data.o,ov_SC01_001_jr_8017AE2C.o,ov_SC01_001_jr_8017BEBC.o,ov_SC01_001_jr_8017D2DC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC01_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_001.o,ov_SC01_001_jr_8012ACE0.o,tail2.data.o,ov_SC01_001_jr_80135888.o,tail3.data.o,ov_SC01_001_jr_80135A4C.o,tail4.data.o,ov_SC01_001_jr_80135D20.o,tail5.data.o,ov_SC01_001_jr_801380E0.o,ov_SC01_001_o0c.o,tail6.data.o,ov_SC01_001_jr_8013F350.o,tail7.data.o,ov_SC01_001_jr_8013FFD8.o,tail8.data.o,ov_SC01_001_jr_80140608.o,tail9.data.o,ov_SC01_001_jr_8015444C.o,ov_SC01_001_jr_80154C24.o,ov_SC01_001_jr_801588CC.o,tail10.data.o,ov_SC01_001_jr_80159C84.o,tail11.data.o,ov_SC01_001_jr_8015A3C8.o,tail12.data.o,ov_SC01_001_jr_8015AE2C.o,tail13.data.o,ov_SC01_001_jr_8015C32C.o,tail14.data.o,ov_SC01_001_jr_8016AB6C.o,tail15.data.o,ov_SC01_001_jr_80171B4C.o,ov_SC01_001_jr_801734BC.o,tail16.data.o,ov_SC01_001_jr_801789AC.o,ov_SC01_001_jr_80178D40.o,tail17.data.o,ov_SC01_001_jr_8017A4AC.o,tail18.data.o,ov_SC01_001_jr_8017AE2C.o,ov_SC01_001_jr_8017BEBC.o,ov_SC01_001_jr_8017D2DC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC01_001/ov_SC01_001.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC01_001/ov_SC01_001_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC01_001/ov_SC01_001_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC01_001/ov_SC01_001_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_001/ov_SC01_001_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC01_001/ov_SC01_001_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC01_001/ov_SC01_001_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC01_001/ov_SC01_001_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC01_001/ov_SC01_001_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -226,12 +231,13 @@ ov_SC02_000_ELF := $(ov_SC02_000_OUT).elf ov_SC02_000_MAPFILE := $(ov_SC02_000_OUT).map ov_SC02_000_LD_SCRIPT := $(ov_SC02_000_OUT).ld ov_SC02_000_SPLAT_YAML := config/splat.ov_SC02_000.yaml -ov_SC02_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_000.o,ov_SC02_000_jr_8012ACE0.o,tail2.data.o,ov_SC02_000_jr_80135888.o,tail3.data.o,ov_SC02_000_jr_80135A4C.o,tail4.data.o,ov_SC02_000_jr_80135D20.o,tail5.data.o,ov_SC02_000_jr_801380E0.o,ov_SC02_000_o0c.o,tail6.data.o,ov_SC02_000_jr_8013F350.o,tail7.data.o,ov_SC02_000_jr_8013FFD8.o,tail8.data.o,ov_SC02_000_jr_80140608.o,tail9.data.o,ov_SC02_000_jr_8015444C.o,tail10.data.o,ov_SC02_000_jr_80154C24.o,ov_SC02_000_jr_801588CC.o,tail11.data.o,ov_SC02_000_jr_80159C84.o,tail12.data.o,ov_SC02_000_jr_8015A3C8.o,tail13.data.o,ov_SC02_000_jr_8015AE2C.o,tail14.data.o,ov_SC02_000_jr_8015C32C.o,tail15.data.o,ov_SC02_000_jr_8016AB6C.o,tail16.data.o,ov_SC02_000_jr_80171B4C.o,ov_SC02_000_jr_801734BC.o,tail17.data.o,ov_SC02_000_jr_801789AC.o,ov_SC02_000_jr_80178D40.o,tail18.data.o,ov_SC02_000_jr_8017A4AC.o,tail19.data.o,ov_SC02_000_jr_8017AE2C.o,tail20.data.o,ov_SC02_000_jr_8017FCB0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_000.o,ov_SC02_000_jr_8012ACE0.o,tail2.data.o,ov_SC02_000_jr_80135888.o,tail3.data.o,ov_SC02_000_jr_80135A4C.o,tail4.data.o,ov_SC02_000_jr_80135D20.o,tail5.data.o,ov_SC02_000_jr_801380E0.o,ov_SC02_000_o0c.o,tail6.data.o,ov_SC02_000_jr_8013F350.o,tail7.data.o,ov_SC02_000_jr_8013FFD8.o,tail8.data.o,ov_SC02_000_jr_80140608.o,tail9.data.o,ov_SC02_000_jr_8015444C.o,ov_SC02_000_jr_80154C24.o,ov_SC02_000_jr_801588CC.o,tail10.data.o,ov_SC02_000_jr_80159C84.o,tail11.data.o,ov_SC02_000_jr_8015A3C8.o,tail12.data.o,ov_SC02_000_jr_8015AE2C.o,tail13.data.o,ov_SC02_000_jr_8015C32C.o,tail14.data.o,ov_SC02_000_jr_8016AB6C.o,tail15.data.o,ov_SC02_000_jr_80171B4C.o,ov_SC02_000_jr_801734BC.o,tail16.data.o,ov_SC02_000_jr_801789AC.o,ov_SC02_000_jr_80178D40.o,tail17.data.o,ov_SC02_000_jr_8017A4AC.o,tail18.data.o,ov_SC02_000_jr_8017AE2C.o,tail19.data.o,ov_SC02_000_jr_8017FCB0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_000/ov_SC02_000.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_000/ov_SC02_000_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_000/ov_SC02_000_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_000/ov_SC02_000_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_000/ov_SC02_000_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_000/ov_SC02_000_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_000/ov_SC02_000_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_000/ov_SC02_000_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_000/ov_SC02_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -260,12 +266,13 @@ ov_SC02_003_ELF := $(ov_SC02_003_OUT).elf ov_SC02_003_MAPFILE := $(ov_SC02_003_OUT).map ov_SC02_003_LD_SCRIPT := $(ov_SC02_003_OUT).ld ov_SC02_003_SPLAT_YAML := config/splat.ov_SC02_003.yaml -ov_SC02_003_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_003.o,ov_SC02_003_jr_8012ACE0.o,tail2.data.o,ov_SC02_003_jr_80135888.o,tail3.data.o,ov_SC02_003_jr_80135A4C.o,tail4.data.o,ov_SC02_003_jr_80135D20.o,tail5.data.o,ov_SC02_003_jr_801380E0.o,ov_SC02_003_o0c.o,tail6.data.o,ov_SC02_003_jr_8013F350.o,tail7.data.o,ov_SC02_003_jr_8013FFD8.o,tail8.data.o,ov_SC02_003_jr_80140608.o,tail9.data.o,ov_SC02_003_jr_8015444C.o,tail10.data.o,ov_SC02_003_jr_80154C24.o,ov_SC02_003_jr_801588CC.o,tail11.data.o,ov_SC02_003_jr_80159C84.o,tail12.data.o,ov_SC02_003_jr_8015A3C8.o,tail13.data.o,ov_SC02_003_jr_8015AE2C.o,tail14.data.o,ov_SC02_003_jr_8015C32C.o,tail15.data.o,ov_SC02_003_jr_8016AB6C.o,tail16.data.o,ov_SC02_003_jr_80171B4C.o,ov_SC02_003_jr_801734BC.o,tail17.data.o,ov_SC02_003_jr_801789AC.o,ov_SC02_003_jr_80178D40.o,tail18.data.o,ov_SC02_003_jr_8017A4AC.o,tail19.data.o,ov_SC02_003_jr_8017AE2C.o,tail20.data.o,ov_SC02_003_jr_8017FCB0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_003_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_003.o,ov_SC02_003_jr_8012ACE0.o,tail2.data.o,ov_SC02_003_jr_80135888.o,tail3.data.o,ov_SC02_003_jr_80135A4C.o,tail4.data.o,ov_SC02_003_jr_80135D20.o,tail5.data.o,ov_SC02_003_jr_801380E0.o,ov_SC02_003_o0c.o,tail6.data.o,ov_SC02_003_jr_8013F350.o,tail7.data.o,ov_SC02_003_jr_8013FFD8.o,tail8.data.o,ov_SC02_003_jr_80140608.o,tail9.data.o,ov_SC02_003_jr_8015444C.o,ov_SC02_003_jr_80154C24.o,ov_SC02_003_jr_801588CC.o,tail10.data.o,ov_SC02_003_jr_80159C84.o,tail11.data.o,ov_SC02_003_jr_8015A3C8.o,tail12.data.o,ov_SC02_003_jr_8015AE2C.o,tail13.data.o,ov_SC02_003_jr_8015C32C.o,tail14.data.o,ov_SC02_003_jr_8016AB6C.o,tail15.data.o,ov_SC02_003_jr_80171B4C.o,ov_SC02_003_jr_801734BC.o,tail16.data.o,ov_SC02_003_jr_801789AC.o,ov_SC02_003_jr_80178D40.o,tail17.data.o,ov_SC02_003_jr_8017A4AC.o,tail18.data.o,ov_SC02_003_jr_8017AE2C.o,tail19.data.o,ov_SC02_003_jr_8017FCB0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_003/ov_SC02_003.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_003/ov_SC02_003_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_003/ov_SC02_003_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_003/ov_SC02_003_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_003/ov_SC02_003_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_003/ov_SC02_003_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_003/ov_SC02_003_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_003/ov_SC02_003_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_003/ov_SC02_003_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -294,12 +301,13 @@ ov_SC03_002_ELF := $(ov_SC03_002_OUT).elf ov_SC03_002_MAPFILE := $(ov_SC03_002_OUT).map ov_SC03_002_LD_SCRIPT := $(ov_SC03_002_OUT).ld ov_SC03_002_SPLAT_YAML := config/splat.ov_SC03_002.yaml -ov_SC03_002_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_002.o,ov_SC03_002_jr_8012ACE0.o,tail2.data.o,ov_SC03_002_jr_80135888.o,tail3.data.o,ov_SC03_002_jr_80135A4C.o,tail4.data.o,ov_SC03_002_jr_80135D20.o,tail5.data.o,ov_SC03_002_jr_801380E0.o,ov_SC03_002_o0c.o,tail6.data.o,ov_SC03_002_jr_8013F350.o,tail7.data.o,ov_SC03_002_jr_8013FFD8.o,tail8.data.o,ov_SC03_002_jr_80140608.o,tail9.data.o,ov_SC03_002_jr_8015444C.o,tail10.data.o,ov_SC03_002_jr_80154C24.o,ov_SC03_002_jr_801588CC.o,tail11.data.o,ov_SC03_002_jr_80159C84.o,tail12.data.o,ov_SC03_002_jr_8015A3C8.o,tail13.data.o,ov_SC03_002_jr_8015AE2C.o,tail14.data.o,ov_SC03_002_jr_8015C32C.o,tail15.data.o,ov_SC03_002_jr_8016AB6C.o,tail16.data.o,ov_SC03_002_jr_80171B4C.o,ov_SC03_002_jr_801734BC.o,tail17.data.o,ov_SC03_002_jr_801789AC.o,ov_SC03_002_jr_80178D40.o,tail18.data.o,ov_SC03_002_jr_8017A4AC.o,tail19.data.o,ov_SC03_002_jr_8017AE2C.o,ov_SC03_002_jr_8017D604.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_002_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_002.o,ov_SC03_002_jr_8012ACE0.o,tail2.data.o,ov_SC03_002_jr_80135888.o,tail3.data.o,ov_SC03_002_jr_80135A4C.o,tail4.data.o,ov_SC03_002_jr_80135D20.o,tail5.data.o,ov_SC03_002_jr_801380E0.o,ov_SC03_002_o0c.o,tail6.data.o,ov_SC03_002_jr_8013F350.o,tail7.data.o,ov_SC03_002_jr_8013FFD8.o,tail8.data.o,ov_SC03_002_jr_80140608.o,tail9.data.o,ov_SC03_002_jr_8015444C.o,ov_SC03_002_jr_80154C24.o,ov_SC03_002_jr_801588CC.o,tail10.data.o,ov_SC03_002_jr_80159C84.o,tail11.data.o,ov_SC03_002_jr_8015A3C8.o,tail12.data.o,ov_SC03_002_jr_8015AE2C.o,tail13.data.o,ov_SC03_002_jr_8015C32C.o,tail14.data.o,ov_SC03_002_jr_8016AB6C.o,tail15.data.o,ov_SC03_002_jr_80171B4C.o,ov_SC03_002_jr_801734BC.o,tail16.data.o,ov_SC03_002_jr_801789AC.o,ov_SC03_002_jr_80178D40.o,tail17.data.o,ov_SC03_002_jr_8017A4AC.o,tail18.data.o,ov_SC03_002_jr_8017AE2C.o,ov_SC03_002_jr_8017D604.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_002/ov_SC03_002.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_002/ov_SC03_002_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_002/ov_SC03_002_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_002/ov_SC03_002_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_002/ov_SC03_002_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_002/ov_SC03_002_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_002/ov_SC03_002_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_002/ov_SC03_002_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_002/ov_SC03_002_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -328,12 +336,13 @@ ov_SC03_006_ELF := $(ov_SC03_006_OUT).elf ov_SC03_006_MAPFILE := $(ov_SC03_006_OUT).map ov_SC03_006_LD_SCRIPT := $(ov_SC03_006_OUT).ld ov_SC03_006_SPLAT_YAML := config/splat.ov_SC03_006.yaml -ov_SC03_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_006.o,ov_SC03_006_jr_8012ACE0.o,tail2.data.o,ov_SC03_006_jr_80135888.o,tail3.data.o,ov_SC03_006_jr_80135A4C.o,tail4.data.o,ov_SC03_006_jr_80135D20.o,tail5.data.o,ov_SC03_006_jr_801380E0.o,ov_SC03_006_o0c.o,tail6.data.o,ov_SC03_006_jr_8013F350.o,tail7.data.o,ov_SC03_006_jr_8013FFD8.o,tail8.data.o,ov_SC03_006_jr_80140608.o,tail9.data.o,ov_SC03_006_jr_8015444C.o,tail10.data.o,ov_SC03_006_jr_80154C24.o,ov_SC03_006_jr_801588CC.o,tail11.data.o,ov_SC03_006_jr_80159C84.o,tail12.data.o,ov_SC03_006_jr_8015A3C8.o,tail13.data.o,ov_SC03_006_jr_8015AE2C.o,tail14.data.o,ov_SC03_006_jr_8015C32C.o,tail15.data.o,ov_SC03_006_jr_8016AB6C.o,tail16.data.o,ov_SC03_006_jr_80171B4C.o,ov_SC03_006_jr_801734BC.o,tail17.data.o,ov_SC03_006_jr_801789AC.o,ov_SC03_006_jr_80178D40.o,tail18.data.o,ov_SC03_006_jr_8017A4AC.o,tail19.data.o,ov_SC03_006_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_006.o,ov_SC03_006_jr_8012ACE0.o,tail2.data.o,ov_SC03_006_jr_80135888.o,tail3.data.o,ov_SC03_006_jr_80135A4C.o,tail4.data.o,ov_SC03_006_jr_80135D20.o,tail5.data.o,ov_SC03_006_jr_801380E0.o,ov_SC03_006_o0c.o,tail6.data.o,ov_SC03_006_jr_8013F350.o,tail7.data.o,ov_SC03_006_jr_8013FFD8.o,tail8.data.o,ov_SC03_006_jr_80140608.o,tail9.data.o,ov_SC03_006_jr_8015444C.o,ov_SC03_006_jr_80154C24.o,ov_SC03_006_jr_801588CC.o,tail10.data.o,ov_SC03_006_jr_80159C84.o,tail11.data.o,ov_SC03_006_jr_8015A3C8.o,tail12.data.o,ov_SC03_006_jr_8015AE2C.o,tail13.data.o,ov_SC03_006_jr_8015C32C.o,tail14.data.o,ov_SC03_006_jr_8016AB6C.o,tail15.data.o,ov_SC03_006_jr_80171B4C.o,ov_SC03_006_jr_801734BC.o,tail16.data.o,ov_SC03_006_jr_801789AC.o,ov_SC03_006_jr_80178D40.o,tail17.data.o,ov_SC03_006_jr_8017A4AC.o,tail18.data.o,ov_SC03_006_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_006/ov_SC03_006.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_006/ov_SC03_006_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_006/ov_SC03_006_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_006/ov_SC03_006_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_006/ov_SC03_006_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_006/ov_SC03_006_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_006/ov_SC03_006_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_006/ov_SC03_006_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_006/ov_SC03_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -362,12 +371,13 @@ ov_SC04_000_ELF := $(ov_SC04_000_OUT).elf ov_SC04_000_MAPFILE := $(ov_SC04_000_OUT).map ov_SC04_000_LD_SCRIPT := $(ov_SC04_000_OUT).ld ov_SC04_000_SPLAT_YAML := config/splat.ov_SC04_000.yaml -ov_SC04_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_000.o,ov_SC04_000_jr_8012ACE0.o,tail2.data.o,ov_SC04_000_jr_80135888.o,tail3.data.o,ov_SC04_000_jr_80135A4C.o,tail4.data.o,ov_SC04_000_jr_80135D20.o,tail5.data.o,ov_SC04_000_jr_801380E0.o,ov_SC04_000_o0c.o,tail6.data.o,ov_SC04_000_jr_8013F350.o,tail7.data.o,ov_SC04_000_jr_8013FFD8.o,tail8.data.o,ov_SC04_000_jr_80140608.o,tail9.data.o,ov_SC04_000_jr_8015444C.o,tail10.data.o,ov_SC04_000_jr_80154C24.o,ov_SC04_000_jr_801588CC.o,tail11.data.o,ov_SC04_000_jr_80159C84.o,tail12.data.o,ov_SC04_000_jr_8015A3C8.o,tail13.data.o,ov_SC04_000_jr_8015AE2C.o,tail14.data.o,ov_SC04_000_jr_8015C32C.o,tail15.data.o,ov_SC04_000_jr_8016AB6C.o,tail16.data.o,ov_SC04_000_jr_80171B4C.o,ov_SC04_000_jr_801734BC.o,tail17.data.o,ov_SC04_000_jr_801789AC.o,ov_SC04_000_jr_80178D40.o,tail18.data.o,ov_SC04_000_jr_8017A4AC.o,tail19.data.o,ov_SC04_000_jr_8017AE2C.o,ov_SC04_000_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_000.o,ov_SC04_000_jr_8012ACE0.o,tail2.data.o,ov_SC04_000_jr_80135888.o,tail3.data.o,ov_SC04_000_jr_80135A4C.o,tail4.data.o,ov_SC04_000_jr_80135D20.o,tail5.data.o,ov_SC04_000_jr_801380E0.o,ov_SC04_000_o0c.o,tail6.data.o,ov_SC04_000_jr_8013F350.o,tail7.data.o,ov_SC04_000_jr_8013FFD8.o,tail8.data.o,ov_SC04_000_jr_80140608.o,tail9.data.o,ov_SC04_000_jr_8015444C.o,ov_SC04_000_jr_80154C24.o,ov_SC04_000_jr_801588CC.o,tail10.data.o,ov_SC04_000_jr_80159C84.o,tail11.data.o,ov_SC04_000_jr_8015A3C8.o,tail12.data.o,ov_SC04_000_jr_8015AE2C.o,tail13.data.o,ov_SC04_000_jr_8015C32C.o,tail14.data.o,ov_SC04_000_jr_8016AB6C.o,tail15.data.o,ov_SC04_000_jr_80171B4C.o,ov_SC04_000_jr_801734BC.o,tail16.data.o,ov_SC04_000_jr_801789AC.o,ov_SC04_000_jr_80178D40.o,tail17.data.o,ov_SC04_000_jr_8017A4AC.o,tail18.data.o,ov_SC04_000_jr_8017AE2C.o,ov_SC04_000_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_000/ov_SC04_000.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_000/ov_SC04_000_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_000/ov_SC04_000_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_000/ov_SC04_000_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_000/ov_SC04_000_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_000/ov_SC04_000_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_000/ov_SC04_000_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_000/ov_SC04_000_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_000/ov_SC04_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -396,12 +406,13 @@ ov_SC04_018_ELF := $(ov_SC04_018_OUT).elf ov_SC04_018_MAPFILE := $(ov_SC04_018_OUT).map ov_SC04_018_LD_SCRIPT := $(ov_SC04_018_OUT).ld ov_SC04_018_SPLAT_YAML := config/splat.ov_SC04_018.yaml -ov_SC04_018_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_018.o,ov_SC04_018_jr_8012ACE0.o,tail2.data.o,ov_SC04_018_jr_80135888.o,tail3.data.o,ov_SC04_018_jr_80135A4C.o,tail4.data.o,ov_SC04_018_jr_80135D20.o,tail5.data.o,ov_SC04_018_jr_801380E0.o,ov_SC04_018_o0c.o,tail6.data.o,ov_SC04_018_jr_8013F350.o,tail7.data.o,ov_SC04_018_jr_8013FFD8.o,tail8.data.o,ov_SC04_018_jr_80140608.o,tail9.data.o,ov_SC04_018_jr_8015444C.o,tail10.data.o,ov_SC04_018_jr_80154C24.o,ov_SC04_018_jr_801588CC.o,tail11.data.o,ov_SC04_018_jr_80159C84.o,tail12.data.o,ov_SC04_018_jr_8015A3C8.o,tail13.data.o,ov_SC04_018_jr_8015AE2C.o,tail14.data.o,ov_SC04_018_jr_8015C32C.o,tail15.data.o,ov_SC04_018_jr_8016AB6C.o,tail16.data.o,ov_SC04_018_jr_80171B4C.o,ov_SC04_018_jr_801734BC.o,tail17.data.o,ov_SC04_018_jr_801789AC.o,ov_SC04_018_jr_80178D40.o,tail18.data.o,ov_SC04_018_jr_8017A4AC.o,tail19.data.o,ov_SC04_018_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_018_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_018.o,ov_SC04_018_jr_8012ACE0.o,tail2.data.o,ov_SC04_018_jr_80135888.o,tail3.data.o,ov_SC04_018_jr_80135A4C.o,tail4.data.o,ov_SC04_018_jr_80135D20.o,tail5.data.o,ov_SC04_018_jr_801380E0.o,ov_SC04_018_o0c.o,tail6.data.o,ov_SC04_018_jr_8013F350.o,tail7.data.o,ov_SC04_018_jr_8013FFD8.o,tail8.data.o,ov_SC04_018_jr_80140608.o,tail9.data.o,ov_SC04_018_jr_8015444C.o,ov_SC04_018_jr_80154C24.o,ov_SC04_018_jr_801588CC.o,tail10.data.o,ov_SC04_018_jr_80159C84.o,tail11.data.o,ov_SC04_018_jr_8015A3C8.o,tail12.data.o,ov_SC04_018_jr_8015AE2C.o,tail13.data.o,ov_SC04_018_jr_8015C32C.o,tail14.data.o,ov_SC04_018_jr_8016AB6C.o,tail15.data.o,ov_SC04_018_jr_80171B4C.o,ov_SC04_018_jr_801734BC.o,tail16.data.o,ov_SC04_018_jr_801789AC.o,ov_SC04_018_jr_80178D40.o,tail17.data.o,ov_SC04_018_jr_8017A4AC.o,tail18.data.o,ov_SC04_018_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_018/ov_SC04_018.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_018/ov_SC04_018_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_018/ov_SC04_018_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_018/ov_SC04_018_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_018/ov_SC04_018_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_018/ov_SC04_018_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_018/ov_SC04_018_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_018/ov_SC04_018_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_018/ov_SC04_018_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -431,12 +442,13 @@ ov_SC04_019_ELF := $(ov_SC04_019_OUT).elf ov_SC04_019_MAPFILE := $(ov_SC04_019_OUT).map ov_SC04_019_LD_SCRIPT := $(ov_SC04_019_OUT).ld ov_SC04_019_SPLAT_YAML := config/splat.ov_SC04_019.yaml -ov_SC04_019_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_019.o,ov_SC04_019_jr_8012ACE0.o,tail2.data.o,ov_SC04_019_jr_80135888.o,tail3.data.o,ov_SC04_019_jr_80135A4C.o,tail4.data.o,ov_SC04_019_jr_80135D20.o,tail5.data.o,ov_SC04_019_jr_801380E0.o,ov_SC04_019_o0c.o,tail6.data.o,ov_SC04_019_jr_8013F350.o,tail7.data.o,ov_SC04_019_jr_8013FFD8.o,tail8.data.o,ov_SC04_019_jr_80140608.o,tail9.data.o,ov_SC04_019_jr_8015444C.o,tail10.data.o,ov_SC04_019_jr_80154C24.o,ov_SC04_019_jr_801588CC.o,tail11.data.o,ov_SC04_019_jr_80159C84.o,tail12.data.o,ov_SC04_019_jr_8015A3C8.o,tail13.data.o,ov_SC04_019_jr_8015AE2C.o,tail14.data.o,ov_SC04_019_jr_8015C32C.o,tail15.data.o,ov_SC04_019_jr_8016AB6C.o,tail16.data.o,ov_SC04_019_jr_80171B4C.o,ov_SC04_019_jr_801734BC.o,tail17.data.o,ov_SC04_019_jr_801789AC.o,ov_SC04_019_jr_80178D40.o,tail18.data.o,ov_SC04_019_jr_8017A4AC.o,tail19.data.o,ov_SC04_019_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_019_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_019.o,ov_SC04_019_jr_8012ACE0.o,tail2.data.o,ov_SC04_019_jr_80135888.o,tail3.data.o,ov_SC04_019_jr_80135A4C.o,tail4.data.o,ov_SC04_019_jr_80135D20.o,tail5.data.o,ov_SC04_019_jr_801380E0.o,ov_SC04_019_o0c.o,tail6.data.o,ov_SC04_019_jr_8013F350.o,tail7.data.o,ov_SC04_019_jr_8013FFD8.o,tail8.data.o,ov_SC04_019_jr_80140608.o,tail9.data.o,ov_SC04_019_jr_8015444C.o,ov_SC04_019_jr_80154C24.o,ov_SC04_019_jr_801588CC.o,tail10.data.o,ov_SC04_019_jr_80159C84.o,tail11.data.o,ov_SC04_019_jr_8015A3C8.o,tail12.data.o,ov_SC04_019_jr_8015AE2C.o,tail13.data.o,ov_SC04_019_jr_8015C32C.o,tail14.data.o,ov_SC04_019_jr_8016AB6C.o,tail15.data.o,ov_SC04_019_jr_80171B4C.o,ov_SC04_019_jr_801734BC.o,tail16.data.o,ov_SC04_019_jr_801789AC.o,ov_SC04_019_jr_80178D40.o,tail17.data.o,ov_SC04_019_jr_8017A4AC.o,tail18.data.o,ov_SC04_019_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_019/ov_SC04_019.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_019/ov_SC04_019_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_019/ov_SC04_019_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_019/ov_SC04_019_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_019/ov_SC04_019_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_019/ov_SC04_019_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_019/ov_SC04_019_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_019/ov_SC04_019_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_019/ov_SC04_019_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -466,12 +478,13 @@ ov_SC05_000_ELF := $(ov_SC05_000_OUT).elf ov_SC05_000_MAPFILE := $(ov_SC05_000_OUT).map ov_SC05_000_LD_SCRIPT := $(ov_SC05_000_OUT).ld ov_SC05_000_SPLAT_YAML := config/splat.ov_SC05_000.yaml -ov_SC05_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_000.o,ov_SC05_000_jr_8012ACE0.o,tail2.data.o,ov_SC05_000_jr_80135888.o,tail3.data.o,ov_SC05_000_jr_80135A4C.o,tail4.data.o,ov_SC05_000_jr_80135D20.o,tail5.data.o,ov_SC05_000_jr_801380E0.o,ov_SC05_000_o0c.o,tail6.data.o,ov_SC05_000_jr_8013F350.o,tail7.data.o,ov_SC05_000_jr_8013FFD8.o,tail8.data.o,ov_SC05_000_jr_80140608.o,tail9.data.o,ov_SC05_000_jr_8015444C.o,tail10.data.o,ov_SC05_000_jr_80154C24.o,ov_SC05_000_jr_801588CC.o,tail11.data.o,ov_SC05_000_jr_80159C84.o,tail12.data.o,ov_SC05_000_jr_8015A3C8.o,tail13.data.o,ov_SC05_000_jr_8015AE2C.o,tail14.data.o,ov_SC05_000_jr_8015C32C.o,tail15.data.o,ov_SC05_000_jr_8016AB6C.o,tail16.data.o,ov_SC05_000_jr_80171B4C.o,ov_SC05_000_jr_801734BC.o,tail17.data.o,ov_SC05_000_jr_801789AC.o,ov_SC05_000_jr_80178D40.o,tail18.data.o,ov_SC05_000_jr_8017A4AC.o,tail19.data.o,ov_SC05_000_jr_8017AE2C.o,ov_SC05_000_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_000.o,ov_SC05_000_jr_8012ACE0.o,tail2.data.o,ov_SC05_000_jr_80135888.o,tail3.data.o,ov_SC05_000_jr_80135A4C.o,tail4.data.o,ov_SC05_000_jr_80135D20.o,tail5.data.o,ov_SC05_000_jr_801380E0.o,ov_SC05_000_o0c.o,tail6.data.o,ov_SC05_000_jr_8013F350.o,tail7.data.o,ov_SC05_000_jr_8013FFD8.o,tail8.data.o,ov_SC05_000_jr_80140608.o,tail9.data.o,ov_SC05_000_jr_8015444C.o,ov_SC05_000_jr_80154C24.o,ov_SC05_000_jr_801588CC.o,tail10.data.o,ov_SC05_000_jr_80159C84.o,tail11.data.o,ov_SC05_000_jr_8015A3C8.o,tail12.data.o,ov_SC05_000_jr_8015AE2C.o,tail13.data.o,ov_SC05_000_jr_8015C32C.o,tail14.data.o,ov_SC05_000_jr_8016AB6C.o,tail15.data.o,ov_SC05_000_jr_80171B4C.o,ov_SC05_000_jr_801734BC.o,tail16.data.o,ov_SC05_000_jr_801789AC.o,ov_SC05_000_jr_80178D40.o,tail17.data.o,ov_SC05_000_jr_8017A4AC.o,tail18.data.o,ov_SC05_000_jr_8017AE2C.o,ov_SC05_000_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_000/ov_SC05_000.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_000/ov_SC05_000_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_000/ov_SC05_000_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_000/ov_SC05_000_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_000/ov_SC05_000_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_000/ov_SC05_000_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_000/ov_SC05_000_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_000/ov_SC05_000_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_000/ov_SC05_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -500,12 +513,13 @@ ov_SC06_000_ELF := $(ov_SC06_000_OUT).elf ov_SC06_000_MAPFILE := $(ov_SC06_000_OUT).map ov_SC06_000_LD_SCRIPT := $(ov_SC06_000_OUT).ld ov_SC06_000_SPLAT_YAML := config/splat.ov_SC06_000.yaml -ov_SC06_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_000.o,ov_SC06_000_jr_8012ACE0.o,tail2.data.o,ov_SC06_000_jr_80135888.o,tail3.data.o,ov_SC06_000_jr_80135A4C.o,tail4.data.o,ov_SC06_000_jr_80135D20.o,tail5.data.o,ov_SC06_000_jr_801380E0.o,ov_SC06_000_o0c.o,tail6.data.o,ov_SC06_000_jr_8013F350.o,tail7.data.o,ov_SC06_000_jr_8014032C.o,tail8.data.o,ov_SC06_000_jr_80140608.o,tail9.data.o,ov_SC06_000_jr_8015444C.o,tail10.data.o,ov_SC06_000_jr_80154C24.o,ov_SC06_000_jr_801588CC.o,tail11.data.o,ov_SC06_000_jr_80159C84.o,tail12.data.o,ov_SC06_000_jr_8015A3C8.o,tail13.data.o,ov_SC06_000_jr_8015AE2C.o,tail14.data.o,ov_SC06_000_jr_8015C32C.o,tail15.data.o,ov_SC06_000_jr_8016AB6C.o,tail16.data.o,ov_SC06_000_jr_80171B4C.o,ov_SC06_000_jr_801734BC.o,tail17.data.o,ov_SC06_000_jr_801789AC.o,ov_SC06_000_jr_80178D40.o,tail18.data.o,ov_SC06_000_jr_8017A4AC.o,tail19.data.o,ov_SC06_000_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_000.o,ov_SC06_000_jr_8012ACE0.o,tail2.data.o,ov_SC06_000_jr_80135888.o,tail3.data.o,ov_SC06_000_jr_80135A4C.o,tail4.data.o,ov_SC06_000_jr_80135D20.o,tail5.data.o,ov_SC06_000_jr_801380E0.o,ov_SC06_000_o0c.o,tail6.data.o,ov_SC06_000_jr_8013F350.o,tail7.data.o,ov_SC06_000_jr_8014032C.o,tail8.data.o,ov_SC06_000_jr_80140608.o,tail9.data.o,ov_SC06_000_jr_8015444C.o,ov_SC06_000_jr_80154C24.o,ov_SC06_000_jr_801588CC.o,tail10.data.o,ov_SC06_000_jr_80159C84.o,tail11.data.o,ov_SC06_000_jr_8015A3C8.o,tail12.data.o,ov_SC06_000_jr_8015AE2C.o,tail13.data.o,ov_SC06_000_jr_8015C32C.o,tail14.data.o,ov_SC06_000_jr_8016AB6C.o,tail15.data.o,ov_SC06_000_jr_80171B4C.o,ov_SC06_000_jr_801734BC.o,tail16.data.o,ov_SC06_000_jr_801789AC.o,ov_SC06_000_jr_80178D40.o,tail17.data.o,ov_SC06_000_jr_8017A4AC.o,tail18.data.o,ov_SC06_000_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_000/ov_SC06_000.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_000/ov_SC06_000_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_000/ov_SC06_000_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_000/ov_SC06_000_jr_8013F350.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 build/src/ov_SC06_000/ov_SC06_000_jr_8014032C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC06_000/ov_SC06_000_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_000/ov_SC06_000_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_000/ov_SC06_000_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_000/ov_SC06_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -534,12 +548,13 @@ ov_SC07_000_ELF := $(ov_SC07_000_OUT).elf ov_SC07_000_MAPFILE := $(ov_SC07_000_OUT).map ov_SC07_000_LD_SCRIPT := $(ov_SC07_000_OUT).ld ov_SC07_000_SPLAT_YAML := config/splat.ov_SC07_000.yaml -ov_SC07_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_000.o,ov_SC07_000_jr_8012ACE0.o,tail2.data.o,ov_SC07_000_jr_80135888.o,tail3.data.o,ov_SC07_000_jr_80135A4C.o,tail4.data.o,ov_SC07_000_jr_80135D20.o,tail5.data.o,ov_SC07_000_jr_801380E0.o,ov_SC07_000_o0c.o,tail6.data.o,ov_SC07_000_jr_8013F350.o,tail7.data.o,ov_SC07_000_jr_8013FFD8.o,tail8.data.o,ov_SC07_000_jr_80140608.o,tail9.data.o,ov_SC07_000_jr_8015444C.o,tail10.data.o,ov_SC07_000_jr_80154C24.o,ov_SC07_000_jr_801588CC.o,tail11.data.o,ov_SC07_000_jr_80159C84.o,tail12.data.o,ov_SC07_000_jr_8015A3C8.o,tail13.data.o,ov_SC07_000_jr_8015AE2C.o,tail14.data.o,ov_SC07_000_jr_8015C32C.o,tail15.data.o,ov_SC07_000_jr_8016AB6C.o,tail16.data.o,ov_SC07_000_jr_80171B4C.o,ov_SC07_000_jr_801734BC.o,tail17.data.o,ov_SC07_000_jr_801789AC.o,ov_SC07_000_jr_80178D40.o,tail18.data.o,ov_SC07_000_jr_8017A4AC.o,tail19.data.o,ov_SC07_000_jr_8017AE2C.o,ov_SC07_000_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC07_000_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_000.o,ov_SC07_000_jr_8012ACE0.o,tail2.data.o,ov_SC07_000_jr_80135888.o,tail3.data.o,ov_SC07_000_jr_80135A4C.o,tail4.data.o,ov_SC07_000_jr_80135D20.o,tail5.data.o,ov_SC07_000_jr_801380E0.o,ov_SC07_000_o0c.o,tail6.data.o,ov_SC07_000_jr_8013F350.o,tail7.data.o,ov_SC07_000_jr_8013FFD8.o,tail8.data.o,ov_SC07_000_jr_80140608.o,tail9.data.o,ov_SC07_000_jr_8015444C.o,ov_SC07_000_jr_80154C24.o,ov_SC07_000_jr_801588CC.o,tail10.data.o,ov_SC07_000_jr_80159C84.o,tail11.data.o,ov_SC07_000_jr_8015A3C8.o,tail12.data.o,ov_SC07_000_jr_8015AE2C.o,tail13.data.o,ov_SC07_000_jr_8015C32C.o,tail14.data.o,ov_SC07_000_jr_8016AB6C.o,tail15.data.o,ov_SC07_000_jr_80171B4C.o,ov_SC07_000_jr_801734BC.o,tail16.data.o,ov_SC07_000_jr_801789AC.o,ov_SC07_000_jr_80178D40.o,tail17.data.o,ov_SC07_000_jr_8017A4AC.o,tail18.data.o,ov_SC07_000_jr_8017AE2C.o,ov_SC07_000_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC07_000/ov_SC07_000.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_000/ov_SC07_000_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC07_000/ov_SC07_000_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC07_000/ov_SC07_000_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_000/ov_SC07_000_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC07_000/ov_SC07_000_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC07_000/ov_SC07_000_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_000/ov_SC07_000_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC07_000/ov_SC07_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -568,12 +583,13 @@ ov_SC01_004_ELF := $(ov_SC01_004_OUT).elf ov_SC01_004_MAPFILE := $(ov_SC01_004_OUT).map ov_SC01_004_LD_SCRIPT := $(ov_SC01_004_OUT).ld ov_SC01_004_SPLAT_YAML := config/splat.ov_SC01_004.yaml -ov_SC01_004_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_004.o,ov_SC01_004_jr_8012ACE0.o,tail2.data.o,ov_SC01_004_jr_80135888.o,tail3.data.o,ov_SC01_004_jr_80135A4C.o,tail4.data.o,ov_SC01_004_jr_80135D20.o,tail5.data.o,ov_SC01_004_jr_801380E0.o,ov_SC01_004_o0c.o,tail6.data.o,ov_SC01_004_jr_8013F350.o,tail7.data.o,ov_SC01_004_jr_8013FFD8.o,tail8.data.o,ov_SC01_004_jr_80140608.o,tail9.data.o,ov_SC01_004_jr_8015444C.o,tail10.data.o,ov_SC01_004_jr_80154C24.o,ov_SC01_004_jr_801588CC.o,tail11.data.o,ov_SC01_004_jr_80159C84.o,tail12.data.o,ov_SC01_004_jr_8015A3C8.o,tail13.data.o,ov_SC01_004_jr_8015AE2C.o,tail14.data.o,ov_SC01_004_jr_8015C32C.o,tail15.data.o,ov_SC01_004_jr_8016AB6C.o,tail16.data.o,ov_SC01_004_jr_80171B4C.o,ov_SC01_004_jr_801734BC.o,tail17.data.o,ov_SC01_004_jr_801789AC.o,ov_SC01_004_jr_80178D40.o,tail18.data.o,ov_SC01_004_jr_8017A4AC.o,tail19.data.o,ov_SC01_004_jr_8017AE2C.o,ov_SC01_004_jr_8017BE9C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC01_004_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_004.o,ov_SC01_004_jr_8012ACE0.o,tail2.data.o,ov_SC01_004_jr_80135888.o,tail3.data.o,ov_SC01_004_jr_80135A4C.o,tail4.data.o,ov_SC01_004_jr_80135D20.o,tail5.data.o,ov_SC01_004_jr_801380E0.o,ov_SC01_004_o0c.o,tail6.data.o,ov_SC01_004_jr_8013F350.o,tail7.data.o,ov_SC01_004_jr_8013FFD8.o,tail8.data.o,ov_SC01_004_jr_80140608.o,tail9.data.o,ov_SC01_004_jr_8015444C.o,ov_SC01_004_jr_80154C24.o,ov_SC01_004_jr_801588CC.o,tail10.data.o,ov_SC01_004_jr_80159C84.o,tail11.data.o,ov_SC01_004_jr_8015A3C8.o,tail12.data.o,ov_SC01_004_jr_8015AE2C.o,tail13.data.o,ov_SC01_004_jr_8015C32C.o,tail14.data.o,ov_SC01_004_jr_8016AB6C.o,tail15.data.o,ov_SC01_004_jr_80171B4C.o,ov_SC01_004_jr_801734BC.o,tail16.data.o,ov_SC01_004_jr_801789AC.o,ov_SC01_004_jr_80178D40.o,tail17.data.o,ov_SC01_004_jr_8017A4AC.o,tail18.data.o,ov_SC01_004_jr_8017AE2C.o,ov_SC01_004_jr_8017BE9C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC01_004/ov_SC01_004.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC01_004/ov_SC01_004_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC01_004/ov_SC01_004_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC01_004/ov_SC01_004_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_004/ov_SC01_004_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC01_004/ov_SC01_004_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC01_004/ov_SC01_004_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC01_004/ov_SC01_004_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC01_004/ov_SC01_004_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -602,12 +618,13 @@ ov_SC01_008_ELF := $(ov_SC01_008_OUT).elf ov_SC01_008_MAPFILE := $(ov_SC01_008_OUT).map ov_SC01_008_LD_SCRIPT := $(ov_SC01_008_OUT).ld ov_SC01_008_SPLAT_YAML := config/splat.ov_SC01_008.yaml -ov_SC01_008_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_008.o,ov_SC01_008_jr_8012ACE0.o,tail2.data.o,ov_SC01_008_jr_80135888.o,tail3.data.o,ov_SC01_008_jr_80135A4C.o,tail4.data.o,ov_SC01_008_jr_80135D20.o,tail5.data.o,ov_SC01_008_jr_801380E0.o,ov_SC01_008_o0c.o,tail6.data.o,ov_SC01_008_jr_8013F350.o,tail7.data.o,ov_SC01_008_jr_8013FFD8.o,tail8.data.o,ov_SC01_008_jr_80140608.o,tail9.data.o,ov_SC01_008_jr_8015444C.o,tail10.data.o,ov_SC01_008_jr_80154C24.o,ov_SC01_008_jr_801588CC.o,tail11.data.o,ov_SC01_008_jr_80159C84.o,tail12.data.o,ov_SC01_008_jr_8015A3C8.o,tail13.data.o,ov_SC01_008_jr_8015AE2C.o,tail14.data.o,ov_SC01_008_jr_8015C32C.o,tail15.data.o,ov_SC01_008_jr_8016AB6C.o,tail16.data.o,ov_SC01_008_jr_80171B4C.o,ov_SC01_008_jr_801734BC.o,tail17.data.o,ov_SC01_008_jr_801789AC.o,ov_SC01_008_jr_80178D40.o,tail18.data.o,ov_SC01_008_jr_8017A4AC.o,tail19.data.o,ov_SC01_008_jr_8017AE2C.o,ov_SC01_008_jr_8017BE9C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC01_008_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_008.o,ov_SC01_008_jr_8012ACE0.o,tail2.data.o,ov_SC01_008_jr_80135888.o,tail3.data.o,ov_SC01_008_jr_80135A4C.o,tail4.data.o,ov_SC01_008_jr_80135D20.o,tail5.data.o,ov_SC01_008_jr_801380E0.o,ov_SC01_008_o0c.o,tail6.data.o,ov_SC01_008_jr_8013F350.o,tail7.data.o,ov_SC01_008_jr_8013FFD8.o,tail8.data.o,ov_SC01_008_jr_80140608.o,tail9.data.o,ov_SC01_008_jr_8015444C.o,ov_SC01_008_jr_80154C24.o,ov_SC01_008_jr_801588CC.o,tail10.data.o,ov_SC01_008_jr_80159C84.o,tail11.data.o,ov_SC01_008_jr_8015A3C8.o,tail12.data.o,ov_SC01_008_jr_8015AE2C.o,tail13.data.o,ov_SC01_008_jr_8015C32C.o,tail14.data.o,ov_SC01_008_jr_8016AB6C.o,tail15.data.o,ov_SC01_008_jr_80171B4C.o,ov_SC01_008_jr_801734BC.o,tail16.data.o,ov_SC01_008_jr_801789AC.o,ov_SC01_008_jr_80178D40.o,tail17.data.o,ov_SC01_008_jr_8017A4AC.o,tail18.data.o,ov_SC01_008_jr_8017AE2C.o,ov_SC01_008_jr_8017BE9C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC01_008/ov_SC01_008.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC01_008/ov_SC01_008_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC01_008/ov_SC01_008_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC01_008/ov_SC01_008_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_008/ov_SC01_008_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC01_008/ov_SC01_008_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC01_008/ov_SC01_008_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC01_008/ov_SC01_008_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC01_008/ov_SC01_008_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -636,12 +653,13 @@ ov_SC01_009_ELF := $(ov_SC01_009_OUT).elf ov_SC01_009_MAPFILE := $(ov_SC01_009_OUT).map ov_SC01_009_LD_SCRIPT := $(ov_SC01_009_OUT).ld ov_SC01_009_SPLAT_YAML := config/splat.ov_SC01_009.yaml -ov_SC01_009_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_009.o,ov_SC01_009_jr_8012ACE0.o,tail2.data.o,ov_SC01_009_jr_80135888.o,tail3.data.o,ov_SC01_009_jr_80135A4C.o,tail4.data.o,ov_SC01_009_jr_80135D20.o,tail5.data.o,ov_SC01_009_jr_801380E0.o,ov_SC01_009_o0c.o,tail6.data.o,ov_SC01_009_jr_8013F350.o,tail7.data.o,ov_SC01_009_jr_8013FFD8.o,tail8.data.o,ov_SC01_009_jr_80140608.o,tail9.data.o,ov_SC01_009_jr_8015444C.o,tail10.data.o,ov_SC01_009_jr_80154C24.o,ov_SC01_009_jr_801588CC.o,tail11.data.o,ov_SC01_009_jr_80159C84.o,tail12.data.o,ov_SC01_009_jr_8015A3C8.o,tail13.data.o,ov_SC01_009_jr_8015AE2C.o,tail14.data.o,ov_SC01_009_jr_8015C32C.o,tail15.data.o,ov_SC01_009_jr_8016AB6C.o,tail16.data.o,ov_SC01_009_jr_80171B4C.o,ov_SC01_009_jr_801734BC.o,tail17.data.o,ov_SC01_009_jr_801789AC.o,ov_SC01_009_jr_80178D40.o,tail18.data.o,ov_SC01_009_jr_8017A4AC.o,tail19.data.o,ov_SC01_009_jr_8017AE2C.o,ov_SC01_009_jr_8017BE9C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC01_009_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_009.o,ov_SC01_009_jr_8012ACE0.o,tail2.data.o,ov_SC01_009_jr_80135888.o,tail3.data.o,ov_SC01_009_jr_80135A4C.o,tail4.data.o,ov_SC01_009_jr_80135D20.o,tail5.data.o,ov_SC01_009_jr_801380E0.o,ov_SC01_009_o0c.o,tail6.data.o,ov_SC01_009_jr_8013F350.o,tail7.data.o,ov_SC01_009_jr_8013FFD8.o,tail8.data.o,ov_SC01_009_jr_80140608.o,tail9.data.o,ov_SC01_009_jr_8015444C.o,ov_SC01_009_jr_80154C24.o,ov_SC01_009_jr_801588CC.o,tail10.data.o,ov_SC01_009_jr_80159C84.o,tail11.data.o,ov_SC01_009_jr_8015A3C8.o,tail12.data.o,ov_SC01_009_jr_8015AE2C.o,tail13.data.o,ov_SC01_009_jr_8015C32C.o,tail14.data.o,ov_SC01_009_jr_8016AB6C.o,tail15.data.o,ov_SC01_009_jr_80171B4C.o,ov_SC01_009_jr_801734BC.o,tail16.data.o,ov_SC01_009_jr_801789AC.o,ov_SC01_009_jr_80178D40.o,tail17.data.o,ov_SC01_009_jr_8017A4AC.o,tail18.data.o,ov_SC01_009_jr_8017AE2C.o,ov_SC01_009_jr_8017BE9C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC01_009/ov_SC01_009.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC01_009/ov_SC01_009_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC01_009/ov_SC01_009_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC01_009/ov_SC01_009_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_009/ov_SC01_009_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC01_009/ov_SC01_009_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC01_009/ov_SC01_009_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC01_009/ov_SC01_009_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC01_009/ov_SC01_009_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -670,12 +688,13 @@ ov_SC01_074_ELF := $(ov_SC01_074_OUT).elf ov_SC01_074_MAPFILE := $(ov_SC01_074_OUT).map ov_SC01_074_LD_SCRIPT := $(ov_SC01_074_OUT).ld ov_SC01_074_SPLAT_YAML := config/splat.ov_SC01_074.yaml -ov_SC01_074_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_074.o,ov_SC01_074_jr_8012ACE0.o,tail2.data.o,ov_SC01_074_jr_80135888.o,tail3.data.o,ov_SC01_074_jr_80135A4C.o,tail4.data.o,ov_SC01_074_jr_80135D20.o,tail5.data.o,ov_SC01_074_jr_801380E0.o,ov_SC01_074_o0c.o,tail6.data.o,ov_SC01_074_jr_8013F350.o,tail7.data.o,ov_SC01_074_jr_8013FFD8.o,tail8.data.o,ov_SC01_074_jr_80140608.o,tail9.data.o,ov_SC01_074_jr_8015444C.o,tail10.data.o,ov_SC01_074_jr_80154C24.o,ov_SC01_074_jr_801588CC.o,tail11.data.o,ov_SC01_074_jr_80159C84.o,tail12.data.o,ov_SC01_074_jr_8015A3C8.o,tail13.data.o,ov_SC01_074_jr_8015AE2C.o,tail14.data.o,ov_SC01_074_jr_8015C32C.o,tail15.data.o,ov_SC01_074_jr_8016AB6C.o,tail16.data.o,ov_SC01_074_jr_80171B4C.o,ov_SC01_074_jr_801734BC.o,tail17.data.o,ov_SC01_074_jr_801789AC.o,ov_SC01_074_jr_80178D40.o,tail18.data.o,ov_SC01_074_jr_8017A4AC.o,tail19.data.o,ov_SC01_074_jr_8017AE2C.o,ov_SC01_074_jr_8017BE9C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC01_074_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_074.o,ov_SC01_074_jr_8012ACE0.o,tail2.data.o,ov_SC01_074_jr_80135888.o,tail3.data.o,ov_SC01_074_jr_80135A4C.o,tail4.data.o,ov_SC01_074_jr_80135D20.o,tail5.data.o,ov_SC01_074_jr_801380E0.o,ov_SC01_074_o0c.o,tail6.data.o,ov_SC01_074_jr_8013F350.o,tail7.data.o,ov_SC01_074_jr_8013FFD8.o,tail8.data.o,ov_SC01_074_jr_80140608.o,tail9.data.o,ov_SC01_074_jr_8015444C.o,ov_SC01_074_jr_80154C24.o,ov_SC01_074_jr_801588CC.o,tail10.data.o,ov_SC01_074_jr_80159C84.o,tail11.data.o,ov_SC01_074_jr_8015A3C8.o,tail12.data.o,ov_SC01_074_jr_8015AE2C.o,tail13.data.o,ov_SC01_074_jr_8015C32C.o,tail14.data.o,ov_SC01_074_jr_8016AB6C.o,tail15.data.o,ov_SC01_074_jr_80171B4C.o,ov_SC01_074_jr_801734BC.o,tail16.data.o,ov_SC01_074_jr_801789AC.o,ov_SC01_074_jr_80178D40.o,tail17.data.o,ov_SC01_074_jr_8017A4AC.o,tail18.data.o,ov_SC01_074_jr_8017AE2C.o,ov_SC01_074_jr_8017BE9C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC01_074/ov_SC01_074.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC01_074/ov_SC01_074_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC01_074/ov_SC01_074_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC01_074/ov_SC01_074_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_074/ov_SC01_074_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC01_074/ov_SC01_074_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC01_074/ov_SC01_074_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC01_074/ov_SC01_074_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC01_074/ov_SC01_074_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -704,12 +723,13 @@ ov_SC01_080_ELF := $(ov_SC01_080_OUT).elf ov_SC01_080_MAPFILE := $(ov_SC01_080_OUT).map ov_SC01_080_LD_SCRIPT := $(ov_SC01_080_OUT).ld ov_SC01_080_SPLAT_YAML := config/splat.ov_SC01_080.yaml -ov_SC01_080_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_080.o,ov_SC01_080_jr_8012ACE0.o,tail2.data.o,ov_SC01_080_jr_80135888.o,tail3.data.o,ov_SC01_080_jr_80135A4C.o,tail4.data.o,ov_SC01_080_jr_80135D20.o,tail5.data.o,ov_SC01_080_jr_801380E0.o,ov_SC01_080_o0c.o,tail6.data.o,ov_SC01_080_jr_8013F350.o,tail7.data.o,ov_SC01_080_jr_8013FFD8.o,tail8.data.o,ov_SC01_080_jr_80140608.o,tail9.data.o,ov_SC01_080_jr_8015444C.o,tail10.data.o,ov_SC01_080_jr_80154C24.o,ov_SC01_080_jr_801588CC.o,tail11.data.o,ov_SC01_080_jr_80159C84.o,tail12.data.o,ov_SC01_080_jr_8015A3C8.o,tail13.data.o,ov_SC01_080_jr_8015AE2C.o,tail14.data.o,ov_SC01_080_jr_8015C32C.o,tail15.data.o,ov_SC01_080_jr_8016AB6C.o,tail16.data.o,ov_SC01_080_jr_80171B4C.o,ov_SC01_080_jr_801734BC.o,tail17.data.o,ov_SC01_080_jr_801789AC.o,ov_SC01_080_jr_80178D40.o,tail18.data.o,ov_SC01_080_jr_8017A4AC.o,tail19.data.o,ov_SC01_080_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC01_080_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_080.o,ov_SC01_080_jr_8012ACE0.o,tail2.data.o,ov_SC01_080_jr_80135888.o,tail3.data.o,ov_SC01_080_jr_80135A4C.o,tail4.data.o,ov_SC01_080_jr_80135D20.o,tail5.data.o,ov_SC01_080_jr_801380E0.o,ov_SC01_080_o0c.o,tail6.data.o,ov_SC01_080_jr_8013F350.o,tail7.data.o,ov_SC01_080_jr_8013FFD8.o,tail8.data.o,ov_SC01_080_jr_80140608.o,tail9.data.o,ov_SC01_080_jr_8015444C.o,ov_SC01_080_jr_80154C24.o,ov_SC01_080_jr_801588CC.o,tail10.data.o,ov_SC01_080_jr_80159C84.o,tail11.data.o,ov_SC01_080_jr_8015A3C8.o,tail12.data.o,ov_SC01_080_jr_8015AE2C.o,tail13.data.o,ov_SC01_080_jr_8015C32C.o,tail14.data.o,ov_SC01_080_jr_8016AB6C.o,tail15.data.o,ov_SC01_080_jr_80171B4C.o,ov_SC01_080_jr_801734BC.o,tail16.data.o,ov_SC01_080_jr_801789AC.o,ov_SC01_080_jr_80178D40.o,tail17.data.o,ov_SC01_080_jr_8017A4AC.o,tail18.data.o,ov_SC01_080_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC01_080/ov_SC01_080.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC01_080/ov_SC01_080_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC01_080/ov_SC01_080_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC01_080/ov_SC01_080_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_080/ov_SC01_080_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC01_080/ov_SC01_080_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC01_080/ov_SC01_080_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC01_080/ov_SC01_080_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC01_080/ov_SC01_080_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -738,12 +758,13 @@ ov_SC01_084_ELF := $(ov_SC01_084_OUT).elf ov_SC01_084_MAPFILE := $(ov_SC01_084_OUT).map ov_SC01_084_LD_SCRIPT := $(ov_SC01_084_OUT).ld ov_SC01_084_SPLAT_YAML := config/splat.ov_SC01_084.yaml -ov_SC01_084_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_084.o,ov_SC01_084_jr_8012ACE0.o,tail2.data.o,ov_SC01_084_jr_80135888.o,tail3.data.o,ov_SC01_084_jr_80135A4C.o,tail4.data.o,ov_SC01_084_jr_80135D20.o,tail5.data.o,ov_SC01_084_jr_801380E0.o,ov_SC01_084_o0c.o,tail6.data.o,ov_SC01_084_jr_8013F350.o,tail7.data.o,ov_SC01_084_jr_8013FFD8.o,tail8.data.o,ov_SC01_084_jr_80140608.o,tail9.data.o,ov_SC01_084_jr_8015444C.o,tail10.data.o,ov_SC01_084_jr_80154C24.o,ov_SC01_084_jr_801588CC.o,tail11.data.o,ov_SC01_084_jr_80159C84.o,tail12.data.o,ov_SC01_084_jr_8015A3C8.o,tail13.data.o,ov_SC01_084_jr_8015AE2C.o,tail14.data.o,ov_SC01_084_jr_8015C32C.o,tail15.data.o,ov_SC01_084_jr_8016AB6C.o,tail16.data.o,ov_SC01_084_jr_80171B4C.o,ov_SC01_084_jr_801734BC.o,tail17.data.o,ov_SC01_084_jr_801789AC.o,ov_SC01_084_jr_80178D40.o,tail18.data.o,ov_SC01_084_jr_8017A4AC.o,tail19.data.o,ov_SC01_084_jr_8017AE2C.o,ov_SC01_084_jr_8017CA80.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC01_084_JTBL_INTERLEAVE := --order tail.data.o,ov_SC01_084.o,ov_SC01_084_jr_8012ACE0.o,tail2.data.o,ov_SC01_084_jr_80135888.o,tail3.data.o,ov_SC01_084_jr_80135A4C.o,tail4.data.o,ov_SC01_084_jr_80135D20.o,tail5.data.o,ov_SC01_084_jr_801380E0.o,ov_SC01_084_o0c.o,tail6.data.o,ov_SC01_084_jr_8013F350.o,tail7.data.o,ov_SC01_084_jr_8013FFD8.o,tail8.data.o,ov_SC01_084_jr_80140608.o,tail9.data.o,ov_SC01_084_jr_8015444C.o,ov_SC01_084_jr_80154C24.o,ov_SC01_084_jr_801588CC.o,tail10.data.o,ov_SC01_084_jr_80159C84.o,tail11.data.o,ov_SC01_084_jr_8015A3C8.o,tail12.data.o,ov_SC01_084_jr_8015AE2C.o,tail13.data.o,ov_SC01_084_jr_8015C32C.o,tail14.data.o,ov_SC01_084_jr_8016AB6C.o,tail15.data.o,ov_SC01_084_jr_80171B4C.o,ov_SC01_084_jr_801734BC.o,tail16.data.o,ov_SC01_084_jr_801789AC.o,ov_SC01_084_jr_80178D40.o,tail17.data.o,ov_SC01_084_jr_8017A4AC.o,tail18.data.o,ov_SC01_084_jr_8017AE2C.o,ov_SC01_084_jr_8017CA80.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC01_084/ov_SC01_084.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC01_084/ov_SC01_084_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC01_084/ov_SC01_084_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC01_084/ov_SC01_084_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_084/ov_SC01_084_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC01_084/ov_SC01_084_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC01_084/ov_SC01_084_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC01_084/ov_SC01_084_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC01_084/ov_SC01_084_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -772,12 +793,13 @@ ov_SC02_004_ELF := $(ov_SC02_004_OUT).elf ov_SC02_004_MAPFILE := $(ov_SC02_004_OUT).map ov_SC02_004_LD_SCRIPT := $(ov_SC02_004_OUT).ld ov_SC02_004_SPLAT_YAML := config/splat.ov_SC02_004.yaml -ov_SC02_004_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_004.o,ov_SC02_004_jr_8012ACE0.o,tail2.data.o,ov_SC02_004_jr_80135888.o,tail3.data.o,ov_SC02_004_jr_80135A4C.o,tail4.data.o,ov_SC02_004_jr_80135D20.o,tail5.data.o,ov_SC02_004_jr_801380E0.o,ov_SC02_004_o0c.o,tail6.data.o,ov_SC02_004_jr_8013F350.o,tail7.data.o,ov_SC02_004_jr_8013FFD8.o,tail8.data.o,ov_SC02_004_jr_80140608.o,tail9.data.o,ov_SC02_004_jr_8015444C.o,tail10.data.o,ov_SC02_004_jr_80154C24.o,ov_SC02_004_jr_801588CC.o,tail11.data.o,ov_SC02_004_jr_80159C84.o,tail12.data.o,ov_SC02_004_jr_8015A3C8.o,tail13.data.o,ov_SC02_004_jr_8015AE2C.o,tail14.data.o,ov_SC02_004_jr_8015C32C.o,tail15.data.o,ov_SC02_004_jr_8016AB6C.o,tail16.data.o,ov_SC02_004_jr_80171B4C.o,ov_SC02_004_jr_801734BC.o,tail17.data.o,ov_SC02_004_jr_801789AC.o,ov_SC02_004_jr_80178D40.o,tail18.data.o,ov_SC02_004_jr_8017A4AC.o,tail19.data.o,ov_SC02_004_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_004_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_004.o,ov_SC02_004_jr_8012ACE0.o,tail2.data.o,ov_SC02_004_jr_80135888.o,tail3.data.o,ov_SC02_004_jr_80135A4C.o,tail4.data.o,ov_SC02_004_jr_80135D20.o,tail5.data.o,ov_SC02_004_jr_801380E0.o,ov_SC02_004_o0c.o,tail6.data.o,ov_SC02_004_jr_8013F350.o,tail7.data.o,ov_SC02_004_jr_8013FFD8.o,tail8.data.o,ov_SC02_004_jr_80140608.o,tail9.data.o,ov_SC02_004_jr_8015444C.o,ov_SC02_004_jr_80154C24.o,ov_SC02_004_jr_801588CC.o,tail10.data.o,ov_SC02_004_jr_80159C84.o,tail11.data.o,ov_SC02_004_jr_8015A3C8.o,tail12.data.o,ov_SC02_004_jr_8015AE2C.o,tail13.data.o,ov_SC02_004_jr_8015C32C.o,tail14.data.o,ov_SC02_004_jr_8016AB6C.o,tail15.data.o,ov_SC02_004_jr_80171B4C.o,ov_SC02_004_jr_801734BC.o,tail16.data.o,ov_SC02_004_jr_801789AC.o,ov_SC02_004_jr_80178D40.o,tail17.data.o,ov_SC02_004_jr_8017A4AC.o,tail18.data.o,ov_SC02_004_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_004/ov_SC02_004.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_004/ov_SC02_004_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_004/ov_SC02_004_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_004/ov_SC02_004_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_004/ov_SC02_004_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_004/ov_SC02_004_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_004/ov_SC02_004_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_004/ov_SC02_004_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_004/ov_SC02_004_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -806,12 +828,13 @@ ov_SC02_005_ELF := $(ov_SC02_005_OUT).elf ov_SC02_005_MAPFILE := $(ov_SC02_005_OUT).map ov_SC02_005_LD_SCRIPT := $(ov_SC02_005_OUT).ld ov_SC02_005_SPLAT_YAML := config/splat.ov_SC02_005.yaml -ov_SC02_005_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_005.o,ov_SC02_005_jr_8012ACE0.o,tail2.data.o,ov_SC02_005_jr_80135888.o,tail3.data.o,ov_SC02_005_jr_80135A4C.o,tail4.data.o,ov_SC02_005_jr_80135D20.o,tail5.data.o,ov_SC02_005_jr_801380E0.o,ov_SC02_005_o0c.o,tail6.data.o,ov_SC02_005_jr_8013F350.o,tail7.data.o,ov_SC02_005_jr_8013FFD8.o,tail8.data.o,ov_SC02_005_jr_80140608.o,tail9.data.o,ov_SC02_005_jr_8015444C.o,tail10.data.o,ov_SC02_005_jr_80154C24.o,ov_SC02_005_jr_801588CC.o,tail11.data.o,ov_SC02_005_jr_80159C84.o,tail12.data.o,ov_SC02_005_jr_8015A3C8.o,tail13.data.o,ov_SC02_005_jr_8015AE2C.o,tail14.data.o,ov_SC02_005_jr_8015C32C.o,tail15.data.o,ov_SC02_005_jr_8016AB6C.o,tail16.data.o,ov_SC02_005_jr_80171B4C.o,ov_SC02_005_jr_801734BC.o,tail17.data.o,ov_SC02_005_jr_801789AC.o,ov_SC02_005_jr_80178D40.o,tail18.data.o,ov_SC02_005_jr_8017A4AC.o,tail19.data.o,ov_SC02_005_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_005_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_005.o,ov_SC02_005_jr_8012ACE0.o,tail2.data.o,ov_SC02_005_jr_80135888.o,tail3.data.o,ov_SC02_005_jr_80135A4C.o,tail4.data.o,ov_SC02_005_jr_80135D20.o,tail5.data.o,ov_SC02_005_jr_801380E0.o,ov_SC02_005_o0c.o,tail6.data.o,ov_SC02_005_jr_8013F350.o,tail7.data.o,ov_SC02_005_jr_8013FFD8.o,tail8.data.o,ov_SC02_005_jr_80140608.o,tail9.data.o,ov_SC02_005_jr_8015444C.o,ov_SC02_005_jr_80154C24.o,ov_SC02_005_jr_801588CC.o,tail10.data.o,ov_SC02_005_jr_80159C84.o,tail11.data.o,ov_SC02_005_jr_8015A3C8.o,tail12.data.o,ov_SC02_005_jr_8015AE2C.o,tail13.data.o,ov_SC02_005_jr_8015C32C.o,tail14.data.o,ov_SC02_005_jr_8016AB6C.o,tail15.data.o,ov_SC02_005_jr_80171B4C.o,ov_SC02_005_jr_801734BC.o,tail16.data.o,ov_SC02_005_jr_801789AC.o,ov_SC02_005_jr_80178D40.o,tail17.data.o,ov_SC02_005_jr_8017A4AC.o,tail18.data.o,ov_SC02_005_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_005/ov_SC02_005.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_005/ov_SC02_005_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_005/ov_SC02_005_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_005/ov_SC02_005_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_005/ov_SC02_005_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_005/ov_SC02_005_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_005/ov_SC02_005_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_005/ov_SC02_005_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_005/ov_SC02_005_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -840,12 +863,13 @@ ov_SC02_011_ELF := $(ov_SC02_011_OUT).elf ov_SC02_011_MAPFILE := $(ov_SC02_011_OUT).map ov_SC02_011_LD_SCRIPT := $(ov_SC02_011_OUT).ld ov_SC02_011_SPLAT_YAML := config/splat.ov_SC02_011.yaml -ov_SC02_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_011.o,ov_SC02_011_jr_8012ACE0.o,tail2.data.o,ov_SC02_011_jr_80135888.o,tail3.data.o,ov_SC02_011_jr_80135A4C.o,tail4.data.o,ov_SC02_011_jr_80135D20.o,tail5.data.o,ov_SC02_011_jr_801380E0.o,ov_SC02_011_o0c.o,tail6.data.o,ov_SC02_011_jr_8013F350.o,tail7.data.o,ov_SC02_011_jr_8013FFD8.o,tail8.data.o,ov_SC02_011_jr_80140608.o,tail9.data.o,ov_SC02_011_jr_8015444C.o,tail10.data.o,ov_SC02_011_jr_80154C24.o,ov_SC02_011_jr_801588CC.o,tail11.data.o,ov_SC02_011_jr_80159C84.o,tail12.data.o,ov_SC02_011_jr_8015A3C8.o,tail13.data.o,ov_SC02_011_jr_8015AE2C.o,tail14.data.o,ov_SC02_011_jr_8015C32C.o,tail15.data.o,ov_SC02_011_jr_8016AB6C.o,tail16.data.o,ov_SC02_011_jr_80171B4C.o,ov_SC02_011_jr_801734BC.o,tail17.data.o,ov_SC02_011_jr_801789AC.o,ov_SC02_011_jr_80178D40.o,tail18.data.o,ov_SC02_011_jr_8017A4AC.o,tail19.data.o,ov_SC02_011_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_011.o,ov_SC02_011_jr_8012ACE0.o,tail2.data.o,ov_SC02_011_jr_80135888.o,tail3.data.o,ov_SC02_011_jr_80135A4C.o,tail4.data.o,ov_SC02_011_jr_80135D20.o,tail5.data.o,ov_SC02_011_jr_801380E0.o,ov_SC02_011_o0c.o,tail6.data.o,ov_SC02_011_jr_8013F350.o,tail7.data.o,ov_SC02_011_jr_8013FFD8.o,tail8.data.o,ov_SC02_011_jr_80140608.o,tail9.data.o,ov_SC02_011_jr_8015444C.o,ov_SC02_011_jr_80154C24.o,ov_SC02_011_jr_801588CC.o,tail10.data.o,ov_SC02_011_jr_80159C84.o,tail11.data.o,ov_SC02_011_jr_8015A3C8.o,tail12.data.o,ov_SC02_011_jr_8015AE2C.o,tail13.data.o,ov_SC02_011_jr_8015C32C.o,tail14.data.o,ov_SC02_011_jr_8016AB6C.o,tail15.data.o,ov_SC02_011_jr_80171B4C.o,ov_SC02_011_jr_801734BC.o,tail16.data.o,ov_SC02_011_jr_801789AC.o,ov_SC02_011_jr_80178D40.o,tail17.data.o,ov_SC02_011_jr_8017A4AC.o,tail18.data.o,ov_SC02_011_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_011/ov_SC02_011.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_011/ov_SC02_011_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_011/ov_SC02_011_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_011/ov_SC02_011_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_011/ov_SC02_011_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_011/ov_SC02_011_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_011/ov_SC02_011_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_011/ov_SC02_011_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_011/ov_SC02_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -874,12 +898,13 @@ ov_SC02_015_ELF := $(ov_SC02_015_OUT).elf ov_SC02_015_MAPFILE := $(ov_SC02_015_OUT).map ov_SC02_015_LD_SCRIPT := $(ov_SC02_015_OUT).ld ov_SC02_015_SPLAT_YAML := config/splat.ov_SC02_015.yaml -ov_SC02_015_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_015.o,ov_SC02_015_jr_8012ACE0.o,tail2.data.o,ov_SC02_015_jr_80135888.o,tail3.data.o,ov_SC02_015_jr_80135A4C.o,tail4.data.o,ov_SC02_015_jr_80135D20.o,tail5.data.o,ov_SC02_015_jr_801380E0.o,ov_SC02_015_o0c.o,tail6.data.o,ov_SC02_015_jr_8013F350.o,tail7.data.o,ov_SC02_015_jr_8013FFD8.o,tail8.data.o,ov_SC02_015_jr_80140608.o,tail9.data.o,ov_SC02_015_jr_8015444C.o,tail10.data.o,ov_SC02_015_jr_80154C24.o,ov_SC02_015_jr_801588CC.o,tail11.data.o,ov_SC02_015_jr_80159C84.o,tail12.data.o,ov_SC02_015_jr_8015A3C8.o,tail13.data.o,ov_SC02_015_jr_8015AE2C.o,tail14.data.o,ov_SC02_015_jr_8015C32C.o,tail15.data.o,ov_SC02_015_jr_8016AB6C.o,tail16.data.o,ov_SC02_015_jr_80171B4C.o,ov_SC02_015_jr_801734BC.o,tail17.data.o,ov_SC02_015_jr_801789AC.o,ov_SC02_015_jr_80178D40.o,tail18.data.o,ov_SC02_015_jr_8017A4AC.o,tail19.data.o,ov_SC02_015_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_015_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_015.o,ov_SC02_015_jr_8012ACE0.o,tail2.data.o,ov_SC02_015_jr_80135888.o,tail3.data.o,ov_SC02_015_jr_80135A4C.o,tail4.data.o,ov_SC02_015_jr_80135D20.o,tail5.data.o,ov_SC02_015_jr_801380E0.o,ov_SC02_015_o0c.o,tail6.data.o,ov_SC02_015_jr_8013F350.o,tail7.data.o,ov_SC02_015_jr_8013FFD8.o,tail8.data.o,ov_SC02_015_jr_80140608.o,tail9.data.o,ov_SC02_015_jr_8015444C.o,ov_SC02_015_jr_80154C24.o,ov_SC02_015_jr_801588CC.o,tail10.data.o,ov_SC02_015_jr_80159C84.o,tail11.data.o,ov_SC02_015_jr_8015A3C8.o,tail12.data.o,ov_SC02_015_jr_8015AE2C.o,tail13.data.o,ov_SC02_015_jr_8015C32C.o,tail14.data.o,ov_SC02_015_jr_8016AB6C.o,tail15.data.o,ov_SC02_015_jr_80171B4C.o,ov_SC02_015_jr_801734BC.o,tail16.data.o,ov_SC02_015_jr_801789AC.o,ov_SC02_015_jr_80178D40.o,tail17.data.o,ov_SC02_015_jr_8017A4AC.o,tail18.data.o,ov_SC02_015_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_015/ov_SC02_015.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_015/ov_SC02_015_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_015/ov_SC02_015_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_015/ov_SC02_015_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_015/ov_SC02_015_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_015/ov_SC02_015_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_015/ov_SC02_015_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_015/ov_SC02_015_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_015/ov_SC02_015_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -909,12 +934,13 @@ ov_SC02_016_ELF := $(ov_SC02_016_OUT).elf ov_SC02_016_MAPFILE := $(ov_SC02_016_OUT).map ov_SC02_016_LD_SCRIPT := $(ov_SC02_016_OUT).ld ov_SC02_016_SPLAT_YAML := config/splat.ov_SC02_016.yaml -ov_SC02_016_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_016.o,ov_SC02_016_jr_8012ACE0.o,tail2.data.o,ov_SC02_016_jr_80135888.o,tail3.data.o,ov_SC02_016_jr_80135A4C.o,tail4.data.o,ov_SC02_016_jr_80135D20.o,tail5.data.o,ov_SC02_016_jr_801380E0.o,ov_SC02_016_o0c.o,tail6.data.o,ov_SC02_016_jr_8013F350.o,tail7.data.o,ov_SC02_016_jr_8013FFD8.o,tail8.data.o,ov_SC02_016_jr_80140608.o,tail9.data.o,ov_SC02_016_jr_8015444C.o,tail10.data.o,ov_SC02_016_jr_80154C24.o,ov_SC02_016_jr_801588CC.o,tail11.data.o,ov_SC02_016_jr_80159C84.o,tail12.data.o,ov_SC02_016_jr_8015A3C8.o,tail13.data.o,ov_SC02_016_jr_8015AE2C.o,tail14.data.o,ov_SC02_016_jr_8015C32C.o,tail15.data.o,ov_SC02_016_jr_8016AB6C.o,tail16.data.o,ov_SC02_016_jr_80171B4C.o,ov_SC02_016_jr_801734BC.o,tail17.data.o,ov_SC02_016_jr_801789AC.o,ov_SC02_016_jr_80178D40.o,tail18.data.o,ov_SC02_016_jr_8017A4AC.o,tail19.data.o,ov_SC02_016_jr_8017AE2C.o,ov_SC02_016_jr_8017DC70.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_016_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_016.o,ov_SC02_016_jr_8012ACE0.o,tail2.data.o,ov_SC02_016_jr_80135888.o,tail3.data.o,ov_SC02_016_jr_80135A4C.o,tail4.data.o,ov_SC02_016_jr_80135D20.o,tail5.data.o,ov_SC02_016_jr_801380E0.o,ov_SC02_016_o0c.o,tail6.data.o,ov_SC02_016_jr_8013F350.o,tail7.data.o,ov_SC02_016_jr_8013FFD8.o,tail8.data.o,ov_SC02_016_jr_80140608.o,tail9.data.o,ov_SC02_016_jr_8015444C.o,ov_SC02_016_jr_80154C24.o,ov_SC02_016_jr_801588CC.o,tail10.data.o,ov_SC02_016_jr_80159C84.o,tail11.data.o,ov_SC02_016_jr_8015A3C8.o,tail12.data.o,ov_SC02_016_jr_8015AE2C.o,tail13.data.o,ov_SC02_016_jr_8015C32C.o,tail14.data.o,ov_SC02_016_jr_8016AB6C.o,tail15.data.o,ov_SC02_016_jr_80171B4C.o,ov_SC02_016_jr_801734BC.o,tail16.data.o,ov_SC02_016_jr_801789AC.o,ov_SC02_016_jr_80178D40.o,tail17.data.o,ov_SC02_016_jr_8017A4AC.o,tail18.data.o,ov_SC02_016_jr_8017AE2C.o,ov_SC02_016_jr_8017DC70.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_016/ov_SC02_016.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_016/ov_SC02_016_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_016/ov_SC02_016_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_016/ov_SC02_016_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_016/ov_SC02_016_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_016/ov_SC02_016_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_016/ov_SC02_016_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_016/ov_SC02_016_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_016/ov_SC02_016_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -943,12 +969,13 @@ ov_SC02_017_ELF := $(ov_SC02_017_OUT).elf ov_SC02_017_MAPFILE := $(ov_SC02_017_OUT).map ov_SC02_017_LD_SCRIPT := $(ov_SC02_017_OUT).ld ov_SC02_017_SPLAT_YAML := config/splat.ov_SC02_017.yaml -ov_SC02_017_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_017.o,ov_SC02_017_jr_8012ACE0.o,tail2.data.o,ov_SC02_017_jr_80135888.o,tail3.data.o,ov_SC02_017_jr_80135A4C.o,tail4.data.o,ov_SC02_017_jr_80135D20.o,tail5.data.o,ov_SC02_017_jr_801380E0.o,ov_SC02_017_o0c.o,tail6.data.o,ov_SC02_017_jr_8013F350.o,tail7.data.o,ov_SC02_017_jr_8013FFD8.o,tail8.data.o,ov_SC02_017_jr_80140608.o,tail9.data.o,ov_SC02_017_jr_8015444C.o,tail10.data.o,ov_SC02_017_jr_80154C24.o,ov_SC02_017_jr_801588CC.o,tail11.data.o,ov_SC02_017_jr_80159C84.o,tail12.data.o,ov_SC02_017_jr_8015A3C8.o,tail13.data.o,ov_SC02_017_jr_8015AE2C.o,tail14.data.o,ov_SC02_017_jr_8015C32C.o,tail15.data.o,ov_SC02_017_jr_8016AB6C.o,tail16.data.o,ov_SC02_017_jr_80171B4C.o,ov_SC02_017_jr_801734BC.o,tail17.data.o,ov_SC02_017_jr_801789AC.o,ov_SC02_017_jr_80178D40.o,tail18.data.o,ov_SC02_017_jr_8017A4AC.o,tail19.data.o,ov_SC02_017_jr_8017AE2C.o,ov_SC02_017_jr_8017DF34.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_017_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_017.o,ov_SC02_017_jr_8012ACE0.o,tail2.data.o,ov_SC02_017_jr_80135888.o,tail3.data.o,ov_SC02_017_jr_80135A4C.o,tail4.data.o,ov_SC02_017_jr_80135D20.o,tail5.data.o,ov_SC02_017_jr_801380E0.o,ov_SC02_017_o0c.o,tail6.data.o,ov_SC02_017_jr_8013F350.o,tail7.data.o,ov_SC02_017_jr_8013FFD8.o,tail8.data.o,ov_SC02_017_jr_80140608.o,tail9.data.o,ov_SC02_017_jr_8015444C.o,ov_SC02_017_jr_80154C24.o,ov_SC02_017_jr_801588CC.o,tail10.data.o,ov_SC02_017_jr_80159C84.o,tail11.data.o,ov_SC02_017_jr_8015A3C8.o,tail12.data.o,ov_SC02_017_jr_8015AE2C.o,tail13.data.o,ov_SC02_017_jr_8015C32C.o,tail14.data.o,ov_SC02_017_jr_8016AB6C.o,tail15.data.o,ov_SC02_017_jr_80171B4C.o,ov_SC02_017_jr_801734BC.o,tail16.data.o,ov_SC02_017_jr_801789AC.o,ov_SC02_017_jr_80178D40.o,tail17.data.o,ov_SC02_017_jr_8017A4AC.o,tail18.data.o,ov_SC02_017_jr_8017AE2C.o,ov_SC02_017_jr_8017DF34.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_017/ov_SC02_017.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_017/ov_SC02_017_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_017/ov_SC02_017_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_017/ov_SC02_017_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_017/ov_SC02_017_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_017/ov_SC02_017_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_017/ov_SC02_017_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_017/ov_SC02_017_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_017/ov_SC02_017_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -977,12 +1004,13 @@ ov_SC02_021_ELF := $(ov_SC02_021_OUT).elf ov_SC02_021_MAPFILE := $(ov_SC02_021_OUT).map ov_SC02_021_LD_SCRIPT := $(ov_SC02_021_OUT).ld ov_SC02_021_SPLAT_YAML := config/splat.ov_SC02_021.yaml -ov_SC02_021_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_021.o,ov_SC02_021_jr_8012ACE0.o,tail2.data.o,ov_SC02_021_jr_80135888.o,tail3.data.o,ov_SC02_021_jr_80135A4C.o,tail4.data.o,ov_SC02_021_jr_80135D20.o,tail5.data.o,ov_SC02_021_jr_801380E0.o,ov_SC02_021_o0c.o,tail6.data.o,ov_SC02_021_jr_8013F350.o,tail7.data.o,ov_SC02_021_jr_8013FFD8.o,tail8.data.o,ov_SC02_021_jr_80140608.o,tail9.data.o,ov_SC02_021_jr_8015444C.o,tail10.data.o,ov_SC02_021_jr_80154C24.o,ov_SC02_021_jr_801588CC.o,tail11.data.o,ov_SC02_021_jr_80159C84.o,tail12.data.o,ov_SC02_021_jr_8015A3C8.o,tail13.data.o,ov_SC02_021_jr_8015AE2C.o,tail14.data.o,ov_SC02_021_jr_8015C32C.o,tail15.data.o,ov_SC02_021_jr_8016AB6C.o,tail16.data.o,ov_SC02_021_jr_80171B4C.o,ov_SC02_021_jr_801734BC.o,tail17.data.o,ov_SC02_021_jr_801789AC.o,ov_SC02_021_jr_80178D40.o,tail18.data.o,ov_SC02_021_jr_8017A4AC.o,tail19.data.o,ov_SC02_021_jr_8017AE2C.o,ov_SC02_021_jr_8017C294.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_021_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_021.o,ov_SC02_021_jr_8012ACE0.o,tail2.data.o,ov_SC02_021_jr_80135888.o,tail3.data.o,ov_SC02_021_jr_80135A4C.o,tail4.data.o,ov_SC02_021_jr_80135D20.o,tail5.data.o,ov_SC02_021_jr_801380E0.o,ov_SC02_021_o0c.o,tail6.data.o,ov_SC02_021_jr_8013F350.o,tail7.data.o,ov_SC02_021_jr_8013FFD8.o,tail8.data.o,ov_SC02_021_jr_80140608.o,tail9.data.o,ov_SC02_021_jr_8015444C.o,ov_SC02_021_jr_80154C24.o,ov_SC02_021_jr_801588CC.o,tail10.data.o,ov_SC02_021_jr_80159C84.o,tail11.data.o,ov_SC02_021_jr_8015A3C8.o,tail12.data.o,ov_SC02_021_jr_8015AE2C.o,tail13.data.o,ov_SC02_021_jr_8015C32C.o,tail14.data.o,ov_SC02_021_jr_8016AB6C.o,tail15.data.o,ov_SC02_021_jr_80171B4C.o,ov_SC02_021_jr_801734BC.o,tail16.data.o,ov_SC02_021_jr_801789AC.o,ov_SC02_021_jr_80178D40.o,tail17.data.o,ov_SC02_021_jr_8017A4AC.o,tail18.data.o,ov_SC02_021_jr_8017AE2C.o,ov_SC02_021_jr_8017C294.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_021/ov_SC02_021.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_021/ov_SC02_021_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_021/ov_SC02_021_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_021/ov_SC02_021_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_021/ov_SC02_021_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_021/ov_SC02_021_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_021/ov_SC02_021_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_021/ov_SC02_021_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_021/ov_SC02_021_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1011,12 +1039,13 @@ ov_SC02_026_ELF := $(ov_SC02_026_OUT).elf ov_SC02_026_MAPFILE := $(ov_SC02_026_OUT).map ov_SC02_026_LD_SCRIPT := $(ov_SC02_026_OUT).ld ov_SC02_026_SPLAT_YAML := config/splat.ov_SC02_026.yaml -ov_SC02_026_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_026.o,ov_SC02_026_jr_8012ACE0.o,tail2.data.o,ov_SC02_026_jr_80135888.o,tail3.data.o,ov_SC02_026_jr_80135A4C.o,tail4.data.o,ov_SC02_026_jr_80135D20.o,tail5.data.o,ov_SC02_026_jr_801380E0.o,ov_SC02_026_o0c.o,tail6.data.o,ov_SC02_026_jr_8013F350.o,tail7.data.o,ov_SC02_026_jr_8013FFD8.o,tail8.data.o,ov_SC02_026_jr_80140608.o,tail9.data.o,ov_SC02_026_jr_8015444C.o,tail10.data.o,ov_SC02_026_jr_80154C24.o,ov_SC02_026_jr_801588CC.o,tail11.data.o,ov_SC02_026_jr_80159C84.o,tail12.data.o,ov_SC02_026_jr_8015A3C8.o,tail13.data.o,ov_SC02_026_jr_8015AE2C.o,tail14.data.o,ov_SC02_026_jr_8015C32C.o,tail15.data.o,ov_SC02_026_jr_8016AB6C.o,tail16.data.o,ov_SC02_026_jr_80171B4C.o,ov_SC02_026_jr_801734BC.o,tail17.data.o,ov_SC02_026_jr_801789AC.o,ov_SC02_026_jr_80178D40.o,tail18.data.o,ov_SC02_026_jr_8017A4AC.o,tail19.data.o,ov_SC02_026_jr_8017AE2C.o,ov_SC02_026_jr_8017C180.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_026_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_026.o,ov_SC02_026_jr_8012ACE0.o,tail2.data.o,ov_SC02_026_jr_80135888.o,tail3.data.o,ov_SC02_026_jr_80135A4C.o,tail4.data.o,ov_SC02_026_jr_80135D20.o,tail5.data.o,ov_SC02_026_jr_801380E0.o,ov_SC02_026_o0c.o,tail6.data.o,ov_SC02_026_jr_8013F350.o,tail7.data.o,ov_SC02_026_jr_8013FFD8.o,tail8.data.o,ov_SC02_026_jr_80140608.o,tail9.data.o,ov_SC02_026_jr_8015444C.o,ov_SC02_026_jr_80154C24.o,ov_SC02_026_jr_801588CC.o,tail10.data.o,ov_SC02_026_jr_80159C84.o,tail11.data.o,ov_SC02_026_jr_8015A3C8.o,tail12.data.o,ov_SC02_026_jr_8015AE2C.o,tail13.data.o,ov_SC02_026_jr_8015C32C.o,tail14.data.o,ov_SC02_026_jr_8016AB6C.o,tail15.data.o,ov_SC02_026_jr_80171B4C.o,ov_SC02_026_jr_801734BC.o,tail16.data.o,ov_SC02_026_jr_801789AC.o,ov_SC02_026_jr_80178D40.o,tail17.data.o,ov_SC02_026_jr_8017A4AC.o,tail18.data.o,ov_SC02_026_jr_8017AE2C.o,ov_SC02_026_jr_8017C180.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_026/ov_SC02_026.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_026/ov_SC02_026_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_026/ov_SC02_026_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_026/ov_SC02_026_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_026/ov_SC02_026_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_026/ov_SC02_026_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_026/ov_SC02_026_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_026/ov_SC02_026_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_026/ov_SC02_026_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1045,12 +1074,13 @@ ov_SC02_027_ELF := $(ov_SC02_027_OUT).elf ov_SC02_027_MAPFILE := $(ov_SC02_027_OUT).map ov_SC02_027_LD_SCRIPT := $(ov_SC02_027_OUT).ld ov_SC02_027_SPLAT_YAML := config/splat.ov_SC02_027.yaml -ov_SC02_027_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_027.o,ov_SC02_027_jr_8012ACE0.o,tail2.data.o,ov_SC02_027_jr_80135888.o,tail3.data.o,ov_SC02_027_jr_80135A4C.o,tail4.data.o,ov_SC02_027_jr_80135D20.o,tail5.data.o,ov_SC02_027_jr_801380E0.o,ov_SC02_027_o0c.o,tail6.data.o,ov_SC02_027_jr_8013F350.o,tail7.data.o,ov_SC02_027_jr_8013FFD8.o,tail8.data.o,ov_SC02_027_jr_80140608.o,tail9.data.o,ov_SC02_027_jr_8015444C.o,tail10.data.o,ov_SC02_027_jr_80154C24.o,ov_SC02_027_jr_801588CC.o,tail11.data.o,ov_SC02_027_jr_80159C84.o,tail12.data.o,ov_SC02_027_jr_8015A3C8.o,tail13.data.o,ov_SC02_027_jr_8015AE2C.o,tail14.data.o,ov_SC02_027_jr_8015C32C.o,tail15.data.o,ov_SC02_027_jr_8016AB6C.o,tail16.data.o,ov_SC02_027_jr_80171B4C.o,ov_SC02_027_jr_801734BC.o,tail17.data.o,ov_SC02_027_jr_801789AC.o,ov_SC02_027_jr_80178D40.o,tail18.data.o,ov_SC02_027_jr_8017A4AC.o,tail19.data.o,ov_SC02_027_jr_8017AE2C.o,ov_SC02_027_jr_8017D898.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_027_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_027.o,ov_SC02_027_jr_8012ACE0.o,tail2.data.o,ov_SC02_027_jr_80135888.o,tail3.data.o,ov_SC02_027_jr_80135A4C.o,tail4.data.o,ov_SC02_027_jr_80135D20.o,tail5.data.o,ov_SC02_027_jr_801380E0.o,ov_SC02_027_o0c.o,tail6.data.o,ov_SC02_027_jr_8013F350.o,tail7.data.o,ov_SC02_027_jr_8013FFD8.o,tail8.data.o,ov_SC02_027_jr_80140608.o,tail9.data.o,ov_SC02_027_jr_8015444C.o,ov_SC02_027_jr_80154C24.o,ov_SC02_027_jr_801588CC.o,tail10.data.o,ov_SC02_027_jr_80159C84.o,tail11.data.o,ov_SC02_027_jr_8015A3C8.o,tail12.data.o,ov_SC02_027_jr_8015AE2C.o,tail13.data.o,ov_SC02_027_jr_8015C32C.o,tail14.data.o,ov_SC02_027_jr_8016AB6C.o,tail15.data.o,ov_SC02_027_jr_80171B4C.o,ov_SC02_027_jr_801734BC.o,tail16.data.o,ov_SC02_027_jr_801789AC.o,ov_SC02_027_jr_80178D40.o,tail17.data.o,ov_SC02_027_jr_8017A4AC.o,tail18.data.o,ov_SC02_027_jr_8017AE2C.o,ov_SC02_027_jr_8017D898.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_027/ov_SC02_027.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_027/ov_SC02_027_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_027/ov_SC02_027_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_027/ov_SC02_027_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_027/ov_SC02_027_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_027/ov_SC02_027_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_027/ov_SC02_027_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_027/ov_SC02_027_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_027/ov_SC02_027_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1079,12 +1109,13 @@ ov_SC02_028_ELF := $(ov_SC02_028_OUT).elf ov_SC02_028_MAPFILE := $(ov_SC02_028_OUT).map ov_SC02_028_LD_SCRIPT := $(ov_SC02_028_OUT).ld ov_SC02_028_SPLAT_YAML := config/splat.ov_SC02_028.yaml -ov_SC02_028_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_028.o,ov_SC02_028_jr_8012ACE0.o,tail2.data.o,ov_SC02_028_jr_80135888.o,tail3.data.o,ov_SC02_028_jr_80135A4C.o,tail4.data.o,ov_SC02_028_jr_80135D20.o,tail5.data.o,ov_SC02_028_jr_801380E0.o,ov_SC02_028_o0c.o,tail6.data.o,ov_SC02_028_jr_8013F350.o,tail7.data.o,ov_SC02_028_jr_8013FFD8.o,tail8.data.o,ov_SC02_028_jr_80140608.o,tail9.data.o,ov_SC02_028_jr_8015444C.o,tail10.data.o,ov_SC02_028_jr_80154C24.o,ov_SC02_028_jr_801588CC.o,tail11.data.o,ov_SC02_028_jr_80159C84.o,tail12.data.o,ov_SC02_028_jr_8015A3C8.o,tail13.data.o,ov_SC02_028_jr_8015AE2C.o,tail14.data.o,ov_SC02_028_jr_8015C32C.o,tail15.data.o,ov_SC02_028_jr_8016AB6C.o,tail16.data.o,ov_SC02_028_jr_80171B4C.o,ov_SC02_028_jr_801734BC.o,tail17.data.o,ov_SC02_028_jr_801789AC.o,ov_SC02_028_jr_80178D40.o,tail18.data.o,ov_SC02_028_jr_8017A4AC.o,tail19.data.o,ov_SC02_028_jr_8017AE2C.o,ov_SC02_028_jr_8017D898.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_028_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_028.o,ov_SC02_028_jr_8012ACE0.o,tail2.data.o,ov_SC02_028_jr_80135888.o,tail3.data.o,ov_SC02_028_jr_80135A4C.o,tail4.data.o,ov_SC02_028_jr_80135D20.o,tail5.data.o,ov_SC02_028_jr_801380E0.o,ov_SC02_028_o0c.o,tail6.data.o,ov_SC02_028_jr_8013F350.o,tail7.data.o,ov_SC02_028_jr_8013FFD8.o,tail8.data.o,ov_SC02_028_jr_80140608.o,tail9.data.o,ov_SC02_028_jr_8015444C.o,ov_SC02_028_jr_80154C24.o,ov_SC02_028_jr_801588CC.o,tail10.data.o,ov_SC02_028_jr_80159C84.o,tail11.data.o,ov_SC02_028_jr_8015A3C8.o,tail12.data.o,ov_SC02_028_jr_8015AE2C.o,tail13.data.o,ov_SC02_028_jr_8015C32C.o,tail14.data.o,ov_SC02_028_jr_8016AB6C.o,tail15.data.o,ov_SC02_028_jr_80171B4C.o,ov_SC02_028_jr_801734BC.o,tail16.data.o,ov_SC02_028_jr_801789AC.o,ov_SC02_028_jr_80178D40.o,tail17.data.o,ov_SC02_028_jr_8017A4AC.o,tail18.data.o,ov_SC02_028_jr_8017AE2C.o,ov_SC02_028_jr_8017D898.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_028/ov_SC02_028.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_028/ov_SC02_028_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_028/ov_SC02_028_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_028/ov_SC02_028_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_028/ov_SC02_028_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_028/ov_SC02_028_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_028/ov_SC02_028_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_028/ov_SC02_028_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_028/ov_SC02_028_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1113,12 +1144,13 @@ ov_SC02_031_ELF := $(ov_SC02_031_OUT).elf ov_SC02_031_MAPFILE := $(ov_SC02_031_OUT).map ov_SC02_031_LD_SCRIPT := $(ov_SC02_031_OUT).ld ov_SC02_031_SPLAT_YAML := config/splat.ov_SC02_031.yaml -ov_SC02_031_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_031.o,ov_SC02_031_jr_8012ACE0.o,tail2.data.o,ov_SC02_031_jr_80135888.o,tail3.data.o,ov_SC02_031_jr_80135A4C.o,tail4.data.o,ov_SC02_031_jr_80135D20.o,tail5.data.o,ov_SC02_031_jr_801380E0.o,ov_SC02_031_o0c.o,tail6.data.o,ov_SC02_031_jr_8013F350.o,tail7.data.o,ov_SC02_031_jr_8013FFD8.o,tail8.data.o,ov_SC02_031_jr_80140608.o,tail9.data.o,ov_SC02_031_jr_8015444C.o,tail10.data.o,ov_SC02_031_jr_80154C24.o,ov_SC02_031_jr_801588CC.o,tail11.data.o,ov_SC02_031_jr_80159C84.o,tail12.data.o,ov_SC02_031_jr_8015A3C8.o,tail13.data.o,ov_SC02_031_jr_8015AE2C.o,tail14.data.o,ov_SC02_031_jr_8015C32C.o,tail15.data.o,ov_SC02_031_jr_8016AB6C.o,tail16.data.o,ov_SC02_031_jr_80171B4C.o,ov_SC02_031_jr_801734BC.o,tail17.data.o,ov_SC02_031_jr_801789AC.o,ov_SC02_031_jr_80178D40.o,tail18.data.o,ov_SC02_031_jr_8017A4AC.o,tail19.data.o,ov_SC02_031_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_031_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_031.o,ov_SC02_031_jr_8012ACE0.o,tail2.data.o,ov_SC02_031_jr_80135888.o,tail3.data.o,ov_SC02_031_jr_80135A4C.o,tail4.data.o,ov_SC02_031_jr_80135D20.o,tail5.data.o,ov_SC02_031_jr_801380E0.o,ov_SC02_031_o0c.o,tail6.data.o,ov_SC02_031_jr_8013F350.o,tail7.data.o,ov_SC02_031_jr_8013FFD8.o,tail8.data.o,ov_SC02_031_jr_80140608.o,tail9.data.o,ov_SC02_031_jr_8015444C.o,ov_SC02_031_jr_80154C24.o,ov_SC02_031_jr_801588CC.o,tail10.data.o,ov_SC02_031_jr_80159C84.o,tail11.data.o,ov_SC02_031_jr_8015A3C8.o,tail12.data.o,ov_SC02_031_jr_8015AE2C.o,tail13.data.o,ov_SC02_031_jr_8015C32C.o,tail14.data.o,ov_SC02_031_jr_8016AB6C.o,tail15.data.o,ov_SC02_031_jr_80171B4C.o,ov_SC02_031_jr_801734BC.o,tail16.data.o,ov_SC02_031_jr_801789AC.o,ov_SC02_031_jr_80178D40.o,tail17.data.o,ov_SC02_031_jr_8017A4AC.o,tail18.data.o,ov_SC02_031_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_031/ov_SC02_031.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_031/ov_SC02_031_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_031/ov_SC02_031_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_031/ov_SC02_031_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_031/ov_SC02_031_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_031/ov_SC02_031_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_031/ov_SC02_031_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_031/ov_SC02_031_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_031/ov_SC02_031_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1147,12 +1179,13 @@ ov_SC02_035_ELF := $(ov_SC02_035_OUT).elf ov_SC02_035_MAPFILE := $(ov_SC02_035_OUT).map ov_SC02_035_LD_SCRIPT := $(ov_SC02_035_OUT).ld ov_SC02_035_SPLAT_YAML := config/splat.ov_SC02_035.yaml -ov_SC02_035_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_035.o,ov_SC02_035_jr_8012ACE0.o,tail2.data.o,ov_SC02_035_jr_80135888.o,tail3.data.o,ov_SC02_035_jr_80135A4C.o,tail4.data.o,ov_SC02_035_jr_80135D20.o,tail5.data.o,ov_SC02_035_jr_801380E0.o,ov_SC02_035_o0c.o,tail6.data.o,ov_SC02_035_jr_8013F350.o,tail7.data.o,ov_SC02_035_jr_8013FFD8.o,tail8.data.o,ov_SC02_035_jr_80140608.o,tail9.data.o,ov_SC02_035_jr_8015444C.o,tail10.data.o,ov_SC02_035_jr_80154C24.o,ov_SC02_035_jr_801588CC.o,tail11.data.o,ov_SC02_035_jr_80159C84.o,tail12.data.o,ov_SC02_035_jr_8015A3C8.o,tail13.data.o,ov_SC02_035_jr_8015AE2C.o,tail14.data.o,ov_SC02_035_jr_8015C32C.o,tail15.data.o,ov_SC02_035_jr_8016AB6C.o,tail16.data.o,ov_SC02_035_jr_80171B4C.o,ov_SC02_035_jr_801734BC.o,tail17.data.o,ov_SC02_035_jr_801789AC.o,ov_SC02_035_jr_80178D40.o,tail18.data.o,ov_SC02_035_jr_8017A4AC.o,tail19.data.o,ov_SC02_035_jr_8017AE2C.o,ov_SC02_035_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_035_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_035.o,ov_SC02_035_jr_8012ACE0.o,tail2.data.o,ov_SC02_035_jr_80135888.o,tail3.data.o,ov_SC02_035_jr_80135A4C.o,tail4.data.o,ov_SC02_035_jr_80135D20.o,tail5.data.o,ov_SC02_035_jr_801380E0.o,ov_SC02_035_o0c.o,tail6.data.o,ov_SC02_035_jr_8013F350.o,tail7.data.o,ov_SC02_035_jr_8013FFD8.o,tail8.data.o,ov_SC02_035_jr_80140608.o,tail9.data.o,ov_SC02_035_jr_8015444C.o,ov_SC02_035_jr_80154C24.o,ov_SC02_035_jr_801588CC.o,tail10.data.o,ov_SC02_035_jr_80159C84.o,tail11.data.o,ov_SC02_035_jr_8015A3C8.o,tail12.data.o,ov_SC02_035_jr_8015AE2C.o,tail13.data.o,ov_SC02_035_jr_8015C32C.o,tail14.data.o,ov_SC02_035_jr_8016AB6C.o,tail15.data.o,ov_SC02_035_jr_80171B4C.o,ov_SC02_035_jr_801734BC.o,tail16.data.o,ov_SC02_035_jr_801789AC.o,ov_SC02_035_jr_80178D40.o,tail17.data.o,ov_SC02_035_jr_8017A4AC.o,tail18.data.o,ov_SC02_035_jr_8017AE2C.o,ov_SC02_035_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_035/ov_SC02_035.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_035/ov_SC02_035_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_035/ov_SC02_035_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_035/ov_SC02_035_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_035/ov_SC02_035_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_035/ov_SC02_035_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_035/ov_SC02_035_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_035/ov_SC02_035_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_035/ov_SC02_035_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1181,12 +1214,13 @@ ov_SC02_039_ELF := $(ov_SC02_039_OUT).elf ov_SC02_039_MAPFILE := $(ov_SC02_039_OUT).map ov_SC02_039_LD_SCRIPT := $(ov_SC02_039_OUT).ld ov_SC02_039_SPLAT_YAML := config/splat.ov_SC02_039.yaml -ov_SC02_039_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_039.o,ov_SC02_039_jr_8012ACE0.o,tail2.data.o,ov_SC02_039_jr_80135888.o,tail3.data.o,ov_SC02_039_jr_80135A4C.o,tail4.data.o,ov_SC02_039_jr_80135D20.o,tail5.data.o,ov_SC02_039_jr_801380E0.o,ov_SC02_039_o0c.o,tail6.data.o,ov_SC02_039_jr_8013F350.o,tail7.data.o,ov_SC02_039_jr_8013FFD8.o,tail8.data.o,ov_SC02_039_jr_80140608.o,tail9.data.o,ov_SC02_039_jr_8015444C.o,tail10.data.o,ov_SC02_039_jr_80154C24.o,ov_SC02_039_jr_801588CC.o,tail11.data.o,ov_SC02_039_jr_80159C84.o,tail12.data.o,ov_SC02_039_jr_8015A3C8.o,tail13.data.o,ov_SC02_039_jr_8015AE2C.o,tail14.data.o,ov_SC02_039_jr_8015C32C.o,tail15.data.o,ov_SC02_039_jr_8016AB6C.o,tail16.data.o,ov_SC02_039_jr_80171B4C.o,ov_SC02_039_jr_801734BC.o,tail17.data.o,ov_SC02_039_jr_801789AC.o,ov_SC02_039_jr_80178D40.o,tail18.data.o,ov_SC02_039_jr_8017A4AC.o,tail19.data.o,ov_SC02_039_jr_8017AE2C.o,ov_SC02_039_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_039_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_039.o,ov_SC02_039_jr_8012ACE0.o,tail2.data.o,ov_SC02_039_jr_80135888.o,tail3.data.o,ov_SC02_039_jr_80135A4C.o,tail4.data.o,ov_SC02_039_jr_80135D20.o,tail5.data.o,ov_SC02_039_jr_801380E0.o,ov_SC02_039_o0c.o,tail6.data.o,ov_SC02_039_jr_8013F350.o,tail7.data.o,ov_SC02_039_jr_8013FFD8.o,tail8.data.o,ov_SC02_039_jr_80140608.o,tail9.data.o,ov_SC02_039_jr_8015444C.o,ov_SC02_039_jr_80154C24.o,ov_SC02_039_jr_801588CC.o,tail10.data.o,ov_SC02_039_jr_80159C84.o,tail11.data.o,ov_SC02_039_jr_8015A3C8.o,tail12.data.o,ov_SC02_039_jr_8015AE2C.o,tail13.data.o,ov_SC02_039_jr_8015C32C.o,tail14.data.o,ov_SC02_039_jr_8016AB6C.o,tail15.data.o,ov_SC02_039_jr_80171B4C.o,ov_SC02_039_jr_801734BC.o,tail16.data.o,ov_SC02_039_jr_801789AC.o,ov_SC02_039_jr_80178D40.o,tail17.data.o,ov_SC02_039_jr_8017A4AC.o,tail18.data.o,ov_SC02_039_jr_8017AE2C.o,ov_SC02_039_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_039/ov_SC02_039.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_039/ov_SC02_039_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_039/ov_SC02_039_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_039/ov_SC02_039_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_039/ov_SC02_039_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_039/ov_SC02_039_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_039/ov_SC02_039_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_039/ov_SC02_039_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_039/ov_SC02_039_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1215,12 +1249,13 @@ ov_SC02_041_ELF := $(ov_SC02_041_OUT).elf ov_SC02_041_MAPFILE := $(ov_SC02_041_OUT).map ov_SC02_041_LD_SCRIPT := $(ov_SC02_041_OUT).ld ov_SC02_041_SPLAT_YAML := config/splat.ov_SC02_041.yaml -ov_SC02_041_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_041.o,ov_SC02_041_jr_8012ACE0.o,tail2.data.o,ov_SC02_041_jr_80135888.o,tail3.data.o,ov_SC02_041_jr_80135A4C.o,tail4.data.o,ov_SC02_041_jr_80135D20.o,tail5.data.o,ov_SC02_041_jr_801380E0.o,ov_SC02_041_o0c.o,tail6.data.o,ov_SC02_041_jr_8013F350.o,tail7.data.o,ov_SC02_041_jr_8013FFD8.o,tail8.data.o,ov_SC02_041_jr_80140608.o,tail9.data.o,ov_SC02_041_jr_8015444C.o,tail10.data.o,ov_SC02_041_jr_80154C24.o,ov_SC02_041_jr_801588CC.o,tail11.data.o,ov_SC02_041_jr_80159C84.o,tail12.data.o,ov_SC02_041_jr_8015A3C8.o,tail13.data.o,ov_SC02_041_jr_8015AE2C.o,tail14.data.o,ov_SC02_041_jr_8015C32C.o,tail15.data.o,ov_SC02_041_jr_8016AB6C.o,tail16.data.o,ov_SC02_041_jr_80171B4C.o,ov_SC02_041_jr_801734BC.o,tail17.data.o,ov_SC02_041_jr_801789AC.o,ov_SC02_041_jr_80178D40.o,tail18.data.o,ov_SC02_041_jr_8017A4AC.o,tail19.data.o,ov_SC02_041_jr_8017AE2C.o,ov_SC02_041_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC02_041_JTBL_INTERLEAVE := --order tail.data.o,ov_SC02_041.o,ov_SC02_041_jr_8012ACE0.o,tail2.data.o,ov_SC02_041_jr_80135888.o,tail3.data.o,ov_SC02_041_jr_80135A4C.o,tail4.data.o,ov_SC02_041_jr_80135D20.o,tail5.data.o,ov_SC02_041_jr_801380E0.o,ov_SC02_041_o0c.o,tail6.data.o,ov_SC02_041_jr_8013F350.o,tail7.data.o,ov_SC02_041_jr_8013FFD8.o,tail8.data.o,ov_SC02_041_jr_80140608.o,tail9.data.o,ov_SC02_041_jr_8015444C.o,ov_SC02_041_jr_80154C24.o,ov_SC02_041_jr_801588CC.o,tail10.data.o,ov_SC02_041_jr_80159C84.o,tail11.data.o,ov_SC02_041_jr_8015A3C8.o,tail12.data.o,ov_SC02_041_jr_8015AE2C.o,tail13.data.o,ov_SC02_041_jr_8015C32C.o,tail14.data.o,ov_SC02_041_jr_8016AB6C.o,tail15.data.o,ov_SC02_041_jr_80171B4C.o,ov_SC02_041_jr_801734BC.o,tail16.data.o,ov_SC02_041_jr_801789AC.o,ov_SC02_041_jr_80178D40.o,tail17.data.o,ov_SC02_041_jr_8017A4AC.o,tail18.data.o,ov_SC02_041_jr_8017AE2C.o,ov_SC02_041_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC02_041/ov_SC02_041.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC02_041/ov_SC02_041_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC02_041/ov_SC02_041_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC02_041/ov_SC02_041_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_041/ov_SC02_041_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC02_041/ov_SC02_041_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC02_041/ov_SC02_041_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC02_041/ov_SC02_041_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC02_041/ov_SC02_041_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1249,12 +1284,13 @@ ov_SC03_003_ELF := $(ov_SC03_003_OUT).elf ov_SC03_003_MAPFILE := $(ov_SC03_003_OUT).map ov_SC03_003_LD_SCRIPT := $(ov_SC03_003_OUT).ld ov_SC03_003_SPLAT_YAML := config/splat.ov_SC03_003.yaml -ov_SC03_003_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_003.o,ov_SC03_003_jr_8012ACE0.o,tail2.data.o,ov_SC03_003_jr_80135888.o,tail3.data.o,ov_SC03_003_jr_80135A4C.o,tail4.data.o,ov_SC03_003_jr_80135D20.o,tail5.data.o,ov_SC03_003_jr_801380E0.o,ov_SC03_003_o0c.o,tail6.data.o,ov_SC03_003_jr_8013F350.o,tail7.data.o,ov_SC03_003_jr_8013FFD8.o,tail8.data.o,ov_SC03_003_jr_80140608.o,tail9.data.o,ov_SC03_003_jr_8015444C.o,tail10.data.o,ov_SC03_003_jr_80154C24.o,ov_SC03_003_jr_801588CC.o,tail11.data.o,ov_SC03_003_jr_80159C84.o,tail12.data.o,ov_SC03_003_jr_8015A3C8.o,tail13.data.o,ov_SC03_003_jr_8015AE2C.o,tail14.data.o,ov_SC03_003_jr_8015C32C.o,tail15.data.o,ov_SC03_003_jr_8016AB6C.o,tail16.data.o,ov_SC03_003_jr_80171B4C.o,ov_SC03_003_jr_801734BC.o,tail17.data.o,ov_SC03_003_jr_801789AC.o,ov_SC03_003_jr_80178D40.o,tail18.data.o,ov_SC03_003_jr_8017A4AC.o,tail19.data.o,ov_SC03_003_jr_8017AE2C.o,tail20.data.o,ov_SC03_003_jr_8017D5C0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_003_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_003.o,ov_SC03_003_jr_8012ACE0.o,tail2.data.o,ov_SC03_003_jr_80135888.o,tail3.data.o,ov_SC03_003_jr_80135A4C.o,tail4.data.o,ov_SC03_003_jr_80135D20.o,tail5.data.o,ov_SC03_003_jr_801380E0.o,ov_SC03_003_o0c.o,tail6.data.o,ov_SC03_003_jr_8013F350.o,tail7.data.o,ov_SC03_003_jr_8013FFD8.o,tail8.data.o,ov_SC03_003_jr_80140608.o,tail9.data.o,ov_SC03_003_jr_8015444C.o,ov_SC03_003_jr_80154C24.o,ov_SC03_003_jr_801588CC.o,tail10.data.o,ov_SC03_003_jr_80159C84.o,tail11.data.o,ov_SC03_003_jr_8015A3C8.o,tail12.data.o,ov_SC03_003_jr_8015AE2C.o,tail13.data.o,ov_SC03_003_jr_8015C32C.o,tail14.data.o,ov_SC03_003_jr_8016AB6C.o,tail15.data.o,ov_SC03_003_jr_80171B4C.o,ov_SC03_003_jr_801734BC.o,tail16.data.o,ov_SC03_003_jr_801789AC.o,ov_SC03_003_jr_80178D40.o,tail17.data.o,ov_SC03_003_jr_8017A4AC.o,tail18.data.o,ov_SC03_003_jr_8017AE2C.o,tail19.data.o,ov_SC03_003_jr_8017D5C0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_003/ov_SC03_003.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_003/ov_SC03_003_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_003/ov_SC03_003_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_003/ov_SC03_003_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_003/ov_SC03_003_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_003/ov_SC03_003_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_003/ov_SC03_003_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_003/ov_SC03_003_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_003/ov_SC03_003_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1283,12 +1319,13 @@ ov_SC03_007_ELF := $(ov_SC03_007_OUT).elf ov_SC03_007_MAPFILE := $(ov_SC03_007_OUT).map ov_SC03_007_LD_SCRIPT := $(ov_SC03_007_OUT).ld ov_SC03_007_SPLAT_YAML := config/splat.ov_SC03_007.yaml -ov_SC03_007_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_007.o,ov_SC03_007_jr_8012ACE0.o,tail2.data.o,ov_SC03_007_jr_80135888.o,tail3.data.o,ov_SC03_007_jr_80135A4C.o,tail4.data.o,ov_SC03_007_jr_80135D20.o,tail5.data.o,ov_SC03_007_jr_801380E0.o,ov_SC03_007_o0c.o,tail6.data.o,ov_SC03_007_jr_8013F350.o,tail7.data.o,ov_SC03_007_jr_8013FFD8.o,tail8.data.o,ov_SC03_007_jr_80140608.o,tail9.data.o,ov_SC03_007_jr_8015444C.o,tail10.data.o,ov_SC03_007_jr_80154C24.o,ov_SC03_007_jr_801588CC.o,tail11.data.o,ov_SC03_007_jr_80159C84.o,tail12.data.o,ov_SC03_007_jr_8015A3C8.o,tail13.data.o,ov_SC03_007_jr_8015AE2C.o,tail14.data.o,ov_SC03_007_jr_8015C32C.o,tail15.data.o,ov_SC03_007_jr_8016AB6C.o,tail16.data.o,ov_SC03_007_jr_80171B4C.o,ov_SC03_007_jr_801734BC.o,tail17.data.o,ov_SC03_007_jr_801789AC.o,ov_SC03_007_jr_80178D40.o,tail18.data.o,ov_SC03_007_jr_8017A4AC.o,tail19.data.o,ov_SC03_007_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_007_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_007.o,ov_SC03_007_jr_8012ACE0.o,tail2.data.o,ov_SC03_007_jr_80135888.o,tail3.data.o,ov_SC03_007_jr_80135A4C.o,tail4.data.o,ov_SC03_007_jr_80135D20.o,tail5.data.o,ov_SC03_007_jr_801380E0.o,ov_SC03_007_o0c.o,tail6.data.o,ov_SC03_007_jr_8013F350.o,tail7.data.o,ov_SC03_007_jr_8013FFD8.o,tail8.data.o,ov_SC03_007_jr_80140608.o,tail9.data.o,ov_SC03_007_jr_8015444C.o,ov_SC03_007_jr_80154C24.o,ov_SC03_007_jr_801588CC.o,tail10.data.o,ov_SC03_007_jr_80159C84.o,tail11.data.o,ov_SC03_007_jr_8015A3C8.o,tail12.data.o,ov_SC03_007_jr_8015AE2C.o,tail13.data.o,ov_SC03_007_jr_8015C32C.o,tail14.data.o,ov_SC03_007_jr_8016AB6C.o,tail15.data.o,ov_SC03_007_jr_80171B4C.o,ov_SC03_007_jr_801734BC.o,tail16.data.o,ov_SC03_007_jr_801789AC.o,ov_SC03_007_jr_80178D40.o,tail17.data.o,ov_SC03_007_jr_8017A4AC.o,tail18.data.o,ov_SC03_007_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_007/ov_SC03_007.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_007/ov_SC03_007_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_007/ov_SC03_007_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_007/ov_SC03_007_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_007/ov_SC03_007_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_007/ov_SC03_007_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_007/ov_SC03_007_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_007/ov_SC03_007_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_007/ov_SC03_007_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1317,12 +1354,13 @@ ov_SC03_010_ELF := $(ov_SC03_010_OUT).elf ov_SC03_010_MAPFILE := $(ov_SC03_010_OUT).map ov_SC03_010_LD_SCRIPT := $(ov_SC03_010_OUT).ld ov_SC03_010_SPLAT_YAML := config/splat.ov_SC03_010.yaml -ov_SC03_010_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_010.o,ov_SC03_010_jr_8012ACE0.o,tail2.data.o,ov_SC03_010_jr_80135888.o,tail3.data.o,ov_SC03_010_jr_80135A4C.o,tail4.data.o,ov_SC03_010_jr_80135D20.o,tail5.data.o,ov_SC03_010_jr_801380E0.o,ov_SC03_010_o0c.o,tail6.data.o,ov_SC03_010_jr_8013F350.o,tail7.data.o,ov_SC03_010_jr_8013FFD8.o,tail8.data.o,ov_SC03_010_jr_80140608.o,tail9.data.o,ov_SC03_010_jr_8015444C.o,tail10.data.o,ov_SC03_010_jr_80154C24.o,ov_SC03_010_jr_801588CC.o,tail11.data.o,ov_SC03_010_jr_80159C84.o,tail12.data.o,ov_SC03_010_jr_8015A3C8.o,tail13.data.o,ov_SC03_010_jr_8015AE2C.o,tail14.data.o,ov_SC03_010_jr_8015C32C.o,tail15.data.o,ov_SC03_010_jr_8016AB6C.o,tail16.data.o,ov_SC03_010_jr_80171B4C.o,ov_SC03_010_jr_801734BC.o,tail17.data.o,ov_SC03_010_jr_801789AC.o,ov_SC03_010_jr_80178D40.o,tail18.data.o,ov_SC03_010_jr_8017A4AC.o,tail19.data.o,ov_SC03_010_jr_8017AE2C.o,ov_SC03_010_jr_8017C730.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_010_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_010.o,ov_SC03_010_jr_8012ACE0.o,tail2.data.o,ov_SC03_010_jr_80135888.o,tail3.data.o,ov_SC03_010_jr_80135A4C.o,tail4.data.o,ov_SC03_010_jr_80135D20.o,tail5.data.o,ov_SC03_010_jr_801380E0.o,ov_SC03_010_o0c.o,tail6.data.o,ov_SC03_010_jr_8013F350.o,tail7.data.o,ov_SC03_010_jr_8013FFD8.o,tail8.data.o,ov_SC03_010_jr_80140608.o,tail9.data.o,ov_SC03_010_jr_8015444C.o,ov_SC03_010_jr_80154C24.o,ov_SC03_010_jr_801588CC.o,tail10.data.o,ov_SC03_010_jr_80159C84.o,tail11.data.o,ov_SC03_010_jr_8015A3C8.o,tail12.data.o,ov_SC03_010_jr_8015AE2C.o,tail13.data.o,ov_SC03_010_jr_8015C32C.o,tail14.data.o,ov_SC03_010_jr_8016AB6C.o,tail15.data.o,ov_SC03_010_jr_80171B4C.o,ov_SC03_010_jr_801734BC.o,tail16.data.o,ov_SC03_010_jr_801789AC.o,ov_SC03_010_jr_80178D40.o,tail17.data.o,ov_SC03_010_jr_8017A4AC.o,tail18.data.o,ov_SC03_010_jr_8017AE2C.o,ov_SC03_010_jr_8017C730.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_010/ov_SC03_010.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_010/ov_SC03_010_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_010/ov_SC03_010_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_010/ov_SC03_010_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_010/ov_SC03_010_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_010/ov_SC03_010_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_010/ov_SC03_010_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_010/ov_SC03_010_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_010/ov_SC03_010_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1351,12 +1389,13 @@ ov_SC03_011_ELF := $(ov_SC03_011_OUT).elf ov_SC03_011_MAPFILE := $(ov_SC03_011_OUT).map ov_SC03_011_LD_SCRIPT := $(ov_SC03_011_OUT).ld ov_SC03_011_SPLAT_YAML := config/splat.ov_SC03_011.yaml -ov_SC03_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_011.o,ov_SC03_011_jr_8012ACE0.o,tail2.data.o,ov_SC03_011_jr_80135888.o,tail3.data.o,ov_SC03_011_jr_80135A4C.o,tail4.data.o,ov_SC03_011_jr_80135D20.o,tail5.data.o,ov_SC03_011_jr_801380E0.o,ov_SC03_011_o0c.o,tail6.data.o,ov_SC03_011_jr_8013F350.o,tail7.data.o,ov_SC03_011_jr_8014032C.o,tail8.data.o,ov_SC03_011_jr_80140608.o,tail9.data.o,ov_SC03_011_jr_8015444C.o,tail10.data.o,ov_SC03_011_jr_80154C24.o,ov_SC03_011_jr_801588CC.o,tail11.data.o,ov_SC03_011_jr_80159C84.o,tail12.data.o,ov_SC03_011_jr_8015A3C8.o,tail13.data.o,ov_SC03_011_jr_8015AE2C.o,tail14.data.o,ov_SC03_011_jr_8015C32C.o,tail15.data.o,ov_SC03_011_jr_8016AB6C.o,tail16.data.o,ov_SC03_011_jr_80171B4C.o,ov_SC03_011_jr_801734BC.o,tail17.data.o,ov_SC03_011_jr_801789AC.o,ov_SC03_011_jr_80178D40.o,tail18.data.o,ov_SC03_011_jr_8017A4AC.o,tail19.data.o,ov_SC03_011_jr_8017AE2C.o,ov_SC03_011_jr_8017C730.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_011.o,ov_SC03_011_jr_8012ACE0.o,tail2.data.o,ov_SC03_011_jr_80135888.o,tail3.data.o,ov_SC03_011_jr_80135A4C.o,tail4.data.o,ov_SC03_011_jr_80135D20.o,tail5.data.o,ov_SC03_011_jr_801380E0.o,ov_SC03_011_o0c.o,tail6.data.o,ov_SC03_011_jr_8013F350.o,tail7.data.o,ov_SC03_011_jr_8014032C.o,tail8.data.o,ov_SC03_011_jr_80140608.o,tail9.data.o,ov_SC03_011_jr_8015444C.o,ov_SC03_011_jr_80154C24.o,ov_SC03_011_jr_801588CC.o,tail10.data.o,ov_SC03_011_jr_80159C84.o,tail11.data.o,ov_SC03_011_jr_8015A3C8.o,tail12.data.o,ov_SC03_011_jr_8015AE2C.o,tail13.data.o,ov_SC03_011_jr_8015C32C.o,tail14.data.o,ov_SC03_011_jr_8016AB6C.o,tail15.data.o,ov_SC03_011_jr_80171B4C.o,ov_SC03_011_jr_801734BC.o,tail16.data.o,ov_SC03_011_jr_801789AC.o,ov_SC03_011_jr_80178D40.o,tail17.data.o,ov_SC03_011_jr_8017A4AC.o,tail18.data.o,ov_SC03_011_jr_8017AE2C.o,ov_SC03_011_jr_8017C730.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_011/ov_SC03_011.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_011/ov_SC03_011_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_011/ov_SC03_011_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_011/ov_SC03_011_jr_8013F350.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 build/src/ov_SC03_011/ov_SC03_011_jr_8014032C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC03_011/ov_SC03_011_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_011/ov_SC03_011_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_011/ov_SC03_011_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_011/ov_SC03_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1385,12 +1424,13 @@ ov_SC03_012_ELF := $(ov_SC03_012_OUT).elf ov_SC03_012_MAPFILE := $(ov_SC03_012_OUT).map ov_SC03_012_LD_SCRIPT := $(ov_SC03_012_OUT).ld ov_SC03_012_SPLAT_YAML := config/splat.ov_SC03_012.yaml -ov_SC03_012_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_012.o,ov_SC03_012_jr_8012ACE0.o,tail2.data.o,ov_SC03_012_jr_80135888.o,tail3.data.o,ov_SC03_012_jr_80135A4C.o,tail4.data.o,ov_SC03_012_jr_80135D20.o,tail5.data.o,ov_SC03_012_jr_801380E0.o,ov_SC03_012_o0c.o,tail6.data.o,ov_SC03_012_jr_8013F350.o,tail7.data.o,ov_SC03_012_jr_8013FFD8.o,tail8.data.o,ov_SC03_012_jr_80140608.o,tail9.data.o,ov_SC03_012_jr_8015444C.o,tail10.data.o,ov_SC03_012_jr_80154C24.o,ov_SC03_012_jr_801588CC.o,tail11.data.o,ov_SC03_012_jr_80159C84.o,tail12.data.o,ov_SC03_012_jr_8015A3C8.o,tail13.data.o,ov_SC03_012_jr_8015AE2C.o,tail14.data.o,ov_SC03_012_jr_8015C32C.o,tail15.data.o,ov_SC03_012_jr_8016AB6C.o,tail16.data.o,ov_SC03_012_jr_80171B4C.o,ov_SC03_012_jr_801734BC.o,tail17.data.o,ov_SC03_012_jr_801789AC.o,ov_SC03_012_jr_80178D40.o,tail18.data.o,ov_SC03_012_jr_8017A4AC.o,tail19.data.o,ov_SC03_012_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_012_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_012.o,ov_SC03_012_jr_8012ACE0.o,tail2.data.o,ov_SC03_012_jr_80135888.o,tail3.data.o,ov_SC03_012_jr_80135A4C.o,tail4.data.o,ov_SC03_012_jr_80135D20.o,tail5.data.o,ov_SC03_012_jr_801380E0.o,ov_SC03_012_o0c.o,tail6.data.o,ov_SC03_012_jr_8013F350.o,tail7.data.o,ov_SC03_012_jr_8013FFD8.o,tail8.data.o,ov_SC03_012_jr_80140608.o,tail9.data.o,ov_SC03_012_jr_8015444C.o,ov_SC03_012_jr_80154C24.o,ov_SC03_012_jr_801588CC.o,tail10.data.o,ov_SC03_012_jr_80159C84.o,tail11.data.o,ov_SC03_012_jr_8015A3C8.o,tail12.data.o,ov_SC03_012_jr_8015AE2C.o,tail13.data.o,ov_SC03_012_jr_8015C32C.o,tail14.data.o,ov_SC03_012_jr_8016AB6C.o,tail15.data.o,ov_SC03_012_jr_80171B4C.o,ov_SC03_012_jr_801734BC.o,tail16.data.o,ov_SC03_012_jr_801789AC.o,ov_SC03_012_jr_80178D40.o,tail17.data.o,ov_SC03_012_jr_8017A4AC.o,tail18.data.o,ov_SC03_012_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_012/ov_SC03_012.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_012/ov_SC03_012_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_012/ov_SC03_012_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_012/ov_SC03_012_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_012/ov_SC03_012_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_012/ov_SC03_012_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_012/ov_SC03_012_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_012/ov_SC03_012_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_012/ov_SC03_012_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1419,12 +1459,13 @@ ov_SC03_013_ELF := $(ov_SC03_013_OUT).elf ov_SC03_013_MAPFILE := $(ov_SC03_013_OUT).map ov_SC03_013_LD_SCRIPT := $(ov_SC03_013_OUT).ld ov_SC03_013_SPLAT_YAML := config/splat.ov_SC03_013.yaml -ov_SC03_013_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_013.o,ov_SC03_013_jr_8012ACE0.o,tail2.data.o,ov_SC03_013_jr_80135888.o,tail3.data.o,ov_SC03_013_jr_80135A4C.o,tail4.data.o,ov_SC03_013_jr_80135D20.o,tail5.data.o,ov_SC03_013_jr_801380E0.o,ov_SC03_013_o0c.o,tail6.data.o,ov_SC03_013_jr_8013F350.o,tail7.data.o,ov_SC03_013_jr_8013FFD8.o,tail8.data.o,ov_SC03_013_jr_80140608.o,tail9.data.o,ov_SC03_013_jr_8015444C.o,tail10.data.o,ov_SC03_013_jr_80154C24.o,ov_SC03_013_jr_801588CC.o,tail11.data.o,ov_SC03_013_jr_80159C84.o,tail12.data.o,ov_SC03_013_jr_8015A3C8.o,tail13.data.o,ov_SC03_013_jr_8015AE2C.o,tail14.data.o,ov_SC03_013_jr_8015C32C.o,tail15.data.o,ov_SC03_013_jr_8016AB6C.o,tail16.data.o,ov_SC03_013_jr_80171B4C.o,ov_SC03_013_jr_801734BC.o,tail17.data.o,ov_SC03_013_jr_801789AC.o,ov_SC03_013_jr_80178D40.o,tail18.data.o,ov_SC03_013_jr_8017A4AC.o,tail19.data.o,ov_SC03_013_jr_8017AE2C.o,ov_SC03_013_jr_8017C730.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_013_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_013.o,ov_SC03_013_jr_8012ACE0.o,tail2.data.o,ov_SC03_013_jr_80135888.o,tail3.data.o,ov_SC03_013_jr_80135A4C.o,tail4.data.o,ov_SC03_013_jr_80135D20.o,tail5.data.o,ov_SC03_013_jr_801380E0.o,ov_SC03_013_o0c.o,tail6.data.o,ov_SC03_013_jr_8013F350.o,tail7.data.o,ov_SC03_013_jr_8013FFD8.o,tail8.data.o,ov_SC03_013_jr_80140608.o,tail9.data.o,ov_SC03_013_jr_8015444C.o,ov_SC03_013_jr_80154C24.o,ov_SC03_013_jr_801588CC.o,tail10.data.o,ov_SC03_013_jr_80159C84.o,tail11.data.o,ov_SC03_013_jr_8015A3C8.o,tail12.data.o,ov_SC03_013_jr_8015AE2C.o,tail13.data.o,ov_SC03_013_jr_8015C32C.o,tail14.data.o,ov_SC03_013_jr_8016AB6C.o,tail15.data.o,ov_SC03_013_jr_80171B4C.o,ov_SC03_013_jr_801734BC.o,tail16.data.o,ov_SC03_013_jr_801789AC.o,ov_SC03_013_jr_80178D40.o,tail17.data.o,ov_SC03_013_jr_8017A4AC.o,tail18.data.o,ov_SC03_013_jr_8017AE2C.o,ov_SC03_013_jr_8017C730.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_013/ov_SC03_013.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_013/ov_SC03_013_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_013/ov_SC03_013_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_013/ov_SC03_013_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_013/ov_SC03_013_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_013/ov_SC03_013_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_013/ov_SC03_013_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_013/ov_SC03_013_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_013/ov_SC03_013_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1453,12 +1494,13 @@ ov_SC03_014_ELF := $(ov_SC03_014_OUT).elf ov_SC03_014_MAPFILE := $(ov_SC03_014_OUT).map ov_SC03_014_LD_SCRIPT := $(ov_SC03_014_OUT).ld ov_SC03_014_SPLAT_YAML := config/splat.ov_SC03_014.yaml -ov_SC03_014_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_014.o,ov_SC03_014_jr_8012ACE0.o,tail2.data.o,ov_SC03_014_jr_80135888.o,tail3.data.o,ov_SC03_014_jr_80135A4C.o,tail4.data.o,ov_SC03_014_jr_80135D20.o,tail5.data.o,ov_SC03_014_jr_801380E0.o,ov_SC03_014_o0e.o,tail6.data.o,ov_SC03_014_jr_8013F350.o,tail7.data.o,ov_SC03_014_jr_8013FFD8.o,tail8.data.o,ov_SC03_014_jr_80140608.o,tail9.data.o,ov_SC03_014_jr_8015444C.o,tail10.data.o,ov_SC03_014_jr_80154C24.o,ov_SC03_014_jr_801588CC.o,tail11.data.o,ov_SC03_014_jr_80159C84.o,tail12.data.o,ov_SC03_014_jr_8015A3C8.o,tail13.data.o,ov_SC03_014_jr_8015AE2C.o,tail14.data.o,ov_SC03_014_jr_8015C32C.o,tail15.data.o,ov_SC03_014_jr_8016AB6C.o,tail16.data.o,ov_SC03_014_jr_80171B4C.o,ov_SC03_014_jr_801734BC.o,tail17.data.o,ov_SC03_014_jr_801789AC.o,ov_SC03_014_jr_80178D40.o,tail18.data.o,ov_SC03_014_jr_8017A4AC.o,tail19.data.o,ov_SC03_014_jr_8017AE2C.o,tail20.data.o,ov_SC03_014_jr_8017EB7C.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_014_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_014.o,ov_SC03_014_jr_8012ACE0.o,tail2.data.o,ov_SC03_014_jr_80135888.o,tail3.data.o,ov_SC03_014_jr_80135A4C.o,tail4.data.o,ov_SC03_014_jr_80135D20.o,tail5.data.o,ov_SC03_014_jr_801380E0.o,ov_SC03_014_o0e.o,tail6.data.o,ov_SC03_014_jr_8013F350.o,tail7.data.o,ov_SC03_014_jr_8013FFD8.o,tail8.data.o,ov_SC03_014_jr_80140608.o,tail9.data.o,ov_SC03_014_jr_8015444C.o,ov_SC03_014_jr_80154C24.o,ov_SC03_014_jr_801588CC.o,tail10.data.o,ov_SC03_014_jr_80159C84.o,tail11.data.o,ov_SC03_014_jr_8015A3C8.o,tail12.data.o,ov_SC03_014_jr_8015AE2C.o,tail13.data.o,ov_SC03_014_jr_8015C32C.o,tail14.data.o,ov_SC03_014_jr_8016AB6C.o,tail15.data.o,ov_SC03_014_jr_80171B4C.o,ov_SC03_014_jr_801734BC.o,tail16.data.o,ov_SC03_014_jr_801789AC.o,ov_SC03_014_jr_80178D40.o,tail17.data.o,ov_SC03_014_jr_8017A4AC.o,tail18.data.o,ov_SC03_014_jr_8017AE2C.o,tail19.data.o,ov_SC03_014_jr_8017EB7C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_014/ov_SC03_014.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_014/ov_SC03_014_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_014/ov_SC03_014_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_014/ov_SC03_014_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_014/ov_SC03_014_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_014/ov_SC03_014_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_014/ov_SC03_014_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_014/ov_SC03_014_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_014/ov_SC03_014_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1487,12 +1529,13 @@ ov_SC03_015_ELF := $(ov_SC03_015_OUT).elf ov_SC03_015_MAPFILE := $(ov_SC03_015_OUT).map ov_SC03_015_LD_SCRIPT := $(ov_SC03_015_OUT).ld ov_SC03_015_SPLAT_YAML := config/splat.ov_SC03_015.yaml -ov_SC03_015_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_015.o,ov_SC03_015_jr_8012ACE0.o,tail2.data.o,ov_SC03_015_jr_80135888.o,tail3.data.o,ov_SC03_015_jr_80135A4C.o,tail4.data.o,ov_SC03_015_jr_80135D20.o,tail5.data.o,ov_SC03_015_jr_801380E0.o,ov_SC03_015_o0e.o,tail6.data.o,ov_SC03_015_jr_8013F350.o,tail7.data.o,ov_SC03_015_jr_8013FFD8.o,tail8.data.o,ov_SC03_015_jr_80140608.o,tail9.data.o,ov_SC03_015_jr_8015444C.o,tail10.data.o,ov_SC03_015_jr_80154C24.o,ov_SC03_015_jr_801588CC.o,tail11.data.o,ov_SC03_015_jr_80159C84.o,tail12.data.o,ov_SC03_015_jr_8015A3C8.o,tail13.data.o,ov_SC03_015_jr_8015AE2C.o,tail14.data.o,ov_SC03_015_jr_8015C32C.o,tail15.data.o,ov_SC03_015_jr_8016AB6C.o,tail16.data.o,ov_SC03_015_jr_80171B4C.o,ov_SC03_015_jr_801734BC.o,tail17.data.o,ov_SC03_015_jr_801789AC.o,ov_SC03_015_jr_80178D40.o,tail18.data.o,ov_SC03_015_jr_8017A4AC.o,tail19.data.o,ov_SC03_015_jr_8017AE2C.o,tail20.data.o,ov_SC03_015_jr_8017EB7C.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_015_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_015.o,ov_SC03_015_jr_8012ACE0.o,tail2.data.o,ov_SC03_015_jr_80135888.o,tail3.data.o,ov_SC03_015_jr_80135A4C.o,tail4.data.o,ov_SC03_015_jr_80135D20.o,tail5.data.o,ov_SC03_015_jr_801380E0.o,ov_SC03_015_o0e.o,tail6.data.o,ov_SC03_015_jr_8013F350.o,tail7.data.o,ov_SC03_015_jr_8013FFD8.o,tail8.data.o,ov_SC03_015_jr_80140608.o,tail9.data.o,ov_SC03_015_jr_8015444C.o,ov_SC03_015_jr_80154C24.o,ov_SC03_015_jr_801588CC.o,tail10.data.o,ov_SC03_015_jr_80159C84.o,tail11.data.o,ov_SC03_015_jr_8015A3C8.o,tail12.data.o,ov_SC03_015_jr_8015AE2C.o,tail13.data.o,ov_SC03_015_jr_8015C32C.o,tail14.data.o,ov_SC03_015_jr_8016AB6C.o,tail15.data.o,ov_SC03_015_jr_80171B4C.o,ov_SC03_015_jr_801734BC.o,tail16.data.o,ov_SC03_015_jr_801789AC.o,ov_SC03_015_jr_80178D40.o,tail17.data.o,ov_SC03_015_jr_8017A4AC.o,tail18.data.o,ov_SC03_015_jr_8017AE2C.o,tail19.data.o,ov_SC03_015_jr_8017EB7C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_015/ov_SC03_015.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_015/ov_SC03_015_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_015/ov_SC03_015_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_015/ov_SC03_015_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_015/ov_SC03_015_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_015/ov_SC03_015_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_015/ov_SC03_015_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_015/ov_SC03_015_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_015/ov_SC03_015_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1521,12 +1564,13 @@ ov_SC03_023_ELF := $(ov_SC03_023_OUT).elf ov_SC03_023_MAPFILE := $(ov_SC03_023_OUT).map ov_SC03_023_LD_SCRIPT := $(ov_SC03_023_OUT).ld ov_SC03_023_SPLAT_YAML := config/splat.ov_SC03_023.yaml -ov_SC03_023_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_023.o,ov_SC03_023_jr_8012ACE0.o,tail2.data.o,ov_SC03_023_jr_80135888.o,tail3.data.o,ov_SC03_023_jr_80135A4C.o,tail4.data.o,ov_SC03_023_jr_80135D20.o,tail5.data.o,ov_SC03_023_jr_801380E0.o,ov_SC03_023_o0c.o,tail6.data.o,ov_SC03_023_jr_8013F350.o,tail7.data.o,ov_SC03_023_jr_8013FFD8.o,tail8.data.o,ov_SC03_023_jr_80140608.o,tail9.data.o,ov_SC03_023_jr_8015444C.o,tail10.data.o,ov_SC03_023_jr_80154C24.o,ov_SC03_023_jr_801588CC.o,tail11.data.o,ov_SC03_023_jr_80159C84.o,tail12.data.o,ov_SC03_023_jr_8015A3C8.o,tail13.data.o,ov_SC03_023_jr_8015AE2C.o,tail14.data.o,ov_SC03_023_jr_8015C32C.o,tail15.data.o,ov_SC03_023_jr_8016AB6C.o,tail16.data.o,ov_SC03_023_jr_80171B4C.o,ov_SC03_023_jr_801734BC.o,tail17.data.o,ov_SC03_023_jr_801789AC.o,ov_SC03_023_jr_80178D40.o,tail18.data.o,ov_SC03_023_jr_8017A4AC.o,tail19.data.o,ov_SC03_023_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_023_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_023.o,ov_SC03_023_jr_8012ACE0.o,tail2.data.o,ov_SC03_023_jr_80135888.o,tail3.data.o,ov_SC03_023_jr_80135A4C.o,tail4.data.o,ov_SC03_023_jr_80135D20.o,tail5.data.o,ov_SC03_023_jr_801380E0.o,ov_SC03_023_o0c.o,tail6.data.o,ov_SC03_023_jr_8013F350.o,tail7.data.o,ov_SC03_023_jr_8013FFD8.o,tail8.data.o,ov_SC03_023_jr_80140608.o,tail9.data.o,ov_SC03_023_jr_8015444C.o,ov_SC03_023_jr_80154C24.o,ov_SC03_023_jr_801588CC.o,tail10.data.o,ov_SC03_023_jr_80159C84.o,tail11.data.o,ov_SC03_023_jr_8015A3C8.o,tail12.data.o,ov_SC03_023_jr_8015AE2C.o,tail13.data.o,ov_SC03_023_jr_8015C32C.o,tail14.data.o,ov_SC03_023_jr_8016AB6C.o,tail15.data.o,ov_SC03_023_jr_80171B4C.o,ov_SC03_023_jr_801734BC.o,tail16.data.o,ov_SC03_023_jr_801789AC.o,ov_SC03_023_jr_80178D40.o,tail17.data.o,ov_SC03_023_jr_8017A4AC.o,tail18.data.o,ov_SC03_023_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_023/ov_SC03_023.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_023/ov_SC03_023_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_023/ov_SC03_023_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_023/ov_SC03_023_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_023/ov_SC03_023_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_023/ov_SC03_023_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_023/ov_SC03_023_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_023/ov_SC03_023_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_023/ov_SC03_023_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1555,12 +1599,13 @@ ov_SC03_024_ELF := $(ov_SC03_024_OUT).elf ov_SC03_024_MAPFILE := $(ov_SC03_024_OUT).map ov_SC03_024_LD_SCRIPT := $(ov_SC03_024_OUT).ld ov_SC03_024_SPLAT_YAML := config/splat.ov_SC03_024.yaml -ov_SC03_024_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_024.o,ov_SC03_024_jr_8012ACE0.o,tail2.data.o,ov_SC03_024_jr_80135888.o,tail3.data.o,ov_SC03_024_jr_80135A4C.o,tail4.data.o,ov_SC03_024_jr_80135D20.o,tail5.data.o,ov_SC03_024_jr_801380E0.o,ov_SC03_024_o0c.o,tail6.data.o,ov_SC03_024_jr_8013F350.o,tail7.data.o,ov_SC03_024_jr_8013FFD8.o,tail8.data.o,ov_SC03_024_jr_80140608.o,tail9.data.o,ov_SC03_024_jr_8015444C.o,tail10.data.o,ov_SC03_024_jr_80154C24.o,ov_SC03_024_jr_801588CC.o,tail11.data.o,ov_SC03_024_jr_80159C84.o,tail12.data.o,ov_SC03_024_jr_8015A3C8.o,tail13.data.o,ov_SC03_024_jr_8015AE2C.o,tail14.data.o,ov_SC03_024_jr_8015C32C.o,tail15.data.o,ov_SC03_024_jr_8016AB6C.o,tail16.data.o,ov_SC03_024_jr_80171B4C.o,ov_SC03_024_jr_801734BC.o,tail17.data.o,ov_SC03_024_jr_801789AC.o,ov_SC03_024_jr_80178D40.o,tail18.data.o,ov_SC03_024_jr_8017A4AC.o,tail19.data.o,ov_SC03_024_jr_8017AE2C.o,tail20.data.o,ov_SC03_024_jr_8017DF84.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_024_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_024.o,ov_SC03_024_jr_8012ACE0.o,tail2.data.o,ov_SC03_024_jr_80135888.o,tail3.data.o,ov_SC03_024_jr_80135A4C.o,tail4.data.o,ov_SC03_024_jr_80135D20.o,tail5.data.o,ov_SC03_024_jr_801380E0.o,ov_SC03_024_o0c.o,tail6.data.o,ov_SC03_024_jr_8013F350.o,tail7.data.o,ov_SC03_024_jr_8013FFD8.o,tail8.data.o,ov_SC03_024_jr_80140608.o,tail9.data.o,ov_SC03_024_jr_8015444C.o,ov_SC03_024_jr_80154C24.o,ov_SC03_024_jr_801588CC.o,tail10.data.o,ov_SC03_024_jr_80159C84.o,tail11.data.o,ov_SC03_024_jr_8015A3C8.o,tail12.data.o,ov_SC03_024_jr_8015AE2C.o,tail13.data.o,ov_SC03_024_jr_8015C32C.o,tail14.data.o,ov_SC03_024_jr_8016AB6C.o,tail15.data.o,ov_SC03_024_jr_80171B4C.o,ov_SC03_024_jr_801734BC.o,tail16.data.o,ov_SC03_024_jr_801789AC.o,ov_SC03_024_jr_80178D40.o,tail17.data.o,ov_SC03_024_jr_8017A4AC.o,tail18.data.o,ov_SC03_024_jr_8017AE2C.o,tail19.data.o,ov_SC03_024_jr_8017DF84.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_024/ov_SC03_024.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_024/ov_SC03_024_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_024/ov_SC03_024_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_024/ov_SC03_024_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_024/ov_SC03_024_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_024/ov_SC03_024_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_024/ov_SC03_024_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_024/ov_SC03_024_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_024/ov_SC03_024_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1589,12 +1634,13 @@ ov_SC03_028_ELF := $(ov_SC03_028_OUT).elf ov_SC03_028_MAPFILE := $(ov_SC03_028_OUT).map ov_SC03_028_LD_SCRIPT := $(ov_SC03_028_OUT).ld ov_SC03_028_SPLAT_YAML := config/splat.ov_SC03_028.yaml -ov_SC03_028_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_028.o,ov_SC03_028_jr_8012ACE0.o,tail2.data.o,ov_SC03_028_jr_80135888.o,tail3.data.o,ov_SC03_028_jr_80135A4C.o,tail4.data.o,ov_SC03_028_jr_80135D20.o,tail5.data.o,ov_SC03_028_jr_801380E0.o,ov_SC03_028_o0c.o,tail6.data.o,ov_SC03_028_jr_8013F350.o,tail7.data.o,ov_SC03_028_jr_8013FFD8.o,tail8.data.o,ov_SC03_028_jr_80140608.o,tail9.data.o,ov_SC03_028_jr_8015444C.o,tail10.data.o,ov_SC03_028_jr_80154C24.o,ov_SC03_028_jr_801588CC.o,tail11.data.o,ov_SC03_028_jr_80159C84.o,tail12.data.o,ov_SC03_028_jr_8015A3C8.o,tail13.data.o,ov_SC03_028_jr_8015AE2C.o,tail14.data.o,ov_SC03_028_jr_8015C32C.o,tail15.data.o,ov_SC03_028_jr_8016AB6C.o,tail16.data.o,ov_SC03_028_jr_80171B4C.o,ov_SC03_028_jr_801734BC.o,tail17.data.o,ov_SC03_028_jr_801789AC.o,ov_SC03_028_jr_80178D40.o,tail18.data.o,ov_SC03_028_jr_8017A4AC.o,tail19.data.o,ov_SC03_028_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_028_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_028.o,ov_SC03_028_jr_8012ACE0.o,tail2.data.o,ov_SC03_028_jr_80135888.o,tail3.data.o,ov_SC03_028_jr_80135A4C.o,tail4.data.o,ov_SC03_028_jr_80135D20.o,tail5.data.o,ov_SC03_028_jr_801380E0.o,ov_SC03_028_o0c.o,tail6.data.o,ov_SC03_028_jr_8013F350.o,tail7.data.o,ov_SC03_028_jr_8013FFD8.o,tail8.data.o,ov_SC03_028_jr_80140608.o,tail9.data.o,ov_SC03_028_jr_8015444C.o,ov_SC03_028_jr_80154C24.o,ov_SC03_028_jr_801588CC.o,tail10.data.o,ov_SC03_028_jr_80159C84.o,tail11.data.o,ov_SC03_028_jr_8015A3C8.o,tail12.data.o,ov_SC03_028_jr_8015AE2C.o,tail13.data.o,ov_SC03_028_jr_8015C32C.o,tail14.data.o,ov_SC03_028_jr_8016AB6C.o,tail15.data.o,ov_SC03_028_jr_80171B4C.o,ov_SC03_028_jr_801734BC.o,tail16.data.o,ov_SC03_028_jr_801789AC.o,ov_SC03_028_jr_80178D40.o,tail17.data.o,ov_SC03_028_jr_8017A4AC.o,tail18.data.o,ov_SC03_028_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_028/ov_SC03_028.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_028/ov_SC03_028_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_028/ov_SC03_028_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_028/ov_SC03_028_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_028/ov_SC03_028_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_028/ov_SC03_028_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_028/ov_SC03_028_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_028/ov_SC03_028_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_028/ov_SC03_028_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1623,12 +1669,13 @@ ov_SC03_029_ELF := $(ov_SC03_029_OUT).elf ov_SC03_029_MAPFILE := $(ov_SC03_029_OUT).map ov_SC03_029_LD_SCRIPT := $(ov_SC03_029_OUT).ld ov_SC03_029_SPLAT_YAML := config/splat.ov_SC03_029.yaml -ov_SC03_029_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_029.o,ov_SC03_029_jr_8012ACE0.o,tail2.data.o,ov_SC03_029_jr_80135888.o,tail3.data.o,ov_SC03_029_jr_80135A4C.o,tail4.data.o,ov_SC03_029_jr_80135D20.o,tail5.data.o,ov_SC03_029_jr_801380E0.o,ov_SC03_029_o0c.o,tail6.data.o,ov_SC03_029_jr_8013F350.o,tail7.data.o,ov_SC03_029_jr_8013FFD8.o,tail8.data.o,ov_SC03_029_jr_80140608.o,tail9.data.o,ov_SC03_029_jr_8015444C.o,tail10.data.o,ov_SC03_029_jr_80154C24.o,ov_SC03_029_jr_801588CC.o,tail11.data.o,ov_SC03_029_jr_80159C84.o,tail12.data.o,ov_SC03_029_jr_8015A3C8.o,tail13.data.o,ov_SC03_029_jr_8015AE2C.o,tail14.data.o,ov_SC03_029_jr_8015C32C.o,tail15.data.o,ov_SC03_029_jr_8016AB6C.o,tail16.data.o,ov_SC03_029_jr_80171B4C.o,ov_SC03_029_jr_801734BC.o,tail17.data.o,ov_SC03_029_jr_801789AC.o,ov_SC03_029_jr_80178D40.o,tail18.data.o,ov_SC03_029_jr_8017A4AC.o,tail19.data.o,ov_SC03_029_jr_8017AE2C.o,ov_SC03_029_jr_8017DC70.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_029_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_029.o,ov_SC03_029_jr_8012ACE0.o,tail2.data.o,ov_SC03_029_jr_80135888.o,tail3.data.o,ov_SC03_029_jr_80135A4C.o,tail4.data.o,ov_SC03_029_jr_80135D20.o,tail5.data.o,ov_SC03_029_jr_801380E0.o,ov_SC03_029_o0c.o,tail6.data.o,ov_SC03_029_jr_8013F350.o,tail7.data.o,ov_SC03_029_jr_8013FFD8.o,tail8.data.o,ov_SC03_029_jr_80140608.o,tail9.data.o,ov_SC03_029_jr_8015444C.o,ov_SC03_029_jr_80154C24.o,ov_SC03_029_jr_801588CC.o,tail10.data.o,ov_SC03_029_jr_80159C84.o,tail11.data.o,ov_SC03_029_jr_8015A3C8.o,tail12.data.o,ov_SC03_029_jr_8015AE2C.o,tail13.data.o,ov_SC03_029_jr_8015C32C.o,tail14.data.o,ov_SC03_029_jr_8016AB6C.o,tail15.data.o,ov_SC03_029_jr_80171B4C.o,ov_SC03_029_jr_801734BC.o,tail16.data.o,ov_SC03_029_jr_801789AC.o,ov_SC03_029_jr_80178D40.o,tail17.data.o,ov_SC03_029_jr_8017A4AC.o,tail18.data.o,ov_SC03_029_jr_8017AE2C.o,ov_SC03_029_jr_8017DC70.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_029/ov_SC03_029.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_029/ov_SC03_029_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_029/ov_SC03_029_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_029/ov_SC03_029_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_029/ov_SC03_029_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_029/ov_SC03_029_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_029/ov_SC03_029_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_029/ov_SC03_029_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_029/ov_SC03_029_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1657,12 +1704,13 @@ ov_SC03_030_ELF := $(ov_SC03_030_OUT).elf ov_SC03_030_MAPFILE := $(ov_SC03_030_OUT).map ov_SC03_030_LD_SCRIPT := $(ov_SC03_030_OUT).ld ov_SC03_030_SPLAT_YAML := config/splat.ov_SC03_030.yaml -ov_SC03_030_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_030.o,ov_SC03_030_jr_8012ACE0.o,tail2.data.o,ov_SC03_030_jr_80135888.o,tail3.data.o,ov_SC03_030_jr_80135A4C.o,tail4.data.o,ov_SC03_030_jr_80135D20.o,tail5.data.o,ov_SC03_030_jr_801380E0.o,ov_SC03_030_o0c.o,tail6.data.o,ov_SC03_030_jr_8013F350.o,tail7.data.o,ov_SC03_030_jr_8014032C.o,tail8.data.o,ov_SC03_030_jr_80140608.o,tail9.data.o,ov_SC03_030_jr_8015444C.o,tail10.data.o,ov_SC03_030_jr_80154C24.o,ov_SC03_030_jr_801588CC.o,tail11.data.o,ov_SC03_030_jr_80159C84.o,tail12.data.o,ov_SC03_030_jr_8015A3C8.o,tail13.data.o,ov_SC03_030_jr_8015AE2C.o,tail14.data.o,ov_SC03_030_jr_8015C32C.o,tail15.data.o,ov_SC03_030_jr_8016AB6C.o,tail16.data.o,ov_SC03_030_jr_80171B4C.o,ov_SC03_030_jr_801734BC.o,tail17.data.o,ov_SC03_030_jr_801789AC.o,ov_SC03_030_jr_80178D40.o,tail18.data.o,ov_SC03_030_jr_8017A4AC.o,tail19.data.o,ov_SC03_030_jr_8017AE2C.o,tail20.data.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_030_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_030.o,ov_SC03_030_jr_8012ACE0.o,tail2.data.o,ov_SC03_030_jr_80135888.o,tail3.data.o,ov_SC03_030_jr_80135A4C.o,tail4.data.o,ov_SC03_030_jr_80135D20.o,tail5.data.o,ov_SC03_030_jr_801380E0.o,ov_SC03_030_o0c.o,tail6.data.o,ov_SC03_030_jr_8013F350.o,tail7.data.o,ov_SC03_030_jr_8014032C.o,tail8.data.o,ov_SC03_030_jr_80140608.o,tail9.data.o,ov_SC03_030_jr_8015444C.o,ov_SC03_030_jr_80154C24.o,ov_SC03_030_jr_801588CC.o,tail10.data.o,ov_SC03_030_jr_80159C84.o,tail11.data.o,ov_SC03_030_jr_8015A3C8.o,tail12.data.o,ov_SC03_030_jr_8015AE2C.o,tail13.data.o,ov_SC03_030_jr_8015C32C.o,tail14.data.o,ov_SC03_030_jr_8016AB6C.o,tail15.data.o,ov_SC03_030_jr_80171B4C.o,ov_SC03_030_jr_801734BC.o,tail16.data.o,ov_SC03_030_jr_801789AC.o,ov_SC03_030_jr_80178D40.o,tail17.data.o,ov_SC03_030_jr_8017A4AC.o,tail18.data.o,ov_SC03_030_jr_8017AE2C.o,tail19.data.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_030/ov_SC03_030.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_030/ov_SC03_030_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_030/ov_SC03_030_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_030/ov_SC03_030_jr_8013F350.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 build/src/ov_SC03_030/ov_SC03_030_jr_8014032C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC03_030/ov_SC03_030_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_030/ov_SC03_030_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_030/ov_SC03_030_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_030/ov_SC03_030_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1691,12 +1739,13 @@ ov_SC03_031_ELF := $(ov_SC03_031_OUT).elf ov_SC03_031_MAPFILE := $(ov_SC03_031_OUT).map ov_SC03_031_LD_SCRIPT := $(ov_SC03_031_OUT).ld ov_SC03_031_SPLAT_YAML := config/splat.ov_SC03_031.yaml -ov_SC03_031_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_031.o,ov_SC03_031_jr_8012ACE0.o,tail2.data.o,ov_SC03_031_jr_80135888.o,tail3.data.o,ov_SC03_031_jr_80135A4C.o,tail4.data.o,ov_SC03_031_jr_80135D20.o,tail5.data.o,ov_SC03_031_jr_801380E0.o,ov_SC03_031_o0c.o,tail6.data.o,ov_SC03_031_jr_8013F350.o,tail7.data.o,ov_SC03_031_jr_8013FFD8.o,tail8.data.o,ov_SC03_031_jr_80140608.o,tail9.data.o,ov_SC03_031_jr_8015444C.o,tail10.data.o,ov_SC03_031_jr_80154C24.o,ov_SC03_031_jr_801588CC.o,tail11.data.o,ov_SC03_031_jr_80159C84.o,tail12.data.o,ov_SC03_031_jr_8015A3C8.o,tail13.data.o,ov_SC03_031_jr_8015AE2C.o,tail14.data.o,ov_SC03_031_jr_8015C32C.o,tail15.data.o,ov_SC03_031_jr_8016AB6C.o,tail16.data.o,ov_SC03_031_jr_80171B4C.o,ov_SC03_031_jr_801734BC.o,tail17.data.o,ov_SC03_031_jr_801789AC.o,ov_SC03_031_jr_80178D40.o,tail18.data.o,ov_SC03_031_jr_8017A4AC.o,tail19.data.o,ov_SC03_031_jr_8017AE2C.o,ov_SC03_031_jr_8017DB5C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_031_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_031.o,ov_SC03_031_jr_8012ACE0.o,tail2.data.o,ov_SC03_031_jr_80135888.o,tail3.data.o,ov_SC03_031_jr_80135A4C.o,tail4.data.o,ov_SC03_031_jr_80135D20.o,tail5.data.o,ov_SC03_031_jr_801380E0.o,ov_SC03_031_o0c.o,tail6.data.o,ov_SC03_031_jr_8013F350.o,tail7.data.o,ov_SC03_031_jr_8013FFD8.o,tail8.data.o,ov_SC03_031_jr_80140608.o,tail9.data.o,ov_SC03_031_jr_8015444C.o,ov_SC03_031_jr_80154C24.o,ov_SC03_031_jr_801588CC.o,tail10.data.o,ov_SC03_031_jr_80159C84.o,tail11.data.o,ov_SC03_031_jr_8015A3C8.o,tail12.data.o,ov_SC03_031_jr_8015AE2C.o,tail13.data.o,ov_SC03_031_jr_8015C32C.o,tail14.data.o,ov_SC03_031_jr_8016AB6C.o,tail15.data.o,ov_SC03_031_jr_80171B4C.o,ov_SC03_031_jr_801734BC.o,tail16.data.o,ov_SC03_031_jr_801789AC.o,ov_SC03_031_jr_80178D40.o,tail17.data.o,ov_SC03_031_jr_8017A4AC.o,tail18.data.o,ov_SC03_031_jr_8017AE2C.o,ov_SC03_031_jr_8017DB5C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_031/ov_SC03_031.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_031/ov_SC03_031_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_031/ov_SC03_031_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_031/ov_SC03_031_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_031/ov_SC03_031_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_031/ov_SC03_031_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_031/ov_SC03_031_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_031/ov_SC03_031_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_031/ov_SC03_031_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1725,12 +1774,13 @@ ov_SC03_089_ELF := $(ov_SC03_089_OUT).elf ov_SC03_089_MAPFILE := $(ov_SC03_089_OUT).map ov_SC03_089_LD_SCRIPT := $(ov_SC03_089_OUT).ld ov_SC03_089_SPLAT_YAML := config/splat.ov_SC03_089.yaml -ov_SC03_089_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_089.o,ov_SC03_089_jr_8012ACE0.o,tail2.data.o,ov_SC03_089_jr_80135888.o,tail3.data.o,ov_SC03_089_jr_80135A4C.o,tail4.data.o,ov_SC03_089_jr_80135D20.o,tail5.data.o,ov_SC03_089_jr_801380E0.o,ov_SC03_089_o0c.o,tail6.data.o,ov_SC03_089_jr_8013F350.o,tail7.data.o,ov_SC03_089_jr_8013FFD8.o,tail8.data.o,ov_SC03_089_jr_80140608.o,tail9.data.o,ov_SC03_089_jr_8015444C.o,tail10.data.o,ov_SC03_089_jr_80154C24.o,ov_SC03_089_jr_801588CC.o,tail11.data.o,ov_SC03_089_jr_80159C84.o,tail12.data.o,ov_SC03_089_jr_8015A3C8.o,tail13.data.o,ov_SC03_089_jr_8015AE2C.o,tail14.data.o,ov_SC03_089_jr_8015C32C.o,tail15.data.o,ov_SC03_089_jr_8016AB6C.o,tail16.data.o,ov_SC03_089_jr_80171B4C.o,ov_SC03_089_jr_801734BC.o,tail17.data.o,ov_SC03_089_jr_801789AC.o,ov_SC03_089_jr_80178D40.o,tail18.data.o,ov_SC03_089_jr_8017A4AC.o,tail19.data.o,ov_SC03_089_jr_8017AE2C.o,ov_SC03_089_jr_8017CA80.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_089_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_089.o,ov_SC03_089_jr_8012ACE0.o,tail2.data.o,ov_SC03_089_jr_80135888.o,tail3.data.o,ov_SC03_089_jr_80135A4C.o,tail4.data.o,ov_SC03_089_jr_80135D20.o,tail5.data.o,ov_SC03_089_jr_801380E0.o,ov_SC03_089_o0c.o,tail6.data.o,ov_SC03_089_jr_8013F350.o,tail7.data.o,ov_SC03_089_jr_8013FFD8.o,tail8.data.o,ov_SC03_089_jr_80140608.o,tail9.data.o,ov_SC03_089_jr_8015444C.o,ov_SC03_089_jr_80154C24.o,ov_SC03_089_jr_801588CC.o,tail10.data.o,ov_SC03_089_jr_80159C84.o,tail11.data.o,ov_SC03_089_jr_8015A3C8.o,tail12.data.o,ov_SC03_089_jr_8015AE2C.o,tail13.data.o,ov_SC03_089_jr_8015C32C.o,tail14.data.o,ov_SC03_089_jr_8016AB6C.o,tail15.data.o,ov_SC03_089_jr_80171B4C.o,ov_SC03_089_jr_801734BC.o,tail16.data.o,ov_SC03_089_jr_801789AC.o,ov_SC03_089_jr_80178D40.o,tail17.data.o,ov_SC03_089_jr_8017A4AC.o,tail18.data.o,ov_SC03_089_jr_8017AE2C.o,ov_SC03_089_jr_8017CA80.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_089/ov_SC03_089.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_089/ov_SC03_089_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_089/ov_SC03_089_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_089/ov_SC03_089_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_089/ov_SC03_089_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_089/ov_SC03_089_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_089/ov_SC03_089_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_089/ov_SC03_089_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_089/ov_SC03_089_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1759,12 +1809,13 @@ ov_SC03_090_ELF := $(ov_SC03_090_OUT).elf ov_SC03_090_MAPFILE := $(ov_SC03_090_OUT).map ov_SC03_090_LD_SCRIPT := $(ov_SC03_090_OUT).ld ov_SC03_090_SPLAT_YAML := config/splat.ov_SC03_090.yaml -ov_SC03_090_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_090.o,ov_SC03_090_jr_8012ACE0.o,tail2.data.o,ov_SC03_090_jr_80135888.o,tail3.data.o,ov_SC03_090_jr_80135A4C.o,tail4.data.o,ov_SC03_090_jr_80135D20.o,tail5.data.o,ov_SC03_090_jr_801380E0.o,ov_SC03_090_o0c.o,tail6.data.o,ov_SC03_090_jr_8013F350.o,tail7.data.o,ov_SC03_090_jr_8013FFD8.o,tail8.data.o,ov_SC03_090_jr_80140608.o,tail9.data.o,ov_SC03_090_jr_8015444C.o,tail10.data.o,ov_SC03_090_jr_80154C24.o,ov_SC03_090_jr_801588CC.o,tail11.data.o,ov_SC03_090_jr_80159C84.o,tail12.data.o,ov_SC03_090_jr_8015A3C8.o,tail13.data.o,ov_SC03_090_jr_8015AE2C.o,tail14.data.o,ov_SC03_090_jr_8015C32C.o,tail15.data.o,ov_SC03_090_jr_8016AB6C.o,tail16.data.o,ov_SC03_090_jr_80171B4C.o,ov_SC03_090_jr_801734BC.o,tail17.data.o,ov_SC03_090_jr_801789AC.o,ov_SC03_090_jr_80178D40.o,tail18.data.o,ov_SC03_090_jr_8017A4AC.o,tail19.data.o,ov_SC03_090_jr_8017AE2C.o,ov_SC03_090_jr_8017CA80.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_090_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_090.o,ov_SC03_090_jr_8012ACE0.o,tail2.data.o,ov_SC03_090_jr_80135888.o,tail3.data.o,ov_SC03_090_jr_80135A4C.o,tail4.data.o,ov_SC03_090_jr_80135D20.o,tail5.data.o,ov_SC03_090_jr_801380E0.o,ov_SC03_090_o0c.o,tail6.data.o,ov_SC03_090_jr_8013F350.o,tail7.data.o,ov_SC03_090_jr_8013FFD8.o,tail8.data.o,ov_SC03_090_jr_80140608.o,tail9.data.o,ov_SC03_090_jr_8015444C.o,ov_SC03_090_jr_80154C24.o,ov_SC03_090_jr_801588CC.o,tail10.data.o,ov_SC03_090_jr_80159C84.o,tail11.data.o,ov_SC03_090_jr_8015A3C8.o,tail12.data.o,ov_SC03_090_jr_8015AE2C.o,tail13.data.o,ov_SC03_090_jr_8015C32C.o,tail14.data.o,ov_SC03_090_jr_8016AB6C.o,tail15.data.o,ov_SC03_090_jr_80171B4C.o,ov_SC03_090_jr_801734BC.o,tail16.data.o,ov_SC03_090_jr_801789AC.o,ov_SC03_090_jr_80178D40.o,tail17.data.o,ov_SC03_090_jr_8017A4AC.o,tail18.data.o,ov_SC03_090_jr_8017AE2C.o,ov_SC03_090_jr_8017CA80.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_090/ov_SC03_090.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_090/ov_SC03_090_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_090/ov_SC03_090_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_090/ov_SC03_090_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_090/ov_SC03_090_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_090/ov_SC03_090_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_090/ov_SC03_090_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_090/ov_SC03_090_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_090/ov_SC03_090_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1793,12 +1844,13 @@ ov_SC03_091_ELF := $(ov_SC03_091_OUT).elf ov_SC03_091_MAPFILE := $(ov_SC03_091_OUT).map ov_SC03_091_LD_SCRIPT := $(ov_SC03_091_OUT).ld ov_SC03_091_SPLAT_YAML := config/splat.ov_SC03_091.yaml -ov_SC03_091_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_091.o,ov_SC03_091_jr_8012ACE0.o,tail2.data.o,ov_SC03_091_jr_80135888.o,tail3.data.o,ov_SC03_091_jr_80135A4C.o,tail4.data.o,ov_SC03_091_jr_80135D20.o,tail5.data.o,ov_SC03_091_jr_801380E0.o,ov_SC03_091_o0c.o,tail6.data.o,ov_SC03_091_jr_8013F350.o,tail7.data.o,ov_SC03_091_jr_8013FFD8.o,tail8.data.o,ov_SC03_091_jr_80140608.o,tail9.data.o,ov_SC03_091_jr_8015444C.o,tail10.data.o,ov_SC03_091_jr_80154C24.o,ov_SC03_091_jr_801588CC.o,tail11.data.o,ov_SC03_091_jr_80159C84.o,tail12.data.o,ov_SC03_091_jr_8015A3C8.o,tail13.data.o,ov_SC03_091_jr_8015AE2C.o,tail14.data.o,ov_SC03_091_jr_8015C32C.o,tail15.data.o,ov_SC03_091_jr_8016AB6C.o,tail16.data.o,ov_SC03_091_jr_80171B4C.o,ov_SC03_091_jr_801734BC.o,tail17.data.o,ov_SC03_091_jr_801789AC.o,ov_SC03_091_jr_80178D40.o,tail18.data.o,ov_SC03_091_jr_8017A4AC.o,tail19.data.o,ov_SC03_091_jr_8017AE2C.o,ov_SC03_091_jr_8017D898.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_091_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_091.o,ov_SC03_091_jr_8012ACE0.o,tail2.data.o,ov_SC03_091_jr_80135888.o,tail3.data.o,ov_SC03_091_jr_80135A4C.o,tail4.data.o,ov_SC03_091_jr_80135D20.o,tail5.data.o,ov_SC03_091_jr_801380E0.o,ov_SC03_091_o0c.o,tail6.data.o,ov_SC03_091_jr_8013F350.o,tail7.data.o,ov_SC03_091_jr_8013FFD8.o,tail8.data.o,ov_SC03_091_jr_80140608.o,tail9.data.o,ov_SC03_091_jr_8015444C.o,ov_SC03_091_jr_80154C24.o,ov_SC03_091_jr_801588CC.o,tail10.data.o,ov_SC03_091_jr_80159C84.o,tail11.data.o,ov_SC03_091_jr_8015A3C8.o,tail12.data.o,ov_SC03_091_jr_8015AE2C.o,tail13.data.o,ov_SC03_091_jr_8015C32C.o,tail14.data.o,ov_SC03_091_jr_8016AB6C.o,tail15.data.o,ov_SC03_091_jr_80171B4C.o,ov_SC03_091_jr_801734BC.o,tail16.data.o,ov_SC03_091_jr_801789AC.o,ov_SC03_091_jr_80178D40.o,tail17.data.o,ov_SC03_091_jr_8017A4AC.o,tail18.data.o,ov_SC03_091_jr_8017AE2C.o,ov_SC03_091_jr_8017D898.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_091/ov_SC03_091.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_091/ov_SC03_091_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_091/ov_SC03_091_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_091/ov_SC03_091_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_091/ov_SC03_091_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_091/ov_SC03_091_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_091/ov_SC03_091_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_091/ov_SC03_091_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_091/ov_SC03_091_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1827,12 +1879,13 @@ ov_SC03_092_ELF := $(ov_SC03_092_OUT).elf ov_SC03_092_MAPFILE := $(ov_SC03_092_OUT).map ov_SC03_092_LD_SCRIPT := $(ov_SC03_092_OUT).ld ov_SC03_092_SPLAT_YAML := config/splat.ov_SC03_092.yaml -ov_SC03_092_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_092.o,ov_SC03_092_jr_8012ACE0.o,tail2.data.o,ov_SC03_092_jr_80135888.o,tail3.data.o,ov_SC03_092_jr_80135A4C.o,tail4.data.o,ov_SC03_092_jr_80135D20.o,tail5.data.o,ov_SC03_092_jr_801380E0.o,ov_SC03_092_o0c.o,tail6.data.o,ov_SC03_092_jr_8013F350.o,tail7.data.o,ov_SC03_092_jr_8013FFD8.o,tail8.data.o,ov_SC03_092_jr_80140608.o,tail9.data.o,ov_SC03_092_jr_8015444C.o,tail10.data.o,ov_SC03_092_jr_80154C24.o,ov_SC03_092_jr_801588CC.o,tail11.data.o,ov_SC03_092_jr_80159C84.o,tail12.data.o,ov_SC03_092_jr_8015A3C8.o,tail13.data.o,ov_SC03_092_jr_8015AE2C.o,tail14.data.o,ov_SC03_092_jr_8015C32C.o,tail15.data.o,ov_SC03_092_jr_8016AB6C.o,tail16.data.o,ov_SC03_092_jr_80171B4C.o,ov_SC03_092_jr_801734BC.o,tail17.data.o,ov_SC03_092_jr_801789AC.o,ov_SC03_092_jr_80178D40.o,tail18.data.o,ov_SC03_092_jr_8017A4AC.o,tail19.data.o,ov_SC03_092_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_092_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_092.o,ov_SC03_092_jr_8012ACE0.o,tail2.data.o,ov_SC03_092_jr_80135888.o,tail3.data.o,ov_SC03_092_jr_80135A4C.o,tail4.data.o,ov_SC03_092_jr_80135D20.o,tail5.data.o,ov_SC03_092_jr_801380E0.o,ov_SC03_092_o0c.o,tail6.data.o,ov_SC03_092_jr_8013F350.o,tail7.data.o,ov_SC03_092_jr_8013FFD8.o,tail8.data.o,ov_SC03_092_jr_80140608.o,tail9.data.o,ov_SC03_092_jr_8015444C.o,ov_SC03_092_jr_80154C24.o,ov_SC03_092_jr_801588CC.o,tail10.data.o,ov_SC03_092_jr_80159C84.o,tail11.data.o,ov_SC03_092_jr_8015A3C8.o,tail12.data.o,ov_SC03_092_jr_8015AE2C.o,tail13.data.o,ov_SC03_092_jr_8015C32C.o,tail14.data.o,ov_SC03_092_jr_8016AB6C.o,tail15.data.o,ov_SC03_092_jr_80171B4C.o,ov_SC03_092_jr_801734BC.o,tail16.data.o,ov_SC03_092_jr_801789AC.o,ov_SC03_092_jr_80178D40.o,tail17.data.o,ov_SC03_092_jr_8017A4AC.o,tail18.data.o,ov_SC03_092_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_092/ov_SC03_092.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_092/ov_SC03_092_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_092/ov_SC03_092_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_092/ov_SC03_092_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_092/ov_SC03_092_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_092/ov_SC03_092_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_092/ov_SC03_092_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_092/ov_SC03_092_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_092/ov_SC03_092_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1861,12 +1914,13 @@ ov_SC03_093_ELF := $(ov_SC03_093_OUT).elf ov_SC03_093_MAPFILE := $(ov_SC03_093_OUT).map ov_SC03_093_LD_SCRIPT := $(ov_SC03_093_OUT).ld ov_SC03_093_SPLAT_YAML := config/splat.ov_SC03_093.yaml -ov_SC03_093_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_093.o,ov_SC03_093_jr_8012ACE0.o,tail2.data.o,ov_SC03_093_jr_80135888.o,tail3.data.o,ov_SC03_093_jr_80135A4C.o,tail4.data.o,ov_SC03_093_jr_80135D20.o,tail5.data.o,ov_SC03_093_jr_801380E0.o,ov_SC03_093_o0c.o,tail6.data.o,ov_SC03_093_jr_8013F350.o,tail7.data.o,ov_SC03_093_jr_8013FFD8.o,tail8.data.o,ov_SC03_093_jr_80140608.o,tail9.data.o,ov_SC03_093_jr_8015444C.o,tail10.data.o,ov_SC03_093_jr_80154C24.o,ov_SC03_093_jr_801588CC.o,tail11.data.o,ov_SC03_093_jr_80159C84.o,tail12.data.o,ov_SC03_093_jr_8015A3C8.o,tail13.data.o,ov_SC03_093_jr_8015AE2C.o,tail14.data.o,ov_SC03_093_jr_8015C32C.o,tail15.data.o,ov_SC03_093_jr_8016AB6C.o,tail16.data.o,ov_SC03_093_jr_80171B4C.o,ov_SC03_093_jr_801734BC.o,tail17.data.o,ov_SC03_093_jr_801789AC.o,ov_SC03_093_jr_80178D40.o,tail18.data.o,ov_SC03_093_jr_8017A4AC.o,tail19.data.o,ov_SC03_093_jr_8017AE2C.o,ov_SC03_093_jr_8017D898.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_093_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_093.o,ov_SC03_093_jr_8012ACE0.o,tail2.data.o,ov_SC03_093_jr_80135888.o,tail3.data.o,ov_SC03_093_jr_80135A4C.o,tail4.data.o,ov_SC03_093_jr_80135D20.o,tail5.data.o,ov_SC03_093_jr_801380E0.o,ov_SC03_093_o0c.o,tail6.data.o,ov_SC03_093_jr_8013F350.o,tail7.data.o,ov_SC03_093_jr_8013FFD8.o,tail8.data.o,ov_SC03_093_jr_80140608.o,tail9.data.o,ov_SC03_093_jr_8015444C.o,ov_SC03_093_jr_80154C24.o,ov_SC03_093_jr_801588CC.o,tail10.data.o,ov_SC03_093_jr_80159C84.o,tail11.data.o,ov_SC03_093_jr_8015A3C8.o,tail12.data.o,ov_SC03_093_jr_8015AE2C.o,tail13.data.o,ov_SC03_093_jr_8015C32C.o,tail14.data.o,ov_SC03_093_jr_8016AB6C.o,tail15.data.o,ov_SC03_093_jr_80171B4C.o,ov_SC03_093_jr_801734BC.o,tail16.data.o,ov_SC03_093_jr_801789AC.o,ov_SC03_093_jr_80178D40.o,tail17.data.o,ov_SC03_093_jr_8017A4AC.o,tail18.data.o,ov_SC03_093_jr_8017AE2C.o,ov_SC03_093_jr_8017D898.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_093/ov_SC03_093.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_093/ov_SC03_093_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_093/ov_SC03_093_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_093/ov_SC03_093_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_093/ov_SC03_093_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_093/ov_SC03_093_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_093/ov_SC03_093_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_093/ov_SC03_093_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_093/ov_SC03_093_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1895,12 +1949,13 @@ ov_SC03_094_ELF := $(ov_SC03_094_OUT).elf ov_SC03_094_MAPFILE := $(ov_SC03_094_OUT).map ov_SC03_094_LD_SCRIPT := $(ov_SC03_094_OUT).ld ov_SC03_094_SPLAT_YAML := config/splat.ov_SC03_094.yaml -ov_SC03_094_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_094.o,ov_SC03_094_jr_8012ACE0.o,tail2.data.o,ov_SC03_094_jr_80135888.o,tail3.data.o,ov_SC03_094_jr_80135A4C.o,tail4.data.o,ov_SC03_094_jr_80135D20.o,tail5.data.o,ov_SC03_094_jr_801380E0.o,ov_SC03_094_o0c.o,tail6.data.o,ov_SC03_094_jr_8013F350.o,tail7.data.o,ov_SC03_094_jr_8013FFD8.o,tail8.data.o,ov_SC03_094_jr_80140608.o,tail9.data.o,ov_SC03_094_jr_8015444C.o,tail10.data.o,ov_SC03_094_jr_80154C24.o,ov_SC03_094_jr_801588CC.o,tail11.data.o,ov_SC03_094_jr_80159C84.o,tail12.data.o,ov_SC03_094_jr_8015A3C8.o,tail13.data.o,ov_SC03_094_jr_8015AE2C.o,tail14.data.o,ov_SC03_094_jr_8015C32C.o,tail15.data.o,ov_SC03_094_jr_8016AB6C.o,tail16.data.o,ov_SC03_094_jr_80171B4C.o,ov_SC03_094_jr_801734BC.o,tail17.data.o,ov_SC03_094_jr_801789AC.o,ov_SC03_094_jr_80178D40.o,tail18.data.o,ov_SC03_094_jr_8017A4AC.o,tail19.data.o,ov_SC03_094_jr_8017AE2C.o,ov_SC03_094_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_094_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_094.o,ov_SC03_094_jr_8012ACE0.o,tail2.data.o,ov_SC03_094_jr_80135888.o,tail3.data.o,ov_SC03_094_jr_80135A4C.o,tail4.data.o,ov_SC03_094_jr_80135D20.o,tail5.data.o,ov_SC03_094_jr_801380E0.o,ov_SC03_094_o0c.o,tail6.data.o,ov_SC03_094_jr_8013F350.o,tail7.data.o,ov_SC03_094_jr_8013FFD8.o,tail8.data.o,ov_SC03_094_jr_80140608.o,tail9.data.o,ov_SC03_094_jr_8015444C.o,ov_SC03_094_jr_80154C24.o,ov_SC03_094_jr_801588CC.o,tail10.data.o,ov_SC03_094_jr_80159C84.o,tail11.data.o,ov_SC03_094_jr_8015A3C8.o,tail12.data.o,ov_SC03_094_jr_8015AE2C.o,tail13.data.o,ov_SC03_094_jr_8015C32C.o,tail14.data.o,ov_SC03_094_jr_8016AB6C.o,tail15.data.o,ov_SC03_094_jr_80171B4C.o,ov_SC03_094_jr_801734BC.o,tail16.data.o,ov_SC03_094_jr_801789AC.o,ov_SC03_094_jr_80178D40.o,tail17.data.o,ov_SC03_094_jr_8017A4AC.o,tail18.data.o,ov_SC03_094_jr_8017AE2C.o,ov_SC03_094_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_094/ov_SC03_094.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_094/ov_SC03_094_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_094/ov_SC03_094_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_094/ov_SC03_094_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_094/ov_SC03_094_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_094/ov_SC03_094_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_094/ov_SC03_094_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_094/ov_SC03_094_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_094/ov_SC03_094_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1929,12 +1984,13 @@ ov_SC03_095_ELF := $(ov_SC03_095_OUT).elf ov_SC03_095_MAPFILE := $(ov_SC03_095_OUT).map ov_SC03_095_LD_SCRIPT := $(ov_SC03_095_OUT).ld ov_SC03_095_SPLAT_YAML := config/splat.ov_SC03_095.yaml -ov_SC03_095_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_095.o,ov_SC03_095_jr_8012ACE0.o,tail2.data.o,ov_SC03_095_jr_80135888.o,tail3.data.o,ov_SC03_095_jr_80135A4C.o,tail4.data.o,ov_SC03_095_jr_80135D20.o,tail5.data.o,ov_SC03_095_jr_801380E0.o,ov_SC03_095_o0c.o,tail6.data.o,ov_SC03_095_jr_8013F350.o,tail7.data.o,ov_SC03_095_jr_8013FFD8.o,tail8.data.o,ov_SC03_095_jr_80140608.o,tail9.data.o,ov_SC03_095_jr_8015444C.o,tail10.data.o,ov_SC03_095_jr_80154C24.o,ov_SC03_095_jr_801588CC.o,tail11.data.o,ov_SC03_095_jr_80159C84.o,tail12.data.o,ov_SC03_095_jr_8015A3C8.o,tail13.data.o,ov_SC03_095_jr_8015AE2C.o,tail14.data.o,ov_SC03_095_jr_8015C32C.o,tail15.data.o,ov_SC03_095_jr_8016AB6C.o,tail16.data.o,ov_SC03_095_jr_80171B4C.o,ov_SC03_095_jr_801734BC.o,tail17.data.o,ov_SC03_095_jr_801789AC.o,ov_SC03_095_jr_80178D40.o,tail18.data.o,ov_SC03_095_jr_8017A4AC.o,tail19.data.o,ov_SC03_095_jr_8017AE2C.o,ov_SC03_095_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_095_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_095.o,ov_SC03_095_jr_8012ACE0.o,tail2.data.o,ov_SC03_095_jr_80135888.o,tail3.data.o,ov_SC03_095_jr_80135A4C.o,tail4.data.o,ov_SC03_095_jr_80135D20.o,tail5.data.o,ov_SC03_095_jr_801380E0.o,ov_SC03_095_o0c.o,tail6.data.o,ov_SC03_095_jr_8013F350.o,tail7.data.o,ov_SC03_095_jr_8013FFD8.o,tail8.data.o,ov_SC03_095_jr_80140608.o,tail9.data.o,ov_SC03_095_jr_8015444C.o,ov_SC03_095_jr_80154C24.o,ov_SC03_095_jr_801588CC.o,tail10.data.o,ov_SC03_095_jr_80159C84.o,tail11.data.o,ov_SC03_095_jr_8015A3C8.o,tail12.data.o,ov_SC03_095_jr_8015AE2C.o,tail13.data.o,ov_SC03_095_jr_8015C32C.o,tail14.data.o,ov_SC03_095_jr_8016AB6C.o,tail15.data.o,ov_SC03_095_jr_80171B4C.o,ov_SC03_095_jr_801734BC.o,tail16.data.o,ov_SC03_095_jr_801789AC.o,ov_SC03_095_jr_80178D40.o,tail17.data.o,ov_SC03_095_jr_8017A4AC.o,tail18.data.o,ov_SC03_095_jr_8017AE2C.o,ov_SC03_095_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_095/ov_SC03_095.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_095/ov_SC03_095_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_095/ov_SC03_095_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_095/ov_SC03_095_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_095/ov_SC03_095_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_095/ov_SC03_095_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_095/ov_SC03_095_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_095/ov_SC03_095_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_095/ov_SC03_095_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1963,12 +2019,13 @@ ov_SC03_096_ELF := $(ov_SC03_096_OUT).elf ov_SC03_096_MAPFILE := $(ov_SC03_096_OUT).map ov_SC03_096_LD_SCRIPT := $(ov_SC03_096_OUT).ld ov_SC03_096_SPLAT_YAML := config/splat.ov_SC03_096.yaml -ov_SC03_096_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_096.o,ov_SC03_096_jr_8012ACE0.o,tail2.data.o,ov_SC03_096_jr_80135888.o,tail3.data.o,ov_SC03_096_jr_80135A4C.o,tail4.data.o,ov_SC03_096_jr_80135D20.o,tail5.data.o,ov_SC03_096_jr_801380E0.o,ov_SC03_096_o0c.o,tail6.data.o,ov_SC03_096_jr_8013F350.o,tail7.data.o,ov_SC03_096_jr_8013FFD8.o,tail8.data.o,ov_SC03_096_jr_80140608.o,tail9.data.o,ov_SC03_096_jr_8015444C.o,tail10.data.o,ov_SC03_096_jr_80154C24.o,ov_SC03_096_jr_801588CC.o,tail11.data.o,ov_SC03_096_jr_80159C84.o,tail12.data.o,ov_SC03_096_jr_8015A3C8.o,tail13.data.o,ov_SC03_096_jr_8015AE2C.o,tail14.data.o,ov_SC03_096_jr_8015C32C.o,tail15.data.o,ov_SC03_096_jr_8016AB6C.o,tail16.data.o,ov_SC03_096_jr_80171B4C.o,ov_SC03_096_jr_801734BC.o,tail17.data.o,ov_SC03_096_jr_801789AC.o,ov_SC03_096_jr_80178D40.o,tail18.data.o,ov_SC03_096_jr_8017A4AC.o,tail19.data.o,ov_SC03_096_jr_8017AE2C.o,ov_SC03_096_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_096_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_096.o,ov_SC03_096_jr_8012ACE0.o,tail2.data.o,ov_SC03_096_jr_80135888.o,tail3.data.o,ov_SC03_096_jr_80135A4C.o,tail4.data.o,ov_SC03_096_jr_80135D20.o,tail5.data.o,ov_SC03_096_jr_801380E0.o,ov_SC03_096_o0c.o,tail6.data.o,ov_SC03_096_jr_8013F350.o,tail7.data.o,ov_SC03_096_jr_8013FFD8.o,tail8.data.o,ov_SC03_096_jr_80140608.o,tail9.data.o,ov_SC03_096_jr_8015444C.o,ov_SC03_096_jr_80154C24.o,ov_SC03_096_jr_801588CC.o,tail10.data.o,ov_SC03_096_jr_80159C84.o,tail11.data.o,ov_SC03_096_jr_8015A3C8.o,tail12.data.o,ov_SC03_096_jr_8015AE2C.o,tail13.data.o,ov_SC03_096_jr_8015C32C.o,tail14.data.o,ov_SC03_096_jr_8016AB6C.o,tail15.data.o,ov_SC03_096_jr_80171B4C.o,ov_SC03_096_jr_801734BC.o,tail16.data.o,ov_SC03_096_jr_801789AC.o,ov_SC03_096_jr_80178D40.o,tail17.data.o,ov_SC03_096_jr_8017A4AC.o,tail18.data.o,ov_SC03_096_jr_8017AE2C.o,ov_SC03_096_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_096/ov_SC03_096.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_096/ov_SC03_096_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_096/ov_SC03_096_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_096/ov_SC03_096_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_096/ov_SC03_096_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_096/ov_SC03_096_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_096/ov_SC03_096_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_096/ov_SC03_096_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_096/ov_SC03_096_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -1997,12 +2054,13 @@ ov_SC03_097_ELF := $(ov_SC03_097_OUT).elf ov_SC03_097_MAPFILE := $(ov_SC03_097_OUT).map ov_SC03_097_LD_SCRIPT := $(ov_SC03_097_OUT).ld ov_SC03_097_SPLAT_YAML := config/splat.ov_SC03_097.yaml -ov_SC03_097_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_097.o,ov_SC03_097_jr_8012ACE0.o,tail2.data.o,ov_SC03_097_jr_80135888.o,tail3.data.o,ov_SC03_097_jr_80135A4C.o,tail4.data.o,ov_SC03_097_jr_80135D20.o,tail5.data.o,ov_SC03_097_jr_801380E0.o,ov_SC03_097_o0c.o,tail6.data.o,ov_SC03_097_jr_8013F350.o,tail7.data.o,ov_SC03_097_jr_8013FFD8.o,tail8.data.o,ov_SC03_097_jr_80140608.o,tail9.data.o,ov_SC03_097_jr_8015444C.o,tail10.data.o,ov_SC03_097_jr_80154C24.o,ov_SC03_097_jr_801588CC.o,tail11.data.o,ov_SC03_097_jr_80159C84.o,tail12.data.o,ov_SC03_097_jr_8015A3C8.o,tail13.data.o,ov_SC03_097_jr_8015AE2C.o,tail14.data.o,ov_SC03_097_jr_8015C32C.o,tail15.data.o,ov_SC03_097_jr_8016AB6C.o,tail16.data.o,ov_SC03_097_jr_80171B4C.o,ov_SC03_097_jr_801734BC.o,tail17.data.o,ov_SC03_097_jr_801789AC.o,ov_SC03_097_jr_80178D40.o,tail18.data.o,ov_SC03_097_jr_8017A4AC.o,tail19.data.o,ov_SC03_097_jr_8017AE2C.o,ov_SC03_097_jr_8017D898.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_097_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_097.o,ov_SC03_097_jr_8012ACE0.o,tail2.data.o,ov_SC03_097_jr_80135888.o,tail3.data.o,ov_SC03_097_jr_80135A4C.o,tail4.data.o,ov_SC03_097_jr_80135D20.o,tail5.data.o,ov_SC03_097_jr_801380E0.o,ov_SC03_097_o0c.o,tail6.data.o,ov_SC03_097_jr_8013F350.o,tail7.data.o,ov_SC03_097_jr_8013FFD8.o,tail8.data.o,ov_SC03_097_jr_80140608.o,tail9.data.o,ov_SC03_097_jr_8015444C.o,ov_SC03_097_jr_80154C24.o,ov_SC03_097_jr_801588CC.o,tail10.data.o,ov_SC03_097_jr_80159C84.o,tail11.data.o,ov_SC03_097_jr_8015A3C8.o,tail12.data.o,ov_SC03_097_jr_8015AE2C.o,tail13.data.o,ov_SC03_097_jr_8015C32C.o,tail14.data.o,ov_SC03_097_jr_8016AB6C.o,tail15.data.o,ov_SC03_097_jr_80171B4C.o,ov_SC03_097_jr_801734BC.o,tail16.data.o,ov_SC03_097_jr_801789AC.o,ov_SC03_097_jr_80178D40.o,tail17.data.o,ov_SC03_097_jr_8017A4AC.o,tail18.data.o,ov_SC03_097_jr_8017AE2C.o,ov_SC03_097_jr_8017D898.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_097/ov_SC03_097.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_097/ov_SC03_097_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_097/ov_SC03_097_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_097/ov_SC03_097_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_097/ov_SC03_097_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_097/ov_SC03_097_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_097/ov_SC03_097_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_097/ov_SC03_097_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_097/ov_SC03_097_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2031,12 +2089,13 @@ ov_SC03_098_ELF := $(ov_SC03_098_OUT).elf ov_SC03_098_MAPFILE := $(ov_SC03_098_OUT).map ov_SC03_098_LD_SCRIPT := $(ov_SC03_098_OUT).ld ov_SC03_098_SPLAT_YAML := config/splat.ov_SC03_098.yaml -ov_SC03_098_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_098.o,ov_SC03_098_jr_8012ACE0.o,tail2.data.o,ov_SC03_098_jr_80135888.o,tail3.data.o,ov_SC03_098_jr_80135A4C.o,tail4.data.o,ov_SC03_098_jr_80135D20.o,tail5.data.o,ov_SC03_098_jr_801380E0.o,ov_SC03_098_o0c.o,tail6.data.o,ov_SC03_098_jr_8013F350.o,tail7.data.o,ov_SC03_098_jr_8013FFD8.o,tail8.data.o,ov_SC03_098_jr_80140608.o,tail9.data.o,ov_SC03_098_jr_8015444C.o,tail10.data.o,ov_SC03_098_jr_80154C24.o,ov_SC03_098_jr_801588CC.o,tail11.data.o,ov_SC03_098_jr_80159C84.o,tail12.data.o,ov_SC03_098_jr_8015A3C8.o,tail13.data.o,ov_SC03_098_jr_8015AE2C.o,tail14.data.o,ov_SC03_098_jr_8015C32C.o,tail15.data.o,ov_SC03_098_jr_8016AB6C.o,tail16.data.o,ov_SC03_098_jr_80171B4C.o,ov_SC03_098_jr_801734BC.o,tail17.data.o,ov_SC03_098_jr_801789AC.o,ov_SC03_098_jr_80178D40.o,tail18.data.o,ov_SC03_098_jr_8017A4AC.o,tail19.data.o,ov_SC03_098_jr_8017AE2C.o,ov_SC03_098_jr_8017D898.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_098_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_098.o,ov_SC03_098_jr_8012ACE0.o,tail2.data.o,ov_SC03_098_jr_80135888.o,tail3.data.o,ov_SC03_098_jr_80135A4C.o,tail4.data.o,ov_SC03_098_jr_80135D20.o,tail5.data.o,ov_SC03_098_jr_801380E0.o,ov_SC03_098_o0c.o,tail6.data.o,ov_SC03_098_jr_8013F350.o,tail7.data.o,ov_SC03_098_jr_8013FFD8.o,tail8.data.o,ov_SC03_098_jr_80140608.o,tail9.data.o,ov_SC03_098_jr_8015444C.o,ov_SC03_098_jr_80154C24.o,ov_SC03_098_jr_801588CC.o,tail10.data.o,ov_SC03_098_jr_80159C84.o,tail11.data.o,ov_SC03_098_jr_8015A3C8.o,tail12.data.o,ov_SC03_098_jr_8015AE2C.o,tail13.data.o,ov_SC03_098_jr_8015C32C.o,tail14.data.o,ov_SC03_098_jr_8016AB6C.o,tail15.data.o,ov_SC03_098_jr_80171B4C.o,ov_SC03_098_jr_801734BC.o,tail16.data.o,ov_SC03_098_jr_801789AC.o,ov_SC03_098_jr_80178D40.o,tail17.data.o,ov_SC03_098_jr_8017A4AC.o,tail18.data.o,ov_SC03_098_jr_8017AE2C.o,ov_SC03_098_jr_8017D898.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_098/ov_SC03_098.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_098/ov_SC03_098_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_098/ov_SC03_098_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_098/ov_SC03_098_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_098/ov_SC03_098_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_098/ov_SC03_098_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_098/ov_SC03_098_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_098/ov_SC03_098_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_098/ov_SC03_098_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2065,12 +2124,13 @@ ov_SC03_099_ELF := $(ov_SC03_099_OUT).elf ov_SC03_099_MAPFILE := $(ov_SC03_099_OUT).map ov_SC03_099_LD_SCRIPT := $(ov_SC03_099_OUT).ld ov_SC03_099_SPLAT_YAML := config/splat.ov_SC03_099.yaml -ov_SC03_099_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_099.o,ov_SC03_099_jr_8012ACE0.o,tail2.data.o,ov_SC03_099_jr_80135888.o,tail3.data.o,ov_SC03_099_jr_80135A4C.o,tail4.data.o,ov_SC03_099_jr_80135D20.o,tail5.data.o,ov_SC03_099_jr_801380E0.o,ov_SC03_099_o0c.o,tail6.data.o,ov_SC03_099_jr_8013F350.o,tail7.data.o,ov_SC03_099_jr_8013FFD8.o,tail8.data.o,ov_SC03_099_jr_80140608.o,tail9.data.o,ov_SC03_099_jr_8015444C.o,tail10.data.o,ov_SC03_099_jr_80154C24.o,ov_SC03_099_jr_801588CC.o,tail11.data.o,ov_SC03_099_jr_80159C84.o,tail12.data.o,ov_SC03_099_jr_8015A3C8.o,tail13.data.o,ov_SC03_099_jr_8015AE2C.o,tail14.data.o,ov_SC03_099_jr_8015C32C.o,tail15.data.o,ov_SC03_099_jr_8016AB6C.o,tail16.data.o,ov_SC03_099_jr_80171B4C.o,ov_SC03_099_jr_801734BC.o,tail17.data.o,ov_SC03_099_jr_801789AC.o,ov_SC03_099_jr_80178D40.o,tail18.data.o,ov_SC03_099_jr_8017A4AC.o,tail19.data.o,ov_SC03_099_jr_8017AE2C.o,ov_SC03_099_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_099_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_099.o,ov_SC03_099_jr_8012ACE0.o,tail2.data.o,ov_SC03_099_jr_80135888.o,tail3.data.o,ov_SC03_099_jr_80135A4C.o,tail4.data.o,ov_SC03_099_jr_80135D20.o,tail5.data.o,ov_SC03_099_jr_801380E0.o,ov_SC03_099_o0c.o,tail6.data.o,ov_SC03_099_jr_8013F350.o,tail7.data.o,ov_SC03_099_jr_8013FFD8.o,tail8.data.o,ov_SC03_099_jr_80140608.o,tail9.data.o,ov_SC03_099_jr_8015444C.o,ov_SC03_099_jr_80154C24.o,ov_SC03_099_jr_801588CC.o,tail10.data.o,ov_SC03_099_jr_80159C84.o,tail11.data.o,ov_SC03_099_jr_8015A3C8.o,tail12.data.o,ov_SC03_099_jr_8015AE2C.o,tail13.data.o,ov_SC03_099_jr_8015C32C.o,tail14.data.o,ov_SC03_099_jr_8016AB6C.o,tail15.data.o,ov_SC03_099_jr_80171B4C.o,ov_SC03_099_jr_801734BC.o,tail16.data.o,ov_SC03_099_jr_801789AC.o,ov_SC03_099_jr_80178D40.o,tail17.data.o,ov_SC03_099_jr_8017A4AC.o,tail18.data.o,ov_SC03_099_jr_8017AE2C.o,ov_SC03_099_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_099/ov_SC03_099.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_099/ov_SC03_099_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_099/ov_SC03_099_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_099/ov_SC03_099_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_099/ov_SC03_099_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_099/ov_SC03_099_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_099/ov_SC03_099_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_099/ov_SC03_099_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_099/ov_SC03_099_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2099,12 +2159,13 @@ ov_SC03_100_ELF := $(ov_SC03_100_OUT).elf ov_SC03_100_MAPFILE := $(ov_SC03_100_OUT).map ov_SC03_100_LD_SCRIPT := $(ov_SC03_100_OUT).ld ov_SC03_100_SPLAT_YAML := config/splat.ov_SC03_100.yaml -ov_SC03_100_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_100.o,ov_SC03_100_jr_8012ACE0.o,tail2.data.o,ov_SC03_100_jr_80135888.o,tail3.data.o,ov_SC03_100_jr_80135A4C.o,tail4.data.o,ov_SC03_100_jr_80135D20.o,tail5.data.o,ov_SC03_100_jr_801380E0.o,ov_SC03_100_o0c.o,tail6.data.o,ov_SC03_100_jr_8013F350.o,tail7.data.o,ov_SC03_100_jr_8013FFD8.o,tail8.data.o,ov_SC03_100_jr_80140608.o,tail9.data.o,ov_SC03_100_jr_8015444C.o,tail10.data.o,ov_SC03_100_jr_80154C24.o,ov_SC03_100_jr_801588CC.o,tail11.data.o,ov_SC03_100_jr_80159C84.o,tail12.data.o,ov_SC03_100_jr_8015A3C8.o,tail13.data.o,ov_SC03_100_jr_8015AE2C.o,tail14.data.o,ov_SC03_100_jr_8015C32C.o,tail15.data.o,ov_SC03_100_jr_8016AB6C.o,tail16.data.o,ov_SC03_100_jr_80171B4C.o,ov_SC03_100_jr_801734BC.o,tail17.data.o,ov_SC03_100_jr_801789AC.o,ov_SC03_100_jr_80178D40.o,tail18.data.o,ov_SC03_100_jr_8017A4AC.o,tail19.data.o,ov_SC03_100_jr_8017AE2C.o,ov_SC03_100_jr_8017D898.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_100_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_100.o,ov_SC03_100_jr_8012ACE0.o,tail2.data.o,ov_SC03_100_jr_80135888.o,tail3.data.o,ov_SC03_100_jr_80135A4C.o,tail4.data.o,ov_SC03_100_jr_80135D20.o,tail5.data.o,ov_SC03_100_jr_801380E0.o,ov_SC03_100_o0c.o,tail6.data.o,ov_SC03_100_jr_8013F350.o,tail7.data.o,ov_SC03_100_jr_8013FFD8.o,tail8.data.o,ov_SC03_100_jr_80140608.o,tail9.data.o,ov_SC03_100_jr_8015444C.o,ov_SC03_100_jr_80154C24.o,ov_SC03_100_jr_801588CC.o,tail10.data.o,ov_SC03_100_jr_80159C84.o,tail11.data.o,ov_SC03_100_jr_8015A3C8.o,tail12.data.o,ov_SC03_100_jr_8015AE2C.o,tail13.data.o,ov_SC03_100_jr_8015C32C.o,tail14.data.o,ov_SC03_100_jr_8016AB6C.o,tail15.data.o,ov_SC03_100_jr_80171B4C.o,ov_SC03_100_jr_801734BC.o,tail16.data.o,ov_SC03_100_jr_801789AC.o,ov_SC03_100_jr_80178D40.o,tail17.data.o,ov_SC03_100_jr_8017A4AC.o,tail18.data.o,ov_SC03_100_jr_8017AE2C.o,ov_SC03_100_jr_8017D898.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_100/ov_SC03_100.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_100/ov_SC03_100_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_100/ov_SC03_100_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_100/ov_SC03_100_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_100/ov_SC03_100_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_100/ov_SC03_100_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_100/ov_SC03_100_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_100/ov_SC03_100_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_100/ov_SC03_100_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2133,12 +2194,13 @@ ov_SC03_101_ELF := $(ov_SC03_101_OUT).elf ov_SC03_101_MAPFILE := $(ov_SC03_101_OUT).map ov_SC03_101_LD_SCRIPT := $(ov_SC03_101_OUT).ld ov_SC03_101_SPLAT_YAML := config/splat.ov_SC03_101.yaml -ov_SC03_101_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_101.o,ov_SC03_101_jr_8012ACE0.o,tail2.data.o,ov_SC03_101_jr_80135888.o,tail3.data.o,ov_SC03_101_jr_80135A4C.o,tail4.data.o,ov_SC03_101_jr_80135D20.o,tail5.data.o,ov_SC03_101_jr_801380E0.o,ov_SC03_101_o0c.o,tail6.data.o,ov_SC03_101_jr_8013F350.o,tail7.data.o,ov_SC03_101_jr_8013FFD8.o,tail8.data.o,ov_SC03_101_jr_80140608.o,tail9.data.o,ov_SC03_101_jr_8015444C.o,tail10.data.o,ov_SC03_101_jr_80154C24.o,ov_SC03_101_jr_801588CC.o,tail11.data.o,ov_SC03_101_jr_80159C84.o,tail12.data.o,ov_SC03_101_jr_8015A3C8.o,tail13.data.o,ov_SC03_101_jr_8015AE2C.o,tail14.data.o,ov_SC03_101_jr_8015C32C.o,tail15.data.o,ov_SC03_101_jr_8016AB6C.o,tail16.data.o,ov_SC03_101_jr_80171B4C.o,ov_SC03_101_jr_801734BC.o,tail17.data.o,ov_SC03_101_jr_801789AC.o,ov_SC03_101_jr_80178D40.o,tail18.data.o,ov_SC03_101_jr_8017A4AC.o,tail19.data.o,ov_SC03_101_jr_8017AE2C.o,ov_SC03_101_jr_8017CA80.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_101_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_101.o,ov_SC03_101_jr_8012ACE0.o,tail2.data.o,ov_SC03_101_jr_80135888.o,tail3.data.o,ov_SC03_101_jr_80135A4C.o,tail4.data.o,ov_SC03_101_jr_80135D20.o,tail5.data.o,ov_SC03_101_jr_801380E0.o,ov_SC03_101_o0c.o,tail6.data.o,ov_SC03_101_jr_8013F350.o,tail7.data.o,ov_SC03_101_jr_8013FFD8.o,tail8.data.o,ov_SC03_101_jr_80140608.o,tail9.data.o,ov_SC03_101_jr_8015444C.o,ov_SC03_101_jr_80154C24.o,ov_SC03_101_jr_801588CC.o,tail10.data.o,ov_SC03_101_jr_80159C84.o,tail11.data.o,ov_SC03_101_jr_8015A3C8.o,tail12.data.o,ov_SC03_101_jr_8015AE2C.o,tail13.data.o,ov_SC03_101_jr_8015C32C.o,tail14.data.o,ov_SC03_101_jr_8016AB6C.o,tail15.data.o,ov_SC03_101_jr_80171B4C.o,ov_SC03_101_jr_801734BC.o,tail16.data.o,ov_SC03_101_jr_801789AC.o,ov_SC03_101_jr_80178D40.o,tail17.data.o,ov_SC03_101_jr_8017A4AC.o,tail18.data.o,ov_SC03_101_jr_8017AE2C.o,ov_SC03_101_jr_8017CA80.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_101/ov_SC03_101.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_101/ov_SC03_101_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_101/ov_SC03_101_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_101/ov_SC03_101_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_101/ov_SC03_101_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_101/ov_SC03_101_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_101/ov_SC03_101_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_101/ov_SC03_101_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_101/ov_SC03_101_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2167,12 +2229,13 @@ ov_SC03_102_ELF := $(ov_SC03_102_OUT).elf ov_SC03_102_MAPFILE := $(ov_SC03_102_OUT).map ov_SC03_102_LD_SCRIPT := $(ov_SC03_102_OUT).ld ov_SC03_102_SPLAT_YAML := config/splat.ov_SC03_102.yaml -ov_SC03_102_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_102.o,ov_SC03_102_jr_8012ACE0.o,tail2.data.o,ov_SC03_102_jr_80135888.o,tail3.data.o,ov_SC03_102_jr_80135A4C.o,tail4.data.o,ov_SC03_102_jr_80135D20.o,tail5.data.o,ov_SC03_102_jr_801380E0.o,ov_SC03_102_o0c.o,tail6.data.o,ov_SC03_102_jr_8013F350.o,tail7.data.o,ov_SC03_102_jr_8013FFD8.o,tail8.data.o,ov_SC03_102_jr_80140608.o,tail9.data.o,ov_SC03_102_jr_8015444C.o,tail10.data.o,ov_SC03_102_jr_80154C24.o,ov_SC03_102_jr_801588CC.o,tail11.data.o,ov_SC03_102_jr_80159C84.o,tail12.data.o,ov_SC03_102_jr_8015A3C8.o,tail13.data.o,ov_SC03_102_jr_8015AE2C.o,tail14.data.o,ov_SC03_102_jr_8015C32C.o,tail15.data.o,ov_SC03_102_jr_8016AB6C.o,tail16.data.o,ov_SC03_102_jr_80171B4C.o,ov_SC03_102_jr_801734BC.o,tail17.data.o,ov_SC03_102_jr_801789AC.o,ov_SC03_102_jr_80178D40.o,tail18.data.o,ov_SC03_102_jr_8017A4AC.o,tail19.data.o,ov_SC03_102_jr_8017AE2C.o,ov_SC03_102_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_102_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_102.o,ov_SC03_102_jr_8012ACE0.o,tail2.data.o,ov_SC03_102_jr_80135888.o,tail3.data.o,ov_SC03_102_jr_80135A4C.o,tail4.data.o,ov_SC03_102_jr_80135D20.o,tail5.data.o,ov_SC03_102_jr_801380E0.o,ov_SC03_102_o0c.o,tail6.data.o,ov_SC03_102_jr_8013F350.o,tail7.data.o,ov_SC03_102_jr_8013FFD8.o,tail8.data.o,ov_SC03_102_jr_80140608.o,tail9.data.o,ov_SC03_102_jr_8015444C.o,ov_SC03_102_jr_80154C24.o,ov_SC03_102_jr_801588CC.o,tail10.data.o,ov_SC03_102_jr_80159C84.o,tail11.data.o,ov_SC03_102_jr_8015A3C8.o,tail12.data.o,ov_SC03_102_jr_8015AE2C.o,tail13.data.o,ov_SC03_102_jr_8015C32C.o,tail14.data.o,ov_SC03_102_jr_8016AB6C.o,tail15.data.o,ov_SC03_102_jr_80171B4C.o,ov_SC03_102_jr_801734BC.o,tail16.data.o,ov_SC03_102_jr_801789AC.o,ov_SC03_102_jr_80178D40.o,tail17.data.o,ov_SC03_102_jr_8017A4AC.o,tail18.data.o,ov_SC03_102_jr_8017AE2C.o,ov_SC03_102_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_102/ov_SC03_102.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_102/ov_SC03_102_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_102/ov_SC03_102_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_102/ov_SC03_102_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_102/ov_SC03_102_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_102/ov_SC03_102_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_102/ov_SC03_102_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_102/ov_SC03_102_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_102/ov_SC03_102_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2201,12 +2264,13 @@ ov_SC03_103_ELF := $(ov_SC03_103_OUT).elf ov_SC03_103_MAPFILE := $(ov_SC03_103_OUT).map ov_SC03_103_LD_SCRIPT := $(ov_SC03_103_OUT).ld ov_SC03_103_SPLAT_YAML := config/splat.ov_SC03_103.yaml -ov_SC03_103_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_103.o,ov_SC03_103_jr_8012ACE0.o,tail2.data.o,ov_SC03_103_jr_80135888.o,tail3.data.o,ov_SC03_103_jr_80135A4C.o,tail4.data.o,ov_SC03_103_jr_80135D20.o,tail5.data.o,ov_SC03_103_jr_801380E0.o,ov_SC03_103_o0c.o,tail6.data.o,ov_SC03_103_jr_8013F350.o,tail7.data.o,ov_SC03_103_jr_8014032C.o,tail8.data.o,ov_SC03_103_jr_80140608.o,tail9.data.o,ov_SC03_103_jr_8015444C.o,tail10.data.o,ov_SC03_103_jr_80154C24.o,ov_SC03_103_jr_801588CC.o,tail11.data.o,ov_SC03_103_jr_80159C84.o,tail12.data.o,ov_SC03_103_jr_8015A3C8.o,tail13.data.o,ov_SC03_103_jr_8015AE2C.o,tail14.data.o,ov_SC03_103_jr_8015C32C.o,tail15.data.o,ov_SC03_103_jr_8016AB6C.o,tail16.data.o,ov_SC03_103_jr_80171B4C.o,ov_SC03_103_jr_801734BC.o,tail17.data.o,ov_SC03_103_jr_801789AC.o,ov_SC03_103_jr_80178D40.o,tail18.data.o,ov_SC03_103_jr_8017A4AC.o,tail19.data.o,ov_SC03_103_jr_8017AE2C.o,ov_SC03_103_jr_8017C294.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_103_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_103.o,ov_SC03_103_jr_8012ACE0.o,tail2.data.o,ov_SC03_103_jr_80135888.o,tail3.data.o,ov_SC03_103_jr_80135A4C.o,tail4.data.o,ov_SC03_103_jr_80135D20.o,tail5.data.o,ov_SC03_103_jr_801380E0.o,ov_SC03_103_o0c.o,tail6.data.o,ov_SC03_103_jr_8013F350.o,tail7.data.o,ov_SC03_103_jr_8014032C.o,tail8.data.o,ov_SC03_103_jr_80140608.o,tail9.data.o,ov_SC03_103_jr_8015444C.o,ov_SC03_103_jr_80154C24.o,ov_SC03_103_jr_801588CC.o,tail10.data.o,ov_SC03_103_jr_80159C84.o,tail11.data.o,ov_SC03_103_jr_8015A3C8.o,tail12.data.o,ov_SC03_103_jr_8015AE2C.o,tail13.data.o,ov_SC03_103_jr_8015C32C.o,tail14.data.o,ov_SC03_103_jr_8016AB6C.o,tail15.data.o,ov_SC03_103_jr_80171B4C.o,ov_SC03_103_jr_801734BC.o,tail16.data.o,ov_SC03_103_jr_801789AC.o,ov_SC03_103_jr_80178D40.o,tail17.data.o,ov_SC03_103_jr_8017A4AC.o,tail18.data.o,ov_SC03_103_jr_8017AE2C.o,ov_SC03_103_jr_8017C294.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_103/ov_SC03_103.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_103/ov_SC03_103_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_103/ov_SC03_103_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_103/ov_SC03_103_jr_8013F350.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 build/src/ov_SC03_103/ov_SC03_103_jr_8014032C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC03_103/ov_SC03_103_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_103/ov_SC03_103_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_103/ov_SC03_103_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_103/ov_SC03_103_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2235,12 +2299,13 @@ ov_SC03_104_ELF := $(ov_SC03_104_OUT).elf ov_SC03_104_MAPFILE := $(ov_SC03_104_OUT).map ov_SC03_104_LD_SCRIPT := $(ov_SC03_104_OUT).ld ov_SC03_104_SPLAT_YAML := config/splat.ov_SC03_104.yaml -ov_SC03_104_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_104.o,ov_SC03_104_jr_8012ACE0.o,tail2.data.o,ov_SC03_104_jr_80135888.o,tail3.data.o,ov_SC03_104_jr_80135A4C.o,tail4.data.o,ov_SC03_104_jr_80135D20.o,tail5.data.o,ov_SC03_104_jr_801380E0.o,ov_SC03_104_o0c.o,tail6.data.o,ov_SC03_104_jr_8013F350.o,tail7.data.o,ov_SC03_104_jr_8013FFD8.o,tail8.data.o,ov_SC03_104_jr_80140608.o,tail9.data.o,ov_SC03_104_jr_8015444C.o,tail10.data.o,ov_SC03_104_jr_80154C24.o,ov_SC03_104_jr_801588CC.o,tail11.data.o,ov_SC03_104_jr_80159C84.o,tail12.data.o,ov_SC03_104_jr_8015A3C8.o,tail13.data.o,ov_SC03_104_jr_8015AE2C.o,tail14.data.o,ov_SC03_104_jr_8015C32C.o,tail15.data.o,ov_SC03_104_jr_8016AB6C.o,tail16.data.o,ov_SC03_104_jr_80171B4C.o,ov_SC03_104_jr_801734BC.o,tail17.data.o,ov_SC03_104_jr_801789AC.o,ov_SC03_104_jr_80178D40.o,tail18.data.o,ov_SC03_104_jr_8017A4AC.o,tail19.data.o,ov_SC03_104_jr_8017AE2C.o,ov_SC03_104_jr_8017CA80.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_104_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_104.o,ov_SC03_104_jr_8012ACE0.o,tail2.data.o,ov_SC03_104_jr_80135888.o,tail3.data.o,ov_SC03_104_jr_80135A4C.o,tail4.data.o,ov_SC03_104_jr_80135D20.o,tail5.data.o,ov_SC03_104_jr_801380E0.o,ov_SC03_104_o0c.o,tail6.data.o,ov_SC03_104_jr_8013F350.o,tail7.data.o,ov_SC03_104_jr_8013FFD8.o,tail8.data.o,ov_SC03_104_jr_80140608.o,tail9.data.o,ov_SC03_104_jr_8015444C.o,ov_SC03_104_jr_80154C24.o,ov_SC03_104_jr_801588CC.o,tail10.data.o,ov_SC03_104_jr_80159C84.o,tail11.data.o,ov_SC03_104_jr_8015A3C8.o,tail12.data.o,ov_SC03_104_jr_8015AE2C.o,tail13.data.o,ov_SC03_104_jr_8015C32C.o,tail14.data.o,ov_SC03_104_jr_8016AB6C.o,tail15.data.o,ov_SC03_104_jr_80171B4C.o,ov_SC03_104_jr_801734BC.o,tail16.data.o,ov_SC03_104_jr_801789AC.o,ov_SC03_104_jr_80178D40.o,tail17.data.o,ov_SC03_104_jr_8017A4AC.o,tail18.data.o,ov_SC03_104_jr_8017AE2C.o,ov_SC03_104_jr_8017CA80.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_104/ov_SC03_104.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_104/ov_SC03_104_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_104/ov_SC03_104_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_104/ov_SC03_104_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_104/ov_SC03_104_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_104/ov_SC03_104_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_104/ov_SC03_104_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_104/ov_SC03_104_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_104/ov_SC03_104_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2269,12 +2334,13 @@ ov_SC03_105_ELF := $(ov_SC03_105_OUT).elf ov_SC03_105_MAPFILE := $(ov_SC03_105_OUT).map ov_SC03_105_LD_SCRIPT := $(ov_SC03_105_OUT).ld ov_SC03_105_SPLAT_YAML := config/splat.ov_SC03_105.yaml -ov_SC03_105_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_105.o,ov_SC03_105_jr_8012ACE0.o,tail2.data.o,ov_SC03_105_jr_80135888.o,tail3.data.o,ov_SC03_105_jr_80135A4C.o,tail4.data.o,ov_SC03_105_jr_80135D20.o,tail5.data.o,ov_SC03_105_jr_801380E0.o,ov_SC03_105_o0c.o,tail6.data.o,ov_SC03_105_jr_8013F350.o,tail7.data.o,ov_SC03_105_jr_8013FFD8.o,tail8.data.o,ov_SC03_105_jr_80140608.o,tail9.data.o,ov_SC03_105_jr_8015444C.o,tail10.data.o,ov_SC03_105_jr_80154C24.o,ov_SC03_105_jr_801588CC.o,tail11.data.o,ov_SC03_105_jr_80159C84.o,tail12.data.o,ov_SC03_105_jr_8015A3C8.o,tail13.data.o,ov_SC03_105_jr_8015AE2C.o,tail14.data.o,ov_SC03_105_jr_8015C32C.o,tail15.data.o,ov_SC03_105_jr_8016AB6C.o,tail16.data.o,ov_SC03_105_jr_80171B4C.o,ov_SC03_105_jr_801734BC.o,tail17.data.o,ov_SC03_105_jr_801789AC.o,ov_SC03_105_jr_80178D40.o,tail18.data.o,ov_SC03_105_jr_8017A4AC.o,tail19.data.o,ov_SC03_105_jr_8017AE2C.o,tail20.data.o,ov_SC03_105_jr_8017C8D0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_105_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_105.o,ov_SC03_105_jr_8012ACE0.o,tail2.data.o,ov_SC03_105_jr_80135888.o,tail3.data.o,ov_SC03_105_jr_80135A4C.o,tail4.data.o,ov_SC03_105_jr_80135D20.o,tail5.data.o,ov_SC03_105_jr_801380E0.o,ov_SC03_105_o0c.o,tail6.data.o,ov_SC03_105_jr_8013F350.o,tail7.data.o,ov_SC03_105_jr_8013FFD8.o,tail8.data.o,ov_SC03_105_jr_80140608.o,tail9.data.o,ov_SC03_105_jr_8015444C.o,ov_SC03_105_jr_80154C24.o,ov_SC03_105_jr_801588CC.o,tail10.data.o,ov_SC03_105_jr_80159C84.o,tail11.data.o,ov_SC03_105_jr_8015A3C8.o,tail12.data.o,ov_SC03_105_jr_8015AE2C.o,tail13.data.o,ov_SC03_105_jr_8015C32C.o,tail14.data.o,ov_SC03_105_jr_8016AB6C.o,tail15.data.o,ov_SC03_105_jr_80171B4C.o,ov_SC03_105_jr_801734BC.o,tail16.data.o,ov_SC03_105_jr_801789AC.o,ov_SC03_105_jr_80178D40.o,tail17.data.o,ov_SC03_105_jr_8017A4AC.o,tail18.data.o,ov_SC03_105_jr_8017AE2C.o,tail19.data.o,ov_SC03_105_jr_8017C8D0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_105/ov_SC03_105.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_105/ov_SC03_105_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_105/ov_SC03_105_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_105/ov_SC03_105_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_105/ov_SC03_105_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_105/ov_SC03_105_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_105/ov_SC03_105_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_105/ov_SC03_105_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_105/ov_SC03_105_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2303,12 +2369,13 @@ ov_SC03_108_ELF := $(ov_SC03_108_OUT).elf ov_SC03_108_MAPFILE := $(ov_SC03_108_OUT).map ov_SC03_108_LD_SCRIPT := $(ov_SC03_108_OUT).ld ov_SC03_108_SPLAT_YAML := config/splat.ov_SC03_108.yaml -ov_SC03_108_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_108.o,ov_SC03_108_jr_8012ACE0.o,tail2.data.o,ov_SC03_108_jr_80135888.o,tail3.data.o,ov_SC03_108_jr_80135A4C.o,tail4.data.o,ov_SC03_108_jr_80135D20.o,tail5.data.o,ov_SC03_108_jr_801380E0.o,ov_SC03_108_o0c.o,tail6.data.o,ov_SC03_108_jr_8013F350.o,tail7.data.o,ov_SC03_108_jr_8013FFD8.o,tail8.data.o,ov_SC03_108_jr_80140608.o,tail9.data.o,ov_SC03_108_jr_8015444C.o,tail10.data.o,ov_SC03_108_jr_80154C24.o,ov_SC03_108_jr_801588CC.o,tail11.data.o,ov_SC03_108_jr_80159C84.o,tail12.data.o,ov_SC03_108_jr_8015A3C8.o,tail13.data.o,ov_SC03_108_jr_8015AE2C.o,tail14.data.o,ov_SC03_108_jr_8015C32C.o,tail15.data.o,ov_SC03_108_jr_8016AB6C.o,tail16.data.o,ov_SC03_108_jr_80171B4C.o,ov_SC03_108_jr_801734BC.o,tail17.data.o,ov_SC03_108_jr_801789AC.o,ov_SC03_108_jr_80178D40.o,tail18.data.o,ov_SC03_108_jr_8017A4AC.o,tail19.data.o,ov_SC03_108_jr_8017AE2C.o,ov_SC03_108_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_108_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_108.o,ov_SC03_108_jr_8012ACE0.o,tail2.data.o,ov_SC03_108_jr_80135888.o,tail3.data.o,ov_SC03_108_jr_80135A4C.o,tail4.data.o,ov_SC03_108_jr_80135D20.o,tail5.data.o,ov_SC03_108_jr_801380E0.o,ov_SC03_108_o0c.o,tail6.data.o,ov_SC03_108_jr_8013F350.o,tail7.data.o,ov_SC03_108_jr_8013FFD8.o,tail8.data.o,ov_SC03_108_jr_80140608.o,tail9.data.o,ov_SC03_108_jr_8015444C.o,ov_SC03_108_jr_80154C24.o,ov_SC03_108_jr_801588CC.o,tail10.data.o,ov_SC03_108_jr_80159C84.o,tail11.data.o,ov_SC03_108_jr_8015A3C8.o,tail12.data.o,ov_SC03_108_jr_8015AE2C.o,tail13.data.o,ov_SC03_108_jr_8015C32C.o,tail14.data.o,ov_SC03_108_jr_8016AB6C.o,tail15.data.o,ov_SC03_108_jr_80171B4C.o,ov_SC03_108_jr_801734BC.o,tail16.data.o,ov_SC03_108_jr_801789AC.o,ov_SC03_108_jr_80178D40.o,tail17.data.o,ov_SC03_108_jr_8017A4AC.o,tail18.data.o,ov_SC03_108_jr_8017AE2C.o,ov_SC03_108_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_108/ov_SC03_108.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_108/ov_SC03_108_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_108/ov_SC03_108_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_108/ov_SC03_108_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_108/ov_SC03_108_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_108/ov_SC03_108_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_108/ov_SC03_108_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_108/ov_SC03_108_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_108/ov_SC03_108_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2336,12 +2403,13 @@ ov_SC03_109_ELF := $(ov_SC03_109_OUT).elf ov_SC03_109_MAPFILE := $(ov_SC03_109_OUT).map ov_SC03_109_LD_SCRIPT := $(ov_SC03_109_OUT).ld ov_SC03_109_SPLAT_YAML := config/splat.ov_SC03_109.yaml -ov_SC03_109_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_109.o,ov_SC03_109_jr_8012ACE0.o,tail2.data.o,ov_SC03_109_jr_80135888.o,tail3.data.o,ov_SC03_109_jr_80135A4C.o,tail4.data.o,ov_SC03_109_jr_80135D20.o,tail5.data.o,ov_SC03_109_jr_801380E0.o,ov_SC03_109_o0c.o,tail6.data.o,ov_SC03_109_jr_8013F350.o,tail7.data.o,ov_SC03_109_jr_8013FFD8.o,tail8.data.o,ov_SC03_109_jr_80140608.o,tail9.data.o,ov_SC03_109_jr_8015444C.o,tail10.data.o,ov_SC03_109_jr_80154C24.o,ov_SC03_109_jr_801588CC.o,tail11.data.o,ov_SC03_109_jr_80159C84.o,tail12.data.o,ov_SC03_109_jr_8015A3C8.o,tail13.data.o,ov_SC03_109_jr_8015AE2C.o,tail14.data.o,ov_SC03_109_jr_8015C32C.o,tail15.data.o,ov_SC03_109_jr_8016AB6C.o,tail16.data.o,ov_SC03_109_jr_80171B4C.o,ov_SC03_109_jr_801734BC.o,tail17.data.o,ov_SC03_109_jr_801789AC.o,ov_SC03_109_jr_80178D40.o,tail18.data.o,ov_SC03_109_jr_8017A4AC.o,tail19.data.o,ov_SC03_109_jr_8017AE2C.o,ov_SC03_109_jr_8017C180.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_109_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_109.o,ov_SC03_109_jr_8012ACE0.o,tail2.data.o,ov_SC03_109_jr_80135888.o,tail3.data.o,ov_SC03_109_jr_80135A4C.o,tail4.data.o,ov_SC03_109_jr_80135D20.o,tail5.data.o,ov_SC03_109_jr_801380E0.o,ov_SC03_109_o0c.o,tail6.data.o,ov_SC03_109_jr_8013F350.o,tail7.data.o,ov_SC03_109_jr_8013FFD8.o,tail8.data.o,ov_SC03_109_jr_80140608.o,tail9.data.o,ov_SC03_109_jr_8015444C.o,ov_SC03_109_jr_80154C24.o,ov_SC03_109_jr_801588CC.o,tail10.data.o,ov_SC03_109_jr_80159C84.o,tail11.data.o,ov_SC03_109_jr_8015A3C8.o,tail12.data.o,ov_SC03_109_jr_8015AE2C.o,tail13.data.o,ov_SC03_109_jr_8015C32C.o,tail14.data.o,ov_SC03_109_jr_8016AB6C.o,tail15.data.o,ov_SC03_109_jr_80171B4C.o,ov_SC03_109_jr_801734BC.o,tail16.data.o,ov_SC03_109_jr_801789AC.o,ov_SC03_109_jr_80178D40.o,tail17.data.o,ov_SC03_109_jr_8017A4AC.o,tail18.data.o,ov_SC03_109_jr_8017AE2C.o,ov_SC03_109_jr_8017C180.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_109/ov_SC03_109.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_109/ov_SC03_109_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_109/ov_SC03_109_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_109/ov_SC03_109_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_109/ov_SC03_109_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_109/ov_SC03_109_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_109/ov_SC03_109_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_109/ov_SC03_109_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_109/ov_SC03_109_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2370,12 +2438,13 @@ ov_SC03_110_ELF := $(ov_SC03_110_OUT).elf ov_SC03_110_MAPFILE := $(ov_SC03_110_OUT).map ov_SC03_110_LD_SCRIPT := $(ov_SC03_110_OUT).ld ov_SC03_110_SPLAT_YAML := config/splat.ov_SC03_110.yaml -ov_SC03_110_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_110.o,ov_SC03_110_jr_8012ACE0.o,tail2.data.o,ov_SC03_110_jr_80135888.o,tail3.data.o,ov_SC03_110_jr_80135A4C.o,tail4.data.o,ov_SC03_110_jr_80135D20.o,tail5.data.o,ov_SC03_110_jr_801380E0.o,ov_SC03_110_o0c.o,tail6.data.o,ov_SC03_110_jr_8013F350.o,tail7.data.o,ov_SC03_110_jr_8013FFD8.o,tail8.data.o,ov_SC03_110_jr_80140608.o,tail9.data.o,ov_SC03_110_jr_8015444C.o,tail10.data.o,ov_SC03_110_jr_80154C24.o,ov_SC03_110_jr_801588CC.o,tail11.data.o,ov_SC03_110_jr_80159C84.o,tail12.data.o,ov_SC03_110_jr_8015A3C8.o,tail13.data.o,ov_SC03_110_jr_8015AE2C.o,tail14.data.o,ov_SC03_110_jr_8015C32C.o,tail15.data.o,ov_SC03_110_jr_8016AB6C.o,tail16.data.o,ov_SC03_110_jr_80171B4C.o,ov_SC03_110_jr_801734BC.o,tail17.data.o,ov_SC03_110_jr_801789AC.o,ov_SC03_110_jr_80178D40.o,tail18.data.o,ov_SC03_110_jr_8017A4AC.o,tail19.data.o,ov_SC03_110_jr_8017AE2C.o,ov_SC03_110_jr_8017D898.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_110_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_110.o,ov_SC03_110_jr_8012ACE0.o,tail2.data.o,ov_SC03_110_jr_80135888.o,tail3.data.o,ov_SC03_110_jr_80135A4C.o,tail4.data.o,ov_SC03_110_jr_80135D20.o,tail5.data.o,ov_SC03_110_jr_801380E0.o,ov_SC03_110_o0c.o,tail6.data.o,ov_SC03_110_jr_8013F350.o,tail7.data.o,ov_SC03_110_jr_8013FFD8.o,tail8.data.o,ov_SC03_110_jr_80140608.o,tail9.data.o,ov_SC03_110_jr_8015444C.o,ov_SC03_110_jr_80154C24.o,ov_SC03_110_jr_801588CC.o,tail10.data.o,ov_SC03_110_jr_80159C84.o,tail11.data.o,ov_SC03_110_jr_8015A3C8.o,tail12.data.o,ov_SC03_110_jr_8015AE2C.o,tail13.data.o,ov_SC03_110_jr_8015C32C.o,tail14.data.o,ov_SC03_110_jr_8016AB6C.o,tail15.data.o,ov_SC03_110_jr_80171B4C.o,ov_SC03_110_jr_801734BC.o,tail16.data.o,ov_SC03_110_jr_801789AC.o,ov_SC03_110_jr_80178D40.o,tail17.data.o,ov_SC03_110_jr_8017A4AC.o,tail18.data.o,ov_SC03_110_jr_8017AE2C.o,ov_SC03_110_jr_8017D898.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_110/ov_SC03_110.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_110/ov_SC03_110_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_110/ov_SC03_110_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_110/ov_SC03_110_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_110/ov_SC03_110_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_110/ov_SC03_110_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_110/ov_SC03_110_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_110/ov_SC03_110_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_110/ov_SC03_110_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2404,12 +2473,13 @@ ov_SC03_111_ELF := $(ov_SC03_111_OUT).elf ov_SC03_111_MAPFILE := $(ov_SC03_111_OUT).map ov_SC03_111_LD_SCRIPT := $(ov_SC03_111_OUT).ld ov_SC03_111_SPLAT_YAML := config/splat.ov_SC03_111.yaml -ov_SC03_111_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_111.o,ov_SC03_111_jr_8012ACE0.o,tail2.data.o,ov_SC03_111_jr_80135888.o,tail3.data.o,ov_SC03_111_jr_80135A4C.o,tail4.data.o,ov_SC03_111_jr_80135D20.o,tail5.data.o,ov_SC03_111_jr_801380E0.o,ov_SC03_111_o0c.o,tail6.data.o,ov_SC03_111_jr_8013F350.o,tail7.data.o,ov_SC03_111_jr_8013FFD8.o,tail8.data.o,ov_SC03_111_jr_80140608.o,tail9.data.o,ov_SC03_111_jr_8015444C.o,tail10.data.o,ov_SC03_111_jr_80154C24.o,ov_SC03_111_jr_801588CC.o,tail11.data.o,ov_SC03_111_jr_80159C84.o,tail12.data.o,ov_SC03_111_jr_8015A3C8.o,tail13.data.o,ov_SC03_111_jr_8015AE2C.o,tail14.data.o,ov_SC03_111_jr_8015C32C.o,tail15.data.o,ov_SC03_111_jr_8016AB6C.o,tail16.data.o,ov_SC03_111_jr_80171B4C.o,ov_SC03_111_jr_801734BC.o,tail17.data.o,ov_SC03_111_jr_801789AC.o,ov_SC03_111_jr_80178D40.o,tail18.data.o,ov_SC03_111_jr_8017A4AC.o,tail19.data.o,ov_SC03_111_jr_8017AE2C.o,ov_SC03_111_jr_8017EC58.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_111_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_111.o,ov_SC03_111_jr_8012ACE0.o,tail2.data.o,ov_SC03_111_jr_80135888.o,tail3.data.o,ov_SC03_111_jr_80135A4C.o,tail4.data.o,ov_SC03_111_jr_80135D20.o,tail5.data.o,ov_SC03_111_jr_801380E0.o,ov_SC03_111_o0c.o,tail6.data.o,ov_SC03_111_jr_8013F350.o,tail7.data.o,ov_SC03_111_jr_8013FFD8.o,tail8.data.o,ov_SC03_111_jr_80140608.o,tail9.data.o,ov_SC03_111_jr_8015444C.o,ov_SC03_111_jr_80154C24.o,ov_SC03_111_jr_801588CC.o,tail10.data.o,ov_SC03_111_jr_80159C84.o,tail11.data.o,ov_SC03_111_jr_8015A3C8.o,tail12.data.o,ov_SC03_111_jr_8015AE2C.o,tail13.data.o,ov_SC03_111_jr_8015C32C.o,tail14.data.o,ov_SC03_111_jr_8016AB6C.o,tail15.data.o,ov_SC03_111_jr_80171B4C.o,ov_SC03_111_jr_801734BC.o,tail16.data.o,ov_SC03_111_jr_801789AC.o,ov_SC03_111_jr_80178D40.o,tail17.data.o,ov_SC03_111_jr_8017A4AC.o,tail18.data.o,ov_SC03_111_jr_8017AE2C.o,ov_SC03_111_jr_8017EC58.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_111/ov_SC03_111.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_111/ov_SC03_111_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_111/ov_SC03_111_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_111/ov_SC03_111_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_111/ov_SC03_111_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_111/ov_SC03_111_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_111/ov_SC03_111_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_111/ov_SC03_111_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_111/ov_SC03_111_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2438,12 +2508,13 @@ ov_SC03_112_ELF := $(ov_SC03_112_OUT).elf ov_SC03_112_MAPFILE := $(ov_SC03_112_OUT).map ov_SC03_112_LD_SCRIPT := $(ov_SC03_112_OUT).ld ov_SC03_112_SPLAT_YAML := config/splat.ov_SC03_112.yaml -ov_SC03_112_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_112.o,ov_SC03_112_jr_8012ACE0.o,tail2.data.o,ov_SC03_112_jr_80135888.o,tail3.data.o,ov_SC03_112_jr_80135A4C.o,tail4.data.o,ov_SC03_112_jr_80135D20.o,tail5.data.o,ov_SC03_112_jr_801380E0.o,ov_SC03_112_o0c.o,tail6.data.o,ov_SC03_112_jr_8013F350.o,tail7.data.o,ov_SC03_112_jr_8013FFD8.o,tail8.data.o,ov_SC03_112_jr_80140608.o,tail9.data.o,ov_SC03_112_jr_8015444C.o,tail10.data.o,ov_SC03_112_jr_80154C24.o,ov_SC03_112_jr_801588CC.o,tail11.data.o,ov_SC03_112_jr_80159C84.o,tail12.data.o,ov_SC03_112_jr_8015A3C8.o,tail13.data.o,ov_SC03_112_jr_8015AE2C.o,tail14.data.o,ov_SC03_112_jr_8015C32C.o,tail15.data.o,ov_SC03_112_jr_8016AB6C.o,tail16.data.o,ov_SC03_112_jr_80171B4C.o,ov_SC03_112_jr_801734BC.o,tail17.data.o,ov_SC03_112_jr_801789AC.o,ov_SC03_112_jr_80178D40.o,tail18.data.o,ov_SC03_112_jr_8017A4AC.o,tail19.data.o,ov_SC03_112_jr_8017AE2C.o,ov_SC03_112_jr_8017C294.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_112_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_112.o,ov_SC03_112_jr_8012ACE0.o,tail2.data.o,ov_SC03_112_jr_80135888.o,tail3.data.o,ov_SC03_112_jr_80135A4C.o,tail4.data.o,ov_SC03_112_jr_80135D20.o,tail5.data.o,ov_SC03_112_jr_801380E0.o,ov_SC03_112_o0c.o,tail6.data.o,ov_SC03_112_jr_8013F350.o,tail7.data.o,ov_SC03_112_jr_8013FFD8.o,tail8.data.o,ov_SC03_112_jr_80140608.o,tail9.data.o,ov_SC03_112_jr_8015444C.o,ov_SC03_112_jr_80154C24.o,ov_SC03_112_jr_801588CC.o,tail10.data.o,ov_SC03_112_jr_80159C84.o,tail11.data.o,ov_SC03_112_jr_8015A3C8.o,tail12.data.o,ov_SC03_112_jr_8015AE2C.o,tail13.data.o,ov_SC03_112_jr_8015C32C.o,tail14.data.o,ov_SC03_112_jr_8016AB6C.o,tail15.data.o,ov_SC03_112_jr_80171B4C.o,ov_SC03_112_jr_801734BC.o,tail16.data.o,ov_SC03_112_jr_801789AC.o,ov_SC03_112_jr_80178D40.o,tail17.data.o,ov_SC03_112_jr_8017A4AC.o,tail18.data.o,ov_SC03_112_jr_8017AE2C.o,ov_SC03_112_jr_8017C294.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_112/ov_SC03_112.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_112/ov_SC03_112_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_112/ov_SC03_112_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_112/ov_SC03_112_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_112/ov_SC03_112_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_112/ov_SC03_112_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_112/ov_SC03_112_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_112/ov_SC03_112_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_112/ov_SC03_112_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2472,12 +2543,13 @@ ov_SC03_113_ELF := $(ov_SC03_113_OUT).elf ov_SC03_113_MAPFILE := $(ov_SC03_113_OUT).map ov_SC03_113_LD_SCRIPT := $(ov_SC03_113_OUT).ld ov_SC03_113_SPLAT_YAML := config/splat.ov_SC03_113.yaml -ov_SC03_113_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_113.o,ov_SC03_113_jr_8012ACE0.o,tail2.data.o,ov_SC03_113_jr_80135888.o,tail3.data.o,ov_SC03_113_jr_80135A4C.o,tail4.data.o,ov_SC03_113_jr_80135D20.o,tail5.data.o,ov_SC03_113_jr_801380E0.o,ov_SC03_113_o0c.o,tail6.data.o,ov_SC03_113_jr_8013F350.o,tail7.data.o,ov_SC03_113_jr_8013FFD8.o,tail8.data.o,ov_SC03_113_jr_80140608.o,tail9.data.o,ov_SC03_113_jr_8015444C.o,tail10.data.o,ov_SC03_113_jr_80154C24.o,ov_SC03_113_jr_801588CC.o,tail11.data.o,ov_SC03_113_jr_80159C84.o,tail12.data.o,ov_SC03_113_jr_8015A3C8.o,tail13.data.o,ov_SC03_113_jr_8015AE2C.o,tail14.data.o,ov_SC03_113_jr_8015C32C.o,tail15.data.o,ov_SC03_113_jr_8016AB6C.o,tail16.data.o,ov_SC03_113_jr_80171B4C.o,ov_SC03_113_jr_801734BC.o,tail17.data.o,ov_SC03_113_jr_801789AC.o,ov_SC03_113_jr_80178D40.o,tail18.data.o,ov_SC03_113_jr_8017A4AC.o,tail19.data.o,ov_SC03_113_jr_8017AE2C.o,ov_SC03_113_jr_8017C294.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_113_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_113.o,ov_SC03_113_jr_8012ACE0.o,tail2.data.o,ov_SC03_113_jr_80135888.o,tail3.data.o,ov_SC03_113_jr_80135A4C.o,tail4.data.o,ov_SC03_113_jr_80135D20.o,tail5.data.o,ov_SC03_113_jr_801380E0.o,ov_SC03_113_o0c.o,tail6.data.o,ov_SC03_113_jr_8013F350.o,tail7.data.o,ov_SC03_113_jr_8013FFD8.o,tail8.data.o,ov_SC03_113_jr_80140608.o,tail9.data.o,ov_SC03_113_jr_8015444C.o,ov_SC03_113_jr_80154C24.o,ov_SC03_113_jr_801588CC.o,tail10.data.o,ov_SC03_113_jr_80159C84.o,tail11.data.o,ov_SC03_113_jr_8015A3C8.o,tail12.data.o,ov_SC03_113_jr_8015AE2C.o,tail13.data.o,ov_SC03_113_jr_8015C32C.o,tail14.data.o,ov_SC03_113_jr_8016AB6C.o,tail15.data.o,ov_SC03_113_jr_80171B4C.o,ov_SC03_113_jr_801734BC.o,tail16.data.o,ov_SC03_113_jr_801789AC.o,ov_SC03_113_jr_80178D40.o,tail17.data.o,ov_SC03_113_jr_8017A4AC.o,tail18.data.o,ov_SC03_113_jr_8017AE2C.o,ov_SC03_113_jr_8017C294.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_113/ov_SC03_113.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_113/ov_SC03_113_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_113/ov_SC03_113_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_113/ov_SC03_113_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_113/ov_SC03_113_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_113/ov_SC03_113_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_113/ov_SC03_113_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_113/ov_SC03_113_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_113/ov_SC03_113_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2506,12 +2578,13 @@ ov_SC03_114_ELF := $(ov_SC03_114_OUT).elf ov_SC03_114_MAPFILE := $(ov_SC03_114_OUT).map ov_SC03_114_LD_SCRIPT := $(ov_SC03_114_OUT).ld ov_SC03_114_SPLAT_YAML := config/splat.ov_SC03_114.yaml -ov_SC03_114_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_114.o,ov_SC03_114_jr_8012ACE0.o,tail2.data.o,ov_SC03_114_jr_80135888.o,tail3.data.o,ov_SC03_114_jr_80135A4C.o,tail4.data.o,ov_SC03_114_jr_80135D20.o,tail5.data.o,ov_SC03_114_jr_801380E0.o,ov_SC03_114_o0c.o,tail6.data.o,ov_SC03_114_jr_8013F350.o,tail7.data.o,ov_SC03_114_jr_8013FFD8.o,tail8.data.o,ov_SC03_114_jr_80140608.o,tail9.data.o,ov_SC03_114_jr_8015444C.o,tail10.data.o,ov_SC03_114_jr_80154C24.o,ov_SC03_114_jr_801588CC.o,tail11.data.o,ov_SC03_114_jr_80159C84.o,tail12.data.o,ov_SC03_114_jr_8015A3C8.o,tail13.data.o,ov_SC03_114_jr_8015AE2C.o,tail14.data.o,ov_SC03_114_jr_8015C32C.o,tail15.data.o,ov_SC03_114_jr_8016AB6C.o,tail16.data.o,ov_SC03_114_jr_80171B4C.o,ov_SC03_114_jr_801734BC.o,tail17.data.o,ov_SC03_114_jr_801789AC.o,ov_SC03_114_jr_80178D40.o,tail18.data.o,ov_SC03_114_jr_8017A4AC.o,tail19.data.o,ov_SC03_114_jr_8017AE2C.o,ov_SC03_114_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_114_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_114.o,ov_SC03_114_jr_8012ACE0.o,tail2.data.o,ov_SC03_114_jr_80135888.o,tail3.data.o,ov_SC03_114_jr_80135A4C.o,tail4.data.o,ov_SC03_114_jr_80135D20.o,tail5.data.o,ov_SC03_114_jr_801380E0.o,ov_SC03_114_o0c.o,tail6.data.o,ov_SC03_114_jr_8013F350.o,tail7.data.o,ov_SC03_114_jr_8013FFD8.o,tail8.data.o,ov_SC03_114_jr_80140608.o,tail9.data.o,ov_SC03_114_jr_8015444C.o,ov_SC03_114_jr_80154C24.o,ov_SC03_114_jr_801588CC.o,tail10.data.o,ov_SC03_114_jr_80159C84.o,tail11.data.o,ov_SC03_114_jr_8015A3C8.o,tail12.data.o,ov_SC03_114_jr_8015AE2C.o,tail13.data.o,ov_SC03_114_jr_8015C32C.o,tail14.data.o,ov_SC03_114_jr_8016AB6C.o,tail15.data.o,ov_SC03_114_jr_80171B4C.o,ov_SC03_114_jr_801734BC.o,tail16.data.o,ov_SC03_114_jr_801789AC.o,ov_SC03_114_jr_80178D40.o,tail17.data.o,ov_SC03_114_jr_8017A4AC.o,tail18.data.o,ov_SC03_114_jr_8017AE2C.o,ov_SC03_114_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_114/ov_SC03_114.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_114/ov_SC03_114_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_114/ov_SC03_114_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_114/ov_SC03_114_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_114/ov_SC03_114_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_114/ov_SC03_114_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_114/ov_SC03_114_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_114/ov_SC03_114_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_114/ov_SC03_114_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2540,12 +2613,13 @@ ov_SC03_115_ELF := $(ov_SC03_115_OUT).elf ov_SC03_115_MAPFILE := $(ov_SC03_115_OUT).map ov_SC03_115_LD_SCRIPT := $(ov_SC03_115_OUT).ld ov_SC03_115_SPLAT_YAML := config/splat.ov_SC03_115.yaml -ov_SC03_115_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_115.o,ov_SC03_115_jr_8012ACE0.o,tail2.data.o,ov_SC03_115_jr_80135888.o,tail3.data.o,ov_SC03_115_jr_80135A4C.o,tail4.data.o,ov_SC03_115_jr_80135D20.o,tail5.data.o,ov_SC03_115_jr_801380E0.o,ov_SC03_115_o0c.o,tail6.data.o,ov_SC03_115_jr_8013F350.o,tail7.data.o,ov_SC03_115_jr_8013FFD8.o,tail8.data.o,ov_SC03_115_jr_80140608.o,tail9.data.o,ov_SC03_115_jr_8015444C.o,tail10.data.o,ov_SC03_115_jr_80154C24.o,ov_SC03_115_jr_801588CC.o,tail11.data.o,ov_SC03_115_jr_80159C84.o,tail12.data.o,ov_SC03_115_jr_8015A3C8.o,tail13.data.o,ov_SC03_115_jr_8015AE2C.o,tail14.data.o,ov_SC03_115_jr_8015C32C.o,tail15.data.o,ov_SC03_115_jr_8016AB6C.o,tail16.data.o,ov_SC03_115_jr_80171B4C.o,ov_SC03_115_jr_801734BC.o,tail17.data.o,ov_SC03_115_jr_801789AC.o,ov_SC03_115_jr_80178D40.o,tail18.data.o,ov_SC03_115_jr_8017A4AC.o,tail19.data.o,ov_SC03_115_jr_8017AE2C.o,ov_SC03_115_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_115_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_115.o,ov_SC03_115_jr_8012ACE0.o,tail2.data.o,ov_SC03_115_jr_80135888.o,tail3.data.o,ov_SC03_115_jr_80135A4C.o,tail4.data.o,ov_SC03_115_jr_80135D20.o,tail5.data.o,ov_SC03_115_jr_801380E0.o,ov_SC03_115_o0c.o,tail6.data.o,ov_SC03_115_jr_8013F350.o,tail7.data.o,ov_SC03_115_jr_8013FFD8.o,tail8.data.o,ov_SC03_115_jr_80140608.o,tail9.data.o,ov_SC03_115_jr_8015444C.o,ov_SC03_115_jr_80154C24.o,ov_SC03_115_jr_801588CC.o,tail10.data.o,ov_SC03_115_jr_80159C84.o,tail11.data.o,ov_SC03_115_jr_8015A3C8.o,tail12.data.o,ov_SC03_115_jr_8015AE2C.o,tail13.data.o,ov_SC03_115_jr_8015C32C.o,tail14.data.o,ov_SC03_115_jr_8016AB6C.o,tail15.data.o,ov_SC03_115_jr_80171B4C.o,ov_SC03_115_jr_801734BC.o,tail16.data.o,ov_SC03_115_jr_801789AC.o,ov_SC03_115_jr_80178D40.o,tail17.data.o,ov_SC03_115_jr_8017A4AC.o,tail18.data.o,ov_SC03_115_jr_8017AE2C.o,ov_SC03_115_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_115/ov_SC03_115.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_115/ov_SC03_115_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_115/ov_SC03_115_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_115/ov_SC03_115_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_115/ov_SC03_115_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_115/ov_SC03_115_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_115/ov_SC03_115_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_115/ov_SC03_115_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_115/ov_SC03_115_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2574,12 +2648,13 @@ ov_SC03_116_ELF := $(ov_SC03_116_OUT).elf ov_SC03_116_MAPFILE := $(ov_SC03_116_OUT).map ov_SC03_116_LD_SCRIPT := $(ov_SC03_116_OUT).ld ov_SC03_116_SPLAT_YAML := config/splat.ov_SC03_116.yaml -ov_SC03_116_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_116.o,ov_SC03_116_jr_8012ACE0.o,tail2.data.o,ov_SC03_116_jr_80135888.o,tail3.data.o,ov_SC03_116_jr_80135A4C.o,tail4.data.o,ov_SC03_116_jr_80135D20.o,tail5.data.o,ov_SC03_116_jr_801380E0.o,ov_SC03_116_o0c.o,tail6.data.o,ov_SC03_116_jr_8013F350.o,tail7.data.o,ov_SC03_116_jr_8013FFD8.o,tail8.data.o,ov_SC03_116_jr_80140608.o,tail9.data.o,ov_SC03_116_jr_8015444C.o,tail10.data.o,ov_SC03_116_jr_80154C24.o,ov_SC03_116_jr_801588CC.o,tail11.data.o,ov_SC03_116_jr_80159C84.o,tail12.data.o,ov_SC03_116_jr_8015A3C8.o,tail13.data.o,ov_SC03_116_jr_8015AE2C.o,tail14.data.o,ov_SC03_116_jr_8015C32C.o,tail15.data.o,ov_SC03_116_jr_8016AB6C.o,tail16.data.o,ov_SC03_116_jr_80171B4C.o,ov_SC03_116_jr_801734BC.o,tail17.data.o,ov_SC03_116_jr_801789AC.o,ov_SC03_116_jr_80178D40.o,tail18.data.o,ov_SC03_116_jr_8017A4AC.o,tail19.data.o,ov_SC03_116_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_116_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_116.o,ov_SC03_116_jr_8012ACE0.o,tail2.data.o,ov_SC03_116_jr_80135888.o,tail3.data.o,ov_SC03_116_jr_80135A4C.o,tail4.data.o,ov_SC03_116_jr_80135D20.o,tail5.data.o,ov_SC03_116_jr_801380E0.o,ov_SC03_116_o0c.o,tail6.data.o,ov_SC03_116_jr_8013F350.o,tail7.data.o,ov_SC03_116_jr_8013FFD8.o,tail8.data.o,ov_SC03_116_jr_80140608.o,tail9.data.o,ov_SC03_116_jr_8015444C.o,ov_SC03_116_jr_80154C24.o,ov_SC03_116_jr_801588CC.o,tail10.data.o,ov_SC03_116_jr_80159C84.o,tail11.data.o,ov_SC03_116_jr_8015A3C8.o,tail12.data.o,ov_SC03_116_jr_8015AE2C.o,tail13.data.o,ov_SC03_116_jr_8015C32C.o,tail14.data.o,ov_SC03_116_jr_8016AB6C.o,tail15.data.o,ov_SC03_116_jr_80171B4C.o,ov_SC03_116_jr_801734BC.o,tail16.data.o,ov_SC03_116_jr_801789AC.o,ov_SC03_116_jr_80178D40.o,tail17.data.o,ov_SC03_116_jr_8017A4AC.o,tail18.data.o,ov_SC03_116_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_116/ov_SC03_116.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_116/ov_SC03_116_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_116/ov_SC03_116_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_116/ov_SC03_116_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_116/ov_SC03_116_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_116/ov_SC03_116_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_116/ov_SC03_116_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_116/ov_SC03_116_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_116/ov_SC03_116_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2608,12 +2683,13 @@ ov_SC03_117_ELF := $(ov_SC03_117_OUT).elf ov_SC03_117_MAPFILE := $(ov_SC03_117_OUT).map ov_SC03_117_LD_SCRIPT := $(ov_SC03_117_OUT).ld ov_SC03_117_SPLAT_YAML := config/splat.ov_SC03_117.yaml -ov_SC03_117_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_117.o,ov_SC03_117_jr_8012ACE0.o,tail2.data.o,ov_SC03_117_jr_80135888.o,tail3.data.o,ov_SC03_117_jr_80135A4C.o,tail4.data.o,ov_SC03_117_jr_80135D20.o,tail5.data.o,ov_SC03_117_jr_801380E0.o,ov_SC03_117_o0c.o,tail6.data.o,ov_SC03_117_jr_8013F350.o,tail7.data.o,ov_SC03_117_jr_8013FFD8.o,tail8.data.o,ov_SC03_117_jr_80140608.o,tail9.data.o,ov_SC03_117_jr_8015444C.o,tail10.data.o,ov_SC03_117_jr_80154C24.o,ov_SC03_117_jr_801588CC.o,tail11.data.o,ov_SC03_117_jr_80159C84.o,tail12.data.o,ov_SC03_117_jr_8015A3C8.o,tail13.data.o,ov_SC03_117_jr_8015AE2C.o,tail14.data.o,ov_SC03_117_jr_8015C32C.o,tail15.data.o,ov_SC03_117_jr_8016AB6C.o,tail16.data.o,ov_SC03_117_jr_80171B4C.o,ov_SC03_117_jr_801734BC.o,tail17.data.o,ov_SC03_117_jr_801789AC.o,ov_SC03_117_jr_80178D40.o,tail18.data.o,ov_SC03_117_jr_8017A4AC.o,tail19.data.o,ov_SC03_117_jr_8017AE2C.o,ov_SC03_117_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_117_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_117.o,ov_SC03_117_jr_8012ACE0.o,tail2.data.o,ov_SC03_117_jr_80135888.o,tail3.data.o,ov_SC03_117_jr_80135A4C.o,tail4.data.o,ov_SC03_117_jr_80135D20.o,tail5.data.o,ov_SC03_117_jr_801380E0.o,ov_SC03_117_o0c.o,tail6.data.o,ov_SC03_117_jr_8013F350.o,tail7.data.o,ov_SC03_117_jr_8013FFD8.o,tail8.data.o,ov_SC03_117_jr_80140608.o,tail9.data.o,ov_SC03_117_jr_8015444C.o,ov_SC03_117_jr_80154C24.o,ov_SC03_117_jr_801588CC.o,tail10.data.o,ov_SC03_117_jr_80159C84.o,tail11.data.o,ov_SC03_117_jr_8015A3C8.o,tail12.data.o,ov_SC03_117_jr_8015AE2C.o,tail13.data.o,ov_SC03_117_jr_8015C32C.o,tail14.data.o,ov_SC03_117_jr_8016AB6C.o,tail15.data.o,ov_SC03_117_jr_80171B4C.o,ov_SC03_117_jr_801734BC.o,tail16.data.o,ov_SC03_117_jr_801789AC.o,ov_SC03_117_jr_80178D40.o,tail17.data.o,ov_SC03_117_jr_8017A4AC.o,tail18.data.o,ov_SC03_117_jr_8017AE2C.o,ov_SC03_117_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_117/ov_SC03_117.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_117/ov_SC03_117_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_117/ov_SC03_117_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_117/ov_SC03_117_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_117/ov_SC03_117_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_117/ov_SC03_117_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_117/ov_SC03_117_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_117/ov_SC03_117_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_117/ov_SC03_117_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2642,12 +2718,13 @@ ov_SC03_118_ELF := $(ov_SC03_118_OUT).elf ov_SC03_118_MAPFILE := $(ov_SC03_118_OUT).map ov_SC03_118_LD_SCRIPT := $(ov_SC03_118_OUT).ld ov_SC03_118_SPLAT_YAML := config/splat.ov_SC03_118.yaml -ov_SC03_118_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_118.o,ov_SC03_118_jr_8012ACE0.o,tail2.data.o,ov_SC03_118_jr_80135888.o,tail3.data.o,ov_SC03_118_jr_80135A4C.o,tail4.data.o,ov_SC03_118_jr_80135D20.o,tail5.data.o,ov_SC03_118_jr_801380E0.o,ov_SC03_118_o0c.o,tail6.data.o,ov_SC03_118_jr_8013F350.o,tail7.data.o,ov_SC03_118_jr_8013FFD8.o,tail8.data.o,ov_SC03_118_jr_80140608.o,tail9.data.o,ov_SC03_118_jr_8015444C.o,tail10.data.o,ov_SC03_118_jr_80154C24.o,ov_SC03_118_jr_801588CC.o,tail11.data.o,ov_SC03_118_jr_80159C84.o,tail12.data.o,ov_SC03_118_jr_8015A3C8.o,tail13.data.o,ov_SC03_118_jr_8015AE2C.o,tail14.data.o,ov_SC03_118_jr_8015C32C.o,tail15.data.o,ov_SC03_118_jr_8016AB6C.o,tail16.data.o,ov_SC03_118_jr_80171B4C.o,ov_SC03_118_jr_801734BC.o,tail17.data.o,ov_SC03_118_jr_801789AC.o,ov_SC03_118_jr_80178D40.o,tail18.data.o,ov_SC03_118_jr_8017A4AC.o,tail19.data.o,ov_SC03_118_jr_8017AE2C.o,tail20.data.o,ov_SC03_118_jr_8017FB84.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_118_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_118.o,ov_SC03_118_jr_8012ACE0.o,tail2.data.o,ov_SC03_118_jr_80135888.o,tail3.data.o,ov_SC03_118_jr_80135A4C.o,tail4.data.o,ov_SC03_118_jr_80135D20.o,tail5.data.o,ov_SC03_118_jr_801380E0.o,ov_SC03_118_o0c.o,tail6.data.o,ov_SC03_118_jr_8013F350.o,tail7.data.o,ov_SC03_118_jr_8013FFD8.o,tail8.data.o,ov_SC03_118_jr_80140608.o,tail9.data.o,ov_SC03_118_jr_8015444C.o,ov_SC03_118_jr_80154C24.o,ov_SC03_118_jr_801588CC.o,tail10.data.o,ov_SC03_118_jr_80159C84.o,tail11.data.o,ov_SC03_118_jr_8015A3C8.o,tail12.data.o,ov_SC03_118_jr_8015AE2C.o,tail13.data.o,ov_SC03_118_jr_8015C32C.o,tail14.data.o,ov_SC03_118_jr_8016AB6C.o,tail15.data.o,ov_SC03_118_jr_80171B4C.o,ov_SC03_118_jr_801734BC.o,tail16.data.o,ov_SC03_118_jr_801789AC.o,ov_SC03_118_jr_80178D40.o,tail17.data.o,ov_SC03_118_jr_8017A4AC.o,tail18.data.o,ov_SC03_118_jr_8017AE2C.o,tail19.data.o,ov_SC03_118_jr_8017FB84.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_118/ov_SC03_118.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_118/ov_SC03_118_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_118/ov_SC03_118_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_118/ov_SC03_118_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_118/ov_SC03_118_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_118/ov_SC03_118_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_118/ov_SC03_118_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_118/ov_SC03_118_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_118/ov_SC03_118_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2676,12 +2753,13 @@ ov_SC03_119_ELF := $(ov_SC03_119_OUT).elf ov_SC03_119_MAPFILE := $(ov_SC03_119_OUT).map ov_SC03_119_LD_SCRIPT := $(ov_SC03_119_OUT).ld ov_SC03_119_SPLAT_YAML := config/splat.ov_SC03_119.yaml -ov_SC03_119_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_119.o,ov_SC03_119_jr_8012ACE0.o,tail2.data.o,ov_SC03_119_jr_80135888.o,tail3.data.o,ov_SC03_119_jr_80135A4C.o,tail4.data.o,ov_SC03_119_jr_80135D20.o,tail5.data.o,ov_SC03_119_jr_801380E0.o,ov_SC03_119_o0c.o,tail6.data.o,ov_SC03_119_jr_8013F350.o,tail7.data.o,ov_SC03_119_jr_8013FFD8.o,tail8.data.o,ov_SC03_119_jr_80140608.o,tail9.data.o,ov_SC03_119_jr_8015444C.o,tail10.data.o,ov_SC03_119_jr_80154C24.o,ov_SC03_119_jr_801588CC.o,tail11.data.o,ov_SC03_119_jr_80159C84.o,tail12.data.o,ov_SC03_119_jr_8015A3C8.o,tail13.data.o,ov_SC03_119_jr_8015AE2C.o,tail14.data.o,ov_SC03_119_jr_8015C32C.o,tail15.data.o,ov_SC03_119_jr_8016AB6C.o,tail16.data.o,ov_SC03_119_jr_80171B4C.o,ov_SC03_119_jr_801734BC.o,tail17.data.o,ov_SC03_119_jr_801789AC.o,ov_SC03_119_jr_80178D40.o,tail18.data.o,ov_SC03_119_jr_8017A4AC.o,tail19.data.o,ov_SC03_119_jr_8017AE2C.o,tail20.data.o,ov_SC03_119_jr_8017FB84.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_119_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_119.o,ov_SC03_119_jr_8012ACE0.o,tail2.data.o,ov_SC03_119_jr_80135888.o,tail3.data.o,ov_SC03_119_jr_80135A4C.o,tail4.data.o,ov_SC03_119_jr_80135D20.o,tail5.data.o,ov_SC03_119_jr_801380E0.o,ov_SC03_119_o0c.o,tail6.data.o,ov_SC03_119_jr_8013F350.o,tail7.data.o,ov_SC03_119_jr_8013FFD8.o,tail8.data.o,ov_SC03_119_jr_80140608.o,tail9.data.o,ov_SC03_119_jr_8015444C.o,ov_SC03_119_jr_80154C24.o,ov_SC03_119_jr_801588CC.o,tail10.data.o,ov_SC03_119_jr_80159C84.o,tail11.data.o,ov_SC03_119_jr_8015A3C8.o,tail12.data.o,ov_SC03_119_jr_8015AE2C.o,tail13.data.o,ov_SC03_119_jr_8015C32C.o,tail14.data.o,ov_SC03_119_jr_8016AB6C.o,tail15.data.o,ov_SC03_119_jr_80171B4C.o,ov_SC03_119_jr_801734BC.o,tail16.data.o,ov_SC03_119_jr_801789AC.o,ov_SC03_119_jr_80178D40.o,tail17.data.o,ov_SC03_119_jr_8017A4AC.o,tail18.data.o,ov_SC03_119_jr_8017AE2C.o,tail19.data.o,ov_SC03_119_jr_8017FB84.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_119/ov_SC03_119.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_119/ov_SC03_119_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_119/ov_SC03_119_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_119/ov_SC03_119_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_119/ov_SC03_119_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_119/ov_SC03_119_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_119/ov_SC03_119_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_119/ov_SC03_119_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_119/ov_SC03_119_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2710,12 +2788,13 @@ ov_SC03_121_ELF := $(ov_SC03_121_OUT).elf ov_SC03_121_MAPFILE := $(ov_SC03_121_OUT).map ov_SC03_121_LD_SCRIPT := $(ov_SC03_121_OUT).ld ov_SC03_121_SPLAT_YAML := config/splat.ov_SC03_121.yaml -ov_SC03_121_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_121.o,ov_SC03_121_jr_8012ACE0.o,tail2.data.o,ov_SC03_121_jr_80135888.o,tail3.data.o,ov_SC03_121_jr_80135A4C.o,tail4.data.o,ov_SC03_121_jr_80135D20.o,tail5.data.o,ov_SC03_121_jr_801380E0.o,ov_SC03_121_o0c.o,tail6.data.o,ov_SC03_121_jr_8013F350.o,tail7.data.o,ov_SC03_121_jr_8013FFD8.o,tail8.data.o,ov_SC03_121_jr_80140608.o,tail9.data.o,ov_SC03_121_jr_8015444C.o,tail10.data.o,ov_SC03_121_jr_80154C24.o,ov_SC03_121_jr_801588CC.o,tail11.data.o,ov_SC03_121_jr_80159C84.o,tail12.data.o,ov_SC03_121_jr_8015A3C8.o,tail13.data.o,ov_SC03_121_jr_8015AE2C.o,tail14.data.o,ov_SC03_121_jr_8015C32C.o,tail15.data.o,ov_SC03_121_jr_8016AB6C.o,tail16.data.o,ov_SC03_121_jr_80171B4C.o,ov_SC03_121_jr_801734BC.o,tail17.data.o,ov_SC03_121_jr_801789AC.o,ov_SC03_121_jr_80178D40.o,tail18.data.o,ov_SC03_121_jr_8017A4AC.o,tail19.data.o,ov_SC03_121_jr_8017AE2C.o,ov_SC03_121_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_121_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_121.o,ov_SC03_121_jr_8012ACE0.o,tail2.data.o,ov_SC03_121_jr_80135888.o,tail3.data.o,ov_SC03_121_jr_80135A4C.o,tail4.data.o,ov_SC03_121_jr_80135D20.o,tail5.data.o,ov_SC03_121_jr_801380E0.o,ov_SC03_121_o0c.o,tail6.data.o,ov_SC03_121_jr_8013F350.o,tail7.data.o,ov_SC03_121_jr_8013FFD8.o,tail8.data.o,ov_SC03_121_jr_80140608.o,tail9.data.o,ov_SC03_121_jr_8015444C.o,ov_SC03_121_jr_80154C24.o,ov_SC03_121_jr_801588CC.o,tail10.data.o,ov_SC03_121_jr_80159C84.o,tail11.data.o,ov_SC03_121_jr_8015A3C8.o,tail12.data.o,ov_SC03_121_jr_8015AE2C.o,tail13.data.o,ov_SC03_121_jr_8015C32C.o,tail14.data.o,ov_SC03_121_jr_8016AB6C.o,tail15.data.o,ov_SC03_121_jr_80171B4C.o,ov_SC03_121_jr_801734BC.o,tail16.data.o,ov_SC03_121_jr_801789AC.o,ov_SC03_121_jr_80178D40.o,tail17.data.o,ov_SC03_121_jr_8017A4AC.o,tail18.data.o,ov_SC03_121_jr_8017AE2C.o,ov_SC03_121_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_121/ov_SC03_121.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_121/ov_SC03_121_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_121/ov_SC03_121_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_121/ov_SC03_121_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_121/ov_SC03_121_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_121/ov_SC03_121_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_121/ov_SC03_121_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_121/ov_SC03_121_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_121/ov_SC03_121_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2744,12 +2823,13 @@ ov_SC03_124_ELF := $(ov_SC03_124_OUT).elf ov_SC03_124_MAPFILE := $(ov_SC03_124_OUT).map ov_SC03_124_LD_SCRIPT := $(ov_SC03_124_OUT).ld ov_SC03_124_SPLAT_YAML := config/splat.ov_SC03_124.yaml -ov_SC03_124_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_124.o,ov_SC03_124_jr_8012ACE0.o,tail2.data.o,ov_SC03_124_jr_80135888.o,tail3.data.o,ov_SC03_124_jr_80135A4C.o,tail4.data.o,ov_SC03_124_jr_80135D20.o,tail5.data.o,ov_SC03_124_jr_801380E0.o,ov_SC03_124_o0c.o,tail6.data.o,ov_SC03_124_jr_8013F350.o,tail7.data.o,ov_SC03_124_jr_8013FFD8.o,tail8.data.o,ov_SC03_124_jr_80140608.o,tail9.data.o,ov_SC03_124_jr_8015444C.o,tail10.data.o,ov_SC03_124_jr_80154C24.o,ov_SC03_124_jr_801588CC.o,tail11.data.o,ov_SC03_124_jr_80159C84.o,tail12.data.o,ov_SC03_124_jr_8015A3C8.o,tail13.data.o,ov_SC03_124_jr_8015AE2C.o,tail14.data.o,ov_SC03_124_jr_8015C32C.o,tail15.data.o,ov_SC03_124_jr_8016AB6C.o,tail16.data.o,ov_SC03_124_jr_80171B4C.o,ov_SC03_124_jr_801734BC.o,tail17.data.o,ov_SC03_124_jr_801789AC.o,ov_SC03_124_jr_80178D40.o,tail18.data.o,ov_SC03_124_jr_8017A4AC.o,tail19.data.o,ov_SC03_124_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_124_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_124.o,ov_SC03_124_jr_8012ACE0.o,tail2.data.o,ov_SC03_124_jr_80135888.o,tail3.data.o,ov_SC03_124_jr_80135A4C.o,tail4.data.o,ov_SC03_124_jr_80135D20.o,tail5.data.o,ov_SC03_124_jr_801380E0.o,ov_SC03_124_o0c.o,tail6.data.o,ov_SC03_124_jr_8013F350.o,tail7.data.o,ov_SC03_124_jr_8013FFD8.o,tail8.data.o,ov_SC03_124_jr_80140608.o,tail9.data.o,ov_SC03_124_jr_8015444C.o,ov_SC03_124_jr_80154C24.o,ov_SC03_124_jr_801588CC.o,tail10.data.o,ov_SC03_124_jr_80159C84.o,tail11.data.o,ov_SC03_124_jr_8015A3C8.o,tail12.data.o,ov_SC03_124_jr_8015AE2C.o,tail13.data.o,ov_SC03_124_jr_8015C32C.o,tail14.data.o,ov_SC03_124_jr_8016AB6C.o,tail15.data.o,ov_SC03_124_jr_80171B4C.o,ov_SC03_124_jr_801734BC.o,tail16.data.o,ov_SC03_124_jr_801789AC.o,ov_SC03_124_jr_80178D40.o,tail17.data.o,ov_SC03_124_jr_8017A4AC.o,tail18.data.o,ov_SC03_124_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_124/ov_SC03_124.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_124/ov_SC03_124_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_124/ov_SC03_124_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_124/ov_SC03_124_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_124/ov_SC03_124_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_124/ov_SC03_124_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_124/ov_SC03_124_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_124/ov_SC03_124_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_124/ov_SC03_124_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2779,12 +2859,13 @@ ov_SC03_125_ELF := $(ov_SC03_125_OUT).elf ov_SC03_125_MAPFILE := $(ov_SC03_125_OUT).map ov_SC03_125_LD_SCRIPT := $(ov_SC03_125_OUT).ld ov_SC03_125_SPLAT_YAML := config/splat.ov_SC03_125.yaml -ov_SC03_125_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_125.o,ov_SC03_125_jr_8012ACE0.o,tail2.data.o,ov_SC03_125_jr_80135888.o,tail3.data.o,ov_SC03_125_jr_80135A4C.o,tail4.data.o,ov_SC03_125_jr_80135D20.o,tail5.data.o,ov_SC03_125_jr_801380E0.o,ov_SC03_125_o0c.o,tail6.data.o,ov_SC03_125_jr_8013F350.o,tail7.data.o,ov_SC03_125_jr_8013FFD8.o,tail8.data.o,ov_SC03_125_jr_80140608.o,tail9.data.o,ov_SC03_125_jr_8015444C.o,tail10.data.o,ov_SC03_125_jr_80154C24.o,ov_SC03_125_jr_801588CC.o,tail11.data.o,ov_SC03_125_jr_80159C84.o,tail12.data.o,ov_SC03_125_jr_8015A3C8.o,tail13.data.o,ov_SC03_125_jr_8015AE2C.o,tail14.data.o,ov_SC03_125_jr_8015C32C.o,tail15.data.o,ov_SC03_125_jr_8016AB6C.o,tail16.data.o,ov_SC03_125_jr_80171B4C.o,ov_SC03_125_jr_801734BC.o,tail17.data.o,ov_SC03_125_jr_801789AC.o,ov_SC03_125_jr_80178D40.o,tail18.data.o,ov_SC03_125_jr_8017A4AC.o,tail19.data.o,ov_SC03_125_jr_8017AE2C.o,ov_SC03_125_jr_8017D604.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_125_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_125.o,ov_SC03_125_jr_8012ACE0.o,tail2.data.o,ov_SC03_125_jr_80135888.o,tail3.data.o,ov_SC03_125_jr_80135A4C.o,tail4.data.o,ov_SC03_125_jr_80135D20.o,tail5.data.o,ov_SC03_125_jr_801380E0.o,ov_SC03_125_o0c.o,tail6.data.o,ov_SC03_125_jr_8013F350.o,tail7.data.o,ov_SC03_125_jr_8013FFD8.o,tail8.data.o,ov_SC03_125_jr_80140608.o,tail9.data.o,ov_SC03_125_jr_8015444C.o,ov_SC03_125_jr_80154C24.o,ov_SC03_125_jr_801588CC.o,tail10.data.o,ov_SC03_125_jr_80159C84.o,tail11.data.o,ov_SC03_125_jr_8015A3C8.o,tail12.data.o,ov_SC03_125_jr_8015AE2C.o,tail13.data.o,ov_SC03_125_jr_8015C32C.o,tail14.data.o,ov_SC03_125_jr_8016AB6C.o,tail15.data.o,ov_SC03_125_jr_80171B4C.o,ov_SC03_125_jr_801734BC.o,tail16.data.o,ov_SC03_125_jr_801789AC.o,ov_SC03_125_jr_80178D40.o,tail17.data.o,ov_SC03_125_jr_8017A4AC.o,tail18.data.o,ov_SC03_125_jr_8017AE2C.o,ov_SC03_125_jr_8017D604.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_125/ov_SC03_125.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_125/ov_SC03_125_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_125/ov_SC03_125_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_125/ov_SC03_125_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_125/ov_SC03_125_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_125/ov_SC03_125_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_125/ov_SC03_125_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_125/ov_SC03_125_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_125/ov_SC03_125_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2813,12 +2894,13 @@ ov_SC03_126_ELF := $(ov_SC03_126_OUT).elf ov_SC03_126_MAPFILE := $(ov_SC03_126_OUT).map ov_SC03_126_LD_SCRIPT := $(ov_SC03_126_OUT).ld ov_SC03_126_SPLAT_YAML := config/splat.ov_SC03_126.yaml -ov_SC03_126_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_126.o,ov_SC03_126_jr_8012ACE0.o,tail2.data.o,ov_SC03_126_jr_80135888.o,tail3.data.o,ov_SC03_126_jr_80135A4C.o,tail4.data.o,ov_SC03_126_jr_80135D20.o,tail5.data.o,ov_SC03_126_jr_801380E0.o,ov_SC03_126_o0c.o,tail6.data.o,ov_SC03_126_jr_8013F350.o,tail7.data.o,ov_SC03_126_jr_8013FFD8.o,tail8.data.o,ov_SC03_126_jr_80140608.o,tail9.data.o,ov_SC03_126_jr_8015444C.o,tail10.data.o,ov_SC03_126_jr_80154C24.o,ov_SC03_126_jr_801588CC.o,tail11.data.o,ov_SC03_126_jr_80159C84.o,tail12.data.o,ov_SC03_126_jr_8015A3C8.o,tail13.data.o,ov_SC03_126_jr_8015AE2C.o,tail14.data.o,ov_SC03_126_jr_8015C32C.o,tail15.data.o,ov_SC03_126_jr_8016AB6C.o,tail16.data.o,ov_SC03_126_jr_80171B4C.o,ov_SC03_126_jr_801734BC.o,tail17.data.o,ov_SC03_126_jr_801789AC.o,ov_SC03_126_jr_80178D40.o,tail18.data.o,ov_SC03_126_jr_8017A4AC.o,tail19.data.o,ov_SC03_126_jr_8017AE2C.o,tail20.data.o,ov_SC03_126_jr_8017D5C0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_126_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_126.o,ov_SC03_126_jr_8012ACE0.o,tail2.data.o,ov_SC03_126_jr_80135888.o,tail3.data.o,ov_SC03_126_jr_80135A4C.o,tail4.data.o,ov_SC03_126_jr_80135D20.o,tail5.data.o,ov_SC03_126_jr_801380E0.o,ov_SC03_126_o0c.o,tail6.data.o,ov_SC03_126_jr_8013F350.o,tail7.data.o,ov_SC03_126_jr_8013FFD8.o,tail8.data.o,ov_SC03_126_jr_80140608.o,tail9.data.o,ov_SC03_126_jr_8015444C.o,ov_SC03_126_jr_80154C24.o,ov_SC03_126_jr_801588CC.o,tail10.data.o,ov_SC03_126_jr_80159C84.o,tail11.data.o,ov_SC03_126_jr_8015A3C8.o,tail12.data.o,ov_SC03_126_jr_8015AE2C.o,tail13.data.o,ov_SC03_126_jr_8015C32C.o,tail14.data.o,ov_SC03_126_jr_8016AB6C.o,tail15.data.o,ov_SC03_126_jr_80171B4C.o,ov_SC03_126_jr_801734BC.o,tail16.data.o,ov_SC03_126_jr_801789AC.o,ov_SC03_126_jr_80178D40.o,tail17.data.o,ov_SC03_126_jr_8017A4AC.o,tail18.data.o,ov_SC03_126_jr_8017AE2C.o,tail19.data.o,ov_SC03_126_jr_8017D5C0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_126/ov_SC03_126.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_126/ov_SC03_126_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_126/ov_SC03_126_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC03_126/ov_SC03_126_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_126/ov_SC03_126_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC03_126/ov_SC03_126_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC03_126/ov_SC03_126_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC03_126/ov_SC03_126_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC03_126/ov_SC03_126_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2847,12 +2929,13 @@ ov_SC04_002_ELF := $(ov_SC04_002_OUT).elf ov_SC04_002_MAPFILE := $(ov_SC04_002_OUT).map ov_SC04_002_LD_SCRIPT := $(ov_SC04_002_OUT).ld ov_SC04_002_SPLAT_YAML := config/splat.ov_SC04_002.yaml -ov_SC04_002_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_002.o,ov_SC04_002_jr_8012ACE0.o,tail2.data.o,ov_SC04_002_jr_80135888.o,tail3.data.o,ov_SC04_002_jr_80135A4C.o,tail4.data.o,ov_SC04_002_jr_80135D20.o,tail5.data.o,ov_SC04_002_jr_801380E0.o,ov_SC04_002_o0c.o,tail6.data.o,ov_SC04_002_jr_8013F350.o,tail7.data.o,ov_SC04_002_jr_8013FFD8.o,tail8.data.o,ov_SC04_002_jr_80140608.o,tail9.data.o,ov_SC04_002_jr_8015444C.o,tail10.data.o,ov_SC04_002_jr_80154C24.o,ov_SC04_002_jr_801588CC.o,tail11.data.o,ov_SC04_002_jr_80159C84.o,tail12.data.o,ov_SC04_002_jr_8015A3C8.o,tail13.data.o,ov_SC04_002_jr_8015AE2C.o,tail14.data.o,ov_SC04_002_jr_8015C32C.o,tail15.data.o,ov_SC04_002_jr_8016AB6C.o,tail16.data.o,ov_SC04_002_jr_80171B4C.o,ov_SC04_002_jr_801734BC.o,tail17.data.o,ov_SC04_002_jr_801789AC.o,ov_SC04_002_jr_80178D40.o,tail18.data.o,ov_SC04_002_jr_8017A4AC.o,tail19.data.o,ov_SC04_002_jr_8017AE2C.o,ov_SC04_002_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_002_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_002.o,ov_SC04_002_jr_8012ACE0.o,tail2.data.o,ov_SC04_002_jr_80135888.o,tail3.data.o,ov_SC04_002_jr_80135A4C.o,tail4.data.o,ov_SC04_002_jr_80135D20.o,tail5.data.o,ov_SC04_002_jr_801380E0.o,ov_SC04_002_o0c.o,tail6.data.o,ov_SC04_002_jr_8013F350.o,tail7.data.o,ov_SC04_002_jr_8013FFD8.o,tail8.data.o,ov_SC04_002_jr_80140608.o,tail9.data.o,ov_SC04_002_jr_8015444C.o,ov_SC04_002_jr_80154C24.o,ov_SC04_002_jr_801588CC.o,tail10.data.o,ov_SC04_002_jr_80159C84.o,tail11.data.o,ov_SC04_002_jr_8015A3C8.o,tail12.data.o,ov_SC04_002_jr_8015AE2C.o,tail13.data.o,ov_SC04_002_jr_8015C32C.o,tail14.data.o,ov_SC04_002_jr_8016AB6C.o,tail15.data.o,ov_SC04_002_jr_80171B4C.o,ov_SC04_002_jr_801734BC.o,tail16.data.o,ov_SC04_002_jr_801789AC.o,ov_SC04_002_jr_80178D40.o,tail17.data.o,ov_SC04_002_jr_8017A4AC.o,tail18.data.o,ov_SC04_002_jr_8017AE2C.o,ov_SC04_002_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_002/ov_SC04_002.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_002/ov_SC04_002_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_002/ov_SC04_002_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_002/ov_SC04_002_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_002/ov_SC04_002_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_002/ov_SC04_002_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_002/ov_SC04_002_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_002/ov_SC04_002_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_002/ov_SC04_002_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2881,12 +2964,13 @@ ov_SC04_003_ELF := $(ov_SC04_003_OUT).elf ov_SC04_003_MAPFILE := $(ov_SC04_003_OUT).map ov_SC04_003_LD_SCRIPT := $(ov_SC04_003_OUT).ld ov_SC04_003_SPLAT_YAML := config/splat.ov_SC04_003.yaml -ov_SC04_003_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_003.o,ov_SC04_003_jr_8012ACE0.o,tail2.data.o,ov_SC04_003_jr_80135888.o,tail3.data.o,ov_SC04_003_jr_80135A4C.o,tail4.data.o,ov_SC04_003_jr_80135D20.o,tail5.data.o,ov_SC04_003_jr_801380E0.o,ov_SC04_003_o0c.o,tail6.data.o,ov_SC04_003_jr_8013F350.o,tail7.data.o,ov_SC04_003_jr_8013FFD8.o,tail8.data.o,ov_SC04_003_jr_80140608.o,tail9.data.o,ov_SC04_003_jr_8015444C.o,tail10.data.o,ov_SC04_003_jr_80154C24.o,ov_SC04_003_jr_801588CC.o,tail11.data.o,ov_SC04_003_jr_80159C84.o,tail12.data.o,ov_SC04_003_jr_8015A3C8.o,tail13.data.o,ov_SC04_003_jr_8015AE2C.o,tail14.data.o,ov_SC04_003_jr_8015C32C.o,tail15.data.o,ov_SC04_003_jr_8016AB6C.o,tail16.data.o,ov_SC04_003_jr_80171B4C.o,ov_SC04_003_jr_801734BC.o,tail17.data.o,ov_SC04_003_jr_801789AC.o,ov_SC04_003_jr_80178D40.o,tail18.data.o,ov_SC04_003_jr_8017A4AC.o,tail19.data.o,ov_SC04_003_jr_8017AE2C.o,ov_SC04_003_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_003_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_003.o,ov_SC04_003_jr_8012ACE0.o,tail2.data.o,ov_SC04_003_jr_80135888.o,tail3.data.o,ov_SC04_003_jr_80135A4C.o,tail4.data.o,ov_SC04_003_jr_80135D20.o,tail5.data.o,ov_SC04_003_jr_801380E0.o,ov_SC04_003_o0c.o,tail6.data.o,ov_SC04_003_jr_8013F350.o,tail7.data.o,ov_SC04_003_jr_8013FFD8.o,tail8.data.o,ov_SC04_003_jr_80140608.o,tail9.data.o,ov_SC04_003_jr_8015444C.o,ov_SC04_003_jr_80154C24.o,ov_SC04_003_jr_801588CC.o,tail10.data.o,ov_SC04_003_jr_80159C84.o,tail11.data.o,ov_SC04_003_jr_8015A3C8.o,tail12.data.o,ov_SC04_003_jr_8015AE2C.o,tail13.data.o,ov_SC04_003_jr_8015C32C.o,tail14.data.o,ov_SC04_003_jr_8016AB6C.o,tail15.data.o,ov_SC04_003_jr_80171B4C.o,ov_SC04_003_jr_801734BC.o,tail16.data.o,ov_SC04_003_jr_801789AC.o,ov_SC04_003_jr_80178D40.o,tail17.data.o,ov_SC04_003_jr_8017A4AC.o,tail18.data.o,ov_SC04_003_jr_8017AE2C.o,ov_SC04_003_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_003/ov_SC04_003.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_003/ov_SC04_003_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_003/ov_SC04_003_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_003/ov_SC04_003_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_003/ov_SC04_003_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_003/ov_SC04_003_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_003/ov_SC04_003_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_003/ov_SC04_003_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_003/ov_SC04_003_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2915,12 +2999,13 @@ ov_SC04_004_ELF := $(ov_SC04_004_OUT).elf ov_SC04_004_MAPFILE := $(ov_SC04_004_OUT).map ov_SC04_004_LD_SCRIPT := $(ov_SC04_004_OUT).ld ov_SC04_004_SPLAT_YAML := config/splat.ov_SC04_004.yaml -ov_SC04_004_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_004.o,ov_SC04_004_jr_8012ACE0.o,tail2.data.o,ov_SC04_004_jr_80135888.o,tail3.data.o,ov_SC04_004_jr_80135A4C.o,tail4.data.o,ov_SC04_004_jr_80135D20.o,tail5.data.o,ov_SC04_004_jr_801380E0.o,ov_SC04_004_o0c.o,tail6.data.o,ov_SC04_004_jr_8013F350.o,tail7.data.o,ov_SC04_004_jr_8013FFD8.o,tail8.data.o,ov_SC04_004_jr_80140608.o,tail9.data.o,ov_SC04_004_jr_8015444C.o,tail10.data.o,ov_SC04_004_jr_80154C24.o,ov_SC04_004_jr_801588CC.o,tail11.data.o,ov_SC04_004_jr_80159C84.o,tail12.data.o,ov_SC04_004_jr_8015A3C8.o,tail13.data.o,ov_SC04_004_jr_8015AE2C.o,tail14.data.o,ov_SC04_004_jr_8015C32C.o,tail15.data.o,ov_SC04_004_jr_8016AB6C.o,tail16.data.o,ov_SC04_004_jr_80171B4C.o,ov_SC04_004_jr_801734BC.o,tail17.data.o,ov_SC04_004_jr_801789AC.o,ov_SC04_004_jr_80178D40.o,tail18.data.o,ov_SC04_004_jr_8017A4AC.o,tail19.data.o,ov_SC04_004_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_004_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_004.o,ov_SC04_004_jr_8012ACE0.o,tail2.data.o,ov_SC04_004_jr_80135888.o,tail3.data.o,ov_SC04_004_jr_80135A4C.o,tail4.data.o,ov_SC04_004_jr_80135D20.o,tail5.data.o,ov_SC04_004_jr_801380E0.o,ov_SC04_004_o0c.o,tail6.data.o,ov_SC04_004_jr_8013F350.o,tail7.data.o,ov_SC04_004_jr_8013FFD8.o,tail8.data.o,ov_SC04_004_jr_80140608.o,tail9.data.o,ov_SC04_004_jr_8015444C.o,ov_SC04_004_jr_80154C24.o,ov_SC04_004_jr_801588CC.o,tail10.data.o,ov_SC04_004_jr_80159C84.o,tail11.data.o,ov_SC04_004_jr_8015A3C8.o,tail12.data.o,ov_SC04_004_jr_8015AE2C.o,tail13.data.o,ov_SC04_004_jr_8015C32C.o,tail14.data.o,ov_SC04_004_jr_8016AB6C.o,tail15.data.o,ov_SC04_004_jr_80171B4C.o,ov_SC04_004_jr_801734BC.o,tail16.data.o,ov_SC04_004_jr_801789AC.o,ov_SC04_004_jr_80178D40.o,tail17.data.o,ov_SC04_004_jr_8017A4AC.o,tail18.data.o,ov_SC04_004_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_004/ov_SC04_004.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_004/ov_SC04_004_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_004/ov_SC04_004_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_004/ov_SC04_004_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_004/ov_SC04_004_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_004/ov_SC04_004_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_004/ov_SC04_004_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_004/ov_SC04_004_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_004/ov_SC04_004_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2950,12 +3035,13 @@ ov_SC04_005_ELF := $(ov_SC04_005_OUT).elf ov_SC04_005_MAPFILE := $(ov_SC04_005_OUT).map ov_SC04_005_LD_SCRIPT := $(ov_SC04_005_OUT).ld ov_SC04_005_SPLAT_YAML := config/splat.ov_SC04_005.yaml -ov_SC04_005_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_005.o,ov_SC04_005_jr_8012ACE0.o,tail2.data.o,ov_SC04_005_jr_80135888.o,tail3.data.o,ov_SC04_005_jr_80135A4C.o,tail4.data.o,ov_SC04_005_jr_80135D20.o,tail5.data.o,ov_SC04_005_jr_801380E0.o,ov_SC04_005_o0c.o,tail6.data.o,ov_SC04_005_jr_8013F350.o,tail7.data.o,ov_SC04_005_jr_8013FFD8.o,tail8.data.o,ov_SC04_005_jr_80140608.o,tail9.data.o,ov_SC04_005_jr_8015444C.o,tail10.data.o,ov_SC04_005_jr_80154C24.o,ov_SC04_005_jr_801588CC.o,tail11.data.o,ov_SC04_005_jr_80159C84.o,tail12.data.o,ov_SC04_005_jr_8015A3C8.o,tail13.data.o,ov_SC04_005_jr_8015AE2C.o,tail14.data.o,ov_SC04_005_jr_8015C32C.o,tail15.data.o,ov_SC04_005_jr_8016AB6C.o,tail16.data.o,ov_SC04_005_jr_80171B4C.o,ov_SC04_005_jr_801734BC.o,tail17.data.o,ov_SC04_005_jr_801789AC.o,ov_SC04_005_jr_80178D40.o,tail18.data.o,ov_SC04_005_jr_8017A4AC.o,tail19.data.o,ov_SC04_005_jr_8017AE2C.o,ov_SC04_005_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_005_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_005.o,ov_SC04_005_jr_8012ACE0.o,tail2.data.o,ov_SC04_005_jr_80135888.o,tail3.data.o,ov_SC04_005_jr_80135A4C.o,tail4.data.o,ov_SC04_005_jr_80135D20.o,tail5.data.o,ov_SC04_005_jr_801380E0.o,ov_SC04_005_o0c.o,tail6.data.o,ov_SC04_005_jr_8013F350.o,tail7.data.o,ov_SC04_005_jr_8013FFD8.o,tail8.data.o,ov_SC04_005_jr_80140608.o,tail9.data.o,ov_SC04_005_jr_8015444C.o,ov_SC04_005_jr_80154C24.o,ov_SC04_005_jr_801588CC.o,tail10.data.o,ov_SC04_005_jr_80159C84.o,tail11.data.o,ov_SC04_005_jr_8015A3C8.o,tail12.data.o,ov_SC04_005_jr_8015AE2C.o,tail13.data.o,ov_SC04_005_jr_8015C32C.o,tail14.data.o,ov_SC04_005_jr_8016AB6C.o,tail15.data.o,ov_SC04_005_jr_80171B4C.o,ov_SC04_005_jr_801734BC.o,tail16.data.o,ov_SC04_005_jr_801789AC.o,ov_SC04_005_jr_80178D40.o,tail17.data.o,ov_SC04_005_jr_8017A4AC.o,tail18.data.o,ov_SC04_005_jr_8017AE2C.o,ov_SC04_005_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_005/ov_SC04_005.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_005/ov_SC04_005_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_005/ov_SC04_005_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_005/ov_SC04_005_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_005/ov_SC04_005_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_005/ov_SC04_005_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_005/ov_SC04_005_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_005/ov_SC04_005_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_005/ov_SC04_005_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -2984,12 +3070,13 @@ ov_SC04_006_ELF := $(ov_SC04_006_OUT).elf ov_SC04_006_MAPFILE := $(ov_SC04_006_OUT).map ov_SC04_006_LD_SCRIPT := $(ov_SC04_006_OUT).ld ov_SC04_006_SPLAT_YAML := config/splat.ov_SC04_006.yaml -ov_SC04_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_006.o,ov_SC04_006_jr_8012ACE0.o,tail2.data.o,ov_SC04_006_jr_80135888.o,tail3.data.o,ov_SC04_006_jr_80135A4C.o,tail4.data.o,ov_SC04_006_jr_80135D20.o,tail5.data.o,ov_SC04_006_jr_801380E0.o,ov_SC04_006_o0c.o,tail6.data.o,ov_SC04_006_jr_8013F350.o,tail7.data.o,ov_SC04_006_jr_8013FFD8.o,tail8.data.o,ov_SC04_006_jr_80140608.o,tail9.data.o,ov_SC04_006_jr_8015444C.o,tail10.data.o,ov_SC04_006_jr_80154C24.o,ov_SC04_006_jr_801588CC.o,tail11.data.o,ov_SC04_006_jr_80159C84.o,tail12.data.o,ov_SC04_006_jr_8015A3C8.o,tail13.data.o,ov_SC04_006_jr_8015AE2C.o,tail14.data.o,ov_SC04_006_jr_8015C32C.o,tail15.data.o,ov_SC04_006_jr_8016AB6C.o,tail16.data.o,ov_SC04_006_jr_80171B4C.o,ov_SC04_006_jr_801734BC.o,tail17.data.o,ov_SC04_006_jr_801789AC.o,ov_SC04_006_jr_80178D40.o,tail18.data.o,ov_SC04_006_jr_8017A4AC.o,tail19.data.o,ov_SC04_006_jr_8017AE2C.o,ov_SC04_006_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_006.o,ov_SC04_006_jr_8012ACE0.o,tail2.data.o,ov_SC04_006_jr_80135888.o,tail3.data.o,ov_SC04_006_jr_80135A4C.o,tail4.data.o,ov_SC04_006_jr_80135D20.o,tail5.data.o,ov_SC04_006_jr_801380E0.o,ov_SC04_006_o0c.o,tail6.data.o,ov_SC04_006_jr_8013F350.o,tail7.data.o,ov_SC04_006_jr_8013FFD8.o,tail8.data.o,ov_SC04_006_jr_80140608.o,tail9.data.o,ov_SC04_006_jr_8015444C.o,ov_SC04_006_jr_80154C24.o,ov_SC04_006_jr_801588CC.o,tail10.data.o,ov_SC04_006_jr_80159C84.o,tail11.data.o,ov_SC04_006_jr_8015A3C8.o,tail12.data.o,ov_SC04_006_jr_8015AE2C.o,tail13.data.o,ov_SC04_006_jr_8015C32C.o,tail14.data.o,ov_SC04_006_jr_8016AB6C.o,tail15.data.o,ov_SC04_006_jr_80171B4C.o,ov_SC04_006_jr_801734BC.o,tail16.data.o,ov_SC04_006_jr_801789AC.o,ov_SC04_006_jr_80178D40.o,tail17.data.o,ov_SC04_006_jr_8017A4AC.o,tail18.data.o,ov_SC04_006_jr_8017AE2C.o,ov_SC04_006_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_006/ov_SC04_006.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_006/ov_SC04_006_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_006/ov_SC04_006_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_006/ov_SC04_006_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_006/ov_SC04_006_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_006/ov_SC04_006_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_006/ov_SC04_006_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_006/ov_SC04_006_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_006/ov_SC04_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3018,12 +3105,13 @@ ov_SC04_007_ELF := $(ov_SC04_007_OUT).elf ov_SC04_007_MAPFILE := $(ov_SC04_007_OUT).map ov_SC04_007_LD_SCRIPT := $(ov_SC04_007_OUT).ld ov_SC04_007_SPLAT_YAML := config/splat.ov_SC04_007.yaml -ov_SC04_007_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_007.o,ov_SC04_007_jr_8012ACE0.o,tail2.data.o,ov_SC04_007_jr_80135888.o,tail3.data.o,ov_SC04_007_jr_80135A4C.o,tail4.data.o,ov_SC04_007_jr_80135D20.o,tail5.data.o,ov_SC04_007_jr_801380E0.o,ov_SC04_007_o0c.o,tail6.data.o,ov_SC04_007_jr_8013F350.o,tail7.data.o,ov_SC04_007_jr_8013FFD8.o,tail8.data.o,ov_SC04_007_jr_80140608.o,tail9.data.o,ov_SC04_007_jr_8015444C.o,tail10.data.o,ov_SC04_007_jr_80154C24.o,ov_SC04_007_jr_801588CC.o,tail11.data.o,ov_SC04_007_jr_80159C84.o,tail12.data.o,ov_SC04_007_jr_8015A3C8.o,tail13.data.o,ov_SC04_007_jr_8015AE2C.o,tail14.data.o,ov_SC04_007_jr_8015C32C.o,tail15.data.o,ov_SC04_007_jr_8016AB6C.o,tail16.data.o,ov_SC04_007_jr_80171B4C.o,ov_SC04_007_jr_801734BC.o,tail17.data.o,ov_SC04_007_jr_801789AC.o,ov_SC04_007_jr_80178D40.o,tail18.data.o,ov_SC04_007_jr_8017A4AC.o,tail19.data.o,ov_SC04_007_jr_8017AE2C.o,ov_SC04_007_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_007_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_007.o,ov_SC04_007_jr_8012ACE0.o,tail2.data.o,ov_SC04_007_jr_80135888.o,tail3.data.o,ov_SC04_007_jr_80135A4C.o,tail4.data.o,ov_SC04_007_jr_80135D20.o,tail5.data.o,ov_SC04_007_jr_801380E0.o,ov_SC04_007_o0c.o,tail6.data.o,ov_SC04_007_jr_8013F350.o,tail7.data.o,ov_SC04_007_jr_8013FFD8.o,tail8.data.o,ov_SC04_007_jr_80140608.o,tail9.data.o,ov_SC04_007_jr_8015444C.o,ov_SC04_007_jr_80154C24.o,ov_SC04_007_jr_801588CC.o,tail10.data.o,ov_SC04_007_jr_80159C84.o,tail11.data.o,ov_SC04_007_jr_8015A3C8.o,tail12.data.o,ov_SC04_007_jr_8015AE2C.o,tail13.data.o,ov_SC04_007_jr_8015C32C.o,tail14.data.o,ov_SC04_007_jr_8016AB6C.o,tail15.data.o,ov_SC04_007_jr_80171B4C.o,ov_SC04_007_jr_801734BC.o,tail16.data.o,ov_SC04_007_jr_801789AC.o,ov_SC04_007_jr_80178D40.o,tail17.data.o,ov_SC04_007_jr_8017A4AC.o,tail18.data.o,ov_SC04_007_jr_8017AE2C.o,ov_SC04_007_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_007/ov_SC04_007.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_007/ov_SC04_007_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_007/ov_SC04_007_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_007/ov_SC04_007_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_007/ov_SC04_007_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_007/ov_SC04_007_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_007/ov_SC04_007_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_007/ov_SC04_007_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_007/ov_SC04_007_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3052,12 +3140,13 @@ ov_SC04_008_ELF := $(ov_SC04_008_OUT).elf ov_SC04_008_MAPFILE := $(ov_SC04_008_OUT).map ov_SC04_008_LD_SCRIPT := $(ov_SC04_008_OUT).ld ov_SC04_008_SPLAT_YAML := config/splat.ov_SC04_008.yaml -ov_SC04_008_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_008.o,ov_SC04_008_jr_8012ACE0.o,tail2.data.o,ov_SC04_008_jr_80135888.o,tail3.data.o,ov_SC04_008_jr_80135A4C.o,tail4.data.o,ov_SC04_008_jr_80135D20.o,tail5.data.o,ov_SC04_008_jr_801380E0.o,ov_SC04_008_o0c.o,tail6.data.o,ov_SC04_008_jr_8013F350.o,tail7.data.o,ov_SC04_008_jr_8013FFD8.o,tail8.data.o,ov_SC04_008_jr_80140608.o,tail9.data.o,ov_SC04_008_jr_8015444C.o,tail10.data.o,ov_SC04_008_jr_80154C24.o,ov_SC04_008_jr_801588CC.o,tail11.data.o,ov_SC04_008_jr_80159C84.o,tail12.data.o,ov_SC04_008_jr_8015AE2C.o,tail13.data.o,ov_SC04_008_jr_8015C32C.o,tail14.data.o,ov_SC04_008_jr_8016AB6C.o,tail15.data.o,ov_SC04_008_jr_80171B4C.o,ov_SC04_008_jr_801734BC.o,tail16.data.o,ov_SC04_008_jr_801789AC.o,ov_SC04_008_jr_80178D40.o,tail17.data.o,ov_SC04_008_jr_8017A4AC.o,tail18.data.o,ov_SC04_008_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_008_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_008.o,ov_SC04_008_jr_8012ACE0.o,tail2.data.o,ov_SC04_008_jr_80135888.o,tail3.data.o,ov_SC04_008_jr_80135A4C.o,tail4.data.o,ov_SC04_008_jr_80135D20.o,tail5.data.o,ov_SC04_008_jr_801380E0.o,ov_SC04_008_o0c.o,tail6.data.o,ov_SC04_008_jr_8013F350.o,tail7.data.o,ov_SC04_008_jr_8013FFD8.o,tail8.data.o,ov_SC04_008_jr_80140608.o,tail9.data.o,ov_SC04_008_jr_8015444C.o,ov_SC04_008_jr_80154C24.o,ov_SC04_008_jr_801588CC.o,tail10.data.o,ov_SC04_008_jr_80159C84.o,tail11.data.o,ov_SC04_008_jr_8015AE2C.o,tail12.data.o,ov_SC04_008_jr_8015C32C.o,tail13.data.o,ov_SC04_008_jr_8016AB6C.o,tail14.data.o,ov_SC04_008_jr_80171B4C.o,ov_SC04_008_jr_801734BC.o,tail15.data.o,ov_SC04_008_jr_801789AC.o,ov_SC04_008_jr_80178D40.o,tail16.data.o,ov_SC04_008_jr_8017A4AC.o,tail17.data.o,ov_SC04_008_jr_8017AE2C.o,tail18.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_008/ov_SC04_008.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_008/ov_SC04_008_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_008/ov_SC04_008_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_008/ov_SC04_008_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_008/ov_SC04_008_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_008/ov_SC04_008_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_008/ov_SC04_008_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_008/ov_SC04_008_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_008/ov_SC04_008_jr_80159C84.o: JTBL_PADS := 0,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38 @@ -3087,12 +3176,13 @@ ov_SC04_009_ELF := $(ov_SC04_009_OUT).elf ov_SC04_009_MAPFILE := $(ov_SC04_009_OUT).map ov_SC04_009_LD_SCRIPT := $(ov_SC04_009_OUT).ld ov_SC04_009_SPLAT_YAML := config/splat.ov_SC04_009.yaml -ov_SC04_009_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_009.o,ov_SC04_009_jr_8012ACE0.o,tail2.data.o,ov_SC04_009_jr_80135888.o,tail3.data.o,ov_SC04_009_jr_80135A4C.o,tail4.data.o,ov_SC04_009_jr_80135D20.o,tail5.data.o,ov_SC04_009_jr_801380E0.o,ov_SC04_009_o0c.o,tail6.data.o,ov_SC04_009_jr_8013F350.o,tail7.data.o,ov_SC04_009_jr_8013FFD8.o,tail8.data.o,ov_SC04_009_jr_80140608.o,tail9.data.o,ov_SC04_009_jr_8015444C.o,tail10.data.o,ov_SC04_009_jr_80154C24.o,ov_SC04_009_jr_801588CC.o,tail11.data.o,ov_SC04_009_jr_80159C84.o,tail12.data.o,ov_SC04_009_jr_8015A3C8.o,tail13.data.o,ov_SC04_009_jr_8015AE2C.o,tail14.data.o,ov_SC04_009_jr_8015C32C.o,tail15.data.o,ov_SC04_009_jr_8016AB6C.o,tail16.data.o,ov_SC04_009_jr_80171B4C.o,ov_SC04_009_jr_801734BC.o,tail17.data.o,ov_SC04_009_jr_801789AC.o,ov_SC04_009_jr_80178D40.o,tail18.data.o,ov_SC04_009_jr_8017A4AC.o,tail19.data.o,ov_SC04_009_jr_8017AE2C.o,ov_SC04_009_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_009_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_009.o,ov_SC04_009_jr_8012ACE0.o,tail2.data.o,ov_SC04_009_jr_80135888.o,tail3.data.o,ov_SC04_009_jr_80135A4C.o,tail4.data.o,ov_SC04_009_jr_80135D20.o,tail5.data.o,ov_SC04_009_jr_801380E0.o,ov_SC04_009_o0c.o,tail6.data.o,ov_SC04_009_jr_8013F350.o,tail7.data.o,ov_SC04_009_jr_8013FFD8.o,tail8.data.o,ov_SC04_009_jr_80140608.o,tail9.data.o,ov_SC04_009_jr_8015444C.o,ov_SC04_009_jr_80154C24.o,ov_SC04_009_jr_801588CC.o,tail10.data.o,ov_SC04_009_jr_80159C84.o,tail11.data.o,ov_SC04_009_jr_8015A3C8.o,tail12.data.o,ov_SC04_009_jr_8015AE2C.o,tail13.data.o,ov_SC04_009_jr_8015C32C.o,tail14.data.o,ov_SC04_009_jr_8016AB6C.o,tail15.data.o,ov_SC04_009_jr_80171B4C.o,ov_SC04_009_jr_801734BC.o,tail16.data.o,ov_SC04_009_jr_801789AC.o,ov_SC04_009_jr_80178D40.o,tail17.data.o,ov_SC04_009_jr_8017A4AC.o,tail18.data.o,ov_SC04_009_jr_8017AE2C.o,ov_SC04_009_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_009/ov_SC04_009.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_009/ov_SC04_009_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_009/ov_SC04_009_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_009/ov_SC04_009_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_009/ov_SC04_009_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_009/ov_SC04_009_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_009/ov_SC04_009_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_009/ov_SC04_009_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_009/ov_SC04_009_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3121,12 +3211,13 @@ ov_SC04_010_ELF := $(ov_SC04_010_OUT).elf ov_SC04_010_MAPFILE := $(ov_SC04_010_OUT).map ov_SC04_010_LD_SCRIPT := $(ov_SC04_010_OUT).ld ov_SC04_010_SPLAT_YAML := config/splat.ov_SC04_010.yaml -ov_SC04_010_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_010.o,ov_SC04_010_jr_8012ACE0.o,tail2.data.o,ov_SC04_010_jr_80135888.o,tail3.data.o,ov_SC04_010_jr_80135A4C.o,tail4.data.o,ov_SC04_010_jr_80135D20.o,tail5.data.o,ov_SC04_010_jr_801380E0.o,ov_SC04_010_o0c.o,tail6.data.o,ov_SC04_010_jr_8013F350.o,tail7.data.o,ov_SC04_010_jr_8013FFD8.o,tail8.data.o,ov_SC04_010_jr_80140608.o,tail9.data.o,ov_SC04_010_jr_8015444C.o,tail10.data.o,ov_SC04_010_jr_80154C24.o,ov_SC04_010_jr_801588CC.o,tail11.data.o,ov_SC04_010_jr_80159C84.o,tail12.data.o,ov_SC04_010_jr_8015A3C8.o,tail13.data.o,ov_SC04_010_jr_8015AE2C.o,tail14.data.o,ov_SC04_010_jr_8015C32C.o,tail15.data.o,ov_SC04_010_jr_8016AB6C.o,tail16.data.o,ov_SC04_010_jr_80171B4C.o,ov_SC04_010_jr_801734BC.o,tail17.data.o,ov_SC04_010_jr_801789AC.o,ov_SC04_010_jr_80178D40.o,tail18.data.o,ov_SC04_010_jr_8017A4AC.o,tail19.data.o,ov_SC04_010_jr_8017AE2C.o,ov_SC04_010_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_010_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_010.o,ov_SC04_010_jr_8012ACE0.o,tail2.data.o,ov_SC04_010_jr_80135888.o,tail3.data.o,ov_SC04_010_jr_80135A4C.o,tail4.data.o,ov_SC04_010_jr_80135D20.o,tail5.data.o,ov_SC04_010_jr_801380E0.o,ov_SC04_010_o0c.o,tail6.data.o,ov_SC04_010_jr_8013F350.o,tail7.data.o,ov_SC04_010_jr_8013FFD8.o,tail8.data.o,ov_SC04_010_jr_80140608.o,tail9.data.o,ov_SC04_010_jr_8015444C.o,ov_SC04_010_jr_80154C24.o,ov_SC04_010_jr_801588CC.o,tail10.data.o,ov_SC04_010_jr_80159C84.o,tail11.data.o,ov_SC04_010_jr_8015A3C8.o,tail12.data.o,ov_SC04_010_jr_8015AE2C.o,tail13.data.o,ov_SC04_010_jr_8015C32C.o,tail14.data.o,ov_SC04_010_jr_8016AB6C.o,tail15.data.o,ov_SC04_010_jr_80171B4C.o,ov_SC04_010_jr_801734BC.o,tail16.data.o,ov_SC04_010_jr_801789AC.o,ov_SC04_010_jr_80178D40.o,tail17.data.o,ov_SC04_010_jr_8017A4AC.o,tail18.data.o,ov_SC04_010_jr_8017AE2C.o,ov_SC04_010_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_010/ov_SC04_010.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_010/ov_SC04_010_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_010/ov_SC04_010_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_010/ov_SC04_010_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_010/ov_SC04_010_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_010/ov_SC04_010_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_010/ov_SC04_010_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_010/ov_SC04_010_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_010/ov_SC04_010_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3155,12 +3246,13 @@ ov_SC04_011_ELF := $(ov_SC04_011_OUT).elf ov_SC04_011_MAPFILE := $(ov_SC04_011_OUT).map ov_SC04_011_LD_SCRIPT := $(ov_SC04_011_OUT).ld ov_SC04_011_SPLAT_YAML := config/splat.ov_SC04_011.yaml -ov_SC04_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_011.o,ov_SC04_011_jr_8012ACE0.o,tail2.data.o,ov_SC04_011_jr_80135888.o,tail3.data.o,ov_SC04_011_jr_80135A4C.o,tail4.data.o,ov_SC04_011_jr_80135D20.o,tail5.data.o,ov_SC04_011_jr_801380E0.o,ov_SC04_011_o0c.o,tail6.data.o,ov_SC04_011_jr_8013F350.o,tail7.data.o,ov_SC04_011_jr_8013FFD8.o,tail8.data.o,ov_SC04_011_jr_80140608.o,tail9.data.o,ov_SC04_011_jr_8015444C.o,tail10.data.o,ov_SC04_011_jr_80154C24.o,ov_SC04_011_jr_801588CC.o,tail11.data.o,ov_SC04_011_jr_80159C84.o,tail12.data.o,ov_SC04_011_jr_8015A3C8.o,tail13.data.o,ov_SC04_011_jr_8015AE2C.o,tail14.data.o,ov_SC04_011_jr_8015C32C.o,tail15.data.o,ov_SC04_011_jr_8016AB6C.o,tail16.data.o,ov_SC04_011_jr_80171B4C.o,ov_SC04_011_jr_801734BC.o,tail17.data.o,ov_SC04_011_jr_801789AC.o,ov_SC04_011_jr_80178D40.o,tail18.data.o,ov_SC04_011_jr_8017A4AC.o,tail19.data.o,ov_SC04_011_jr_8017AE2C.o,tail20.data.o,ov_SC04_011_jr_8017D494.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_011.o,ov_SC04_011_jr_8012ACE0.o,tail2.data.o,ov_SC04_011_jr_80135888.o,tail3.data.o,ov_SC04_011_jr_80135A4C.o,tail4.data.o,ov_SC04_011_jr_80135D20.o,tail5.data.o,ov_SC04_011_jr_801380E0.o,ov_SC04_011_o0c.o,tail6.data.o,ov_SC04_011_jr_8013F350.o,tail7.data.o,ov_SC04_011_jr_8013FFD8.o,tail8.data.o,ov_SC04_011_jr_80140608.o,tail9.data.o,ov_SC04_011_jr_8015444C.o,ov_SC04_011_jr_80154C24.o,ov_SC04_011_jr_801588CC.o,tail10.data.o,ov_SC04_011_jr_80159C84.o,tail11.data.o,ov_SC04_011_jr_8015A3C8.o,tail12.data.o,ov_SC04_011_jr_8015AE2C.o,tail13.data.o,ov_SC04_011_jr_8015C32C.o,tail14.data.o,ov_SC04_011_jr_8016AB6C.o,tail15.data.o,ov_SC04_011_jr_80171B4C.o,ov_SC04_011_jr_801734BC.o,tail16.data.o,ov_SC04_011_jr_801789AC.o,ov_SC04_011_jr_80178D40.o,tail17.data.o,ov_SC04_011_jr_8017A4AC.o,tail18.data.o,ov_SC04_011_jr_8017AE2C.o,tail19.data.o,ov_SC04_011_jr_8017D494.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_011/ov_SC04_011.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_011/ov_SC04_011_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_011/ov_SC04_011_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3189,12 +3281,13 @@ ov_SC04_012_ELF := $(ov_SC04_012_OUT).elf ov_SC04_012_MAPFILE := $(ov_SC04_012_OUT).map ov_SC04_012_LD_SCRIPT := $(ov_SC04_012_OUT).ld ov_SC04_012_SPLAT_YAML := config/splat.ov_SC04_012.yaml -ov_SC04_012_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_012.o,ov_SC04_012_jr_8012ACE0.o,tail2.data.o,ov_SC04_012_jr_80135888.o,tail3.data.o,ov_SC04_012_jr_80135A4C.o,tail4.data.o,ov_SC04_012_jr_80135D20.o,tail5.data.o,ov_SC04_012_jr_801380E0.o,ov_SC04_012_o0c.o,tail6.data.o,ov_SC04_012_jr_8013F350.o,tail7.data.o,ov_SC04_012_jr_8013FFD8.o,tail8.data.o,ov_SC04_012_jr_80140608.o,tail9.data.o,ov_SC04_012_jr_8015444C.o,tail10.data.o,ov_SC04_012_jr_80154C24.o,ov_SC04_012_jr_801588CC.o,tail11.data.o,ov_SC04_012_jr_80159C84.o,tail12.data.o,ov_SC04_012_jr_8015A3C8.o,tail13.data.o,ov_SC04_012_jr_8015AE2C.o,tail14.data.o,ov_SC04_012_jr_8015C32C.o,tail15.data.o,ov_SC04_012_jr_8016AB6C.o,tail16.data.o,ov_SC04_012_jr_80171B4C.o,ov_SC04_012_jr_801734BC.o,tail17.data.o,ov_SC04_012_jr_801789AC.o,ov_SC04_012_jr_80178D40.o,tail18.data.o,ov_SC04_012_jr_8017A4AC.o,tail19.data.o,ov_SC04_012_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_012_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_012.o,ov_SC04_012_jr_8012ACE0.o,tail2.data.o,ov_SC04_012_jr_80135888.o,tail3.data.o,ov_SC04_012_jr_80135A4C.o,tail4.data.o,ov_SC04_012_jr_80135D20.o,tail5.data.o,ov_SC04_012_jr_801380E0.o,ov_SC04_012_o0c.o,tail6.data.o,ov_SC04_012_jr_8013F350.o,tail7.data.o,ov_SC04_012_jr_8013FFD8.o,tail8.data.o,ov_SC04_012_jr_80140608.o,tail9.data.o,ov_SC04_012_jr_8015444C.o,ov_SC04_012_jr_80154C24.o,ov_SC04_012_jr_801588CC.o,tail10.data.o,ov_SC04_012_jr_80159C84.o,tail11.data.o,ov_SC04_012_jr_8015A3C8.o,tail12.data.o,ov_SC04_012_jr_8015AE2C.o,tail13.data.o,ov_SC04_012_jr_8015C32C.o,tail14.data.o,ov_SC04_012_jr_8016AB6C.o,tail15.data.o,ov_SC04_012_jr_80171B4C.o,ov_SC04_012_jr_801734BC.o,tail16.data.o,ov_SC04_012_jr_801789AC.o,ov_SC04_012_jr_80178D40.o,tail17.data.o,ov_SC04_012_jr_8017A4AC.o,tail18.data.o,ov_SC04_012_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_012/ov_SC04_012.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_012/ov_SC04_012_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_012/ov_SC04_012_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_012/ov_SC04_012_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_012/ov_SC04_012_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_012/ov_SC04_012_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_012/ov_SC04_012_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_012/ov_SC04_012_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_012/ov_SC04_012_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3224,12 +3317,13 @@ ov_SC04_015_ELF := $(ov_SC04_015_OUT).elf ov_SC04_015_MAPFILE := $(ov_SC04_015_OUT).map ov_SC04_015_LD_SCRIPT := $(ov_SC04_015_OUT).ld ov_SC04_015_SPLAT_YAML := config/splat.ov_SC04_015.yaml -ov_SC04_015_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_015.o,ov_SC04_015_jr_8012ACE0.o,tail2.data.o,ov_SC04_015_jr_80135888.o,tail3.data.o,ov_SC04_015_jr_80135A4C.o,tail4.data.o,ov_SC04_015_jr_80135D20.o,tail5.data.o,ov_SC04_015_jr_801380E0.o,ov_SC04_015_o0c.o,tail6.data.o,ov_SC04_015_jr_8013F350.o,tail7.data.o,ov_SC04_015_jr_8013FFD8.o,tail8.data.o,ov_SC04_015_jr_80140608.o,tail9.data.o,ov_SC04_015_jr_8015444C.o,tail10.data.o,ov_SC04_015_jr_80154C24.o,ov_SC04_015_jr_801588CC.o,tail11.data.o,ov_SC04_015_jr_80159C84.o,tail12.data.o,ov_SC04_015_jr_8015A3C8.o,tail13.data.o,ov_SC04_015_jr_8015AE2C.o,tail14.data.o,ov_SC04_015_jr_8015C32C.o,tail15.data.o,ov_SC04_015_jr_8016AB6C.o,tail16.data.o,ov_SC04_015_jr_80171B4C.o,ov_SC04_015_jr_801734BC.o,tail17.data.o,ov_SC04_015_jr_801789AC.o,ov_SC04_015_jr_80178D40.o,tail18.data.o,ov_SC04_015_jr_8017A4AC.o,tail19.data.o,ov_SC04_015_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_015_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_015.o,ov_SC04_015_jr_8012ACE0.o,tail2.data.o,ov_SC04_015_jr_80135888.o,tail3.data.o,ov_SC04_015_jr_80135A4C.o,tail4.data.o,ov_SC04_015_jr_80135D20.o,tail5.data.o,ov_SC04_015_jr_801380E0.o,ov_SC04_015_o0c.o,tail6.data.o,ov_SC04_015_jr_8013F350.o,tail7.data.o,ov_SC04_015_jr_8013FFD8.o,tail8.data.o,ov_SC04_015_jr_80140608.o,tail9.data.o,ov_SC04_015_jr_8015444C.o,ov_SC04_015_jr_80154C24.o,ov_SC04_015_jr_801588CC.o,tail10.data.o,ov_SC04_015_jr_80159C84.o,tail11.data.o,ov_SC04_015_jr_8015A3C8.o,tail12.data.o,ov_SC04_015_jr_8015AE2C.o,tail13.data.o,ov_SC04_015_jr_8015C32C.o,tail14.data.o,ov_SC04_015_jr_8016AB6C.o,tail15.data.o,ov_SC04_015_jr_80171B4C.o,ov_SC04_015_jr_801734BC.o,tail16.data.o,ov_SC04_015_jr_801789AC.o,ov_SC04_015_jr_80178D40.o,tail17.data.o,ov_SC04_015_jr_8017A4AC.o,tail18.data.o,ov_SC04_015_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_015/ov_SC04_015.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_015/ov_SC04_015_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_015/ov_SC04_015_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_015/ov_SC04_015_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_015/ov_SC04_015_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_015/ov_SC04_015_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_015/ov_SC04_015_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_015/ov_SC04_015_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_015/ov_SC04_015_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3259,12 +3353,13 @@ ov_SC04_016_ELF := $(ov_SC04_016_OUT).elf ov_SC04_016_MAPFILE := $(ov_SC04_016_OUT).map ov_SC04_016_LD_SCRIPT := $(ov_SC04_016_OUT).ld ov_SC04_016_SPLAT_YAML := config/splat.ov_SC04_016.yaml -ov_SC04_016_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_016.o,ov_SC04_016_jr_8012ACE0.o,tail2.data.o,ov_SC04_016_jr_80135888.o,tail3.data.o,ov_SC04_016_jr_80135A4C.o,tail4.data.o,ov_SC04_016_jr_80135D20.o,tail5.data.o,ov_SC04_016_jr_801380E0.o,ov_SC04_016_o0c.o,tail6.data.o,ov_SC04_016_jr_8013F350.o,tail7.data.o,ov_SC04_016_jr_8013FFD8.o,tail8.data.o,ov_SC04_016_jr_80140608.o,tail9.data.o,ov_SC04_016_jr_8015444C.o,tail10.data.o,ov_SC04_016_jr_80154C24.o,ov_SC04_016_jr_801588CC.o,tail11.data.o,ov_SC04_016_jr_80159C84.o,tail12.data.o,ov_SC04_016_jr_8015A3C8.o,tail13.data.o,ov_SC04_016_jr_8015AE2C.o,tail14.data.o,ov_SC04_016_jr_8015C32C.o,tail15.data.o,ov_SC04_016_jr_8016AB6C.o,tail16.data.o,ov_SC04_016_jr_80171B4C.o,ov_SC04_016_jr_801734BC.o,tail17.data.o,ov_SC04_016_jr_801789AC.o,ov_SC04_016_jr_80178D40.o,tail18.data.o,ov_SC04_016_jr_8017A4AC.o,tail19.data.o,ov_SC04_016_jr_8017AE2C.o,ov_SC04_016_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_016_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_016.o,ov_SC04_016_jr_8012ACE0.o,tail2.data.o,ov_SC04_016_jr_80135888.o,tail3.data.o,ov_SC04_016_jr_80135A4C.o,tail4.data.o,ov_SC04_016_jr_80135D20.o,tail5.data.o,ov_SC04_016_jr_801380E0.o,ov_SC04_016_o0c.o,tail6.data.o,ov_SC04_016_jr_8013F350.o,tail7.data.o,ov_SC04_016_jr_8013FFD8.o,tail8.data.o,ov_SC04_016_jr_80140608.o,tail9.data.o,ov_SC04_016_jr_8015444C.o,ov_SC04_016_jr_80154C24.o,ov_SC04_016_jr_801588CC.o,tail10.data.o,ov_SC04_016_jr_80159C84.o,tail11.data.o,ov_SC04_016_jr_8015A3C8.o,tail12.data.o,ov_SC04_016_jr_8015AE2C.o,tail13.data.o,ov_SC04_016_jr_8015C32C.o,tail14.data.o,ov_SC04_016_jr_8016AB6C.o,tail15.data.o,ov_SC04_016_jr_80171B4C.o,ov_SC04_016_jr_801734BC.o,tail16.data.o,ov_SC04_016_jr_801789AC.o,ov_SC04_016_jr_80178D40.o,tail17.data.o,ov_SC04_016_jr_8017A4AC.o,tail18.data.o,ov_SC04_016_jr_8017AE2C.o,ov_SC04_016_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_016/ov_SC04_016.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_016/ov_SC04_016_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_016/ov_SC04_016_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_016/ov_SC04_016_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_016/ov_SC04_016_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_016/ov_SC04_016_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_016/ov_SC04_016_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_016/ov_SC04_016_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_016/ov_SC04_016_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3293,12 +3388,13 @@ ov_SC04_020_ELF := $(ov_SC04_020_OUT).elf ov_SC04_020_MAPFILE := $(ov_SC04_020_OUT).map ov_SC04_020_LD_SCRIPT := $(ov_SC04_020_OUT).ld ov_SC04_020_SPLAT_YAML := config/splat.ov_SC04_020.yaml -ov_SC04_020_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_020.o,ov_SC04_020_jr_8012ACE0.o,tail2.data.o,ov_SC04_020_jr_80135888.o,tail3.data.o,ov_SC04_020_jr_80135A4C.o,tail4.data.o,ov_SC04_020_jr_80135D20.o,tail5.data.o,ov_SC04_020_jr_801380E0.o,ov_SC04_020_o0c.o,tail6.data.o,ov_SC04_020_jr_8013F350.o,tail7.data.o,ov_SC04_020_jr_8013FFD8.o,tail8.data.o,ov_SC04_020_jr_80140608.o,tail9.data.o,ov_SC04_020_jr_8015444C.o,tail10.data.o,ov_SC04_020_jr_80154C24.o,ov_SC04_020_jr_801588CC.o,tail11.data.o,ov_SC04_020_jr_80159C84.o,tail12.data.o,ov_SC04_020_jr_8015A3C8.o,tail13.data.o,ov_SC04_020_jr_8015AE2C.o,tail14.data.o,ov_SC04_020_jr_8015C32C.o,tail15.data.o,ov_SC04_020_jr_8016AB6C.o,tail16.data.o,ov_SC04_020_jr_80171B4C.o,ov_SC04_020_jr_801734BC.o,tail17.data.o,ov_SC04_020_jr_801789AC.o,ov_SC04_020_jr_80178D40.o,tail18.data.o,ov_SC04_020_jr_8017A4AC.o,tail19.data.o,ov_SC04_020_jr_8017AE2C.o,ov_SC04_020_jr_8017D604.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_020_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_020.o,ov_SC04_020_jr_8012ACE0.o,tail2.data.o,ov_SC04_020_jr_80135888.o,tail3.data.o,ov_SC04_020_jr_80135A4C.o,tail4.data.o,ov_SC04_020_jr_80135D20.o,tail5.data.o,ov_SC04_020_jr_801380E0.o,ov_SC04_020_o0c.o,tail6.data.o,ov_SC04_020_jr_8013F350.o,tail7.data.o,ov_SC04_020_jr_8013FFD8.o,tail8.data.o,ov_SC04_020_jr_80140608.o,tail9.data.o,ov_SC04_020_jr_8015444C.o,ov_SC04_020_jr_80154C24.o,ov_SC04_020_jr_801588CC.o,tail10.data.o,ov_SC04_020_jr_80159C84.o,tail11.data.o,ov_SC04_020_jr_8015A3C8.o,tail12.data.o,ov_SC04_020_jr_8015AE2C.o,tail13.data.o,ov_SC04_020_jr_8015C32C.o,tail14.data.o,ov_SC04_020_jr_8016AB6C.o,tail15.data.o,ov_SC04_020_jr_80171B4C.o,ov_SC04_020_jr_801734BC.o,tail16.data.o,ov_SC04_020_jr_801789AC.o,ov_SC04_020_jr_80178D40.o,tail17.data.o,ov_SC04_020_jr_8017A4AC.o,tail18.data.o,ov_SC04_020_jr_8017AE2C.o,ov_SC04_020_jr_8017D604.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_020/ov_SC04_020.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_020/ov_SC04_020_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_020/ov_SC04_020_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_020/ov_SC04_020_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_020/ov_SC04_020_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_020/ov_SC04_020_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_020/ov_SC04_020_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_020/ov_SC04_020_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_020/ov_SC04_020_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3327,12 +3423,13 @@ ov_SC04_021_ELF := $(ov_SC04_021_OUT).elf ov_SC04_021_MAPFILE := $(ov_SC04_021_OUT).map ov_SC04_021_LD_SCRIPT := $(ov_SC04_021_OUT).ld ov_SC04_021_SPLAT_YAML := config/splat.ov_SC04_021.yaml -ov_SC04_021_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_021.o,ov_SC04_021_jr_8012ACE0.o,tail2.data.o,ov_SC04_021_jr_80135888.o,tail3.data.o,ov_SC04_021_jr_80135A4C.o,tail4.data.o,ov_SC04_021_jr_80135D20.o,tail5.data.o,ov_SC04_021_jr_801380E0.o,ov_SC04_021_o0c.o,tail6.data.o,ov_SC04_021_jr_8013F350.o,tail7.data.o,ov_SC04_021_jr_8013FFD8.o,tail8.data.o,ov_SC04_021_jr_80140608.o,tail9.data.o,ov_SC04_021_jr_8015444C.o,tail10.data.o,ov_SC04_021_jr_80154C24.o,ov_SC04_021_jr_801588CC.o,tail11.data.o,ov_SC04_021_jr_80159C84.o,tail12.data.o,ov_SC04_021_jr_8015A3C8.o,tail13.data.o,ov_SC04_021_jr_8015AE2C.o,tail14.data.o,ov_SC04_021_jr_8015C32C.o,tail15.data.o,ov_SC04_021_jr_8016AB6C.o,tail16.data.o,ov_SC04_021_jr_80171B4C.o,ov_SC04_021_jr_801734BC.o,tail17.data.o,ov_SC04_021_jr_801789AC.o,ov_SC04_021_jr_80178D40.o,tail18.data.o,ov_SC04_021_jr_8017A4AC.o,tail19.data.o,ov_SC04_021_jr_8017AE2C.o,tail20.data.o,ov_SC04_021_jr_8017D5C0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_021_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_021.o,ov_SC04_021_jr_8012ACE0.o,tail2.data.o,ov_SC04_021_jr_80135888.o,tail3.data.o,ov_SC04_021_jr_80135A4C.o,tail4.data.o,ov_SC04_021_jr_80135D20.o,tail5.data.o,ov_SC04_021_jr_801380E0.o,ov_SC04_021_o0c.o,tail6.data.o,ov_SC04_021_jr_8013F350.o,tail7.data.o,ov_SC04_021_jr_8013FFD8.o,tail8.data.o,ov_SC04_021_jr_80140608.o,tail9.data.o,ov_SC04_021_jr_8015444C.o,ov_SC04_021_jr_80154C24.o,ov_SC04_021_jr_801588CC.o,tail10.data.o,ov_SC04_021_jr_80159C84.o,tail11.data.o,ov_SC04_021_jr_8015A3C8.o,tail12.data.o,ov_SC04_021_jr_8015AE2C.o,tail13.data.o,ov_SC04_021_jr_8015C32C.o,tail14.data.o,ov_SC04_021_jr_8016AB6C.o,tail15.data.o,ov_SC04_021_jr_80171B4C.o,ov_SC04_021_jr_801734BC.o,tail16.data.o,ov_SC04_021_jr_801789AC.o,ov_SC04_021_jr_80178D40.o,tail17.data.o,ov_SC04_021_jr_8017A4AC.o,tail18.data.o,ov_SC04_021_jr_8017AE2C.o,tail19.data.o,ov_SC04_021_jr_8017D5C0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_021/ov_SC04_021.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_021/ov_SC04_021_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_021/ov_SC04_021_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC04_021/ov_SC04_021_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_021/ov_SC04_021_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC04_021/ov_SC04_021_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC04_021/ov_SC04_021_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC04_021/ov_SC04_021_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC04_021/ov_SC04_021_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3361,12 +3458,13 @@ ov_SC05_001_ELF := $(ov_SC05_001_OUT).elf ov_SC05_001_MAPFILE := $(ov_SC05_001_OUT).map ov_SC05_001_LD_SCRIPT := $(ov_SC05_001_OUT).ld ov_SC05_001_SPLAT_YAML := config/splat.ov_SC05_001.yaml -ov_SC05_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_001.o,ov_SC05_001_jr_8012ACE0.o,tail2.data.o,ov_SC05_001_jr_80135888.o,tail3.data.o,ov_SC05_001_jr_80135A4C.o,tail4.data.o,ov_SC05_001_jr_80135D20.o,tail5.data.o,ov_SC05_001_jr_801380E0.o,ov_SC05_001_o0c.o,tail6.data.o,ov_SC05_001_jr_8013F350.o,tail7.data.o,ov_SC05_001_jr_8013FFD8.o,tail8.data.o,ov_SC05_001_jr_80140608.o,tail9.data.o,ov_SC05_001_jr_8015444C.o,tail10.data.o,ov_SC05_001_jr_80154C24.o,ov_SC05_001_jr_801588CC.o,tail11.data.o,ov_SC05_001_jr_80159C84.o,tail12.data.o,ov_SC05_001_jr_8015A3C8.o,tail13.data.o,ov_SC05_001_jr_8015AE2C.o,tail14.data.o,ov_SC05_001_jr_8015C32C.o,tail15.data.o,ov_SC05_001_jr_8016AB6C.o,tail16.data.o,ov_SC05_001_jr_80171B4C.o,ov_SC05_001_jr_801734BC.o,tail17.data.o,ov_SC05_001_jr_801789AC.o,ov_SC05_001_jr_80178D40.o,tail18.data.o,ov_SC05_001_jr_8017A4AC.o,tail19.data.o,ov_SC05_001_jr_8017AE2C.o,ov_SC05_001_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_001.o,ov_SC05_001_jr_8012ACE0.o,tail2.data.o,ov_SC05_001_jr_80135888.o,tail3.data.o,ov_SC05_001_jr_80135A4C.o,tail4.data.o,ov_SC05_001_jr_80135D20.o,tail5.data.o,ov_SC05_001_jr_801380E0.o,ov_SC05_001_o0c.o,tail6.data.o,ov_SC05_001_jr_8013F350.o,tail7.data.o,ov_SC05_001_jr_8013FFD8.o,tail8.data.o,ov_SC05_001_jr_80140608.o,tail9.data.o,ov_SC05_001_jr_8015444C.o,ov_SC05_001_jr_80154C24.o,ov_SC05_001_jr_801588CC.o,tail10.data.o,ov_SC05_001_jr_80159C84.o,tail11.data.o,ov_SC05_001_jr_8015A3C8.o,tail12.data.o,ov_SC05_001_jr_8015AE2C.o,tail13.data.o,ov_SC05_001_jr_8015C32C.o,tail14.data.o,ov_SC05_001_jr_8016AB6C.o,tail15.data.o,ov_SC05_001_jr_80171B4C.o,ov_SC05_001_jr_801734BC.o,tail16.data.o,ov_SC05_001_jr_801789AC.o,ov_SC05_001_jr_80178D40.o,tail17.data.o,ov_SC05_001_jr_8017A4AC.o,tail18.data.o,ov_SC05_001_jr_8017AE2C.o,ov_SC05_001_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_001/ov_SC05_001.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_001/ov_SC05_001_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_001/ov_SC05_001_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_001/ov_SC05_001_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_001/ov_SC05_001_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_001/ov_SC05_001_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_001/ov_SC05_001_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_001/ov_SC05_001_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_001/ov_SC05_001_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3395,12 +3493,13 @@ ov_SC05_002_ELF := $(ov_SC05_002_OUT).elf ov_SC05_002_MAPFILE := $(ov_SC05_002_OUT).map ov_SC05_002_LD_SCRIPT := $(ov_SC05_002_OUT).ld ov_SC05_002_SPLAT_YAML := config/splat.ov_SC05_002.yaml -ov_SC05_002_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_002.o,ov_SC05_002_jr_8012ACE0.o,tail2.data.o,ov_SC05_002_jr_80135888.o,tail3.data.o,ov_SC05_002_jr_80135A4C.o,tail4.data.o,ov_SC05_002_jr_80135D20.o,tail5.data.o,ov_SC05_002_jr_801380E0.o,ov_SC05_002_o0c.o,tail6.data.o,ov_SC05_002_jr_8013F350.o,tail7.data.o,ov_SC05_002_jr_8013FFD8.o,tail8.data.o,ov_SC05_002_jr_80140608.o,tail9.data.o,ov_SC05_002_jr_8015444C.o,tail10.data.o,ov_SC05_002_jr_80154C24.o,ov_SC05_002_jr_801588CC.o,tail11.data.o,ov_SC05_002_jr_80159C84.o,tail12.data.o,ov_SC05_002_jr_8015A3C8.o,tail13.data.o,ov_SC05_002_jr_8015AE2C.o,tail14.data.o,ov_SC05_002_jr_8015C32C.o,tail15.data.o,ov_SC05_002_jr_8016AB6C.o,tail16.data.o,ov_SC05_002_jr_80171B4C.o,ov_SC05_002_jr_801734BC.o,tail17.data.o,ov_SC05_002_jr_801789AC.o,ov_SC05_002_jr_80178D40.o,tail18.data.o,ov_SC05_002_jr_8017A4AC.o,tail19.data.o,ov_SC05_002_jr_8017AE2C.o,ov_SC05_002_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_002_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_002.o,ov_SC05_002_jr_8012ACE0.o,tail2.data.o,ov_SC05_002_jr_80135888.o,tail3.data.o,ov_SC05_002_jr_80135A4C.o,tail4.data.o,ov_SC05_002_jr_80135D20.o,tail5.data.o,ov_SC05_002_jr_801380E0.o,ov_SC05_002_o0c.o,tail6.data.o,ov_SC05_002_jr_8013F350.o,tail7.data.o,ov_SC05_002_jr_8013FFD8.o,tail8.data.o,ov_SC05_002_jr_80140608.o,tail9.data.o,ov_SC05_002_jr_8015444C.o,ov_SC05_002_jr_80154C24.o,ov_SC05_002_jr_801588CC.o,tail10.data.o,ov_SC05_002_jr_80159C84.o,tail11.data.o,ov_SC05_002_jr_8015A3C8.o,tail12.data.o,ov_SC05_002_jr_8015AE2C.o,tail13.data.o,ov_SC05_002_jr_8015C32C.o,tail14.data.o,ov_SC05_002_jr_8016AB6C.o,tail15.data.o,ov_SC05_002_jr_80171B4C.o,ov_SC05_002_jr_801734BC.o,tail16.data.o,ov_SC05_002_jr_801789AC.o,ov_SC05_002_jr_80178D40.o,tail17.data.o,ov_SC05_002_jr_8017A4AC.o,tail18.data.o,ov_SC05_002_jr_8017AE2C.o,ov_SC05_002_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_002/ov_SC05_002.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_002/ov_SC05_002_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_002/ov_SC05_002_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_002/ov_SC05_002_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_002/ov_SC05_002_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_002/ov_SC05_002_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_002/ov_SC05_002_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_002/ov_SC05_002_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_002/ov_SC05_002_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3429,12 +3528,13 @@ ov_SC05_003_ELF := $(ov_SC05_003_OUT).elf ov_SC05_003_MAPFILE := $(ov_SC05_003_OUT).map ov_SC05_003_LD_SCRIPT := $(ov_SC05_003_OUT).ld ov_SC05_003_SPLAT_YAML := config/splat.ov_SC05_003.yaml -ov_SC05_003_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_003.o,ov_SC05_003_jr_8012ACE0.o,tail2.data.o,ov_SC05_003_jr_80135888.o,tail3.data.o,ov_SC05_003_jr_80135A4C.o,tail4.data.o,ov_SC05_003_jr_80135D20.o,tail5.data.o,ov_SC05_003_jr_801380E0.o,ov_SC05_003_o0c.o,tail6.data.o,ov_SC05_003_jr_8013F350.o,tail7.data.o,ov_SC05_003_jr_8013FFD8.o,tail8.data.o,ov_SC05_003_jr_80140608.o,tail9.data.o,ov_SC05_003_jr_8015444C.o,tail10.data.o,ov_SC05_003_jr_80154C24.o,ov_SC05_003_jr_801588CC.o,tail11.data.o,ov_SC05_003_jr_80159C84.o,tail12.data.o,ov_SC05_003_jr_8015A3C8.o,tail13.data.o,ov_SC05_003_jr_8015AE2C.o,tail14.data.o,ov_SC05_003_jr_8015C32C.o,tail15.data.o,ov_SC05_003_jr_8016AB6C.o,tail16.data.o,ov_SC05_003_jr_80171B4C.o,ov_SC05_003_jr_801734BC.o,tail17.data.o,ov_SC05_003_jr_801789AC.o,ov_SC05_003_jr_80178D40.o,tail18.data.o,ov_SC05_003_jr_8017A4AC.o,tail19.data.o,ov_SC05_003_jr_8017AE2C.o,ov_SC05_003_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_003_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_003.o,ov_SC05_003_jr_8012ACE0.o,tail2.data.o,ov_SC05_003_jr_80135888.o,tail3.data.o,ov_SC05_003_jr_80135A4C.o,tail4.data.o,ov_SC05_003_jr_80135D20.o,tail5.data.o,ov_SC05_003_jr_801380E0.o,ov_SC05_003_o0c.o,tail6.data.o,ov_SC05_003_jr_8013F350.o,tail7.data.o,ov_SC05_003_jr_8013FFD8.o,tail8.data.o,ov_SC05_003_jr_80140608.o,tail9.data.o,ov_SC05_003_jr_8015444C.o,ov_SC05_003_jr_80154C24.o,ov_SC05_003_jr_801588CC.o,tail10.data.o,ov_SC05_003_jr_80159C84.o,tail11.data.o,ov_SC05_003_jr_8015A3C8.o,tail12.data.o,ov_SC05_003_jr_8015AE2C.o,tail13.data.o,ov_SC05_003_jr_8015C32C.o,tail14.data.o,ov_SC05_003_jr_8016AB6C.o,tail15.data.o,ov_SC05_003_jr_80171B4C.o,ov_SC05_003_jr_801734BC.o,tail16.data.o,ov_SC05_003_jr_801789AC.o,ov_SC05_003_jr_80178D40.o,tail17.data.o,ov_SC05_003_jr_8017A4AC.o,tail18.data.o,ov_SC05_003_jr_8017AE2C.o,ov_SC05_003_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_003/ov_SC05_003.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_003/ov_SC05_003_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_003/ov_SC05_003_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_003/ov_SC05_003_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_003/ov_SC05_003_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_003/ov_SC05_003_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_003/ov_SC05_003_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_003/ov_SC05_003_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_003/ov_SC05_003_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3463,12 +3563,13 @@ ov_SC05_004_ELF := $(ov_SC05_004_OUT).elf ov_SC05_004_MAPFILE := $(ov_SC05_004_OUT).map ov_SC05_004_LD_SCRIPT := $(ov_SC05_004_OUT).ld ov_SC05_004_SPLAT_YAML := config/splat.ov_SC05_004.yaml -ov_SC05_004_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_004.o,ov_SC05_004_jr_8012ACE0.o,tail2.data.o,ov_SC05_004_jr_80135888.o,tail3.data.o,ov_SC05_004_jr_80135A4C.o,tail4.data.o,ov_SC05_004_jr_80135D20.o,tail5.data.o,ov_SC05_004_jr_801380E0.o,ov_SC05_004_o0c.o,tail6.data.o,ov_SC05_004_jr_8013F350.o,tail7.data.o,ov_SC05_004_jr_8014032C.o,tail8.data.o,ov_SC05_004_jr_80140608.o,tail9.data.o,ov_SC05_004_jr_8015444C.o,tail10.data.o,ov_SC05_004_jr_80154C24.o,ov_SC05_004_jr_801588CC.o,tail11.data.o,ov_SC05_004_jr_80159C84.o,tail12.data.o,ov_SC05_004_jr_8015A3C8.o,tail13.data.o,ov_SC05_004_jr_8015AE2C.o,tail14.data.o,ov_SC05_004_jr_8015C32C.o,tail15.data.o,ov_SC05_004_jr_8016AB6C.o,tail16.data.o,ov_SC05_004_jr_80171B4C.o,ov_SC05_004_jr_801734BC.o,tail17.data.o,ov_SC05_004_jr_801789AC.o,ov_SC05_004_jr_80178D40.o,tail18.data.o,ov_SC05_004_jr_8017A4AC.o,tail19.data.o,ov_SC05_004_jr_8017AE2C.o,ov_SC05_004_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_004_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_004.o,ov_SC05_004_jr_8012ACE0.o,tail2.data.o,ov_SC05_004_jr_80135888.o,tail3.data.o,ov_SC05_004_jr_80135A4C.o,tail4.data.o,ov_SC05_004_jr_80135D20.o,tail5.data.o,ov_SC05_004_jr_801380E0.o,ov_SC05_004_o0c.o,tail6.data.o,ov_SC05_004_jr_8013F350.o,tail7.data.o,ov_SC05_004_jr_8014032C.o,tail8.data.o,ov_SC05_004_jr_80140608.o,tail9.data.o,ov_SC05_004_jr_8015444C.o,ov_SC05_004_jr_80154C24.o,ov_SC05_004_jr_801588CC.o,tail10.data.o,ov_SC05_004_jr_80159C84.o,tail11.data.o,ov_SC05_004_jr_8015A3C8.o,tail12.data.o,ov_SC05_004_jr_8015AE2C.o,tail13.data.o,ov_SC05_004_jr_8015C32C.o,tail14.data.o,ov_SC05_004_jr_8016AB6C.o,tail15.data.o,ov_SC05_004_jr_80171B4C.o,ov_SC05_004_jr_801734BC.o,tail16.data.o,ov_SC05_004_jr_801789AC.o,ov_SC05_004_jr_80178D40.o,tail17.data.o,ov_SC05_004_jr_8017A4AC.o,tail18.data.o,ov_SC05_004_jr_8017AE2C.o,ov_SC05_004_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_004/ov_SC05_004.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_004/ov_SC05_004_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_004/ov_SC05_004_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_004/ov_SC05_004_jr_8013F350.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 build/src/ov_SC05_004/ov_SC05_004_jr_8014032C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC05_004/ov_SC05_004_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_004/ov_SC05_004_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_004/ov_SC05_004_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_004/ov_SC05_004_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3497,12 +3598,13 @@ ov_SC05_005_ELF := $(ov_SC05_005_OUT).elf ov_SC05_005_MAPFILE := $(ov_SC05_005_OUT).map ov_SC05_005_LD_SCRIPT := $(ov_SC05_005_OUT).ld ov_SC05_005_SPLAT_YAML := config/splat.ov_SC05_005.yaml -ov_SC05_005_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_005.o,ov_SC05_005_jr_8012ACE0.o,tail2.data.o,ov_SC05_005_jr_80135888.o,tail3.data.o,ov_SC05_005_jr_80135A4C.o,tail4.data.o,ov_SC05_005_jr_80135D20.o,tail5.data.o,ov_SC05_005_jr_801380E0.o,ov_SC05_005_o0c.o,tail6.data.o,ov_SC05_005_jr_8013F350.o,tail7.data.o,ov_SC05_005_jr_8013FFD8.o,tail8.data.o,ov_SC05_005_jr_80140608.o,tail9.data.o,ov_SC05_005_jr_8015444C.o,tail10.data.o,ov_SC05_005_jr_80154C24.o,ov_SC05_005_jr_801588CC.o,tail11.data.o,ov_SC05_005_jr_80159C84.o,tail12.data.o,ov_SC05_005_jr_8015A3C8.o,tail13.data.o,ov_SC05_005_jr_8015AE2C.o,tail14.data.o,ov_SC05_005_jr_8015C32C.o,tail15.data.o,ov_SC05_005_jr_8016AB6C.o,tail16.data.o,ov_SC05_005_jr_80171B4C.o,ov_SC05_005_jr_801734BC.o,tail17.data.o,ov_SC05_005_jr_801789AC.o,ov_SC05_005_jr_80178D40.o,tail18.data.o,ov_SC05_005_jr_8017A4AC.o,tail19.data.o,ov_SC05_005_jr_8017AE2C.o,ov_SC05_005_jr_8017D898.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_005_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_005.o,ov_SC05_005_jr_8012ACE0.o,tail2.data.o,ov_SC05_005_jr_80135888.o,tail3.data.o,ov_SC05_005_jr_80135A4C.o,tail4.data.o,ov_SC05_005_jr_80135D20.o,tail5.data.o,ov_SC05_005_jr_801380E0.o,ov_SC05_005_o0c.o,tail6.data.o,ov_SC05_005_jr_8013F350.o,tail7.data.o,ov_SC05_005_jr_8013FFD8.o,tail8.data.o,ov_SC05_005_jr_80140608.o,tail9.data.o,ov_SC05_005_jr_8015444C.o,ov_SC05_005_jr_80154C24.o,ov_SC05_005_jr_801588CC.o,tail10.data.o,ov_SC05_005_jr_80159C84.o,tail11.data.o,ov_SC05_005_jr_8015A3C8.o,tail12.data.o,ov_SC05_005_jr_8015AE2C.o,tail13.data.o,ov_SC05_005_jr_8015C32C.o,tail14.data.o,ov_SC05_005_jr_8016AB6C.o,tail15.data.o,ov_SC05_005_jr_80171B4C.o,ov_SC05_005_jr_801734BC.o,tail16.data.o,ov_SC05_005_jr_801789AC.o,ov_SC05_005_jr_80178D40.o,tail17.data.o,ov_SC05_005_jr_8017A4AC.o,tail18.data.o,ov_SC05_005_jr_8017AE2C.o,ov_SC05_005_jr_8017D898.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_005/ov_SC05_005.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_005/ov_SC05_005_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_005/ov_SC05_005_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_005/ov_SC05_005_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_005/ov_SC05_005_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_005/ov_SC05_005_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_005/ov_SC05_005_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_005/ov_SC05_005_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_005/ov_SC05_005_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3531,12 +3633,13 @@ ov_SC05_006_ELF := $(ov_SC05_006_OUT).elf ov_SC05_006_MAPFILE := $(ov_SC05_006_OUT).map ov_SC05_006_LD_SCRIPT := $(ov_SC05_006_OUT).ld ov_SC05_006_SPLAT_YAML := config/splat.ov_SC05_006.yaml -ov_SC05_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_006.o,ov_SC05_006_jr_8012ACE0.o,tail2.data.o,ov_SC05_006_jr_80135888.o,tail3.data.o,ov_SC05_006_jr_80135A4C.o,tail4.data.o,ov_SC05_006_jr_80135D20.o,tail5.data.o,ov_SC05_006_jr_801380E0.o,ov_SC05_006_o0c.o,tail6.data.o,ov_SC05_006_jr_8013F350.o,tail7.data.o,ov_SC05_006_jr_8013FFD8.o,tail8.data.o,ov_SC05_006_jr_80140608.o,tail9.data.o,ov_SC05_006_jr_8015444C.o,tail10.data.o,ov_SC05_006_jr_80154C24.o,ov_SC05_006_jr_801588CC.o,tail11.data.o,ov_SC05_006_jr_80159C84.o,tail12.data.o,ov_SC05_006_jr_8015A3C8.o,tail13.data.o,ov_SC05_006_jr_8015AE2C.o,tail14.data.o,ov_SC05_006_jr_8015C32C.o,tail15.data.o,ov_SC05_006_jr_8016AB6C.o,tail16.data.o,ov_SC05_006_jr_80171B4C.o,ov_SC05_006_jr_801734BC.o,tail17.data.o,ov_SC05_006_jr_801789AC.o,ov_SC05_006_jr_80178D40.o,tail18.data.o,ov_SC05_006_jr_8017A4AC.o,tail19.data.o,ov_SC05_006_jr_8017AE2C.o,ov_SC05_006_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_006.o,ov_SC05_006_jr_8012ACE0.o,tail2.data.o,ov_SC05_006_jr_80135888.o,tail3.data.o,ov_SC05_006_jr_80135A4C.o,tail4.data.o,ov_SC05_006_jr_80135D20.o,tail5.data.o,ov_SC05_006_jr_801380E0.o,ov_SC05_006_o0c.o,tail6.data.o,ov_SC05_006_jr_8013F350.o,tail7.data.o,ov_SC05_006_jr_8013FFD8.o,tail8.data.o,ov_SC05_006_jr_80140608.o,tail9.data.o,ov_SC05_006_jr_8015444C.o,ov_SC05_006_jr_80154C24.o,ov_SC05_006_jr_801588CC.o,tail10.data.o,ov_SC05_006_jr_80159C84.o,tail11.data.o,ov_SC05_006_jr_8015A3C8.o,tail12.data.o,ov_SC05_006_jr_8015AE2C.o,tail13.data.o,ov_SC05_006_jr_8015C32C.o,tail14.data.o,ov_SC05_006_jr_8016AB6C.o,tail15.data.o,ov_SC05_006_jr_80171B4C.o,ov_SC05_006_jr_801734BC.o,tail16.data.o,ov_SC05_006_jr_801789AC.o,ov_SC05_006_jr_80178D40.o,tail17.data.o,ov_SC05_006_jr_8017A4AC.o,tail18.data.o,ov_SC05_006_jr_8017AE2C.o,ov_SC05_006_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_006/ov_SC05_006.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_006/ov_SC05_006_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_006/ov_SC05_006_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_006/ov_SC05_006_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_006/ov_SC05_006_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_006/ov_SC05_006_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_006/ov_SC05_006_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_006/ov_SC05_006_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_006/ov_SC05_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3565,12 +3668,13 @@ ov_SC05_007_ELF := $(ov_SC05_007_OUT).elf ov_SC05_007_MAPFILE := $(ov_SC05_007_OUT).map ov_SC05_007_LD_SCRIPT := $(ov_SC05_007_OUT).ld ov_SC05_007_SPLAT_YAML := config/splat.ov_SC05_007.yaml -ov_SC05_007_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_007.o,ov_SC05_007_jr_8012ACE0.o,tail2.data.o,ov_SC05_007_jr_80135888.o,tail3.data.o,ov_SC05_007_jr_80135A4C.o,tail4.data.o,ov_SC05_007_jr_80135D20.o,tail5.data.o,ov_SC05_007_jr_801380E0.o,ov_SC05_007_o0c.o,tail6.data.o,ov_SC05_007_jr_8013F350.o,tail7.data.o,ov_SC05_007_jr_8013FFD8.o,tail8.data.o,ov_SC05_007_jr_80140608.o,tail9.data.o,ov_SC05_007_jr_8015444C.o,tail10.data.o,ov_SC05_007_jr_80154C24.o,ov_SC05_007_jr_801588CC.o,tail11.data.o,ov_SC05_007_jr_80159C84.o,tail12.data.o,ov_SC05_007_jr_8015A3C8.o,tail13.data.o,ov_SC05_007_jr_8015AE2C.o,tail14.data.o,ov_SC05_007_jr_8015C32C.o,tail15.data.o,ov_SC05_007_jr_8016AB6C.o,tail16.data.o,ov_SC05_007_jr_80171B4C.o,ov_SC05_007_jr_801734BC.o,tail17.data.o,ov_SC05_007_jr_801789AC.o,ov_SC05_007_jr_80178D40.o,tail18.data.o,ov_SC05_007_jr_8017A4AC.o,tail19.data.o,ov_SC05_007_jr_8017AE2C.o,ov_SC05_007_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_007_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_007.o,ov_SC05_007_jr_8012ACE0.o,tail2.data.o,ov_SC05_007_jr_80135888.o,tail3.data.o,ov_SC05_007_jr_80135A4C.o,tail4.data.o,ov_SC05_007_jr_80135D20.o,tail5.data.o,ov_SC05_007_jr_801380E0.o,ov_SC05_007_o0c.o,tail6.data.o,ov_SC05_007_jr_8013F350.o,tail7.data.o,ov_SC05_007_jr_8013FFD8.o,tail8.data.o,ov_SC05_007_jr_80140608.o,tail9.data.o,ov_SC05_007_jr_8015444C.o,ov_SC05_007_jr_80154C24.o,ov_SC05_007_jr_801588CC.o,tail10.data.o,ov_SC05_007_jr_80159C84.o,tail11.data.o,ov_SC05_007_jr_8015A3C8.o,tail12.data.o,ov_SC05_007_jr_8015AE2C.o,tail13.data.o,ov_SC05_007_jr_8015C32C.o,tail14.data.o,ov_SC05_007_jr_8016AB6C.o,tail15.data.o,ov_SC05_007_jr_80171B4C.o,ov_SC05_007_jr_801734BC.o,tail16.data.o,ov_SC05_007_jr_801789AC.o,ov_SC05_007_jr_80178D40.o,tail17.data.o,ov_SC05_007_jr_8017A4AC.o,tail18.data.o,ov_SC05_007_jr_8017AE2C.o,ov_SC05_007_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_007/ov_SC05_007.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_007/ov_SC05_007_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_007/ov_SC05_007_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_007/ov_SC05_007_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_007/ov_SC05_007_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_007/ov_SC05_007_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_007/ov_SC05_007_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_007/ov_SC05_007_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_007/ov_SC05_007_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3599,12 +3703,13 @@ ov_SC05_008_ELF := $(ov_SC05_008_OUT).elf ov_SC05_008_MAPFILE := $(ov_SC05_008_OUT).map ov_SC05_008_LD_SCRIPT := $(ov_SC05_008_OUT).ld ov_SC05_008_SPLAT_YAML := config/splat.ov_SC05_008.yaml -ov_SC05_008_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_008.o,ov_SC05_008_jr_8012ACE0.o,tail2.data.o,ov_SC05_008_jr_80135888.o,tail3.data.o,ov_SC05_008_jr_80135A4C.o,tail4.data.o,ov_SC05_008_jr_80135D20.o,tail5.data.o,ov_SC05_008_jr_801380E0.o,ov_SC05_008_o0c.o,tail6.data.o,ov_SC05_008_jr_8013F350.o,tail7.data.o,ov_SC05_008_jr_8013FFD8.o,tail8.data.o,ov_SC05_008_jr_80140608.o,tail9.data.o,ov_SC05_008_jr_8015444C.o,tail10.data.o,ov_SC05_008_jr_80154C24.o,ov_SC05_008_jr_801588CC.o,tail11.data.o,ov_SC05_008_jr_80159C84.o,tail12.data.o,ov_SC05_008_jr_8015A3C8.o,tail13.data.o,ov_SC05_008_jr_8015AE2C.o,tail14.data.o,ov_SC05_008_jr_8015C32C.o,tail15.data.o,ov_SC05_008_jr_8016AB6C.o,tail16.data.o,ov_SC05_008_jr_80171B4C.o,ov_SC05_008_jr_801734BC.o,tail17.data.o,ov_SC05_008_jr_801789AC.o,ov_SC05_008_jr_80178D40.o,tail18.data.o,ov_SC05_008_jr_8017A4AC.o,tail19.data.o,ov_SC05_008_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_008_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_008.o,ov_SC05_008_jr_8012ACE0.o,tail2.data.o,ov_SC05_008_jr_80135888.o,tail3.data.o,ov_SC05_008_jr_80135A4C.o,tail4.data.o,ov_SC05_008_jr_80135D20.o,tail5.data.o,ov_SC05_008_jr_801380E0.o,ov_SC05_008_o0c.o,tail6.data.o,ov_SC05_008_jr_8013F350.o,tail7.data.o,ov_SC05_008_jr_8013FFD8.o,tail8.data.o,ov_SC05_008_jr_80140608.o,tail9.data.o,ov_SC05_008_jr_8015444C.o,ov_SC05_008_jr_80154C24.o,ov_SC05_008_jr_801588CC.o,tail10.data.o,ov_SC05_008_jr_80159C84.o,tail11.data.o,ov_SC05_008_jr_8015A3C8.o,tail12.data.o,ov_SC05_008_jr_8015AE2C.o,tail13.data.o,ov_SC05_008_jr_8015C32C.o,tail14.data.o,ov_SC05_008_jr_8016AB6C.o,tail15.data.o,ov_SC05_008_jr_80171B4C.o,ov_SC05_008_jr_801734BC.o,tail16.data.o,ov_SC05_008_jr_801789AC.o,ov_SC05_008_jr_80178D40.o,tail17.data.o,ov_SC05_008_jr_8017A4AC.o,tail18.data.o,ov_SC05_008_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_008/ov_SC05_008.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_008/ov_SC05_008_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_008/ov_SC05_008_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_008/ov_SC05_008_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_008/ov_SC05_008_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_008/ov_SC05_008_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_008/ov_SC05_008_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_008/ov_SC05_008_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_008/ov_SC05_008_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3634,12 +3739,13 @@ ov_SC05_009_ELF := $(ov_SC05_009_OUT).elf ov_SC05_009_MAPFILE := $(ov_SC05_009_OUT).map ov_SC05_009_LD_SCRIPT := $(ov_SC05_009_OUT).ld ov_SC05_009_SPLAT_YAML := config/splat.ov_SC05_009.yaml -ov_SC05_009_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_009.o,ov_SC05_009_jr_8012ACE0.o,tail2.data.o,ov_SC05_009_jr_80135888.o,tail3.data.o,ov_SC05_009_jr_80135A4C.o,tail4.data.o,ov_SC05_009_jr_80135D20.o,tail5.data.o,ov_SC05_009_jr_801380E0.o,ov_SC05_009_o0c.o,tail6.data.o,ov_SC05_009_jr_8013F350.o,tail7.data.o,ov_SC05_009_jr_8013FFD8.o,tail8.data.o,ov_SC05_009_jr_80140608.o,tail9.data.o,ov_SC05_009_jr_8015444C.o,tail10.data.o,ov_SC05_009_jr_80154C24.o,ov_SC05_009_jr_801588CC.o,tail11.data.o,ov_SC05_009_jr_80159C84.o,tail12.data.o,ov_SC05_009_jr_8015AE2C.o,tail13.data.o,ov_SC05_009_jr_8015C32C.o,tail14.data.o,ov_SC05_009_jr_8016AB6C.o,tail15.data.o,ov_SC05_009_jr_80171B4C.o,ov_SC05_009_jr_801734BC.o,tail16.data.o,ov_SC05_009_jr_801789AC.o,ov_SC05_009_jr_80178D40.o,tail17.data.o,ov_SC05_009_jr_8017A4AC.o,tail18.data.o,ov_SC05_009_jr_8017AE2C.o,ov_SC05_009_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_009_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_009.o,ov_SC05_009_jr_8012ACE0.o,tail2.data.o,ov_SC05_009_jr_80135888.o,tail3.data.o,ov_SC05_009_jr_80135A4C.o,tail4.data.o,ov_SC05_009_jr_80135D20.o,tail5.data.o,ov_SC05_009_jr_801380E0.o,ov_SC05_009_o0c.o,tail6.data.o,ov_SC05_009_jr_8013F350.o,tail7.data.o,ov_SC05_009_jr_8013FFD8.o,tail8.data.o,ov_SC05_009_jr_80140608.o,tail9.data.o,ov_SC05_009_jr_8015444C.o,ov_SC05_009_jr_80154C24.o,ov_SC05_009_jr_801588CC.o,tail10.data.o,ov_SC05_009_jr_80159C84.o,tail11.data.o,ov_SC05_009_jr_8015AE2C.o,tail12.data.o,ov_SC05_009_jr_8015C32C.o,tail13.data.o,ov_SC05_009_jr_8016AB6C.o,tail14.data.o,ov_SC05_009_jr_80171B4C.o,ov_SC05_009_jr_801734BC.o,tail15.data.o,ov_SC05_009_jr_801789AC.o,ov_SC05_009_jr_80178D40.o,tail16.data.o,ov_SC05_009_jr_8017A4AC.o,tail17.data.o,ov_SC05_009_jr_8017AE2C.o,ov_SC05_009_jr_8017BEBC.o,tail18.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_009/ov_SC05_009.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_009/ov_SC05_009_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_009/ov_SC05_009_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_009/ov_SC05_009_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_009/ov_SC05_009_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_009/ov_SC05_009_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_009/ov_SC05_009_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_009/ov_SC05_009_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_009/ov_SC05_009_jr_80159C84.o: JTBL_PADS := 0,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38 @@ -3668,12 +3774,13 @@ ov_SC05_010_ELF := $(ov_SC05_010_OUT).elf ov_SC05_010_MAPFILE := $(ov_SC05_010_OUT).map ov_SC05_010_LD_SCRIPT := $(ov_SC05_010_OUT).ld ov_SC05_010_SPLAT_YAML := config/splat.ov_SC05_010.yaml -ov_SC05_010_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_010.o,ov_SC05_010_jr_8012ACE0.o,tail2.data.o,ov_SC05_010_jr_80135888.o,tail3.data.o,ov_SC05_010_jr_80135A4C.o,tail4.data.o,ov_SC05_010_jr_80135D20.o,tail5.data.o,ov_SC05_010_jr_801380E0.o,ov_SC05_010_o0c.o,tail6.data.o,ov_SC05_010_jr_8013F350.o,tail7.data.o,ov_SC05_010_jr_8013FFD8.o,tail8.data.o,ov_SC05_010_jr_80140608.o,tail9.data.o,ov_SC05_010_jr_8015444C.o,tail10.data.o,ov_SC05_010_jr_80154C24.o,ov_SC05_010_jr_801588CC.o,tail11.data.o,ov_SC05_010_jr_80159C84.o,tail12.data.o,ov_SC05_010_jr_8015A3C8.o,tail13.data.o,ov_SC05_010_jr_8015AE2C.o,tail14.data.o,ov_SC05_010_jr_8015C32C.o,tail15.data.o,ov_SC05_010_jr_8016AB6C.o,tail16.data.o,ov_SC05_010_jr_80171B4C.o,ov_SC05_010_jr_801734BC.o,tail17.data.o,ov_SC05_010_jr_801789AC.o,ov_SC05_010_jr_80178D40.o,tail18.data.o,ov_SC05_010_jr_8017A4AC.o,tail19.data.o,ov_SC05_010_jr_8017AE2C.o,tail20.data.o,ov_SC05_010_jr_8017C8D0.o,tail21.data.o,ov_SC05_010_jr_80181CDC.o,tail22.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_010_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_010.o,ov_SC05_010_jr_8012ACE0.o,tail2.data.o,ov_SC05_010_jr_80135888.o,tail3.data.o,ov_SC05_010_jr_80135A4C.o,tail4.data.o,ov_SC05_010_jr_80135D20.o,tail5.data.o,ov_SC05_010_jr_801380E0.o,ov_SC05_010_o0c.o,tail6.data.o,ov_SC05_010_jr_8013F350.o,tail7.data.o,ov_SC05_010_jr_8013FFD8.o,tail8.data.o,ov_SC05_010_jr_80140608.o,tail9.data.o,ov_SC05_010_jr_8015444C.o,ov_SC05_010_jr_80154C24.o,ov_SC05_010_jr_801588CC.o,tail10.data.o,ov_SC05_010_jr_80159C84.o,tail11.data.o,ov_SC05_010_jr_8015A3C8.o,tail12.data.o,ov_SC05_010_jr_8015AE2C.o,tail13.data.o,ov_SC05_010_jr_8015C32C.o,tail14.data.o,ov_SC05_010_jr_8016AB6C.o,tail15.data.o,ov_SC05_010_jr_80171B4C.o,ov_SC05_010_jr_801734BC.o,tail16.data.o,ov_SC05_010_jr_801789AC.o,ov_SC05_010_jr_80178D40.o,tail17.data.o,ov_SC05_010_jr_8017A4AC.o,tail18.data.o,ov_SC05_010_jr_8017AE2C.o,tail19.data.o,ov_SC05_010_jr_8017C8D0.o,tail20.data.o,ov_SC05_010_jr_80181CDC.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_010/ov_SC05_010.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_010/ov_SC05_010_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_010/ov_SC05_010_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_010/ov_SC05_010_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_010/ov_SC05_010_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_010/ov_SC05_010_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_010/ov_SC05_010_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_010/ov_SC05_010_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_010/ov_SC05_010_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3702,12 +3809,13 @@ ov_SC05_011_ELF := $(ov_SC05_011_OUT).elf ov_SC05_011_MAPFILE := $(ov_SC05_011_OUT).map ov_SC05_011_LD_SCRIPT := $(ov_SC05_011_OUT).ld ov_SC05_011_SPLAT_YAML := config/splat.ov_SC05_011.yaml -ov_SC05_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_011.o,ov_SC05_011_jr_8012ACE0.o,tail2.data.o,ov_SC05_011_jr_80135888.o,tail3.data.o,ov_SC05_011_jr_80135A4C.o,tail4.data.o,ov_SC05_011_jr_80135D20.o,tail5.data.o,ov_SC05_011_jr_801380E0.o,ov_SC05_011_o0c.o,tail6.data.o,ov_SC05_011_jr_8013F350.o,tail7.data.o,ov_SC05_011_jr_8013FFD8.o,tail8.data.o,ov_SC05_011_jr_80140608.o,tail9.data.o,ov_SC05_011_jr_8015444C.o,tail10.data.o,ov_SC05_011_jr_80154C24.o,ov_SC05_011_jr_801588CC.o,tail11.data.o,ov_SC05_011_jr_80159C84.o,tail12.data.o,ov_SC05_011_jr_8015A3C8.o,tail13.data.o,ov_SC05_011_jr_8015AE2C.o,tail14.data.o,ov_SC05_011_jr_8015C32C.o,tail15.data.o,ov_SC05_011_jr_8016AB6C.o,tail16.data.o,ov_SC05_011_jr_80171B4C.o,ov_SC05_011_jr_801734BC.o,tail17.data.o,ov_SC05_011_jr_801789AC.o,ov_SC05_011_jr_80178D40.o,tail18.data.o,ov_SC05_011_jr_8017A4AC.o,tail19.data.o,ov_SC05_011_jr_8017AE2C.o,ov_SC05_011_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_011.o,ov_SC05_011_jr_8012ACE0.o,tail2.data.o,ov_SC05_011_jr_80135888.o,tail3.data.o,ov_SC05_011_jr_80135A4C.o,tail4.data.o,ov_SC05_011_jr_80135D20.o,tail5.data.o,ov_SC05_011_jr_801380E0.o,ov_SC05_011_o0c.o,tail6.data.o,ov_SC05_011_jr_8013F350.o,tail7.data.o,ov_SC05_011_jr_8013FFD8.o,tail8.data.o,ov_SC05_011_jr_80140608.o,tail9.data.o,ov_SC05_011_jr_8015444C.o,ov_SC05_011_jr_80154C24.o,ov_SC05_011_jr_801588CC.o,tail10.data.o,ov_SC05_011_jr_80159C84.o,tail11.data.o,ov_SC05_011_jr_8015A3C8.o,tail12.data.o,ov_SC05_011_jr_8015AE2C.o,tail13.data.o,ov_SC05_011_jr_8015C32C.o,tail14.data.o,ov_SC05_011_jr_8016AB6C.o,tail15.data.o,ov_SC05_011_jr_80171B4C.o,ov_SC05_011_jr_801734BC.o,tail16.data.o,ov_SC05_011_jr_801789AC.o,ov_SC05_011_jr_80178D40.o,tail17.data.o,ov_SC05_011_jr_8017A4AC.o,tail18.data.o,ov_SC05_011_jr_8017AE2C.o,ov_SC05_011_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_011/ov_SC05_011.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_011/ov_SC05_011_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_011/ov_SC05_011_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_011/ov_SC05_011_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_011/ov_SC05_011_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_011/ov_SC05_011_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_011/ov_SC05_011_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_011/ov_SC05_011_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_011/ov_SC05_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3736,12 +3844,13 @@ ov_SC05_017_ELF := $(ov_SC05_017_OUT).elf ov_SC05_017_MAPFILE := $(ov_SC05_017_OUT).map ov_SC05_017_LD_SCRIPT := $(ov_SC05_017_OUT).ld ov_SC05_017_SPLAT_YAML := config/splat.ov_SC05_017.yaml -ov_SC05_017_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_017.o,ov_SC05_017_jr_8012ACE0.o,tail2.data.o,ov_SC05_017_jr_80135888.o,tail3.data.o,ov_SC05_017_jr_80135A4C.o,tail4.data.o,ov_SC05_017_jr_80135D20.o,tail5.data.o,ov_SC05_017_jr_801380E0.o,ov_SC05_017_o0c.o,tail6.data.o,ov_SC05_017_jr_8013F350.o,tail7.data.o,ov_SC05_017_jr_8013FFD8.o,tail8.data.o,ov_SC05_017_jr_80140608.o,tail9.data.o,ov_SC05_017_jr_8015444C.o,tail10.data.o,ov_SC05_017_jr_80154C24.o,ov_SC05_017_jr_801588CC.o,tail11.data.o,ov_SC05_017_jr_80159C84.o,tail12.data.o,ov_SC05_017_jr_8015A3C8.o,tail13.data.o,ov_SC05_017_jr_8015AE2C.o,tail14.data.o,ov_SC05_017_jr_8015C32C.o,tail15.data.o,ov_SC05_017_jr_8016AB6C.o,tail16.data.o,ov_SC05_017_jr_80171B4C.o,ov_SC05_017_jr_801734BC.o,tail17.data.o,ov_SC05_017_jr_801789AC.o,ov_SC05_017_jr_80178D40.o,tail18.data.o,ov_SC05_017_jr_8017A4AC.o,tail19.data.o,ov_SC05_017_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_017_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_017.o,ov_SC05_017_jr_8012ACE0.o,tail2.data.o,ov_SC05_017_jr_80135888.o,tail3.data.o,ov_SC05_017_jr_80135A4C.o,tail4.data.o,ov_SC05_017_jr_80135D20.o,tail5.data.o,ov_SC05_017_jr_801380E0.o,ov_SC05_017_o0c.o,tail6.data.o,ov_SC05_017_jr_8013F350.o,tail7.data.o,ov_SC05_017_jr_8013FFD8.o,tail8.data.o,ov_SC05_017_jr_80140608.o,tail9.data.o,ov_SC05_017_jr_8015444C.o,ov_SC05_017_jr_80154C24.o,ov_SC05_017_jr_801588CC.o,tail10.data.o,ov_SC05_017_jr_80159C84.o,tail11.data.o,ov_SC05_017_jr_8015A3C8.o,tail12.data.o,ov_SC05_017_jr_8015AE2C.o,tail13.data.o,ov_SC05_017_jr_8015C32C.o,tail14.data.o,ov_SC05_017_jr_8016AB6C.o,tail15.data.o,ov_SC05_017_jr_80171B4C.o,ov_SC05_017_jr_801734BC.o,tail16.data.o,ov_SC05_017_jr_801789AC.o,ov_SC05_017_jr_80178D40.o,tail17.data.o,ov_SC05_017_jr_8017A4AC.o,tail18.data.o,ov_SC05_017_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_017/ov_SC05_017.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_017/ov_SC05_017_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_017/ov_SC05_017_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_017/ov_SC05_017_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_017/ov_SC05_017_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_017/ov_SC05_017_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_017/ov_SC05_017_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_017/ov_SC05_017_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_017/ov_SC05_017_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3771,12 +3880,13 @@ ov_SC05_018_ELF := $(ov_SC05_018_OUT).elf ov_SC05_018_MAPFILE := $(ov_SC05_018_OUT).map ov_SC05_018_LD_SCRIPT := $(ov_SC05_018_OUT).ld ov_SC05_018_SPLAT_YAML := config/splat.ov_SC05_018.yaml -ov_SC05_018_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_018.o,ov_SC05_018_jr_8012ACE0.o,tail2.data.o,ov_SC05_018_jr_80135888.o,tail3.data.o,ov_SC05_018_jr_80135A4C.o,tail4.data.o,ov_SC05_018_jr_80135D20.o,tail5.data.o,ov_SC05_018_jr_801380E0.o,ov_SC05_018_o0c.o,tail6.data.o,ov_SC05_018_jr_8013F350.o,tail7.data.o,ov_SC05_018_jr_8013FFD8.o,tail8.data.o,ov_SC05_018_jr_80140608.o,tail9.data.o,ov_SC05_018_jr_8015444C.o,tail10.data.o,ov_SC05_018_jr_80154C24.o,ov_SC05_018_jr_801588CC.o,tail11.data.o,ov_SC05_018_jr_80159C84.o,tail12.data.o,ov_SC05_018_jr_8015A3C8.o,tail13.data.o,ov_SC05_018_jr_8015AE2C.o,tail14.data.o,ov_SC05_018_jr_8015C32C.o,tail15.data.o,ov_SC05_018_jr_8016AB6C.o,tail16.data.o,ov_SC05_018_jr_80171B4C.o,ov_SC05_018_jr_801734BC.o,tail17.data.o,ov_SC05_018_jr_801789AC.o,ov_SC05_018_jr_80178D40.o,tail18.data.o,ov_SC05_018_jr_8017A4AC.o,tail19.data.o,ov_SC05_018_jr_8017AE2C.o,ov_SC05_018_jr_8017D604.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_018_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_018.o,ov_SC05_018_jr_8012ACE0.o,tail2.data.o,ov_SC05_018_jr_80135888.o,tail3.data.o,ov_SC05_018_jr_80135A4C.o,tail4.data.o,ov_SC05_018_jr_80135D20.o,tail5.data.o,ov_SC05_018_jr_801380E0.o,ov_SC05_018_o0c.o,tail6.data.o,ov_SC05_018_jr_8013F350.o,tail7.data.o,ov_SC05_018_jr_8013FFD8.o,tail8.data.o,ov_SC05_018_jr_80140608.o,tail9.data.o,ov_SC05_018_jr_8015444C.o,ov_SC05_018_jr_80154C24.o,ov_SC05_018_jr_801588CC.o,tail10.data.o,ov_SC05_018_jr_80159C84.o,tail11.data.o,ov_SC05_018_jr_8015A3C8.o,tail12.data.o,ov_SC05_018_jr_8015AE2C.o,tail13.data.o,ov_SC05_018_jr_8015C32C.o,tail14.data.o,ov_SC05_018_jr_8016AB6C.o,tail15.data.o,ov_SC05_018_jr_80171B4C.o,ov_SC05_018_jr_801734BC.o,tail16.data.o,ov_SC05_018_jr_801789AC.o,ov_SC05_018_jr_80178D40.o,tail17.data.o,ov_SC05_018_jr_8017A4AC.o,tail18.data.o,ov_SC05_018_jr_8017AE2C.o,ov_SC05_018_jr_8017D604.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_018/ov_SC05_018.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_018/ov_SC05_018_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_018/ov_SC05_018_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_018/ov_SC05_018_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_018/ov_SC05_018_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_018/ov_SC05_018_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_018/ov_SC05_018_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_018/ov_SC05_018_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_018/ov_SC05_018_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3805,12 +3915,13 @@ ov_SC05_019_ELF := $(ov_SC05_019_OUT).elf ov_SC05_019_MAPFILE := $(ov_SC05_019_OUT).map ov_SC05_019_LD_SCRIPT := $(ov_SC05_019_OUT).ld ov_SC05_019_SPLAT_YAML := config/splat.ov_SC05_019.yaml -ov_SC05_019_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_019.o,ov_SC05_019_jr_8012ACE0.o,tail2.data.o,ov_SC05_019_jr_80135888.o,tail3.data.o,ov_SC05_019_jr_80135A4C.o,tail4.data.o,ov_SC05_019_jr_80135D20.o,tail5.data.o,ov_SC05_019_jr_801380E0.o,ov_SC05_019_o0c.o,tail6.data.o,ov_SC05_019_jr_8013F350.o,tail7.data.o,ov_SC05_019_jr_8013FFD8.o,tail8.data.o,ov_SC05_019_jr_80140608.o,tail9.data.o,ov_SC05_019_jr_8015444C.o,tail10.data.o,ov_SC05_019_jr_80154C24.o,ov_SC05_019_jr_801588CC.o,tail11.data.o,ov_SC05_019_jr_80159C84.o,tail12.data.o,ov_SC05_019_jr_8015A3C8.o,tail13.data.o,ov_SC05_019_jr_8015AE2C.o,tail14.data.o,ov_SC05_019_jr_8015C32C.o,tail15.data.o,ov_SC05_019_jr_8016AB6C.o,tail16.data.o,ov_SC05_019_jr_80171B4C.o,ov_SC05_019_jr_801734BC.o,tail17.data.o,ov_SC05_019_jr_801789AC.o,ov_SC05_019_jr_80178D40.o,tail18.data.o,ov_SC05_019_jr_8017A4AC.o,tail19.data.o,ov_SC05_019_jr_8017AE2C.o,tail20.data.o,ov_SC05_019_jr_8017D5C0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_019_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_019.o,ov_SC05_019_jr_8012ACE0.o,tail2.data.o,ov_SC05_019_jr_80135888.o,tail3.data.o,ov_SC05_019_jr_80135A4C.o,tail4.data.o,ov_SC05_019_jr_80135D20.o,tail5.data.o,ov_SC05_019_jr_801380E0.o,ov_SC05_019_o0c.o,tail6.data.o,ov_SC05_019_jr_8013F350.o,tail7.data.o,ov_SC05_019_jr_8013FFD8.o,tail8.data.o,ov_SC05_019_jr_80140608.o,tail9.data.o,ov_SC05_019_jr_8015444C.o,ov_SC05_019_jr_80154C24.o,ov_SC05_019_jr_801588CC.o,tail10.data.o,ov_SC05_019_jr_80159C84.o,tail11.data.o,ov_SC05_019_jr_8015A3C8.o,tail12.data.o,ov_SC05_019_jr_8015AE2C.o,tail13.data.o,ov_SC05_019_jr_8015C32C.o,tail14.data.o,ov_SC05_019_jr_8016AB6C.o,tail15.data.o,ov_SC05_019_jr_80171B4C.o,ov_SC05_019_jr_801734BC.o,tail16.data.o,ov_SC05_019_jr_801789AC.o,ov_SC05_019_jr_80178D40.o,tail17.data.o,ov_SC05_019_jr_8017A4AC.o,tail18.data.o,ov_SC05_019_jr_8017AE2C.o,tail19.data.o,ov_SC05_019_jr_8017D5C0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_019/ov_SC05_019.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_019/ov_SC05_019_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_019/ov_SC05_019_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC05_019/ov_SC05_019_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_019/ov_SC05_019_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC05_019/ov_SC05_019_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC05_019/ov_SC05_019_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC05_019/ov_SC05_019_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC05_019/ov_SC05_019_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3839,12 +3950,13 @@ ov_SC06_006_ELF := $(ov_SC06_006_OUT).elf ov_SC06_006_MAPFILE := $(ov_SC06_006_OUT).map ov_SC06_006_LD_SCRIPT := $(ov_SC06_006_OUT).ld ov_SC06_006_SPLAT_YAML := config/splat.ov_SC06_006.yaml -ov_SC06_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_006.o,ov_SC06_006_jr_8012ACE0.o,tail2.data.o,ov_SC06_006_jr_80135888.o,tail3.data.o,ov_SC06_006_jr_80135A4C.o,tail4.data.o,ov_SC06_006_jr_80135D20.o,tail5.data.o,ov_SC06_006_jr_801380E0.o,ov_SC06_006_o0c.o,tail6.data.o,ov_SC06_006_jr_8013F350.o,tail7.data.o,ov_SC06_006_jr_8013FFD8.o,tail8.data.o,ov_SC06_006_jr_80140608.o,tail9.data.o,ov_SC06_006_jr_8015444C.o,tail10.data.o,ov_SC06_006_jr_80154C24.o,ov_SC06_006_jr_801588CC.o,tail11.data.o,ov_SC06_006_jr_80159C84.o,tail12.data.o,ov_SC06_006_jr_8015A3C8.o,tail13.data.o,ov_SC06_006_jr_8015AE2C.o,tail14.data.o,ov_SC06_006_jr_8015C32C.o,tail15.data.o,ov_SC06_006_jr_8016AB6C.o,tail16.data.o,ov_SC06_006_jr_80171B4C.o,ov_SC06_006_jr_801734BC.o,tail17.data.o,ov_SC06_006_jr_801789AC.o,ov_SC06_006_jr_80178D40.o,tail18.data.o,ov_SC06_006_jr_8017A4AC.o,tail19.data.o,ov_SC06_006_jr_8017AE2C.o,ov_SC06_006_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_006.o,ov_SC06_006_jr_8012ACE0.o,tail2.data.o,ov_SC06_006_jr_80135888.o,tail3.data.o,ov_SC06_006_jr_80135A4C.o,tail4.data.o,ov_SC06_006_jr_80135D20.o,tail5.data.o,ov_SC06_006_jr_801380E0.o,ov_SC06_006_o0c.o,tail6.data.o,ov_SC06_006_jr_8013F350.o,tail7.data.o,ov_SC06_006_jr_8013FFD8.o,tail8.data.o,ov_SC06_006_jr_80140608.o,tail9.data.o,ov_SC06_006_jr_8015444C.o,ov_SC06_006_jr_80154C24.o,ov_SC06_006_jr_801588CC.o,tail10.data.o,ov_SC06_006_jr_80159C84.o,tail11.data.o,ov_SC06_006_jr_8015A3C8.o,tail12.data.o,ov_SC06_006_jr_8015AE2C.o,tail13.data.o,ov_SC06_006_jr_8015C32C.o,tail14.data.o,ov_SC06_006_jr_8016AB6C.o,tail15.data.o,ov_SC06_006_jr_80171B4C.o,ov_SC06_006_jr_801734BC.o,tail16.data.o,ov_SC06_006_jr_801789AC.o,ov_SC06_006_jr_80178D40.o,tail17.data.o,ov_SC06_006_jr_8017A4AC.o,tail18.data.o,ov_SC06_006_jr_8017AE2C.o,ov_SC06_006_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_006/ov_SC06_006.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_006/ov_SC06_006_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_006/ov_SC06_006_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_006/ov_SC06_006_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_006/ov_SC06_006_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_006/ov_SC06_006_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_006/ov_SC06_006_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_006/ov_SC06_006_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_006/ov_SC06_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3873,12 +3985,13 @@ ov_SC06_008_ELF := $(ov_SC06_008_OUT).elf ov_SC06_008_MAPFILE := $(ov_SC06_008_OUT).map ov_SC06_008_LD_SCRIPT := $(ov_SC06_008_OUT).ld ov_SC06_008_SPLAT_YAML := config/splat.ov_SC06_008.yaml -ov_SC06_008_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_008.o,ov_SC06_008_jr_8012ACE0.o,tail2.data.o,ov_SC06_008_jr_80135888.o,tail3.data.o,ov_SC06_008_jr_80135A4C.o,tail4.data.o,ov_SC06_008_jr_80135D20.o,tail5.data.o,ov_SC06_008_jr_801380E0.o,ov_SC06_008_o0c.o,tail6.data.o,ov_SC06_008_jr_8013F350.o,tail7.data.o,ov_SC06_008_jr_8013FFD8.o,tail8.data.o,ov_SC06_008_jr_80140608.o,tail9.data.o,ov_SC06_008_jr_8015444C.o,tail10.data.o,ov_SC06_008_jr_80154C24.o,ov_SC06_008_jr_801588CC.o,tail11.data.o,ov_SC06_008_jr_80159C84.o,tail12.data.o,ov_SC06_008_jr_8015A3C8.o,tail13.data.o,ov_SC06_008_jr_8015AE2C.o,tail14.data.o,ov_SC06_008_jr_8015C32C.o,tail15.data.o,ov_SC06_008_jr_8016AB6C.o,tail16.data.o,ov_SC06_008_jr_80171B4C.o,ov_SC06_008_jr_801734BC.o,tail17.data.o,ov_SC06_008_jr_801789AC.o,ov_SC06_008_jr_80178D40.o,tail18.data.o,ov_SC06_008_jr_8017A4AC.o,tail19.data.o,ov_SC06_008_jr_8017AE2C.o,ov_SC06_008_jr_8017C294.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_008_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_008.o,ov_SC06_008_jr_8012ACE0.o,tail2.data.o,ov_SC06_008_jr_80135888.o,tail3.data.o,ov_SC06_008_jr_80135A4C.o,tail4.data.o,ov_SC06_008_jr_80135D20.o,tail5.data.o,ov_SC06_008_jr_801380E0.o,ov_SC06_008_o0c.o,tail6.data.o,ov_SC06_008_jr_8013F350.o,tail7.data.o,ov_SC06_008_jr_8013FFD8.o,tail8.data.o,ov_SC06_008_jr_80140608.o,tail9.data.o,ov_SC06_008_jr_8015444C.o,ov_SC06_008_jr_80154C24.o,ov_SC06_008_jr_801588CC.o,tail10.data.o,ov_SC06_008_jr_80159C84.o,tail11.data.o,ov_SC06_008_jr_8015A3C8.o,tail12.data.o,ov_SC06_008_jr_8015AE2C.o,tail13.data.o,ov_SC06_008_jr_8015C32C.o,tail14.data.o,ov_SC06_008_jr_8016AB6C.o,tail15.data.o,ov_SC06_008_jr_80171B4C.o,ov_SC06_008_jr_801734BC.o,tail16.data.o,ov_SC06_008_jr_801789AC.o,ov_SC06_008_jr_80178D40.o,tail17.data.o,ov_SC06_008_jr_8017A4AC.o,tail18.data.o,ov_SC06_008_jr_8017AE2C.o,ov_SC06_008_jr_8017C294.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_008/ov_SC06_008.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_008/ov_SC06_008_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_008/ov_SC06_008_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_008/ov_SC06_008_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_008/ov_SC06_008_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_008/ov_SC06_008_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_008/ov_SC06_008_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_008/ov_SC06_008_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_008/ov_SC06_008_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3907,12 +4020,13 @@ ov_SC06_010_ELF := $(ov_SC06_010_OUT).elf ov_SC06_010_MAPFILE := $(ov_SC06_010_OUT).map ov_SC06_010_LD_SCRIPT := $(ov_SC06_010_OUT).ld ov_SC06_010_SPLAT_YAML := config/splat.ov_SC06_010.yaml -ov_SC06_010_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_010.o,ov_SC06_010_jr_8012ACE0.o,tail2.data.o,ov_SC06_010_jr_80135888.o,tail3.data.o,ov_SC06_010_jr_80135A4C.o,tail4.data.o,ov_SC06_010_jr_80135D20.o,tail5.data.o,ov_SC06_010_jr_801380E0.o,ov_SC06_010_o0c.o,tail6.data.o,ov_SC06_010_jr_8013F350.o,tail7.data.o,ov_SC06_010_jr_8014032C.o,tail8.data.o,ov_SC06_010_jr_80140608.o,tail9.data.o,ov_SC06_010_jr_8015444C.o,tail10.data.o,ov_SC06_010_jr_80154C24.o,ov_SC06_010_jr_801588CC.o,tail11.data.o,ov_SC06_010_jr_80159C84.o,tail12.data.o,ov_SC06_010_jr_8015A3C8.o,tail13.data.o,ov_SC06_010_jr_8015AE2C.o,tail14.data.o,ov_SC06_010_jr_8015C32C.o,tail15.data.o,ov_SC06_010_jr_8016AB6C.o,tail16.data.o,ov_SC06_010_jr_80171B4C.o,ov_SC06_010_jr_801734BC.o,tail17.data.o,ov_SC06_010_jr_801789AC.o,ov_SC06_010_jr_80178D40.o,tail18.data.o,ov_SC06_010_jr_8017A4AC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_010_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_010.o,ov_SC06_010_jr_8012ACE0.o,tail2.data.o,ov_SC06_010_jr_80135888.o,tail3.data.o,ov_SC06_010_jr_80135A4C.o,tail4.data.o,ov_SC06_010_jr_80135D20.o,tail5.data.o,ov_SC06_010_jr_801380E0.o,ov_SC06_010_o0c.o,tail6.data.o,ov_SC06_010_jr_8013F350.o,tail7.data.o,ov_SC06_010_jr_8014032C.o,tail8.data.o,ov_SC06_010_jr_80140608.o,tail9.data.o,ov_SC06_010_jr_8015444C.o,ov_SC06_010_jr_80154C24.o,ov_SC06_010_jr_801588CC.o,tail10.data.o,ov_SC06_010_jr_80159C84.o,tail11.data.o,ov_SC06_010_jr_8015A3C8.o,tail12.data.o,ov_SC06_010_jr_8015AE2C.o,tail13.data.o,ov_SC06_010_jr_8015C32C.o,tail14.data.o,ov_SC06_010_jr_8016AB6C.o,tail15.data.o,ov_SC06_010_jr_80171B4C.o,ov_SC06_010_jr_801734BC.o,tail16.data.o,ov_SC06_010_jr_801789AC.o,ov_SC06_010_jr_80178D40.o,tail17.data.o,ov_SC06_010_jr_8017A4AC.o,tail18.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_010/ov_SC06_010.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_010/ov_SC06_010_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_010/ov_SC06_010_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_010/ov_SC06_010_jr_8013F350.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 build/src/ov_SC06_010/ov_SC06_010_jr_8014032C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC06_010/ov_SC06_010_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_010/ov_SC06_010_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_010/ov_SC06_010_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_010/ov_SC06_010_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3942,12 +4056,13 @@ ov_SC06_011_ELF := $(ov_SC06_011_OUT).elf ov_SC06_011_MAPFILE := $(ov_SC06_011_OUT).map ov_SC06_011_LD_SCRIPT := $(ov_SC06_011_OUT).ld ov_SC06_011_SPLAT_YAML := config/splat.ov_SC06_011.yaml -ov_SC06_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_011.o,ov_SC06_011_jr_8012ACE0.o,tail2.data.o,ov_SC06_011_jr_80135888.o,tail3.data.o,ov_SC06_011_jr_80135A4C.o,tail4.data.o,ov_SC06_011_jr_80135D20.o,tail5.data.o,ov_SC06_011_jr_801380E0.o,ov_SC06_011_o0c.o,tail6.data.o,ov_SC06_011_jr_8013F350.o,tail7.data.o,ov_SC06_011_jr_8013FFD8.o,tail8.data.o,ov_SC06_011_jr_80140608.o,tail9.data.o,ov_SC06_011_jr_8015444C.o,tail10.data.o,ov_SC06_011_jr_80154C24.o,ov_SC06_011_jr_801588CC.o,tail11.data.o,ov_SC06_011_jr_80159C84.o,tail12.data.o,ov_SC06_011_jr_8015A3C8.o,tail13.data.o,ov_SC06_011_jr_8015AE2C.o,tail14.data.o,ov_SC06_011_jr_8015C32C.o,tail15.data.o,ov_SC06_011_jr_8016AB6C.o,tail16.data.o,ov_SC06_011_jr_80171B4C.o,ov_SC06_011_jr_801734BC.o,tail17.data.o,ov_SC06_011_jr_801789AC.o,ov_SC06_011_jr_80178D40.o,tail18.data.o,ov_SC06_011_jr_8017A4AC.o,tail19.data.o,ov_SC06_011_jr_8017AE2C.o,ov_SC06_011_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_011.o,ov_SC06_011_jr_8012ACE0.o,tail2.data.o,ov_SC06_011_jr_80135888.o,tail3.data.o,ov_SC06_011_jr_80135A4C.o,tail4.data.o,ov_SC06_011_jr_80135D20.o,tail5.data.o,ov_SC06_011_jr_801380E0.o,ov_SC06_011_o0c.o,tail6.data.o,ov_SC06_011_jr_8013F350.o,tail7.data.o,ov_SC06_011_jr_8013FFD8.o,tail8.data.o,ov_SC06_011_jr_80140608.o,tail9.data.o,ov_SC06_011_jr_8015444C.o,ov_SC06_011_jr_80154C24.o,ov_SC06_011_jr_801588CC.o,tail10.data.o,ov_SC06_011_jr_80159C84.o,tail11.data.o,ov_SC06_011_jr_8015A3C8.o,tail12.data.o,ov_SC06_011_jr_8015AE2C.o,tail13.data.o,ov_SC06_011_jr_8015C32C.o,tail14.data.o,ov_SC06_011_jr_8016AB6C.o,tail15.data.o,ov_SC06_011_jr_80171B4C.o,ov_SC06_011_jr_801734BC.o,tail16.data.o,ov_SC06_011_jr_801789AC.o,ov_SC06_011_jr_80178D40.o,tail17.data.o,ov_SC06_011_jr_8017A4AC.o,tail18.data.o,ov_SC06_011_jr_8017AE2C.o,ov_SC06_011_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_011/ov_SC06_011.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_011/ov_SC06_011_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_011/ov_SC06_011_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_011/ov_SC06_011_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_011/ov_SC06_011_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_011/ov_SC06_011_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_011/ov_SC06_011_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_011/ov_SC06_011_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_011/ov_SC06_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -3976,12 +4091,13 @@ ov_SC06_013_ELF := $(ov_SC06_013_OUT).elf ov_SC06_013_MAPFILE := $(ov_SC06_013_OUT).map ov_SC06_013_LD_SCRIPT := $(ov_SC06_013_OUT).ld ov_SC06_013_SPLAT_YAML := config/splat.ov_SC06_013.yaml -ov_SC06_013_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_013.o,ov_SC06_013_jr_8012ACE0.o,tail2.data.o,ov_SC06_013_jr_80135888.o,tail3.data.o,ov_SC06_013_jr_80135A4C.o,tail4.data.o,ov_SC06_013_jr_80135D20.o,tail5.data.o,ov_SC06_013_jr_801380E0.o,ov_SC06_013_o0c.o,tail6.data.o,ov_SC06_013_jr_8013F350.o,tail7.data.o,ov_SC06_013_jr_8013FFD8.o,tail8.data.o,ov_SC06_013_jr_80140608.o,tail9.data.o,ov_SC06_013_jr_8015444C.o,tail10.data.o,ov_SC06_013_jr_80154C24.o,ov_SC06_013_jr_801588CC.o,tail11.data.o,ov_SC06_013_jr_80159C84.o,tail12.data.o,ov_SC06_013_jr_8015A3C8.o,tail13.data.o,ov_SC06_013_jr_8015AE2C.o,tail14.data.o,ov_SC06_013_jr_8015C32C.o,tail15.data.o,ov_SC06_013_jr_8016AB6C.o,tail16.data.o,ov_SC06_013_jr_80171B4C.o,ov_SC06_013_jr_801734BC.o,tail17.data.o,ov_SC06_013_jr_801789AC.o,ov_SC06_013_jr_80178D40.o,tail18.data.o,ov_SC06_013_jr_8017A4AC.o,tail19.data.o,ov_SC06_013_jr_8017AE2C.o,ov_SC06_013_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_013_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_013.o,ov_SC06_013_jr_8012ACE0.o,tail2.data.o,ov_SC06_013_jr_80135888.o,tail3.data.o,ov_SC06_013_jr_80135A4C.o,tail4.data.o,ov_SC06_013_jr_80135D20.o,tail5.data.o,ov_SC06_013_jr_801380E0.o,ov_SC06_013_o0c.o,tail6.data.o,ov_SC06_013_jr_8013F350.o,tail7.data.o,ov_SC06_013_jr_8013FFD8.o,tail8.data.o,ov_SC06_013_jr_80140608.o,tail9.data.o,ov_SC06_013_jr_8015444C.o,ov_SC06_013_jr_80154C24.o,ov_SC06_013_jr_801588CC.o,tail10.data.o,ov_SC06_013_jr_80159C84.o,tail11.data.o,ov_SC06_013_jr_8015A3C8.o,tail12.data.o,ov_SC06_013_jr_8015AE2C.o,tail13.data.o,ov_SC06_013_jr_8015C32C.o,tail14.data.o,ov_SC06_013_jr_8016AB6C.o,tail15.data.o,ov_SC06_013_jr_80171B4C.o,ov_SC06_013_jr_801734BC.o,tail16.data.o,ov_SC06_013_jr_801789AC.o,ov_SC06_013_jr_80178D40.o,tail17.data.o,ov_SC06_013_jr_8017A4AC.o,tail18.data.o,ov_SC06_013_jr_8017AE2C.o,ov_SC06_013_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_013/ov_SC06_013.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_013/ov_SC06_013_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_013/ov_SC06_013_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_013/ov_SC06_013_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_013/ov_SC06_013_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_013/ov_SC06_013_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_013/ov_SC06_013_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_013/ov_SC06_013_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_013/ov_SC06_013_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4010,12 +4126,13 @@ ov_SC06_014_ELF := $(ov_SC06_014_OUT).elf ov_SC06_014_MAPFILE := $(ov_SC06_014_OUT).map ov_SC06_014_LD_SCRIPT := $(ov_SC06_014_OUT).ld ov_SC06_014_SPLAT_YAML := config/splat.ov_SC06_014.yaml -ov_SC06_014_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_014.o,ov_SC06_014_jr_8012ACE0.o,tail2.data.o,ov_SC06_014_jr_80135888.o,tail3.data.o,ov_SC06_014_jr_80135A4C.o,tail4.data.o,ov_SC06_014_jr_80135D20.o,tail5.data.o,ov_SC06_014_jr_801380E0.o,ov_SC06_014_o0c.o,tail6.data.o,ov_SC06_014_jr_8013F350.o,tail7.data.o,ov_SC06_014_jr_8013FFD8.o,tail8.data.o,ov_SC06_014_jr_80140608.o,tail9.data.o,ov_SC06_014_jr_8015444C.o,tail10.data.o,ov_SC06_014_jr_80154C24.o,ov_SC06_014_jr_801588CC.o,tail11.data.o,ov_SC06_014_jr_80159C84.o,tail12.data.o,ov_SC06_014_jr_8015A3C8.o,tail13.data.o,ov_SC06_014_jr_8015AE2C.o,tail14.data.o,ov_SC06_014_jr_8015C32C.o,tail15.data.o,ov_SC06_014_jr_8016AB6C.o,tail16.data.o,ov_SC06_014_jr_80171B4C.o,ov_SC06_014_jr_801734BC.o,tail17.data.o,ov_SC06_014_jr_801789AC.o,ov_SC06_014_jr_80178D40.o,tail18.data.o,ov_SC06_014_jr_8017A4AC.o,tail19.data.o,ov_SC06_014_jr_8017AE2C.o,ov_SC06_014_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_014_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_014.o,ov_SC06_014_jr_8012ACE0.o,tail2.data.o,ov_SC06_014_jr_80135888.o,tail3.data.o,ov_SC06_014_jr_80135A4C.o,tail4.data.o,ov_SC06_014_jr_80135D20.o,tail5.data.o,ov_SC06_014_jr_801380E0.o,ov_SC06_014_o0c.o,tail6.data.o,ov_SC06_014_jr_8013F350.o,tail7.data.o,ov_SC06_014_jr_8013FFD8.o,tail8.data.o,ov_SC06_014_jr_80140608.o,tail9.data.o,ov_SC06_014_jr_8015444C.o,ov_SC06_014_jr_80154C24.o,ov_SC06_014_jr_801588CC.o,tail10.data.o,ov_SC06_014_jr_80159C84.o,tail11.data.o,ov_SC06_014_jr_8015A3C8.o,tail12.data.o,ov_SC06_014_jr_8015AE2C.o,tail13.data.o,ov_SC06_014_jr_8015C32C.o,tail14.data.o,ov_SC06_014_jr_8016AB6C.o,tail15.data.o,ov_SC06_014_jr_80171B4C.o,ov_SC06_014_jr_801734BC.o,tail16.data.o,ov_SC06_014_jr_801789AC.o,ov_SC06_014_jr_80178D40.o,tail17.data.o,ov_SC06_014_jr_8017A4AC.o,tail18.data.o,ov_SC06_014_jr_8017AE2C.o,ov_SC06_014_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_014/ov_SC06_014.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_014/ov_SC06_014_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_014/ov_SC06_014_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_014/ov_SC06_014_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_014/ov_SC06_014_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_014/ov_SC06_014_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_014/ov_SC06_014_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_014/ov_SC06_014_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_014/ov_SC06_014_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4044,12 +4161,13 @@ ov_SC06_015_ELF := $(ov_SC06_015_OUT).elf ov_SC06_015_MAPFILE := $(ov_SC06_015_OUT).map ov_SC06_015_LD_SCRIPT := $(ov_SC06_015_OUT).ld ov_SC06_015_SPLAT_YAML := config/splat.ov_SC06_015.yaml -ov_SC06_015_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_015.o,ov_SC06_015_jr_8012ACE0.o,tail2.data.o,ov_SC06_015_jr_80135888.o,tail3.data.o,ov_SC06_015_jr_80135A4C.o,tail4.data.o,ov_SC06_015_jr_80135D20.o,tail5.data.o,ov_SC06_015_jr_801380E0.o,ov_SC06_015_o0c.o,tail6.data.o,ov_SC06_015_jr_8013F350.o,tail7.data.o,ov_SC06_015_jr_8013FFD8.o,tail8.data.o,ov_SC06_015_jr_80140608.o,tail9.data.o,ov_SC06_015_jr_8015444C.o,tail10.data.o,ov_SC06_015_jr_80154C24.o,ov_SC06_015_jr_801588CC.o,tail11.data.o,ov_SC06_015_jr_80159C84.o,tail12.data.o,ov_SC06_015_jr_8015A3C8.o,tail13.data.o,ov_SC06_015_jr_8015AE2C.o,tail14.data.o,ov_SC06_015_jr_8015C32C.o,tail15.data.o,ov_SC06_015_jr_8016AB6C.o,tail16.data.o,ov_SC06_015_jr_80171B4C.o,ov_SC06_015_jr_801734BC.o,tail17.data.o,ov_SC06_015_jr_801789AC.o,ov_SC06_015_jr_80178D40.o,tail18.data.o,ov_SC06_015_jr_8017A4AC.o,tail19.data.o,ov_SC06_015_jr_8017AE2C.o,ov_SC06_015_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_015_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_015.o,ov_SC06_015_jr_8012ACE0.o,tail2.data.o,ov_SC06_015_jr_80135888.o,tail3.data.o,ov_SC06_015_jr_80135A4C.o,tail4.data.o,ov_SC06_015_jr_80135D20.o,tail5.data.o,ov_SC06_015_jr_801380E0.o,ov_SC06_015_o0c.o,tail6.data.o,ov_SC06_015_jr_8013F350.o,tail7.data.o,ov_SC06_015_jr_8013FFD8.o,tail8.data.o,ov_SC06_015_jr_80140608.o,tail9.data.o,ov_SC06_015_jr_8015444C.o,ov_SC06_015_jr_80154C24.o,ov_SC06_015_jr_801588CC.o,tail10.data.o,ov_SC06_015_jr_80159C84.o,tail11.data.o,ov_SC06_015_jr_8015A3C8.o,tail12.data.o,ov_SC06_015_jr_8015AE2C.o,tail13.data.o,ov_SC06_015_jr_8015C32C.o,tail14.data.o,ov_SC06_015_jr_8016AB6C.o,tail15.data.o,ov_SC06_015_jr_80171B4C.o,ov_SC06_015_jr_801734BC.o,tail16.data.o,ov_SC06_015_jr_801789AC.o,ov_SC06_015_jr_80178D40.o,tail17.data.o,ov_SC06_015_jr_8017A4AC.o,tail18.data.o,ov_SC06_015_jr_8017AE2C.o,ov_SC06_015_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_015/ov_SC06_015.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_015/ov_SC06_015_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_015/ov_SC06_015_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_015/ov_SC06_015_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_015/ov_SC06_015_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_015/ov_SC06_015_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_015/ov_SC06_015_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_015/ov_SC06_015_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_015/ov_SC06_015_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4078,12 +4196,13 @@ ov_SC06_016_ELF := $(ov_SC06_016_OUT).elf ov_SC06_016_MAPFILE := $(ov_SC06_016_OUT).map ov_SC06_016_LD_SCRIPT := $(ov_SC06_016_OUT).ld ov_SC06_016_SPLAT_YAML := config/splat.ov_SC06_016.yaml -ov_SC06_016_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_016.o,ov_SC06_016_jr_8012ACE0.o,tail2.data.o,ov_SC06_016_jr_80135888.o,tail3.data.o,ov_SC06_016_jr_80135A4C.o,tail4.data.o,ov_SC06_016_jr_80135D20.o,tail5.data.o,ov_SC06_016_jr_801380E0.o,ov_SC06_016_o0c.o,tail6.data.o,ov_SC06_016_jr_8013F350.o,tail7.data.o,ov_SC06_016_jr_8013FFD8.o,tail8.data.o,ov_SC06_016_jr_80140608.o,tail9.data.o,ov_SC06_016_jr_8015444C.o,tail10.data.o,ov_SC06_016_jr_80154C24.o,ov_SC06_016_jr_801588CC.o,tail11.data.o,ov_SC06_016_jr_80159C84.o,tail12.data.o,ov_SC06_016_jr_8015A3C8.o,tail13.data.o,ov_SC06_016_jr_8015AE2C.o,tail14.data.o,ov_SC06_016_jr_8015C32C.o,tail15.data.o,ov_SC06_016_jr_8016AB6C.o,tail16.data.o,ov_SC06_016_jr_80171B4C.o,ov_SC06_016_jr_801734BC.o,tail17.data.o,ov_SC06_016_jr_801789AC.o,ov_SC06_016_jr_80178D40.o,tail18.data.o,ov_SC06_016_jr_8017A4AC.o,tail19.data.o,ov_SC06_016_jr_8017AE2C.o,tail20.data.o,ov_SC06_016_jr_8017C8D0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_016_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_016.o,ov_SC06_016_jr_8012ACE0.o,tail2.data.o,ov_SC06_016_jr_80135888.o,tail3.data.o,ov_SC06_016_jr_80135A4C.o,tail4.data.o,ov_SC06_016_jr_80135D20.o,tail5.data.o,ov_SC06_016_jr_801380E0.o,ov_SC06_016_o0c.o,tail6.data.o,ov_SC06_016_jr_8013F350.o,tail7.data.o,ov_SC06_016_jr_8013FFD8.o,tail8.data.o,ov_SC06_016_jr_80140608.o,tail9.data.o,ov_SC06_016_jr_8015444C.o,ov_SC06_016_jr_80154C24.o,ov_SC06_016_jr_801588CC.o,tail10.data.o,ov_SC06_016_jr_80159C84.o,tail11.data.o,ov_SC06_016_jr_8015A3C8.o,tail12.data.o,ov_SC06_016_jr_8015AE2C.o,tail13.data.o,ov_SC06_016_jr_8015C32C.o,tail14.data.o,ov_SC06_016_jr_8016AB6C.o,tail15.data.o,ov_SC06_016_jr_80171B4C.o,ov_SC06_016_jr_801734BC.o,tail16.data.o,ov_SC06_016_jr_801789AC.o,ov_SC06_016_jr_80178D40.o,tail17.data.o,ov_SC06_016_jr_8017A4AC.o,tail18.data.o,ov_SC06_016_jr_8017AE2C.o,tail19.data.o,ov_SC06_016_jr_8017C8D0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_016/ov_SC06_016.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_016/ov_SC06_016_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_016/ov_SC06_016_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_016/ov_SC06_016_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_016/ov_SC06_016_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_016/ov_SC06_016_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_016/ov_SC06_016_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_016/ov_SC06_016_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_016/ov_SC06_016_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4112,12 +4231,13 @@ ov_SC06_018_ELF := $(ov_SC06_018_OUT).elf ov_SC06_018_MAPFILE := $(ov_SC06_018_OUT).map ov_SC06_018_LD_SCRIPT := $(ov_SC06_018_OUT).ld ov_SC06_018_SPLAT_YAML := config/splat.ov_SC06_018.yaml -ov_SC06_018_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_018.o,ov_SC06_018_jr_8012ACE0.o,tail2.data.o,ov_SC06_018_jr_80135888.o,tail3.data.o,ov_SC06_018_jr_80135A4C.o,tail4.data.o,ov_SC06_018_jr_80135D20.o,tail5.data.o,ov_SC06_018_jr_801380E0.o,ov_SC06_018_o0c.o,tail6.data.o,ov_SC06_018_jr_8013F350.o,tail7.data.o,ov_SC06_018_jr_8013FFD8.o,tail8.data.o,ov_SC06_018_jr_80140608.o,tail9.data.o,ov_SC06_018_jr_8015444C.o,tail10.data.o,ov_SC06_018_jr_80154C24.o,ov_SC06_018_jr_801588CC.o,tail11.data.o,ov_SC06_018_jr_80159C84.o,tail12.data.o,ov_SC06_018_jr_8015A3C8.o,tail13.data.o,ov_SC06_018_jr_8015AE2C.o,tail14.data.o,ov_SC06_018_jr_8015C32C.o,tail15.data.o,ov_SC06_018_jr_8016AB6C.o,tail16.data.o,ov_SC06_018_jr_80171B4C.o,ov_SC06_018_jr_801734BC.o,tail17.data.o,ov_SC06_018_jr_801789AC.o,ov_SC06_018_jr_80178D40.o,tail18.data.o,ov_SC06_018_jr_8017A4AC.o,tail19.data.o,ov_SC06_018_jr_8017AE2C.o,ov_SC06_018_jr_8017C24C.o,tail20.data.o,ov_SC06_018_jr_8019059C.o,tail21.data.o,ov_SC06_018_jr_80191C50.o,tail22.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_018_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_018.o,ov_SC06_018_jr_8012ACE0.o,tail2.data.o,ov_SC06_018_jr_80135888.o,tail3.data.o,ov_SC06_018_jr_80135A4C.o,tail4.data.o,ov_SC06_018_jr_80135D20.o,tail5.data.o,ov_SC06_018_jr_801380E0.o,ov_SC06_018_o0c.o,tail6.data.o,ov_SC06_018_jr_8013F350.o,tail7.data.o,ov_SC06_018_jr_8013FFD8.o,tail8.data.o,ov_SC06_018_jr_80140608.o,tail9.data.o,ov_SC06_018_jr_8015444C.o,ov_SC06_018_jr_80154C24.o,ov_SC06_018_jr_801588CC.o,tail10.data.o,ov_SC06_018_jr_80159C84.o,tail11.data.o,ov_SC06_018_jr_8015A3C8.o,tail12.data.o,ov_SC06_018_jr_8015AE2C.o,tail13.data.o,ov_SC06_018_jr_8015C32C.o,tail14.data.o,ov_SC06_018_jr_8016AB6C.o,tail15.data.o,ov_SC06_018_jr_80171B4C.o,ov_SC06_018_jr_801734BC.o,tail16.data.o,ov_SC06_018_jr_801789AC.o,ov_SC06_018_jr_80178D40.o,tail17.data.o,ov_SC06_018_jr_8017A4AC.o,tail18.data.o,ov_SC06_018_jr_8017AE2C.o,ov_SC06_018_jr_8017C24C.o,tail19.data.o,ov_SC06_018_jr_8019059C.o,tail20.data.o,ov_SC06_018_jr_80191C50.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_018/ov_SC06_018.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_018/ov_SC06_018_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_018/ov_SC06_018_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_018/ov_SC06_018_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_018/ov_SC06_018_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_018/ov_SC06_018_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_018/ov_SC06_018_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_018/ov_SC06_018_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_018/ov_SC06_018_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4146,12 +4266,13 @@ ov_SC06_020_ELF := $(ov_SC06_020_OUT).elf ov_SC06_020_MAPFILE := $(ov_SC06_020_OUT).map ov_SC06_020_LD_SCRIPT := $(ov_SC06_020_OUT).ld ov_SC06_020_SPLAT_YAML := config/splat.ov_SC06_020.yaml -ov_SC06_020_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_020.o,ov_SC06_020_jr_8012ACE0.o,tail2.data.o,ov_SC06_020_jr_80135888.o,tail3.data.o,ov_SC06_020_jr_80135A4C.o,tail4.data.o,ov_SC06_020_jr_80135D20.o,tail5.data.o,ov_SC06_020_jr_801380E0.o,ov_SC06_020_o0c.o,tail6.data.o,ov_SC06_020_jr_8013F350.o,tail7.data.o,ov_SC06_020_jr_8013FFD8.o,tail8.data.o,ov_SC06_020_jr_80140608.o,tail9.data.o,ov_SC06_020_jr_8015444C.o,tail10.data.o,ov_SC06_020_jr_80154C24.o,ov_SC06_020_jr_801588CC.o,tail11.data.o,ov_SC06_020_jr_80159C84.o,tail12.data.o,ov_SC06_020_jr_8015A3C8.o,tail13.data.o,ov_SC06_020_jr_8015AE2C.o,tail14.data.o,ov_SC06_020_jr_8015C32C.o,tail15.data.o,ov_SC06_020_jr_8016AB6C.o,tail16.data.o,ov_SC06_020_jr_80171B4C.o,ov_SC06_020_jr_801734BC.o,tail17.data.o,ov_SC06_020_jr_801789AC.o,ov_SC06_020_jr_80178D40.o,tail18.data.o,ov_SC06_020_jr_8017A4AC.o,tail19.data.o,ov_SC06_020_jr_8017AE2C.o,ov_SC06_020_jr_8017C24C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_020_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_020.o,ov_SC06_020_jr_8012ACE0.o,tail2.data.o,ov_SC06_020_jr_80135888.o,tail3.data.o,ov_SC06_020_jr_80135A4C.o,tail4.data.o,ov_SC06_020_jr_80135D20.o,tail5.data.o,ov_SC06_020_jr_801380E0.o,ov_SC06_020_o0c.o,tail6.data.o,ov_SC06_020_jr_8013F350.o,tail7.data.o,ov_SC06_020_jr_8013FFD8.o,tail8.data.o,ov_SC06_020_jr_80140608.o,tail9.data.o,ov_SC06_020_jr_8015444C.o,ov_SC06_020_jr_80154C24.o,ov_SC06_020_jr_801588CC.o,tail10.data.o,ov_SC06_020_jr_80159C84.o,tail11.data.o,ov_SC06_020_jr_8015A3C8.o,tail12.data.o,ov_SC06_020_jr_8015AE2C.o,tail13.data.o,ov_SC06_020_jr_8015C32C.o,tail14.data.o,ov_SC06_020_jr_8016AB6C.o,tail15.data.o,ov_SC06_020_jr_80171B4C.o,ov_SC06_020_jr_801734BC.o,tail16.data.o,ov_SC06_020_jr_801789AC.o,ov_SC06_020_jr_80178D40.o,tail17.data.o,ov_SC06_020_jr_8017A4AC.o,tail18.data.o,ov_SC06_020_jr_8017AE2C.o,ov_SC06_020_jr_8017C24C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_020/ov_SC06_020.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_020/ov_SC06_020_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_020/ov_SC06_020_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_020/ov_SC06_020_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_020/ov_SC06_020_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_020/ov_SC06_020_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_020/ov_SC06_020_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_020/ov_SC06_020_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_020/ov_SC06_020_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4180,12 +4301,13 @@ ov_SC06_022_ELF := $(ov_SC06_022_OUT).elf ov_SC06_022_MAPFILE := $(ov_SC06_022_OUT).map ov_SC06_022_LD_SCRIPT := $(ov_SC06_022_OUT).ld ov_SC06_022_SPLAT_YAML := config/splat.ov_SC06_022.yaml -ov_SC06_022_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_022.o,ov_SC06_022_jr_8012ACE0.o,tail2.data.o,ov_SC06_022_jr_80135888.o,tail3.data.o,ov_SC06_022_jr_80135A4C.o,tail4.data.o,ov_SC06_022_jr_80135D20.o,tail5.data.o,ov_SC06_022_jr_801380E0.o,ov_SC06_022_o0c.o,tail6.data.o,ov_SC06_022_jr_8013F350.o,tail7.data.o,ov_SC06_022_jr_8013FFD8.o,tail8.data.o,ov_SC06_022_jr_80140608.o,tail9.data.o,ov_SC06_022_jr_8015444C.o,tail10.data.o,ov_SC06_022_jr_80154C24.o,ov_SC06_022_jr_801588CC.o,tail11.data.o,ov_SC06_022_jr_80159C84.o,tail12.data.o,ov_SC06_022_jr_8015A3C8.o,tail13.data.o,ov_SC06_022_jr_8015AE2C.o,tail14.data.o,ov_SC06_022_jr_8015C32C.o,tail15.data.o,ov_SC06_022_jr_8016AB6C.o,tail16.data.o,ov_SC06_022_jr_80171B4C.o,ov_SC06_022_jr_801734BC.o,tail17.data.o,ov_SC06_022_jr_801789AC.o,ov_SC06_022_jr_80178D40.o,tail18.data.o,ov_SC06_022_jr_8017A4AC.o,tail19.data.o,ov_SC06_022_jr_8017AE2C.o,ov_SC06_022_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_022_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_022.o,ov_SC06_022_jr_8012ACE0.o,tail2.data.o,ov_SC06_022_jr_80135888.o,tail3.data.o,ov_SC06_022_jr_80135A4C.o,tail4.data.o,ov_SC06_022_jr_80135D20.o,tail5.data.o,ov_SC06_022_jr_801380E0.o,ov_SC06_022_o0c.o,tail6.data.o,ov_SC06_022_jr_8013F350.o,tail7.data.o,ov_SC06_022_jr_8013FFD8.o,tail8.data.o,ov_SC06_022_jr_80140608.o,tail9.data.o,ov_SC06_022_jr_8015444C.o,ov_SC06_022_jr_80154C24.o,ov_SC06_022_jr_801588CC.o,tail10.data.o,ov_SC06_022_jr_80159C84.o,tail11.data.o,ov_SC06_022_jr_8015A3C8.o,tail12.data.o,ov_SC06_022_jr_8015AE2C.o,tail13.data.o,ov_SC06_022_jr_8015C32C.o,tail14.data.o,ov_SC06_022_jr_8016AB6C.o,tail15.data.o,ov_SC06_022_jr_80171B4C.o,ov_SC06_022_jr_801734BC.o,tail16.data.o,ov_SC06_022_jr_801789AC.o,ov_SC06_022_jr_80178D40.o,tail17.data.o,ov_SC06_022_jr_8017A4AC.o,tail18.data.o,ov_SC06_022_jr_8017AE2C.o,ov_SC06_022_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_022/ov_SC06_022.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_022/ov_SC06_022_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_022/ov_SC06_022_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_022/ov_SC06_022_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_022/ov_SC06_022_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_022/ov_SC06_022_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_022/ov_SC06_022_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_022/ov_SC06_022_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_022/ov_SC06_022_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4214,12 +4336,13 @@ ov_SC06_024_ELF := $(ov_SC06_024_OUT).elf ov_SC06_024_MAPFILE := $(ov_SC06_024_OUT).map ov_SC06_024_LD_SCRIPT := $(ov_SC06_024_OUT).ld ov_SC06_024_SPLAT_YAML := config/splat.ov_SC06_024.yaml -ov_SC06_024_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_024.o,ov_SC06_024_jr_8012ACE0.o,tail2.data.o,ov_SC06_024_jr_80135888.o,tail3.data.o,ov_SC06_024_jr_80135A4C.o,tail4.data.o,ov_SC06_024_jr_80135D20.o,tail5.data.o,ov_SC06_024_jr_801380E0.o,ov_SC06_024_o0c.o,tail6.data.o,ov_SC06_024_jr_8013F350.o,tail7.data.o,ov_SC06_024_jr_8013FFD8.o,tail8.data.o,ov_SC06_024_jr_80140608.o,tail9.data.o,ov_SC06_024_jr_8015444C.o,tail10.data.o,ov_SC06_024_jr_80154C24.o,ov_SC06_024_jr_801588CC.o,tail11.data.o,ov_SC06_024_jr_80159C84.o,tail12.data.o,ov_SC06_024_jr_8015A3C8.o,tail13.data.o,ov_SC06_024_jr_8015AE2C.o,tail14.data.o,ov_SC06_024_jr_8015C32C.o,tail15.data.o,ov_SC06_024_jr_8016AB6C.o,tail16.data.o,ov_SC06_024_jr_80171B4C.o,ov_SC06_024_jr_801734BC.o,tail17.data.o,ov_SC06_024_jr_801789AC.o,ov_SC06_024_jr_80178D40.o,tail18.data.o,ov_SC06_024_jr_8017A4AC.o,tail19.data.o,ov_SC06_024_jr_8017AE2C.o,ov_SC06_024_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_024_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_024.o,ov_SC06_024_jr_8012ACE0.o,tail2.data.o,ov_SC06_024_jr_80135888.o,tail3.data.o,ov_SC06_024_jr_80135A4C.o,tail4.data.o,ov_SC06_024_jr_80135D20.o,tail5.data.o,ov_SC06_024_jr_801380E0.o,ov_SC06_024_o0c.o,tail6.data.o,ov_SC06_024_jr_8013F350.o,tail7.data.o,ov_SC06_024_jr_8013FFD8.o,tail8.data.o,ov_SC06_024_jr_80140608.o,tail9.data.o,ov_SC06_024_jr_8015444C.o,ov_SC06_024_jr_80154C24.o,ov_SC06_024_jr_801588CC.o,tail10.data.o,ov_SC06_024_jr_80159C84.o,tail11.data.o,ov_SC06_024_jr_8015A3C8.o,tail12.data.o,ov_SC06_024_jr_8015AE2C.o,tail13.data.o,ov_SC06_024_jr_8015C32C.o,tail14.data.o,ov_SC06_024_jr_8016AB6C.o,tail15.data.o,ov_SC06_024_jr_80171B4C.o,ov_SC06_024_jr_801734BC.o,tail16.data.o,ov_SC06_024_jr_801789AC.o,ov_SC06_024_jr_80178D40.o,tail17.data.o,ov_SC06_024_jr_8017A4AC.o,tail18.data.o,ov_SC06_024_jr_8017AE2C.o,ov_SC06_024_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_024/ov_SC06_024.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_024/ov_SC06_024_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_024/ov_SC06_024_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_024/ov_SC06_024_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_024/ov_SC06_024_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_024/ov_SC06_024_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_024/ov_SC06_024_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_024/ov_SC06_024_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_024/ov_SC06_024_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4248,12 +4371,13 @@ ov_SC06_025_ELF := $(ov_SC06_025_OUT).elf ov_SC06_025_MAPFILE := $(ov_SC06_025_OUT).map ov_SC06_025_LD_SCRIPT := $(ov_SC06_025_OUT).ld ov_SC06_025_SPLAT_YAML := config/splat.ov_SC06_025.yaml -ov_SC06_025_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_025.o,ov_SC06_025_jr_8012ACE0.o,tail2.data.o,ov_SC06_025_jr_80135888.o,tail3.data.o,ov_SC06_025_jr_80135A4C.o,tail4.data.o,ov_SC06_025_jr_80135D20.o,tail5.data.o,ov_SC06_025_jr_801380E0.o,ov_SC06_025_o0c.o,tail6.data.o,ov_SC06_025_jr_8013F350.o,tail7.data.o,ov_SC06_025_jr_8013FFD8.o,tail8.data.o,ov_SC06_025_jr_80140608.o,tail9.data.o,ov_SC06_025_jr_8015444C.o,tail10.data.o,ov_SC06_025_jr_80154C24.o,ov_SC06_025_jr_801588CC.o,tail11.data.o,ov_SC06_025_jr_80159C84.o,tail12.data.o,ov_SC06_025_jr_8015A3C8.o,tail13.data.o,ov_SC06_025_jr_8015AE2C.o,tail14.data.o,ov_SC06_025_jr_8015C32C.o,tail15.data.o,ov_SC06_025_jr_8016AB6C.o,tail16.data.o,ov_SC06_025_jr_80171B4C.o,ov_SC06_025_jr_801734BC.o,tail17.data.o,ov_SC06_025_jr_801789AC.o,ov_SC06_025_jr_80178D40.o,tail18.data.o,ov_SC06_025_jr_8017A4AC.o,tail19.data.o,ov_SC06_025_jr_8017AE2C.o,ov_SC06_025_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_025_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_025.o,ov_SC06_025_jr_8012ACE0.o,tail2.data.o,ov_SC06_025_jr_80135888.o,tail3.data.o,ov_SC06_025_jr_80135A4C.o,tail4.data.o,ov_SC06_025_jr_80135D20.o,tail5.data.o,ov_SC06_025_jr_801380E0.o,ov_SC06_025_o0c.o,tail6.data.o,ov_SC06_025_jr_8013F350.o,tail7.data.o,ov_SC06_025_jr_8013FFD8.o,tail8.data.o,ov_SC06_025_jr_80140608.o,tail9.data.o,ov_SC06_025_jr_8015444C.o,ov_SC06_025_jr_80154C24.o,ov_SC06_025_jr_801588CC.o,tail10.data.o,ov_SC06_025_jr_80159C84.o,tail11.data.o,ov_SC06_025_jr_8015A3C8.o,tail12.data.o,ov_SC06_025_jr_8015AE2C.o,tail13.data.o,ov_SC06_025_jr_8015C32C.o,tail14.data.o,ov_SC06_025_jr_8016AB6C.o,tail15.data.o,ov_SC06_025_jr_80171B4C.o,ov_SC06_025_jr_801734BC.o,tail16.data.o,ov_SC06_025_jr_801789AC.o,ov_SC06_025_jr_80178D40.o,tail17.data.o,ov_SC06_025_jr_8017A4AC.o,tail18.data.o,ov_SC06_025_jr_8017AE2C.o,ov_SC06_025_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_025/ov_SC06_025.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_025/ov_SC06_025_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_025/ov_SC06_025_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_025/ov_SC06_025_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_025/ov_SC06_025_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_025/ov_SC06_025_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_025/ov_SC06_025_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_025/ov_SC06_025_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_025/ov_SC06_025_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4282,12 +4406,13 @@ ov_SC06_027_ELF := $(ov_SC06_027_OUT).elf ov_SC06_027_MAPFILE := $(ov_SC06_027_OUT).map ov_SC06_027_LD_SCRIPT := $(ov_SC06_027_OUT).ld ov_SC06_027_SPLAT_YAML := config/splat.ov_SC06_027.yaml -ov_SC06_027_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_027.o,ov_SC06_027_jr_8012ACE0.o,tail2.data.o,ov_SC06_027_jr_80135888.o,tail3.data.o,ov_SC06_027_jr_80135A4C.o,tail4.data.o,ov_SC06_027_jr_80135D20.o,tail5.data.o,ov_SC06_027_jr_801380E0.o,ov_SC06_027_o0c.o,tail6.data.o,ov_SC06_027_jr_8013F350.o,tail7.data.o,ov_SC06_027_jr_8013FFD8.o,tail8.data.o,ov_SC06_027_jr_80140608.o,tail9.data.o,ov_SC06_027_jr_8015444C.o,tail10.data.o,ov_SC06_027_jr_80154C24.o,ov_SC06_027_jr_801588CC.o,tail11.data.o,ov_SC06_027_jr_80159C84.o,tail12.data.o,ov_SC06_027_jr_8015A3C8.o,tail13.data.o,ov_SC06_027_jr_8015AE2C.o,tail14.data.o,ov_SC06_027_jr_8015C32C.o,tail15.data.o,ov_SC06_027_jr_8016AB6C.o,tail16.data.o,ov_SC06_027_jr_80171B4C.o,ov_SC06_027_jr_801734BC.o,tail17.data.o,ov_SC06_027_jr_801789AC.o,ov_SC06_027_jr_80178D40.o,tail18.data.o,ov_SC06_027_jr_8017A4AC.o,tail19.data.o,ov_SC06_027_jr_8017AE2C.o,ov_SC06_027_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_027_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_027.o,ov_SC06_027_jr_8012ACE0.o,tail2.data.o,ov_SC06_027_jr_80135888.o,tail3.data.o,ov_SC06_027_jr_80135A4C.o,tail4.data.o,ov_SC06_027_jr_80135D20.o,tail5.data.o,ov_SC06_027_jr_801380E0.o,ov_SC06_027_o0c.o,tail6.data.o,ov_SC06_027_jr_8013F350.o,tail7.data.o,ov_SC06_027_jr_8013FFD8.o,tail8.data.o,ov_SC06_027_jr_80140608.o,tail9.data.o,ov_SC06_027_jr_8015444C.o,ov_SC06_027_jr_80154C24.o,ov_SC06_027_jr_801588CC.o,tail10.data.o,ov_SC06_027_jr_80159C84.o,tail11.data.o,ov_SC06_027_jr_8015A3C8.o,tail12.data.o,ov_SC06_027_jr_8015AE2C.o,tail13.data.o,ov_SC06_027_jr_8015C32C.o,tail14.data.o,ov_SC06_027_jr_8016AB6C.o,tail15.data.o,ov_SC06_027_jr_80171B4C.o,ov_SC06_027_jr_801734BC.o,tail16.data.o,ov_SC06_027_jr_801789AC.o,ov_SC06_027_jr_80178D40.o,tail17.data.o,ov_SC06_027_jr_8017A4AC.o,tail18.data.o,ov_SC06_027_jr_8017AE2C.o,ov_SC06_027_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_027/ov_SC06_027.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_027/ov_SC06_027_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_027/ov_SC06_027_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_027/ov_SC06_027_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_027/ov_SC06_027_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_027/ov_SC06_027_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_027/ov_SC06_027_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_027/ov_SC06_027_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_027/ov_SC06_027_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4316,12 +4441,13 @@ ov_SC06_029_ELF := $(ov_SC06_029_OUT).elf ov_SC06_029_MAPFILE := $(ov_SC06_029_OUT).map ov_SC06_029_LD_SCRIPT := $(ov_SC06_029_OUT).ld ov_SC06_029_SPLAT_YAML := config/splat.ov_SC06_029.yaml -ov_SC06_029_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_029.o,ov_SC06_029_jr_8012ACE0.o,tail2.data.o,ov_SC06_029_jr_80135888.o,tail3.data.o,ov_SC06_029_jr_80135A4C.o,tail4.data.o,ov_SC06_029_jr_80135D20.o,tail5.data.o,ov_SC06_029_jr_801380E0.o,ov_SC06_029_o0c.o,tail6.data.o,ov_SC06_029_jr_8013F350.o,tail7.data.o,ov_SC06_029_jr_8013FFD8.o,tail8.data.o,ov_SC06_029_jr_80140608.o,tail9.data.o,ov_SC06_029_jr_8015444C.o,tail10.data.o,ov_SC06_029_jr_80154C24.o,ov_SC06_029_jr_801588CC.o,tail11.data.o,ov_SC06_029_jr_80159C84.o,tail12.data.o,ov_SC06_029_jr_8015A3C8.o,tail13.data.o,ov_SC06_029_jr_8015AE2C.o,tail14.data.o,ov_SC06_029_jr_8015C32C.o,tail15.data.o,ov_SC06_029_jr_8016AB6C.o,tail16.data.o,ov_SC06_029_jr_80171B4C.o,ov_SC06_029_jr_801734BC.o,tail17.data.o,ov_SC06_029_jr_801789AC.o,ov_SC06_029_jr_80178D40.o,tail18.data.o,ov_SC06_029_jr_8017A4AC.o,tail19.data.o,ov_SC06_029_jr_8017AE2C.o,tail20.data.o,ov_SC06_029_jr_8017C954.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_029_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_029.o,ov_SC06_029_jr_8012ACE0.o,tail2.data.o,ov_SC06_029_jr_80135888.o,tail3.data.o,ov_SC06_029_jr_80135A4C.o,tail4.data.o,ov_SC06_029_jr_80135D20.o,tail5.data.o,ov_SC06_029_jr_801380E0.o,ov_SC06_029_o0c.o,tail6.data.o,ov_SC06_029_jr_8013F350.o,tail7.data.o,ov_SC06_029_jr_8013FFD8.o,tail8.data.o,ov_SC06_029_jr_80140608.o,tail9.data.o,ov_SC06_029_jr_8015444C.o,ov_SC06_029_jr_80154C24.o,ov_SC06_029_jr_801588CC.o,tail10.data.o,ov_SC06_029_jr_80159C84.o,tail11.data.o,ov_SC06_029_jr_8015A3C8.o,tail12.data.o,ov_SC06_029_jr_8015AE2C.o,tail13.data.o,ov_SC06_029_jr_8015C32C.o,tail14.data.o,ov_SC06_029_jr_8016AB6C.o,tail15.data.o,ov_SC06_029_jr_80171B4C.o,ov_SC06_029_jr_801734BC.o,tail16.data.o,ov_SC06_029_jr_801789AC.o,ov_SC06_029_jr_80178D40.o,tail17.data.o,ov_SC06_029_jr_8017A4AC.o,tail18.data.o,ov_SC06_029_jr_8017AE2C.o,tail19.data.o,ov_SC06_029_jr_8017C954.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_029/ov_SC06_029.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_029/ov_SC06_029_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_029/ov_SC06_029_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_029/ov_SC06_029_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_029/ov_SC06_029_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_029/ov_SC06_029_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_029/ov_SC06_029_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_029/ov_SC06_029_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_029/ov_SC06_029_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4350,12 +4476,13 @@ ov_SC06_030_ELF := $(ov_SC06_030_OUT).elf ov_SC06_030_MAPFILE := $(ov_SC06_030_OUT).map ov_SC06_030_LD_SCRIPT := $(ov_SC06_030_OUT).ld ov_SC06_030_SPLAT_YAML := config/splat.ov_SC06_030.yaml -ov_SC06_030_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_030.o,ov_SC06_030_jr_8012ACE0.o,tail2.data.o,ov_SC06_030_jr_80135888.o,tail3.data.o,ov_SC06_030_jr_80135A4C.o,tail4.data.o,ov_SC06_030_jr_80135D20.o,tail5.data.o,ov_SC06_030_jr_801380E0.o,ov_SC06_030_o0c.o,tail6.data.o,ov_SC06_030_jr_8013F350.o,tail7.data.o,ov_SC06_030_jr_8013FFD8.o,tail8.data.o,ov_SC06_030_jr_80140608.o,tail9.data.o,ov_SC06_030_jr_8015444C.o,tail10.data.o,ov_SC06_030_jr_80154C24.o,ov_SC06_030_jr_801588CC.o,tail11.data.o,ov_SC06_030_jr_80159C84.o,tail12.data.o,ov_SC06_030_jr_8015A3C8.o,tail13.data.o,ov_SC06_030_jr_8015AE2C.o,tail14.data.o,ov_SC06_030_jr_8015C32C.o,tail15.data.o,ov_SC06_030_jr_8016AB6C.o,tail16.data.o,ov_SC06_030_jr_80171B4C.o,ov_SC06_030_jr_801734BC.o,tail17.data.o,ov_SC06_030_jr_801789AC.o,ov_SC06_030_jr_80178D40.o,tail18.data.o,ov_SC06_030_jr_8017A4AC.o,tail19.data.o,ov_SC06_030_jr_8017AE2C.o,tail20.data.o,ov_SC06_030_jr_8017C8D0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_030_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_030.o,ov_SC06_030_jr_8012ACE0.o,tail2.data.o,ov_SC06_030_jr_80135888.o,tail3.data.o,ov_SC06_030_jr_80135A4C.o,tail4.data.o,ov_SC06_030_jr_80135D20.o,tail5.data.o,ov_SC06_030_jr_801380E0.o,ov_SC06_030_o0c.o,tail6.data.o,ov_SC06_030_jr_8013F350.o,tail7.data.o,ov_SC06_030_jr_8013FFD8.o,tail8.data.o,ov_SC06_030_jr_80140608.o,tail9.data.o,ov_SC06_030_jr_8015444C.o,ov_SC06_030_jr_80154C24.o,ov_SC06_030_jr_801588CC.o,tail10.data.o,ov_SC06_030_jr_80159C84.o,tail11.data.o,ov_SC06_030_jr_8015A3C8.o,tail12.data.o,ov_SC06_030_jr_8015AE2C.o,tail13.data.o,ov_SC06_030_jr_8015C32C.o,tail14.data.o,ov_SC06_030_jr_8016AB6C.o,tail15.data.o,ov_SC06_030_jr_80171B4C.o,ov_SC06_030_jr_801734BC.o,tail16.data.o,ov_SC06_030_jr_801789AC.o,ov_SC06_030_jr_80178D40.o,tail17.data.o,ov_SC06_030_jr_8017A4AC.o,tail18.data.o,ov_SC06_030_jr_8017AE2C.o,tail19.data.o,ov_SC06_030_jr_8017C8D0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_030/ov_SC06_030.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_030/ov_SC06_030_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_030/ov_SC06_030_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_030/ov_SC06_030_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_030/ov_SC06_030_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_030/ov_SC06_030_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_030/ov_SC06_030_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_030/ov_SC06_030_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_030/ov_SC06_030_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4385,12 +4512,13 @@ ov_SC06_032_ELF := $(ov_SC06_032_OUT).elf ov_SC06_032_MAPFILE := $(ov_SC06_032_OUT).map ov_SC06_032_LD_SCRIPT := $(ov_SC06_032_OUT).ld ov_SC06_032_SPLAT_YAML := config/splat.ov_SC06_032.yaml -ov_SC06_032_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_032.o,ov_SC06_032_jr_8012ACE0.o,tail2.data.o,ov_SC06_032_jr_80135888.o,tail3.data.o,ov_SC06_032_jr_80135A4C.o,tail4.data.o,ov_SC06_032_jr_80135D20.o,tail5.data.o,ov_SC06_032_jr_801380E0.o,ov_SC06_032_o0c.o,tail6.data.o,ov_SC06_032_jr_8013F350.o,tail7.data.o,ov_SC06_032_jr_8013FFD8.o,tail8.data.o,ov_SC06_032_jr_80140608.o,tail9.data.o,ov_SC06_032_jr_8015444C.o,tail10.data.o,ov_SC06_032_jr_80154C24.o,ov_SC06_032_jr_801588CC.o,tail11.data.o,ov_SC06_032_jr_80159C84.o,tail12.data.o,ov_SC06_032_jr_8015A3C8.o,tail13.data.o,ov_SC06_032_jr_8015AE2C.o,tail14.data.o,ov_SC06_032_jr_8015C32C.o,tail15.data.o,ov_SC06_032_jr_8016AB6C.o,tail16.data.o,ov_SC06_032_jr_80171B4C.o,ov_SC06_032_jr_801734BC.o,tail17.data.o,ov_SC06_032_jr_801789AC.o,ov_SC06_032_jr_80178D40.o,tail18.data.o,ov_SC06_032_jr_8017A4AC.o,tail19.data.o,ov_SC06_032_jr_8017AE2C.o,ov_SC06_032_jr_8017C24C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_032_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_032.o,ov_SC06_032_jr_8012ACE0.o,tail2.data.o,ov_SC06_032_jr_80135888.o,tail3.data.o,ov_SC06_032_jr_80135A4C.o,tail4.data.o,ov_SC06_032_jr_80135D20.o,tail5.data.o,ov_SC06_032_jr_801380E0.o,ov_SC06_032_o0c.o,tail6.data.o,ov_SC06_032_jr_8013F350.o,tail7.data.o,ov_SC06_032_jr_8013FFD8.o,tail8.data.o,ov_SC06_032_jr_80140608.o,tail9.data.o,ov_SC06_032_jr_8015444C.o,ov_SC06_032_jr_80154C24.o,ov_SC06_032_jr_801588CC.o,tail10.data.o,ov_SC06_032_jr_80159C84.o,tail11.data.o,ov_SC06_032_jr_8015A3C8.o,tail12.data.o,ov_SC06_032_jr_8015AE2C.o,tail13.data.o,ov_SC06_032_jr_8015C32C.o,tail14.data.o,ov_SC06_032_jr_8016AB6C.o,tail15.data.o,ov_SC06_032_jr_80171B4C.o,ov_SC06_032_jr_801734BC.o,tail16.data.o,ov_SC06_032_jr_801789AC.o,ov_SC06_032_jr_80178D40.o,tail17.data.o,ov_SC06_032_jr_8017A4AC.o,tail18.data.o,ov_SC06_032_jr_8017AE2C.o,ov_SC06_032_jr_8017C24C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_032/ov_SC06_032.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_032/ov_SC06_032_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_032/ov_SC06_032_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_032/ov_SC06_032_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_032/ov_SC06_032_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_032/ov_SC06_032_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_032/ov_SC06_032_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_032/ov_SC06_032_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_032/ov_SC06_032_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4419,12 +4547,13 @@ ov_SC06_033_ELF := $(ov_SC06_033_OUT).elf ov_SC06_033_MAPFILE := $(ov_SC06_033_OUT).map ov_SC06_033_LD_SCRIPT := $(ov_SC06_033_OUT).ld ov_SC06_033_SPLAT_YAML := config/splat.ov_SC06_033.yaml -ov_SC06_033_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_033.o,ov_SC06_033_jr_8012ACE0.o,tail2.data.o,ov_SC06_033_jr_80135888.o,tail3.data.o,ov_SC06_033_jr_80135A4C.o,tail4.data.o,ov_SC06_033_jr_80135D20.o,tail5.data.o,ov_SC06_033_jr_801380E0.o,ov_SC06_033_o0c.o,tail6.data.o,ov_SC06_033_jr_8013F350.o,tail7.data.o,ov_SC06_033_jr_8013FFD8.o,tail8.data.o,ov_SC06_033_jr_80140608.o,tail9.data.o,ov_SC06_033_jr_8015444C.o,tail10.data.o,ov_SC06_033_jr_80154C24.o,ov_SC06_033_jr_801588CC.o,tail11.data.o,ov_SC06_033_jr_80159C84.o,tail12.data.o,ov_SC06_033_jr_8015A3C8.o,tail13.data.o,ov_SC06_033_jr_8015AE2C.o,tail14.data.o,ov_SC06_033_jr_8015C32C.o,tail15.data.o,ov_SC06_033_jr_8016AB6C.o,tail16.data.o,ov_SC06_033_jr_80171B4C.o,ov_SC06_033_jr_801734BC.o,tail17.data.o,ov_SC06_033_jr_801789AC.o,ov_SC06_033_jr_80178D40.o,tail18.data.o,ov_SC06_033_jr_8017A4AC.o,tail19.data.o,ov_SC06_033_jr_8017AE2C.o,ov_SC06_033_jr_8017C24C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_033_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_033.o,ov_SC06_033_jr_8012ACE0.o,tail2.data.o,ov_SC06_033_jr_80135888.o,tail3.data.o,ov_SC06_033_jr_80135A4C.o,tail4.data.o,ov_SC06_033_jr_80135D20.o,tail5.data.o,ov_SC06_033_jr_801380E0.o,ov_SC06_033_o0c.o,tail6.data.o,ov_SC06_033_jr_8013F350.o,tail7.data.o,ov_SC06_033_jr_8013FFD8.o,tail8.data.o,ov_SC06_033_jr_80140608.o,tail9.data.o,ov_SC06_033_jr_8015444C.o,ov_SC06_033_jr_80154C24.o,ov_SC06_033_jr_801588CC.o,tail10.data.o,ov_SC06_033_jr_80159C84.o,tail11.data.o,ov_SC06_033_jr_8015A3C8.o,tail12.data.o,ov_SC06_033_jr_8015AE2C.o,tail13.data.o,ov_SC06_033_jr_8015C32C.o,tail14.data.o,ov_SC06_033_jr_8016AB6C.o,tail15.data.o,ov_SC06_033_jr_80171B4C.o,ov_SC06_033_jr_801734BC.o,tail16.data.o,ov_SC06_033_jr_801789AC.o,ov_SC06_033_jr_80178D40.o,tail17.data.o,ov_SC06_033_jr_8017A4AC.o,tail18.data.o,ov_SC06_033_jr_8017AE2C.o,ov_SC06_033_jr_8017C24C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_033/ov_SC06_033.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_033/ov_SC06_033_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_033/ov_SC06_033_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_033/ov_SC06_033_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_033/ov_SC06_033_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC06_033/ov_SC06_033_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC06_033/ov_SC06_033_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC06_033/ov_SC06_033_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC06_033/ov_SC06_033_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4453,12 +4582,13 @@ ov_SC07_001_ELF := $(ov_SC07_001_OUT).elf ov_SC07_001_MAPFILE := $(ov_SC07_001_OUT).map ov_SC07_001_LD_SCRIPT := $(ov_SC07_001_OUT).ld ov_SC07_001_SPLAT_YAML := config/splat.ov_SC07_001.yaml -ov_SC07_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_001.o,ov_SC07_001_jr_8012ACE0.o,tail2.data.o,ov_SC07_001_jr_80135888.o,tail3.data.o,ov_SC07_001_jr_80135A4C.o,tail4.data.o,ov_SC07_001_jr_80135D20.o,tail5.data.o,ov_SC07_001_jr_801380E0.o,ov_SC07_001_o0c.o,tail6.data.o,ov_SC07_001_jr_8013F350.o,tail7.data.o,ov_SC07_001_jr_8013FFD8.o,tail8.data.o,ov_SC07_001_jr_80140608.o,tail9.data.o,ov_SC07_001_jr_8015444C.o,tail10.data.o,ov_SC07_001_jr_80154C24.o,ov_SC07_001_jr_801588CC.o,tail11.data.o,ov_SC07_001_jr_80159C84.o,tail12.data.o,ov_SC07_001_jr_8015A3C8.o,tail13.data.o,ov_SC07_001_jr_8015AE2C.o,tail14.data.o,ov_SC07_001_jr_8015C32C.o,tail15.data.o,ov_SC07_001_jr_8016AB6C.o,tail16.data.o,ov_SC07_001_jr_80171B4C.o,ov_SC07_001_jr_801734BC.o,tail17.data.o,ov_SC07_001_jr_801789AC.o,ov_SC07_001_jr_80178D40.o,tail18.data.o,ov_SC07_001_jr_8017A4AC.o,tail19.data.o,ov_SC07_001_jr_8017AE2C.o,ov_SC07_001_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC07_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_001.o,ov_SC07_001_jr_8012ACE0.o,tail2.data.o,ov_SC07_001_jr_80135888.o,tail3.data.o,ov_SC07_001_jr_80135A4C.o,tail4.data.o,ov_SC07_001_jr_80135D20.o,tail5.data.o,ov_SC07_001_jr_801380E0.o,ov_SC07_001_o0c.o,tail6.data.o,ov_SC07_001_jr_8013F350.o,tail7.data.o,ov_SC07_001_jr_8013FFD8.o,tail8.data.o,ov_SC07_001_jr_80140608.o,tail9.data.o,ov_SC07_001_jr_8015444C.o,ov_SC07_001_jr_80154C24.o,ov_SC07_001_jr_801588CC.o,tail10.data.o,ov_SC07_001_jr_80159C84.o,tail11.data.o,ov_SC07_001_jr_8015A3C8.o,tail12.data.o,ov_SC07_001_jr_8015AE2C.o,tail13.data.o,ov_SC07_001_jr_8015C32C.o,tail14.data.o,ov_SC07_001_jr_8016AB6C.o,tail15.data.o,ov_SC07_001_jr_80171B4C.o,ov_SC07_001_jr_801734BC.o,tail16.data.o,ov_SC07_001_jr_801789AC.o,ov_SC07_001_jr_80178D40.o,tail17.data.o,ov_SC07_001_jr_8017A4AC.o,tail18.data.o,ov_SC07_001_jr_8017AE2C.o,ov_SC07_001_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC07_001/ov_SC07_001.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_001/ov_SC07_001_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC07_001/ov_SC07_001_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC07_001/ov_SC07_001_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_001/ov_SC07_001_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC07_001/ov_SC07_001_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC07_001/ov_SC07_001_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_001/ov_SC07_001_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC07_001/ov_SC07_001_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4487,12 +4617,13 @@ ov_SC07_002_ELF := $(ov_SC07_002_OUT).elf ov_SC07_002_MAPFILE := $(ov_SC07_002_OUT).map ov_SC07_002_LD_SCRIPT := $(ov_SC07_002_OUT).ld ov_SC07_002_SPLAT_YAML := config/splat.ov_SC07_002.yaml -ov_SC07_002_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_002.o,ov_SC07_002_jr_8012ACE0.o,tail2.data.o,ov_SC07_002_jr_80135888.o,tail3.data.o,ov_SC07_002_jr_80135A4C.o,tail4.data.o,ov_SC07_002_jr_80135D20.o,tail5.data.o,ov_SC07_002_jr_801380E0.o,ov_SC07_002_o0c.o,tail6.data.o,ov_SC07_002_jr_8013F350.o,tail7.data.o,ov_SC07_002_jr_8013FFD8.o,tail8.data.o,ov_SC07_002_jr_80140608.o,tail9.data.o,ov_SC07_002_jr_8015444C.o,tail10.data.o,ov_SC07_002_jr_80154C24.o,ov_SC07_002_jr_801588CC.o,tail11.data.o,ov_SC07_002_jr_80159C84.o,tail12.data.o,ov_SC07_002_jr_8015A3C8.o,tail13.data.o,ov_SC07_002_jr_8015AE2C.o,tail14.data.o,ov_SC07_002_jr_8015C32C.o,tail15.data.o,ov_SC07_002_jr_8016AB6C.o,tail16.data.o,ov_SC07_002_jr_80171B4C.o,ov_SC07_002_jr_801734BC.o,tail17.data.o,ov_SC07_002_jr_801789AC.o,ov_SC07_002_jr_80178D40.o,tail18.data.o,ov_SC07_002_jr_8017A4AC.o,tail19.data.o,ov_SC07_002_jr_8017AE2C.o,tail20.data.o,ov_SC07_002_jr_8017C8D0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC07_002_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_002.o,ov_SC07_002_jr_8012ACE0.o,tail2.data.o,ov_SC07_002_jr_80135888.o,tail3.data.o,ov_SC07_002_jr_80135A4C.o,tail4.data.o,ov_SC07_002_jr_80135D20.o,tail5.data.o,ov_SC07_002_jr_801380E0.o,ov_SC07_002_o0c.o,tail6.data.o,ov_SC07_002_jr_8013F350.o,tail7.data.o,ov_SC07_002_jr_8013FFD8.o,tail8.data.o,ov_SC07_002_jr_80140608.o,tail9.data.o,ov_SC07_002_jr_8015444C.o,ov_SC07_002_jr_80154C24.o,ov_SC07_002_jr_801588CC.o,tail10.data.o,ov_SC07_002_jr_80159C84.o,tail11.data.o,ov_SC07_002_jr_8015A3C8.o,tail12.data.o,ov_SC07_002_jr_8015AE2C.o,tail13.data.o,ov_SC07_002_jr_8015C32C.o,tail14.data.o,ov_SC07_002_jr_8016AB6C.o,tail15.data.o,ov_SC07_002_jr_80171B4C.o,ov_SC07_002_jr_801734BC.o,tail16.data.o,ov_SC07_002_jr_801789AC.o,ov_SC07_002_jr_80178D40.o,tail17.data.o,ov_SC07_002_jr_8017A4AC.o,tail18.data.o,ov_SC07_002_jr_8017AE2C.o,tail19.data.o,ov_SC07_002_jr_8017C8D0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC07_002/ov_SC07_002.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_002/ov_SC07_002_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC07_002/ov_SC07_002_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC07_002/ov_SC07_002_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_002/ov_SC07_002_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC07_002/ov_SC07_002_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC07_002/ov_SC07_002_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_002/ov_SC07_002_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC07_002/ov_SC07_002_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4521,12 +4652,13 @@ ov_SC07_008_ELF := $(ov_SC07_008_OUT).elf ov_SC07_008_MAPFILE := $(ov_SC07_008_OUT).map ov_SC07_008_LD_SCRIPT := $(ov_SC07_008_OUT).ld ov_SC07_008_SPLAT_YAML := config/splat.ov_SC07_008.yaml -ov_SC07_008_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_008.o,ov_SC07_008_jr_8012ACE0.o,tail2.data.o,ov_SC07_008_jr_80135888.o,tail3.data.o,ov_SC07_008_jr_80135A4C.o,tail4.data.o,ov_SC07_008_jr_80135D20.o,tail5.data.o,ov_SC07_008_jr_801380E0.o,ov_SC07_008_o0c.o,tail6.data.o,ov_SC07_008_jr_8013F350.o,tail7.data.o,ov_SC07_008_jr_8013FFD8.o,tail8.data.o,ov_SC07_008_jr_80140608.o,tail9.data.o,ov_SC07_008_jr_8015444C.o,tail10.data.o,ov_SC07_008_jr_80154C24.o,ov_SC07_008_jr_801588CC.o,tail11.data.o,ov_SC07_008_jr_80159C84.o,tail12.data.o,ov_SC07_008_jr_8015A3C8.o,tail13.data.o,ov_SC07_008_jr_8015AE2C.o,tail14.data.o,ov_SC07_008_jr_8015C32C.o,tail15.data.o,ov_SC07_008_jr_8016AB6C.o,tail16.data.o,ov_SC07_008_jr_80171B4C.o,ov_SC07_008_jr_801734BC.o,tail17.data.o,ov_SC07_008_jr_801789AC.o,ov_SC07_008_jr_80178D40.o,tail18.data.o,ov_SC07_008_jr_8017A4AC.o,tail19.data.o,ov_SC07_008_jr_8017AE2C.o,ov_SC07_008_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC07_008_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_008.o,ov_SC07_008_jr_8012ACE0.o,tail2.data.o,ov_SC07_008_jr_80135888.o,tail3.data.o,ov_SC07_008_jr_80135A4C.o,tail4.data.o,ov_SC07_008_jr_80135D20.o,tail5.data.o,ov_SC07_008_jr_801380E0.o,ov_SC07_008_o0c.o,tail6.data.o,ov_SC07_008_jr_8013F350.o,tail7.data.o,ov_SC07_008_jr_8013FFD8.o,tail8.data.o,ov_SC07_008_jr_80140608.o,tail9.data.o,ov_SC07_008_jr_8015444C.o,ov_SC07_008_jr_80154C24.o,ov_SC07_008_jr_801588CC.o,tail10.data.o,ov_SC07_008_jr_80159C84.o,tail11.data.o,ov_SC07_008_jr_8015A3C8.o,tail12.data.o,ov_SC07_008_jr_8015AE2C.o,tail13.data.o,ov_SC07_008_jr_8015C32C.o,tail14.data.o,ov_SC07_008_jr_8016AB6C.o,tail15.data.o,ov_SC07_008_jr_80171B4C.o,ov_SC07_008_jr_801734BC.o,tail16.data.o,ov_SC07_008_jr_801789AC.o,ov_SC07_008_jr_80178D40.o,tail17.data.o,ov_SC07_008_jr_8017A4AC.o,tail18.data.o,ov_SC07_008_jr_8017AE2C.o,ov_SC07_008_jr_8017BEBC.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC07_008/ov_SC07_008.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_008/ov_SC07_008_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC07_008/ov_SC07_008_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC07_008/ov_SC07_008_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_008/ov_SC07_008_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC07_008/ov_SC07_008_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC07_008/ov_SC07_008_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_008/ov_SC07_008_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC07_008/ov_SC07_008_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4555,12 +4687,13 @@ ov_SC07_009_ELF := $(ov_SC07_009_OUT).elf ov_SC07_009_MAPFILE := $(ov_SC07_009_OUT).map ov_SC07_009_LD_SCRIPT := $(ov_SC07_009_OUT).ld ov_SC07_009_SPLAT_YAML := config/splat.ov_SC07_009.yaml -ov_SC07_009_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_009.o,ov_SC07_009_jr_8012ACE0.o,tail2.data.o,ov_SC07_009_jr_80135888.o,tail3.data.o,ov_SC07_009_jr_80135A4C.o,tail4.data.o,ov_SC07_009_jr_80135D20.o,tail5.data.o,ov_SC07_009_jr_801380E0.o,ov_SC07_009_o0c.o,tail6.data.o,ov_SC07_009_jr_8013F350.o,tail7.data.o,ov_SC07_009_jr_8013FFD8.o,tail8.data.o,ov_SC07_009_jr_80140608.o,tail9.data.o,ov_SC07_009_jr_8015444C.o,tail10.data.o,ov_SC07_009_jr_80154C24.o,ov_SC07_009_jr_801588CC.o,tail11.data.o,ov_SC07_009_jr_80159C84.o,tail12.data.o,ov_SC07_009_jr_8015A3C8.o,tail13.data.o,ov_SC07_009_jr_8015AE2C.o,tail14.data.o,ov_SC07_009_jr_8015C32C.o,tail15.data.o,ov_SC07_009_jr_8016AB6C.o,tail16.data.o,ov_SC07_009_jr_80171B4C.o,ov_SC07_009_jr_801734BC.o,tail17.data.o,ov_SC07_009_jr_801789AC.o,ov_SC07_009_jr_80178D40.o,tail18.data.o,ov_SC07_009_jr_8017A4AC.o,tail19.data.o,ov_SC07_009_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC07_009_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_009.o,ov_SC07_009_jr_8012ACE0.o,tail2.data.o,ov_SC07_009_jr_80135888.o,tail3.data.o,ov_SC07_009_jr_80135A4C.o,tail4.data.o,ov_SC07_009_jr_80135D20.o,tail5.data.o,ov_SC07_009_jr_801380E0.o,ov_SC07_009_o0c.o,tail6.data.o,ov_SC07_009_jr_8013F350.o,tail7.data.o,ov_SC07_009_jr_8013FFD8.o,tail8.data.o,ov_SC07_009_jr_80140608.o,tail9.data.o,ov_SC07_009_jr_8015444C.o,ov_SC07_009_jr_80154C24.o,ov_SC07_009_jr_801588CC.o,tail10.data.o,ov_SC07_009_jr_80159C84.o,tail11.data.o,ov_SC07_009_jr_8015A3C8.o,tail12.data.o,ov_SC07_009_jr_8015AE2C.o,tail13.data.o,ov_SC07_009_jr_8015C32C.o,tail14.data.o,ov_SC07_009_jr_8016AB6C.o,tail15.data.o,ov_SC07_009_jr_80171B4C.o,ov_SC07_009_jr_801734BC.o,tail16.data.o,ov_SC07_009_jr_801789AC.o,ov_SC07_009_jr_80178D40.o,tail17.data.o,ov_SC07_009_jr_8017A4AC.o,tail18.data.o,ov_SC07_009_jr_8017AE2C.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC07_009/ov_SC07_009.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_009/ov_SC07_009_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC07_009/ov_SC07_009_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC07_009/ov_SC07_009_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_009/ov_SC07_009_jr_8013FFD8.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 +build/src/ov_SC07_009/ov_SC07_009_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC07_009/ov_SC07_009_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_009/ov_SC07_009_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC07_009/ov_SC07_009_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4590,12 +4723,13 @@ ov_SC07_006_ELF := $(ov_SC07_006_OUT).elf ov_SC07_006_MAPFILE := $(ov_SC07_006_OUT).map ov_SC07_006_LD_SCRIPT := $(ov_SC07_006_OUT).ld ov_SC07_006_SPLAT_YAML := config/splat.ov_SC07_006.yaml -ov_SC07_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_006.o,tail2.data.o,ov_SC07_006_jr_80131340.o,tail3.data.o,ov_SC07_006_jr_80135888.o,tail4.data.o,ov_SC07_006_jr_80135A4C.o,tail5.data.o,ov_SC07_006_jr_80135D20.o,tail6.data.o,ov_SC07_006_o0c.o,tail7.data.o,ov_SC07_006_jr_8013F350.o,tail8.data.o,ov_SC07_006_jr_8014032C.o,tail9.data.o,ov_SC07_006_jr_80140608.o,tail10.data.o,ov_SC07_006_jr_8015444C.o,tail11.data.o,ov_SC07_006_jr_80154C24.o,ov_SC07_006_jr_801588CC.o,tail12.data.o,ov_SC07_006_jr_80159C84.o,tail13.data.o,ov_SC07_006_jr_8015A3C8.o,tail14.data.o,ov_SC07_006_jr_8015B950.o,tail15.data.o,ov_SC07_006_jr_8015C32C.o,tail16.data.o,ov_SC07_006_jr_8016AE5C.o,tail17.data.o,ov_SC07_006_jr_80171B4C.o,tail18.data.o,ov_SC07_006_jr_801789AC.o,tail19.data.o,ov_SC07_006_jr_80179B74.o,tail20.data.o,ov_SC07_006_jr_8017AE2C.o,ov_SC07_006_jr_8017BEBC.o,tail21.data.o,ov_SC07_006_jr_80183814.o,tail22.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC07_006_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_006.o,tail2.data.o,ov_SC07_006_jr_80131340.o,tail3.data.o,ov_SC07_006_jr_80135888.o,tail4.data.o,ov_SC07_006_jr_80135A4C.o,tail5.data.o,ov_SC07_006_jr_80135D20.o,tail6.data.o,ov_SC07_006_o0c.o,tail7.data.o,ov_SC07_006_jr_8013F350.o,tail8.data.o,ov_SC07_006_jr_8014032C.o,tail9.data.o,ov_SC07_006_jr_80140608.o,tail10.data.o,ov_SC07_006_jr_8015444C.o,ov_SC07_006_jr_80154C24.o,ov_SC07_006_jr_801588CC.o,tail11.data.o,ov_SC07_006_jr_80159C84.o,tail12.data.o,ov_SC07_006_jr_8015A3C8.o,tail13.data.o,ov_SC07_006_jr_8015B950.o,tail14.data.o,ov_SC07_006_jr_8015C32C.o,tail15.data.o,ov_SC07_006_jr_8016AE5C.o,tail16.data.o,ov_SC07_006_jr_80171B4C.o,tail17.data.o,ov_SC07_006_jr_801789AC.o,tail18.data.o,ov_SC07_006_jr_80179B74.o,tail19.data.o,ov_SC07_006_jr_8017AE2C.o,ov_SC07_006_jr_8017BEBC.o,tail20.data.o,ov_SC07_006_jr_80183814.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC07_006/ov_SC07_006.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_006/ov_SC07_006_jr_80131340.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_006/ov_SC07_006_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC07_006/ov_SC07_006_jr_8013F350.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 build/src/ov_SC07_006/ov_SC07_006_jr_8014032C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC07_006/ov_SC07_006_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC07_006/ov_SC07_006_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_006/ov_SC07_006_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC07_006/ov_SC07_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4623,12 +4757,13 @@ ov_SC07_007_ELF := $(ov_SC07_007_OUT).elf ov_SC07_007_MAPFILE := $(ov_SC07_007_OUT).map ov_SC07_007_LD_SCRIPT := $(ov_SC07_007_OUT).ld ov_SC07_007_SPLAT_YAML := config/splat.ov_SC07_007.yaml -ov_SC07_007_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_007.o,tail2.data.o,ov_SC07_007_jr_80131340.o,tail3.data.o,ov_SC07_007_jr_80135888.o,tail4.data.o,ov_SC07_007_jr_80135A4C.o,tail5.data.o,ov_SC07_007_jr_80135D20.o,tail6.data.o,ov_SC07_007_o0c.o,tail7.data.o,ov_SC07_007_jr_8013F350.o,tail8.data.o,ov_SC07_007_jr_8014032C.o,tail9.data.o,ov_SC07_007_jr_80140608.o,tail10.data.o,ov_SC07_007_jr_8015444C.o,tail11.data.o,ov_SC07_007_jr_80154C24.o,ov_SC07_007_jr_801588CC.o,tail12.data.o,ov_SC07_007_jr_80159C84.o,tail13.data.o,ov_SC07_007_jr_8015A3C8.o,tail14.data.o,ov_SC07_007_jr_8015B950.o,tail15.data.o,ov_SC07_007_jr_8015C32C.o,tail16.data.o,ov_SC07_007_jr_8016AE5C.o,tail17.data.o,ov_SC07_007_jr_80171B4C.o,tail18.data.o,ov_SC07_007_jr_801789AC.o,tail19.data.o,ov_SC07_007_jr_80179B74.o,tail20.data.o,ov_SC07_007_jr_8017AE2C.o,ov_SC07_007_jr_8017BEBC.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC07_007_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_007.o,tail2.data.o,ov_SC07_007_jr_80131340.o,tail3.data.o,ov_SC07_007_jr_80135888.o,tail4.data.o,ov_SC07_007_jr_80135A4C.o,tail5.data.o,ov_SC07_007_jr_80135D20.o,tail6.data.o,ov_SC07_007_o0c.o,tail7.data.o,ov_SC07_007_jr_8013F350.o,tail8.data.o,ov_SC07_007_jr_8014032C.o,tail9.data.o,ov_SC07_007_jr_80140608.o,tail10.data.o,ov_SC07_007_jr_8015444C.o,ov_SC07_007_jr_80154C24.o,ov_SC07_007_jr_801588CC.o,tail11.data.o,ov_SC07_007_jr_80159C84.o,tail12.data.o,ov_SC07_007_jr_8015A3C8.o,tail13.data.o,ov_SC07_007_jr_8015B950.o,tail14.data.o,ov_SC07_007_jr_8015C32C.o,tail15.data.o,ov_SC07_007_jr_8016AE5C.o,tail16.data.o,ov_SC07_007_jr_80171B4C.o,tail17.data.o,ov_SC07_007_jr_801789AC.o,tail18.data.o,ov_SC07_007_jr_80179B74.o,tail19.data.o,ov_SC07_007_jr_8017AE2C.o,ov_SC07_007_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC07_007/ov_SC07_007.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_007/ov_SC07_007_jr_80131340.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_007/ov_SC07_007_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC07_007/ov_SC07_007_jr_8013F350.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 build/src/ov_SC07_007/ov_SC07_007_jr_8014032C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC07_007/ov_SC07_007_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC07_007/ov_SC07_007_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_007/ov_SC07_007_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC07_007/ov_SC07_007_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4656,11 +4791,12 @@ ov_SC07_010_ELF := $(ov_SC07_010_OUT).elf ov_SC07_010_MAPFILE := $(ov_SC07_010_OUT).map ov_SC07_010_LD_SCRIPT := $(ov_SC07_010_OUT).ld ov_SC07_010_SPLAT_YAML := config/splat.ov_SC07_010.yaml -ov_SC07_010_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_010.o,tail2.data.o,ov_SC07_010_jr_80131340.o,tail3.data.o,ov_SC07_010_jr_80135888.o,tail4.data.o,ov_SC07_010_jr_80135A4C.o,tail5.data.o,ov_SC07_010_jr_80135D20.o,tail6.data.o,ov_SC07_010_o0.o,tail7.data.o,ov_SC07_010_jr_8013F350.o,tail8.data.o,ov_SC07_010_jr_8014032C.o,tail9.data.o,ov_SC07_010_jr_80140608.o,tail10.data.o,ov_SC07_010_jr_8015444C.o,tail11.data.o,ov_SC07_010_jr_80154C24.o,ov_SC07_010_jr_801588CC.o,tail12.data.o,ov_SC07_010_jr_80159C84.o,tail13.data.o,ov_SC07_010_jr_8015A3C8.o,tail14.data.o,ov_SC07_010_jr_8015B950.o,tail15.data.o,ov_SC07_010_jr_8015C32C.o,tail16.data.o,ov_SC07_010_jr_8016AE5C.o,tail17.data.o,ov_SC07_010_jr_80171B4C.o,tail18.data.o,ov_SC07_010_jr_801789AC.o,tail19.data.o,ov_SC07_010_jr_80179B74.o,tail20.data.o,ov_SC07_010_jr_8017AE2C.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC07_010_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_010.o,tail2.data.o,ov_SC07_010_jr_80131340.o,tail3.data.o,ov_SC07_010_jr_80135888.o,tail4.data.o,ov_SC07_010_jr_80135A4C.o,tail5.data.o,ov_SC07_010_jr_80135D20.o,tail6.data.o,ov_SC07_010_o0.o,tail7.data.o,ov_SC07_010_jr_8013F350.o,tail8.data.o,ov_SC07_010_jr_8014032C.o,tail9.data.o,ov_SC07_010_jr_80140608.o,tail10.data.o,ov_SC07_010_jr_8015444C.o,ov_SC07_010_jr_80154C24.o,ov_SC07_010_jr_801588CC.o,tail11.data.o,ov_SC07_010_jr_80159C84.o,tail12.data.o,ov_SC07_010_jr_8015A3C8.o,tail13.data.o,ov_SC07_010_jr_8015B950.o,tail14.data.o,ov_SC07_010_jr_8015C32C.o,tail15.data.o,ov_SC07_010_jr_8016AE5C.o,tail16.data.o,ov_SC07_010_jr_80171B4C.o,tail17.data.o,ov_SC07_010_jr_801789AC.o,tail18.data.o,ov_SC07_010_jr_80179B74.o,tail19.data.o,ov_SC07_010_jr_8017AE2C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC07_010/ov_SC07_010.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_010/ov_SC07_010_jr_80131340.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_010/ov_SC07_010_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC07_010/ov_SC07_010_jr_8014032C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC07_010/ov_SC07_010_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC07_010/ov_SC07_010_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_010/ov_SC07_010_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC07_010/ov_SC07_010_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 @@ -4688,12 +4824,13 @@ ov_SC07_011_ELF := $(ov_SC07_011_OUT).elf ov_SC07_011_MAPFILE := $(ov_SC07_011_OUT).map ov_SC07_011_LD_SCRIPT := $(ov_SC07_011_OUT).ld ov_SC07_011_SPLAT_YAML := config/splat.ov_SC07_011.yaml -ov_SC07_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_011.o,tail2.data.o,ov_SC07_011_jr_80131340.o,tail3.data.o,ov_SC07_011_jr_80135888.o,tail4.data.o,ov_SC07_011_jr_80135A4C.o,tail5.data.o,ov_SC07_011_jr_80135D20.o,tail6.data.o,ov_SC07_011_o0c.o,tail7.data.o,ov_SC07_011_jr_8013F350.o,tail8.data.o,ov_SC07_011_jr_8014032C.o,tail9.data.o,ov_SC07_011_jr_80140608.o,tail10.data.o,ov_SC07_011_jr_8015444C.o,tail11.data.o,ov_SC07_011_jr_80154C24.o,ov_SC07_011_jr_801588CC.o,tail12.data.o,ov_SC07_011_jr_80159C84.o,tail13.data.o,ov_SC07_011_jr_8015A3C8.o,tail14.data.o,ov_SC07_011_jr_8015B950.o,tail15.data.o,ov_SC07_011_jr_8015C32C.o,tail16.data.o,ov_SC07_011_jr_8016AE5C.o,tail17.data.o,ov_SC07_011_jr_80171B4C.o,tail18.data.o,ov_SC07_011_jr_801789AC.o,tail19.data.o,ov_SC07_011_jr_80179B74.o,tail20.data.o,ov_SC07_011_jr_8017AE2C.o,ov_SC07_011_jr_8017BEBC.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC07_011_JTBL_INTERLEAVE := --order tail.data.o,ov_SC07_011.o,tail2.data.o,ov_SC07_011_jr_80131340.o,tail3.data.o,ov_SC07_011_jr_80135888.o,tail4.data.o,ov_SC07_011_jr_80135A4C.o,tail5.data.o,ov_SC07_011_jr_80135D20.o,tail6.data.o,ov_SC07_011_o0c.o,tail7.data.o,ov_SC07_011_jr_8013F350.o,tail8.data.o,ov_SC07_011_jr_8014032C.o,tail9.data.o,ov_SC07_011_jr_80140608.o,tail10.data.o,ov_SC07_011_jr_8015444C.o,ov_SC07_011_jr_80154C24.o,ov_SC07_011_jr_801588CC.o,tail11.data.o,ov_SC07_011_jr_80159C84.o,tail12.data.o,ov_SC07_011_jr_8015A3C8.o,tail13.data.o,ov_SC07_011_jr_8015B950.o,tail14.data.o,ov_SC07_011_jr_8015C32C.o,tail15.data.o,ov_SC07_011_jr_8016AE5C.o,tail16.data.o,ov_SC07_011_jr_80171B4C.o,tail17.data.o,ov_SC07_011_jr_801789AC.o,tail18.data.o,ov_SC07_011_jr_80179B74.o,tail19.data.o,ov_SC07_011_jr_8017AE2C.o,ov_SC07_011_jr_8017BEBC.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC07_011/ov_SC07_011.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_011/ov_SC07_011_jr_80131340.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC07_011/ov_SC07_011_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC07_011/ov_SC07_011_jr_8013F350.o: JTBL_PADS := 0,0,4,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38,+0x58 build/src/ov_SC07_011/ov_SC07_011_jr_8014032C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC07_011/ov_SC07_011_jr_8015444C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 build/src/ov_SC07_011/ov_SC07_011_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_011/ov_SC07_011_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 build/src/ov_SC07_011/ov_SC07_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 diff --git a/config/splat.ov_SC01_000.yaml b/config/splat.ov_SC01_000.yaml index b01191caf5..e07e778703 100644 --- a/config/splat.ov_SC01_000.yaml +++ b/config/splat.ov_SC01_000.yaml @@ -141,31 +141,30 @@ segments: - [0x7ba54, .rodata, ov_SC01_000_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7ba68, data, tail9] - [0x7ba80, .rodata, ov_SC01_000_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7baec, data, tail10] - [0x7bb5c, .rodata, ov_SC01_000_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7bba0, .rodata, ov_SC01_000_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bbe8, data, tail11] + - [0x7bbe8, data, tail10] - [0x7bc48, .rodata, ov_SC01_000_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bc7c, data, tail12] + - [0x7bc7c, data, tail11] - [0x7bc80, .rodata, ov_SC01_000_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bc9c, data, tail13] + - [0x7bc9c, data, tail12] - [0x7bca0, .rodata, ov_SC01_000_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bcdc, data, tail14] + - [0x7bcdc, data, tail13] - [0x7bce0, .rodata, ov_SC01_000_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bcfc, data, tail15] + - [0x7bcfc, data, tail14] - [0x7bd14, .rodata, ov_SC01_000_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bd54, data, tail16] + - [0x7bd54, data, tail15] - [0x7bd94, .rodata, ov_SC01_000_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7bdb4, .rodata, ov_SC01_000_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bdc8, data, tail17] + - [0x7bdc8, data, tail16] - [0x7bf58, .rodata, ov_SC01_000_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7bf70, .rodata, ov_SC01_000_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7c174, data, tail18] + - [0x7c174, data, tail17] - [0x7c178, .rodata, ov_SC01_000_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7c204, data, tail19] + - [0x7c204, data, tail18] - [0x7c208, .rodata, ov_SC01_000_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7c21c, .rodata, ov_SC01_000_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7c23c, data, tail20] + - [0x7c23c, data, tail19] - [0x7D78C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x7D78F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC01_001.yaml b/config/splat.ov_SC01_001.yaml index 6d925b59ae..7cc7ac3ace 100644 --- a/config/splat.ov_SC01_001.yaml +++ b/config/splat.ov_SC01_001.yaml @@ -142,32 +142,31 @@ segments: - [0xc3b2c, .rodata, ov_SC01_001_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc3b40, data, tail9] - [0xc3b58, .rodata, ov_SC01_001_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3bc4, data, tail10] - [0xc3c34, .rodata, ov_SC01_001_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc3c78, .rodata, ov_SC01_001_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3cc0, data, tail11] + - [0xc3cc0, data, tail10] - [0xc3d20, .rodata, ov_SC01_001_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3d54, data, tail12] + - [0xc3d54, data, tail11] - [0xc3d58, .rodata, ov_SC01_001_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3d74, data, tail13] + - [0xc3d74, data, tail12] - [0xc3d78, .rodata, ov_SC01_001_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3db4, data, tail14] + - [0xc3db4, data, tail13] - [0xc3db8, .rodata, ov_SC01_001_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3dd4, data, tail15] + - [0xc3dd4, data, tail14] - [0xc3dec, .rodata, ov_SC01_001_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3e2c, data, tail16] + - [0xc3e2c, data, tail15] - [0xc3e6c, .rodata, ov_SC01_001_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc3e8c, .rodata, ov_SC01_001_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3ea0, data, tail17] + - [0xc3ea0, data, tail16] - [0xc4030, .rodata, ov_SC01_001_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc4048, .rodata, ov_SC01_001_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc424c, data, tail18] + - [0xc424c, data, tail17] - [0xc4250, .rodata, ov_SC01_001_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc42dc, data, tail19] + - [0xc42dc, data, tail18] - [0xc42e0, .rodata, ov_SC01_001_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc42f4, .rodata, ov_SC01_001_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc4314, .rodata, ov_SC01_001_jr_8017D2DC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc4508, data, tail20] + - [0xc4508, data, tail19] - [0xCB06C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xCB06F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC01_004.yaml b/config/splat.ov_SC01_004.yaml index 6d7290fa18..e7a505675a 100644 --- a/config/splat.ov_SC01_004.yaml +++ b/config/splat.ov_SC01_004.yaml @@ -141,31 +141,30 @@ segments: - [0x65f0c, .rodata, ov_SC01_004_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65f20, data, tail9] - [0x65f38, .rodata, ov_SC01_004_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65fa4, data, tail10] - [0x66014, .rodata, ov_SC01_004_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66058, .rodata, ov_SC01_004_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x660a0, data, tail11] + - [0x660a0, data, tail10] - [0x66100, .rodata, ov_SC01_004_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66134, data, tail12] + - [0x66134, data, tail11] - [0x66138, .rodata, ov_SC01_004_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66154, data, tail13] + - [0x66154, data, tail12] - [0x66158, .rodata, ov_SC01_004_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66194, data, tail14] + - [0x66194, data, tail13] - [0x66198, .rodata, ov_SC01_004_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x661b4, data, tail15] + - [0x661b4, data, tail14] - [0x661cc, .rodata, ov_SC01_004_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6620c, data, tail16] + - [0x6620c, data, tail15] - [0x6624c, .rodata, ov_SC01_004_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6626c, .rodata, ov_SC01_004_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66280, data, tail17] + - [0x66280, data, tail16] - [0x66410, .rodata, ov_SC01_004_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66428, .rodata, ov_SC01_004_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6662c, data, tail18] + - [0x6662c, data, tail17] - [0x66630, .rodata, ov_SC01_004_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x666bc, data, tail19] + - [0x666bc, data, tail18] - [0x666c0, .rodata, ov_SC01_004_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x666d4, .rodata, ov_SC01_004_jr_8017BE9C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x666f4, data, tail20] + - [0x666f4, data, tail19] - [0x68274, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x68277] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC01_005.yaml b/config/splat.ov_SC01_005.yaml index aaf146e2d7..d88dfaeca8 100644 --- a/config/splat.ov_SC01_005.yaml +++ b/config/splat.ov_SC01_005.yaml @@ -141,31 +141,30 @@ segments: - [0xa366c, .rodata, ov_SC01_005_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa3680, data, tail9] - [0xa3698, .rodata, ov_SC01_005_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3704, data, tail10] - [0xa3774, .rodata, ov_SC01_005_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa37b8, .rodata, ov_SC01_005_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3800, data, tail11] + - [0xa3800, data, tail10] - [0xa3860, .rodata, ov_SC01_005_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3894, data, tail12] + - [0xa3894, data, tail11] - [0xa3898, .rodata, ov_SC01_005_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa38b4, data, tail13] + - [0xa38b4, data, tail12] - [0xa38b8, .rodata, ov_SC01_005_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa38f4, data, tail14] + - [0xa38f4, data, tail13] - [0xa38f8, .rodata, ov_SC01_005_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3914, data, tail15] + - [0xa3914, data, tail14] - [0xa392c, .rodata, ov_SC01_005_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa396c, data, tail16] + - [0xa396c, data, tail15] - [0xa39ac, .rodata, ov_SC01_005_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa39cc, .rodata, ov_SC01_005_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa39e0, data, tail17] + - [0xa39e0, data, tail16] - [0xa3b70, .rodata, ov_SC01_005_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa3b88, .rodata, ov_SC01_005_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3d8c, data, tail18] + - [0xa3d8c, data, tail17] - [0xa3d90, .rodata, ov_SC01_005_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3e1c, data, tail19] + - [0xa3e1c, data, tail18] - [0xa3e20, .rodata, ov_SC01_005_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa3e34, .rodata, ov_SC01_005_jr_8017C340] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3e54, data, tail20] + - [0xa3e54, data, tail19] - [0xA5F08, bin, trailing] # final 1 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA5F09] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC01_006.yaml b/config/splat.ov_SC01_006.yaml index 53560ac321..61bbc5d12d 100644 --- a/config/splat.ov_SC01_006.yaml +++ b/config/splat.ov_SC01_006.yaml @@ -141,31 +141,30 @@ segments: - [0xa366c, .rodata, ov_SC01_006_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa3680, data, tail9] - [0xa3698, .rodata, ov_SC01_006_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3704, data, tail10] - [0xa3774, .rodata, ov_SC01_006_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa37b8, .rodata, ov_SC01_006_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3800, data, tail11] + - [0xa3800, data, tail10] - [0xa3860, .rodata, ov_SC01_006_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3894, data, tail12] + - [0xa3894, data, tail11] - [0xa3898, .rodata, ov_SC01_006_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa38b4, data, tail13] + - [0xa38b4, data, tail12] - [0xa38b8, .rodata, ov_SC01_006_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa38f4, data, tail14] + - [0xa38f4, data, tail13] - [0xa38f8, .rodata, ov_SC01_006_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3914, data, tail15] + - [0xa3914, data, tail14] - [0xa392c, .rodata, ov_SC01_006_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa396c, data, tail16] + - [0xa396c, data, tail15] - [0xa39ac, .rodata, ov_SC01_006_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa39cc, .rodata, ov_SC01_006_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa39e0, data, tail17] + - [0xa39e0, data, tail16] - [0xa3b70, .rodata, ov_SC01_006_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa3b88, .rodata, ov_SC01_006_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3d8c, data, tail18] + - [0xa3d8c, data, tail17] - [0xa3d90, .rodata, ov_SC01_006_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3e1c, data, tail19] + - [0xa3e1c, data, tail18] - [0xa3e20, .rodata, ov_SC01_006_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa3e34, .rodata, ov_SC01_006_jr_8017C340] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3e54, data, tail20] + - [0xa3e54, data, tail19] - [0xA5F08, bin, trailing] # final 1 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA5F09] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC01_008.yaml b/config/splat.ov_SC01_008.yaml index 38729ada16..624282da2d 100644 --- a/config/splat.ov_SC01_008.yaml +++ b/config/splat.ov_SC01_008.yaml @@ -141,31 +141,30 @@ segments: - [0x7911c, .rodata, ov_SC01_008_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x79130, data, tail9] - [0x79148, .rodata, ov_SC01_008_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x791b4, data, tail10] - [0x79224, .rodata, ov_SC01_008_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x79268, .rodata, ov_SC01_008_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x792b0, data, tail11] + - [0x792b0, data, tail10] - [0x79310, .rodata, ov_SC01_008_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x79344, data, tail12] + - [0x79344, data, tail11] - [0x79348, .rodata, ov_SC01_008_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x79364, data, tail13] + - [0x79364, data, tail12] - [0x79368, .rodata, ov_SC01_008_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x793a4, data, tail14] + - [0x793a4, data, tail13] - [0x793a8, .rodata, ov_SC01_008_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x793c4, data, tail15] + - [0x793c4, data, tail14] - [0x793dc, .rodata, ov_SC01_008_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7941c, data, tail16] + - [0x7941c, data, tail15] - [0x7945c, .rodata, ov_SC01_008_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7947c, .rodata, ov_SC01_008_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x79490, data, tail17] + - [0x79490, data, tail16] - [0x79620, .rodata, ov_SC01_008_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x79638, .rodata, ov_SC01_008_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7983c, data, tail18] + - [0x7983c, data, tail17] - [0x79840, .rodata, ov_SC01_008_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x798cc, data, tail19] + - [0x798cc, data, tail18] - [0x798d0, .rodata, ov_SC01_008_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x798e4, .rodata, ov_SC01_008_jr_8017BE9C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x79904, data, tail20] + - [0x79904, data, tail19] - [0x7B484, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x7B487] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC01_009.yaml b/config/splat.ov_SC01_009.yaml index 2e933a3dd2..98836821ae 100644 --- a/config/splat.ov_SC01_009.yaml +++ b/config/splat.ov_SC01_009.yaml @@ -141,31 +141,30 @@ segments: - [0xc8ee0, .rodata, ov_SC01_009_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc8ef4, data, tail9] - [0xc8f0c, .rodata, ov_SC01_009_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc8f78, data, tail10] - [0xc8fe8, .rodata, ov_SC01_009_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc902c, .rodata, ov_SC01_009_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc9074, data, tail11] + - [0xc9074, data, tail10] - [0xc90d4, .rodata, ov_SC01_009_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc9108, data, tail12] + - [0xc9108, data, tail11] - [0xc910c, .rodata, ov_SC01_009_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc9128, data, tail13] + - [0xc9128, data, tail12] - [0xc912c, .rodata, ov_SC01_009_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc9168, data, tail14] + - [0xc9168, data, tail13] - [0xc916c, .rodata, ov_SC01_009_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc9188, data, tail15] + - [0xc9188, data, tail14] - [0xc91a0, .rodata, ov_SC01_009_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc91e0, data, tail16] + - [0xc91e0, data, tail15] - [0xc9220, .rodata, ov_SC01_009_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc9240, .rodata, ov_SC01_009_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc9254, data, tail17] + - [0xc9254, data, tail16] - [0xc93e4, .rodata, ov_SC01_009_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc93fc, .rodata, ov_SC01_009_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc9600, data, tail18] + - [0xc9600, data, tail17] - [0xc9604, .rodata, ov_SC01_009_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc9690, data, tail19] + - [0xc9690, data, tail18] - [0xc9694, .rodata, ov_SC01_009_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc96a8, .rodata, ov_SC01_009_jr_8017BE9C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc96c8, data, tail20] + - [0xc96c8, data, tail19] - [0xCB304, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xCB307] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC01_074.yaml b/config/splat.ov_SC01_074.yaml index 372398c770..5a64db0465 100644 --- a/config/splat.ov_SC01_074.yaml +++ b/config/splat.ov_SC01_074.yaml @@ -141,31 +141,30 @@ segments: - [0x71f70, .rodata, ov_SC01_074_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71f84, data, tail9] - [0x71f9c, .rodata, ov_SC01_074_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72008, data, tail10] - [0x72078, .rodata, ov_SC01_074_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x720bc, .rodata, ov_SC01_074_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72104, data, tail11] + - [0x72104, data, tail10] - [0x72164, .rodata, ov_SC01_074_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72198, data, tail12] + - [0x72198, data, tail11] - [0x7219c, .rodata, ov_SC01_074_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x721b8, data, tail13] + - [0x721b8, data, tail12] - [0x721bc, .rodata, ov_SC01_074_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x721f8, data, tail14] + - [0x721f8, data, tail13] - [0x721fc, .rodata, ov_SC01_074_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72218, data, tail15] + - [0x72218, data, tail14] - [0x72230, .rodata, ov_SC01_074_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72270, data, tail16] + - [0x72270, data, tail15] - [0x722b0, .rodata, ov_SC01_074_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x722d0, .rodata, ov_SC01_074_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x722e4, data, tail17] + - [0x722e4, data, tail16] - [0x72474, .rodata, ov_SC01_074_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7248c, .rodata, ov_SC01_074_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72690, data, tail18] + - [0x72690, data, tail17] - [0x72694, .rodata, ov_SC01_074_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72720, data, tail19] + - [0x72720, data, tail18] - [0x72724, .rodata, ov_SC01_074_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x72738, .rodata, ov_SC01_074_jr_8017BE9C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72758, data, tail20] + - [0x72758, data, tail19] - [0x73C14, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x73C17] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC01_080.yaml b/config/splat.ov_SC01_080.yaml index bc4be664d6..a6072d3b0a 100644 --- a/config/splat.ov_SC01_080.yaml +++ b/config/splat.ov_SC01_080.yaml @@ -140,30 +140,29 @@ segments: - [0x9bd90, .rodata, ov_SC01_080_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9bda4, data, tail9] - [0x9bdbc, .rodata, ov_SC01_080_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9be28, data, tail10] - [0x9be98, .rodata, ov_SC01_080_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9bedc, .rodata, ov_SC01_080_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9bf24, data, tail11] + - [0x9bf24, data, tail10] - [0x9bf84, .rodata, ov_SC01_080_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9bfb8, data, tail12] + - [0x9bfb8, data, tail11] - [0x9bfbc, .rodata, ov_SC01_080_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9bfd8, data, tail13] + - [0x9bfd8, data, tail12] - [0x9bfdc, .rodata, ov_SC01_080_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c018, data, tail14] + - [0x9c018, data, tail13] - [0x9c01c, .rodata, ov_SC01_080_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c038, data, tail15] + - [0x9c038, data, tail14] - [0x9c050, .rodata, ov_SC01_080_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c090, data, tail16] + - [0x9c090, data, tail15] - [0x9c0d0, .rodata, ov_SC01_080_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9c0f0, .rodata, ov_SC01_080_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c104, data, tail17] + - [0x9c104, data, tail16] - [0x9c294, .rodata, ov_SC01_080_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9c2ac, .rodata, ov_SC01_080_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c4b0, data, tail18] + - [0x9c4b0, data, tail17] - [0x9c4b4, .rodata, ov_SC01_080_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c540, data, tail19] + - [0x9c540, data, tail18] - [0x9c544, .rodata, ov_SC01_080_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c558, data, tail20] + - [0x9c558, data, tail19] - [0x9FDF4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9FDF7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC01_084.yaml b/config/splat.ov_SC01_084.yaml index a6c0c665c6..e23e7d0ef5 100644 --- a/config/splat.ov_SC01_084.yaml +++ b/config/splat.ov_SC01_084.yaml @@ -141,31 +141,30 @@ segments: - [0x9d760, .rodata, ov_SC01_084_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9d774, data, tail9] - [0x9d78c, .rodata, ov_SC01_084_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d7f8, data, tail10] - [0x9d868, .rodata, ov_SC01_084_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9d8ac, .rodata, ov_SC01_084_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d8f4, data, tail11] + - [0x9d8f4, data, tail10] - [0x9d954, .rodata, ov_SC01_084_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d988, data, tail12] + - [0x9d988, data, tail11] - [0x9d98c, .rodata, ov_SC01_084_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d9a8, data, tail13] + - [0x9d9a8, data, tail12] - [0x9d9ac, .rodata, ov_SC01_084_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d9e8, data, tail14] + - [0x9d9e8, data, tail13] - [0x9d9ec, .rodata, ov_SC01_084_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9da08, data, tail15] + - [0x9da08, data, tail14] - [0x9da20, .rodata, ov_SC01_084_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9da60, data, tail16] + - [0x9da60, data, tail15] - [0x9daa0, .rodata, ov_SC01_084_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9dac0, .rodata, ov_SC01_084_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9dad4, data, tail17] + - [0x9dad4, data, tail16] - [0x9dc64, .rodata, ov_SC01_084_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9dc7c, .rodata, ov_SC01_084_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9de80, data, tail18] + - [0x9de80, data, tail17] - [0x9de84, .rodata, ov_SC01_084_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9df10, data, tail19] + - [0x9df10, data, tail18] - [0x9df14, .rodata, ov_SC01_084_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9df28, .rodata, ov_SC01_084_jr_8017CA80] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9df48, data, tail20] + - [0x9df48, data, tail19] - [0x9FA9C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9FA9F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_000.yaml b/config/splat.ov_SC02_000.yaml index 73b83b144f..104add17a9 100644 --- a/config/splat.ov_SC02_000.yaml +++ b/config/splat.ov_SC02_000.yaml @@ -141,32 +141,31 @@ segments: - [0xbdfb4, .rodata, ov_SC02_000_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbdfc8, data, tail9] - [0xbdfe0, .rodata, ov_SC02_000_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe04c, data, tail10] - [0xbe0bc, .rodata, ov_SC02_000_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbe100, .rodata, ov_SC02_000_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe148, data, tail11] + - [0xbe148, data, tail10] - [0xbe1a8, .rodata, ov_SC02_000_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe1dc, data, tail12] + - [0xbe1dc, data, tail11] - [0xbe1e0, .rodata, ov_SC02_000_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe1fc, data, tail13] + - [0xbe1fc, data, tail12] - [0xbe200, .rodata, ov_SC02_000_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe23c, data, tail14] + - [0xbe23c, data, tail13] - [0xbe240, .rodata, ov_SC02_000_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe25c, data, tail15] + - [0xbe25c, data, tail14] - [0xbe274, .rodata, ov_SC02_000_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe2b4, data, tail16] + - [0xbe2b4, data, tail15] - [0xbe2f4, .rodata, ov_SC02_000_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbe314, .rodata, ov_SC02_000_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe328, data, tail17] + - [0xbe328, data, tail16] - [0xbe4b8, .rodata, ov_SC02_000_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbe4d0, .rodata, ov_SC02_000_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe6d4, data, tail18] + - [0xbe6d4, data, tail17] - [0xbe6d8, .rodata, ov_SC02_000_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe764, data, tail19] + - [0xbe764, data, tail18] - [0xbe768, .rodata, ov_SC02_000_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe77c, data, tail20] + - [0xbe77c, data, tail19] - [0xbe944, .rodata, ov_SC02_000_jr_8017FCB0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe964, data, tail21] + - [0xbe964, data, tail20] - [0xC070C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC070F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_003.yaml b/config/splat.ov_SC02_003.yaml index 68c6dbdfa0..9f4decc608 100644 --- a/config/splat.ov_SC02_003.yaml +++ b/config/splat.ov_SC02_003.yaml @@ -141,32 +141,31 @@ segments: - [0xbdfb4, .rodata, ov_SC02_003_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbdfc8, data, tail9] - [0xbdfe0, .rodata, ov_SC02_003_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe04c, data, tail10] - [0xbe0bc, .rodata, ov_SC02_003_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbe100, .rodata, ov_SC02_003_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe148, data, tail11] + - [0xbe148, data, tail10] - [0xbe1a8, .rodata, ov_SC02_003_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe1dc, data, tail12] + - [0xbe1dc, data, tail11] - [0xbe1e0, .rodata, ov_SC02_003_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe1fc, data, tail13] + - [0xbe1fc, data, tail12] - [0xbe200, .rodata, ov_SC02_003_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe23c, data, tail14] + - [0xbe23c, data, tail13] - [0xbe240, .rodata, ov_SC02_003_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe25c, data, tail15] + - [0xbe25c, data, tail14] - [0xbe274, .rodata, ov_SC02_003_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe2b4, data, tail16] + - [0xbe2b4, data, tail15] - [0xbe2f4, .rodata, ov_SC02_003_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbe314, .rodata, ov_SC02_003_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe328, data, tail17] + - [0xbe328, data, tail16] - [0xbe4b8, .rodata, ov_SC02_003_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbe4d0, .rodata, ov_SC02_003_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe6d4, data, tail18] + - [0xbe6d4, data, tail17] - [0xbe6d8, .rodata, ov_SC02_003_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe764, data, tail19] + - [0xbe764, data, tail18] - [0xbe768, .rodata, ov_SC02_003_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe77c, data, tail20] + - [0xbe77c, data, tail19] - [0xbe944, .rodata, ov_SC02_003_jr_8017FCB0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbe964, data, tail21] + - [0xbe964, data, tail20] - [0xC070C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC070F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_004.yaml b/config/splat.ov_SC02_004.yaml index 75910cf826..fe7f3949f5 100644 --- a/config/splat.ov_SC02_004.yaml +++ b/config/splat.ov_SC02_004.yaml @@ -140,30 +140,29 @@ segments: - [0x6c5c4, .rodata, ov_SC02_004_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6c5d8, data, tail9] - [0x6c5f0, .rodata, ov_SC02_004_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c65c, data, tail10] - [0x6c6cc, .rodata, ov_SC02_004_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6c710, .rodata, ov_SC02_004_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c758, data, tail11] + - [0x6c758, data, tail10] - [0x6c7b8, .rodata, ov_SC02_004_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c7ec, data, tail12] + - [0x6c7ec, data, tail11] - [0x6c7f0, .rodata, ov_SC02_004_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c80c, data, tail13] + - [0x6c80c, data, tail12] - [0x6c810, .rodata, ov_SC02_004_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c84c, data, tail14] + - [0x6c84c, data, tail13] - [0x6c850, .rodata, ov_SC02_004_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c86c, data, tail15] + - [0x6c86c, data, tail14] - [0x6c884, .rodata, ov_SC02_004_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c8c4, data, tail16] + - [0x6c8c4, data, tail15] - [0x6c904, .rodata, ov_SC02_004_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6c924, .rodata, ov_SC02_004_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c938, data, tail17] + - [0x6c938, data, tail16] - [0x6cac8, .rodata, ov_SC02_004_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6cae0, .rodata, ov_SC02_004_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cce4, data, tail18] + - [0x6cce4, data, tail17] - [0x6cce8, .rodata, ov_SC02_004_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cd74, data, tail19] + - [0x6cd74, data, tail18] - [0x6cd78, .rodata, ov_SC02_004_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cd8c, data, tail20] + - [0x6cd8c, data, tail19] - [0x6E26C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x6E26F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_005.yaml b/config/splat.ov_SC02_005.yaml index 42e18e3878..3581651d2c 100644 --- a/config/splat.ov_SC02_005.yaml +++ b/config/splat.ov_SC02_005.yaml @@ -140,30 +140,29 @@ segments: - [0xba2f8, .rodata, ov_SC02_005_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xba30c, data, tail9] - [0xba324, .rodata, ov_SC02_005_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xba390, data, tail10] - [0xba400, .rodata, ov_SC02_005_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xba444, .rodata, ov_SC02_005_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xba48c, data, tail11] + - [0xba48c, data, tail10] - [0xba4ec, .rodata, ov_SC02_005_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xba520, data, tail12] + - [0xba520, data, tail11] - [0xba524, .rodata, ov_SC02_005_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xba540, data, tail13] + - [0xba540, data, tail12] - [0xba544, .rodata, ov_SC02_005_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xba580, data, tail14] + - [0xba580, data, tail13] - [0xba584, .rodata, ov_SC02_005_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xba5a0, data, tail15] + - [0xba5a0, data, tail14] - [0xba5b8, .rodata, ov_SC02_005_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xba5f8, data, tail16] + - [0xba5f8, data, tail15] - [0xba638, .rodata, ov_SC02_005_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xba658, .rodata, ov_SC02_005_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xba66c, data, tail17] + - [0xba66c, data, tail16] - [0xba7fc, .rodata, ov_SC02_005_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xba814, .rodata, ov_SC02_005_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbaa18, data, tail18] + - [0xbaa18, data, tail17] - [0xbaa1c, .rodata, ov_SC02_005_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbaaa8, data, tail19] + - [0xbaaa8, data, tail18] - [0xbaaac, .rodata, ov_SC02_005_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbaac0, data, tail20] + - [0xbaac0, data, tail19] - [0xBCB00, bin, trailing] # final 1 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xBCB01] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_011.yaml b/config/splat.ov_SC02_011.yaml index a5b8a2ba6c..a77541f261 100644 --- a/config/splat.ov_SC02_011.yaml +++ b/config/splat.ov_SC02_011.yaml @@ -140,30 +140,29 @@ segments: - [0xc1454, .rodata, ov_SC02_011_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc1468, data, tail9] - [0xc1480, .rodata, ov_SC02_011_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc14ec, data, tail10] - [0xc155c, .rodata, ov_SC02_011_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc15a0, .rodata, ov_SC02_011_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc15e8, data, tail11] + - [0xc15e8, data, tail10] - [0xc1648, .rodata, ov_SC02_011_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc167c, data, tail12] + - [0xc167c, data, tail11] - [0xc1680, .rodata, ov_SC02_011_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc169c, data, tail13] + - [0xc169c, data, tail12] - [0xc16a0, .rodata, ov_SC02_011_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc16dc, data, tail14] + - [0xc16dc, data, tail13] - [0xc16e0, .rodata, ov_SC02_011_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc16fc, data, tail15] + - [0xc16fc, data, tail14] - [0xc1714, .rodata, ov_SC02_011_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1754, data, tail16] + - [0xc1754, data, tail15] - [0xc1794, .rodata, ov_SC02_011_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc17b4, .rodata, ov_SC02_011_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc17c8, data, tail17] + - [0xc17c8, data, tail16] - [0xc1958, .rodata, ov_SC02_011_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc1970, .rodata, ov_SC02_011_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1b74, data, tail18] + - [0xc1b74, data, tail17] - [0xc1b78, .rodata, ov_SC02_011_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1c04, data, tail19] + - [0xc1c04, data, tail18] - [0xc1c08, .rodata, ov_SC02_011_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1c1c, data, tail20] + - [0xc1c1c, data, tail19] - [0xC3924, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC3927] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_015.yaml b/config/splat.ov_SC02_015.yaml index b9912ae20d..1308f39b40 100644 --- a/config/splat.ov_SC02_015.yaml +++ b/config/splat.ov_SC02_015.yaml @@ -140,30 +140,29 @@ segments: - [0x666ac, .rodata, ov_SC02_015_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x666c0, data, tail9] - [0x666d8, .rodata, ov_SC02_015_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66744, data, tail10] - [0x667b4, .rodata, ov_SC02_015_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x667f8, .rodata, ov_SC02_015_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66840, data, tail11] + - [0x66840, data, tail10] - [0x668a0, .rodata, ov_SC02_015_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x668d4, data, tail12] + - [0x668d4, data, tail11] - [0x668d8, .rodata, ov_SC02_015_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x668f4, data, tail13] + - [0x668f4, data, tail12] - [0x668f8, .rodata, ov_SC02_015_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66934, data, tail14] + - [0x66934, data, tail13] - [0x66938, .rodata, ov_SC02_015_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66954, data, tail15] + - [0x66954, data, tail14] - [0x6696c, .rodata, ov_SC02_015_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x669ac, data, tail16] + - [0x669ac, data, tail15] - [0x669ec, .rodata, ov_SC02_015_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66a0c, .rodata, ov_SC02_015_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66a20, data, tail17] + - [0x66a20, data, tail16] - [0x66bb0, .rodata, ov_SC02_015_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66bc8, .rodata, ov_SC02_015_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66dcc, data, tail18] + - [0x66dcc, data, tail17] - [0x66dd0, .rodata, ov_SC02_015_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66e5c, data, tail19] + - [0x66e5c, data, tail18] - [0x66e60, .rodata, ov_SC02_015_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66e94, data, tail20] + - [0x66e94, data, tail19] - [0x68544, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x68547] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_016.yaml b/config/splat.ov_SC02_016.yaml index 4a42e81ee6..7cc82828f2 100644 --- a/config/splat.ov_SC02_016.yaml +++ b/config/splat.ov_SC02_016.yaml @@ -141,31 +141,30 @@ segments: - [0x8a28c, .rodata, ov_SC02_016_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8a2a0, data, tail9] - [0x8a2b8, .rodata, ov_SC02_016_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a324, data, tail10] - [0x8a394, .rodata, ov_SC02_016_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8a3d8, .rodata, ov_SC02_016_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a420, data, tail11] + - [0x8a420, data, tail10] - [0x8a480, .rodata, ov_SC02_016_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a4b4, data, tail12] + - [0x8a4b4, data, tail11] - [0x8a4b8, .rodata, ov_SC02_016_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a4d4, data, tail13] + - [0x8a4d4, data, tail12] - [0x8a4d8, .rodata, ov_SC02_016_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a514, data, tail14] + - [0x8a514, data, tail13] - [0x8a518, .rodata, ov_SC02_016_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a534, data, tail15] + - [0x8a534, data, tail14] - [0x8a54c, .rodata, ov_SC02_016_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a58c, data, tail16] + - [0x8a58c, data, tail15] - [0x8a5cc, .rodata, ov_SC02_016_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8a5ec, .rodata, ov_SC02_016_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a600, data, tail17] + - [0x8a600, data, tail16] - [0x8a790, .rodata, ov_SC02_016_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8a7a8, .rodata, ov_SC02_016_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a9ac, data, tail18] + - [0x8a9ac, data, tail17] - [0x8a9b0, .rodata, ov_SC02_016_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8aa3c, data, tail19] + - [0x8aa3c, data, tail18] - [0x8aa40, .rodata, ov_SC02_016_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8aa54, .rodata, ov_SC02_016_jr_8017DC70] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8aa74, data, tail20] + - [0x8aa74, data, tail19] - [0x8C97C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x8C97F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_017.yaml b/config/splat.ov_SC02_017.yaml index 447b35b1ea..1b2d2eb4f6 100644 --- a/config/splat.ov_SC02_017.yaml +++ b/config/splat.ov_SC02_017.yaml @@ -141,31 +141,30 @@ segments: - [0xc5aac, .rodata, ov_SC02_017_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc5ac0, data, tail9] - [0xc5ad8, .rodata, ov_SC02_017_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5b44, data, tail10] - [0xc5bb4, .rodata, ov_SC02_017_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc5bf8, .rodata, ov_SC02_017_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5c40, data, tail11] + - [0xc5c40, data, tail10] - [0xc5ca0, .rodata, ov_SC02_017_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5cd4, data, tail12] + - [0xc5cd4, data, tail11] - [0xc5cd8, .rodata, ov_SC02_017_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5cf4, data, tail13] + - [0xc5cf4, data, tail12] - [0xc5cf8, .rodata, ov_SC02_017_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5d34, data, tail14] + - [0xc5d34, data, tail13] - [0xc5d38, .rodata, ov_SC02_017_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5d54, data, tail15] + - [0xc5d54, data, tail14] - [0xc5d6c, .rodata, ov_SC02_017_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5dac, data, tail16] + - [0xc5dac, data, tail15] - [0xc5dec, .rodata, ov_SC02_017_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc5e0c, .rodata, ov_SC02_017_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5e20, data, tail17] + - [0xc5e20, data, tail16] - [0xc5fb0, .rodata, ov_SC02_017_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc5fc8, .rodata, ov_SC02_017_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc61cc, data, tail18] + - [0xc61cc, data, tail17] - [0xc61d0, .rodata, ov_SC02_017_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc625c, data, tail19] + - [0xc625c, data, tail18] - [0xc6260, .rodata, ov_SC02_017_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc6274, .rodata, ov_SC02_017_jr_8017DF34] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc6294, data, tail20] + - [0xc6294, data, tail19] - [0xC7BDC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC7BDF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_021.yaml b/config/splat.ov_SC02_021.yaml index d8a44f8fc8..8d258b0477 100644 --- a/config/splat.ov_SC02_021.yaml +++ b/config/splat.ov_SC02_021.yaml @@ -141,31 +141,30 @@ segments: - [0x69028, .rodata, ov_SC02_021_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6903c, data, tail9] - [0x69054, .rodata, ov_SC02_021_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x690c0, data, tail10] - [0x69130, .rodata, ov_SC02_021_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x69174, .rodata, ov_SC02_021_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x691bc, data, tail11] + - [0x691bc, data, tail10] - [0x6921c, .rodata, ov_SC02_021_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x69250, data, tail12] + - [0x69250, data, tail11] - [0x69254, .rodata, ov_SC02_021_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x69270, data, tail13] + - [0x69270, data, tail12] - [0x69274, .rodata, ov_SC02_021_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x692b0, data, tail14] + - [0x692b0, data, tail13] - [0x692b4, .rodata, ov_SC02_021_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x692d0, data, tail15] + - [0x692d0, data, tail14] - [0x692e8, .rodata, ov_SC02_021_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x69328, data, tail16] + - [0x69328, data, tail15] - [0x69368, .rodata, ov_SC02_021_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x69388, .rodata, ov_SC02_021_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6939c, data, tail17] + - [0x6939c, data, tail16] - [0x6952c, .rodata, ov_SC02_021_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x69544, .rodata, ov_SC02_021_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x69748, data, tail18] + - [0x69748, data, tail17] - [0x6974c, .rodata, ov_SC02_021_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x697d8, data, tail19] + - [0x697d8, data, tail18] - [0x697dc, .rodata, ov_SC02_021_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x697f0, .rodata, ov_SC02_021_jr_8017C294] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x69810, data, tail20] + - [0x69810, data, tail19] - [0x6B744, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x6B747] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_026.yaml b/config/splat.ov_SC02_026.yaml index b6858564a9..6a1fcf919e 100644 --- a/config/splat.ov_SC02_026.yaml +++ b/config/splat.ov_SC02_026.yaml @@ -141,31 +141,30 @@ segments: - [0xa645c, .rodata, ov_SC02_026_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6470, data, tail9] - [0xa6488, .rodata, ov_SC02_026_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa64f4, data, tail10] - [0xa6564, .rodata, ov_SC02_026_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa65a8, .rodata, ov_SC02_026_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa65f0, data, tail11] + - [0xa65f0, data, tail10] - [0xa6650, .rodata, ov_SC02_026_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6684, data, tail12] + - [0xa6684, data, tail11] - [0xa6688, .rodata, ov_SC02_026_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa66a4, data, tail13] + - [0xa66a4, data, tail12] - [0xa66a8, .rodata, ov_SC02_026_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa66e4, data, tail14] + - [0xa66e4, data, tail13] - [0xa66e8, .rodata, ov_SC02_026_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6704, data, tail15] + - [0xa6704, data, tail14] - [0xa671c, .rodata, ov_SC02_026_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa675c, data, tail16] + - [0xa675c, data, tail15] - [0xa679c, .rodata, ov_SC02_026_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa67bc, .rodata, ov_SC02_026_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa67d0, data, tail17] + - [0xa67d0, data, tail16] - [0xa6960, .rodata, ov_SC02_026_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6978, .rodata, ov_SC02_026_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6b7c, data, tail18] + - [0xa6b7c, data, tail17] - [0xa6b80, .rodata, ov_SC02_026_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6c0c, data, tail19] + - [0xa6c0c, data, tail18] - [0xa6c10, .rodata, ov_SC02_026_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6c24, .rodata, ov_SC02_026_jr_8017C180] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6c44, data, tail20] + - [0xa6c44, data, tail19] - [0xA8164, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA8167] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_027.yaml b/config/splat.ov_SC02_027.yaml index 7790e72a3f..47fc11b3c4 100644 --- a/config/splat.ov_SC02_027.yaml +++ b/config/splat.ov_SC02_027.yaml @@ -141,31 +141,30 @@ segments: - [0xb01c8, .rodata, ov_SC02_027_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb01dc, data, tail9] - [0xb01f4, .rodata, ov_SC02_027_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb0260, data, tail10] - [0xb02d0, .rodata, ov_SC02_027_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb0314, .rodata, ov_SC02_027_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb035c, data, tail11] + - [0xb035c, data, tail10] - [0xb03bc, .rodata, ov_SC02_027_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb03f0, data, tail12] + - [0xb03f0, data, tail11] - [0xb03f4, .rodata, ov_SC02_027_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb0410, data, tail13] + - [0xb0410, data, tail12] - [0xb0414, .rodata, ov_SC02_027_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb0450, data, tail14] + - [0xb0450, data, tail13] - [0xb0454, .rodata, ov_SC02_027_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb0470, data, tail15] + - [0xb0470, data, tail14] - [0xb0488, .rodata, ov_SC02_027_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb04c8, data, tail16] + - [0xb04c8, data, tail15] - [0xb0508, .rodata, ov_SC02_027_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb0528, .rodata, ov_SC02_027_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb053c, data, tail17] + - [0xb053c, data, tail16] - [0xb06cc, .rodata, ov_SC02_027_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb06e4, .rodata, ov_SC02_027_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb08e8, data, tail18] + - [0xb08e8, data, tail17] - [0xb08ec, .rodata, ov_SC02_027_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb0978, data, tail19] + - [0xb0978, data, tail18] - [0xb097c, .rodata, ov_SC02_027_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb0990, .rodata, ov_SC02_027_jr_8017D898] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb09b0, data, tail20] + - [0xb09b0, data, tail19] - [0xB28E4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xB28E7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_028.yaml b/config/splat.ov_SC02_028.yaml index 76a610553f..cadc389f1e 100644 --- a/config/splat.ov_SC02_028.yaml +++ b/config/splat.ov_SC02_028.yaml @@ -141,31 +141,30 @@ segments: - [0xa914c, .rodata, ov_SC02_028_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa9160, data, tail9] - [0xa9178, .rodata, ov_SC02_028_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa91e4, data, tail10] - [0xa9254, .rodata, ov_SC02_028_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa9298, .rodata, ov_SC02_028_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa92e0, data, tail11] + - [0xa92e0, data, tail10] - [0xa9340, .rodata, ov_SC02_028_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa9374, data, tail12] + - [0xa9374, data, tail11] - [0xa9378, .rodata, ov_SC02_028_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa9394, data, tail13] + - [0xa9394, data, tail12] - [0xa9398, .rodata, ov_SC02_028_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa93d4, data, tail14] + - [0xa93d4, data, tail13] - [0xa93d8, .rodata, ov_SC02_028_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa93f4, data, tail15] + - [0xa93f4, data, tail14] - [0xa940c, .rodata, ov_SC02_028_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa944c, data, tail16] + - [0xa944c, data, tail15] - [0xa948c, .rodata, ov_SC02_028_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa94ac, .rodata, ov_SC02_028_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa94c0, data, tail17] + - [0xa94c0, data, tail16] - [0xa9650, .rodata, ov_SC02_028_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa9668, .rodata, ov_SC02_028_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa986c, data, tail18] + - [0xa986c, data, tail17] - [0xa9870, .rodata, ov_SC02_028_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa98fc, data, tail19] + - [0xa98fc, data, tail18] - [0xa9900, .rodata, ov_SC02_028_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa9914, .rodata, ov_SC02_028_jr_8017D898] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa9934, data, tail20] + - [0xa9934, data, tail19] - [0xAB4E4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xAB4E7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_031.yaml b/config/splat.ov_SC02_031.yaml index cfb1961997..2c7d840b9c 100644 --- a/config/splat.ov_SC02_031.yaml +++ b/config/splat.ov_SC02_031.yaml @@ -140,30 +140,29 @@ segments: - [0x8d948, .rodata, ov_SC02_031_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8d95c, data, tail9] - [0x8d974, .rodata, ov_SC02_031_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8d9e0, data, tail10] - [0x8da50, .rodata, ov_SC02_031_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8da94, .rodata, ov_SC02_031_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8dadc, data, tail11] + - [0x8dadc, data, tail10] - [0x8db3c, .rodata, ov_SC02_031_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8db70, data, tail12] + - [0x8db70, data, tail11] - [0x8db74, .rodata, ov_SC02_031_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8db90, data, tail13] + - [0x8db90, data, tail12] - [0x8db94, .rodata, ov_SC02_031_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8dbd0, data, tail14] + - [0x8dbd0, data, tail13] - [0x8dbd4, .rodata, ov_SC02_031_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8dbf0, data, tail15] + - [0x8dbf0, data, tail14] - [0x8dc08, .rodata, ov_SC02_031_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8dc48, data, tail16] + - [0x8dc48, data, tail15] - [0x8dc88, .rodata, ov_SC02_031_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8dca8, .rodata, ov_SC02_031_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8dcbc, data, tail17] + - [0x8dcbc, data, tail16] - [0x8de4c, .rodata, ov_SC02_031_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8de64, .rodata, ov_SC02_031_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8e068, data, tail18] + - [0x8e068, data, tail17] - [0x8e06c, .rodata, ov_SC02_031_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8e0f8, data, tail19] + - [0x8e0f8, data, tail18] - [0x8e0fc, .rodata, ov_SC02_031_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8e110, data, tail20] + - [0x8e110, data, tail19] - [0x8F9B4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x8F9B7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_035.yaml b/config/splat.ov_SC02_035.yaml index eab0304bd0..8a2511dc8f 100644 --- a/config/splat.ov_SC02_035.yaml +++ b/config/splat.ov_SC02_035.yaml @@ -141,31 +141,30 @@ segments: - [0x94c10, .rodata, ov_SC02_035_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x94c24, data, tail9] - [0x94c3c, .rodata, ov_SC02_035_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x94ca8, data, tail10] - [0x94d18, .rodata, ov_SC02_035_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x94d5c, .rodata, ov_SC02_035_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x94da4, data, tail11] + - [0x94da4, data, tail10] - [0x94e04, .rodata, ov_SC02_035_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x94e38, data, tail12] + - [0x94e38, data, tail11] - [0x94e3c, .rodata, ov_SC02_035_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x94e58, data, tail13] + - [0x94e58, data, tail12] - [0x94e5c, .rodata, ov_SC02_035_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x94e98, data, tail14] + - [0x94e98, data, tail13] - [0x94e9c, .rodata, ov_SC02_035_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x94eb8, data, tail15] + - [0x94eb8, data, tail14] - [0x94ed0, .rodata, ov_SC02_035_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x94f10, data, tail16] + - [0x94f10, data, tail15] - [0x94f50, .rodata, ov_SC02_035_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x94f70, .rodata, ov_SC02_035_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x94f84, data, tail17] + - [0x94f84, data, tail16] - [0x95114, .rodata, ov_SC02_035_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9512c, .rodata, ov_SC02_035_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x95330, data, tail18] + - [0x95330, data, tail17] - [0x95334, .rodata, ov_SC02_035_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x953c0, data, tail19] + - [0x953c0, data, tail18] - [0x953c4, .rodata, ov_SC02_035_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x953d8, .rodata, ov_SC02_035_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x953f8, data, tail20] + - [0x953f8, data, tail19] - [0x968EC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x968EF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_039.yaml b/config/splat.ov_SC02_039.yaml index 3e5561aa2a..82e74c41f0 100644 --- a/config/splat.ov_SC02_039.yaml +++ b/config/splat.ov_SC02_039.yaml @@ -141,31 +141,30 @@ segments: - [0x76ffc, .rodata, ov_SC02_039_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77010, data, tail9] - [0x77028, .rodata, ov_SC02_039_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77094, data, tail10] - [0x77104, .rodata, ov_SC02_039_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77148, .rodata, ov_SC02_039_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77190, data, tail11] + - [0x77190, data, tail10] - [0x771f0, .rodata, ov_SC02_039_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77224, data, tail12] + - [0x77224, data, tail11] - [0x77228, .rodata, ov_SC02_039_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77244, data, tail13] + - [0x77244, data, tail12] - [0x77248, .rodata, ov_SC02_039_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77284, data, tail14] + - [0x77284, data, tail13] - [0x77288, .rodata, ov_SC02_039_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x772a4, data, tail15] + - [0x772a4, data, tail14] - [0x772bc, .rodata, ov_SC02_039_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x772fc, data, tail16] + - [0x772fc, data, tail15] - [0x7733c, .rodata, ov_SC02_039_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7735c, .rodata, ov_SC02_039_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77370, data, tail17] + - [0x77370, data, tail16] - [0x77500, .rodata, ov_SC02_039_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77518, .rodata, ov_SC02_039_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7771c, data, tail18] + - [0x7771c, data, tail17] - [0x77720, .rodata, ov_SC02_039_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x777ac, data, tail19] + - [0x777ac, data, tail18] - [0x777b0, .rodata, ov_SC02_039_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x777c4, .rodata, ov_SC02_039_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x777e4, data, tail20] + - [0x777e4, data, tail19] - [0x78CA4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x78CA7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC02_041.yaml b/config/splat.ov_SC02_041.yaml index 56659b1a9d..3200bffa92 100644 --- a/config/splat.ov_SC02_041.yaml +++ b/config/splat.ov_SC02_041.yaml @@ -141,31 +141,30 @@ segments: - [0x8f368, .rodata, ov_SC02_041_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f37c, data, tail9] - [0x8f394, .rodata, ov_SC02_041_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f400, data, tail10] - [0x8f470, .rodata, ov_SC02_041_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f4b4, .rodata, ov_SC02_041_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f4fc, data, tail11] + - [0x8f4fc, data, tail10] - [0x8f55c, .rodata, ov_SC02_041_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f590, data, tail12] + - [0x8f590, data, tail11] - [0x8f594, .rodata, ov_SC02_041_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f5b0, data, tail13] + - [0x8f5b0, data, tail12] - [0x8f5b4, .rodata, ov_SC02_041_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f5f0, data, tail14] + - [0x8f5f0, data, tail13] - [0x8f5f4, .rodata, ov_SC02_041_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f610, data, tail15] + - [0x8f610, data, tail14] - [0x8f628, .rodata, ov_SC02_041_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f668, data, tail16] + - [0x8f668, data, tail15] - [0x8f6a8, .rodata, ov_SC02_041_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f6c8, .rodata, ov_SC02_041_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f6dc, data, tail17] + - [0x8f6dc, data, tail16] - [0x8f86c, .rodata, ov_SC02_041_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f884, .rodata, ov_SC02_041_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fa88, data, tail18] + - [0x8fa88, data, tail17] - [0x8fa8c, .rodata, ov_SC02_041_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fb18, data, tail19] + - [0x8fb18, data, tail18] - [0x8fb1c, .rodata, ov_SC02_041_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8fb30, .rodata, ov_SC02_041_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fb50, data, tail20] + - [0x8fb50, data, tail19] - [0x9157C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9157F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_001.yaml b/config/splat.ov_SC03_001.yaml index 29be2fbbb5..fc317ebebd 100644 --- a/config/splat.ov_SC03_001.yaml +++ b/config/splat.ov_SC03_001.yaml @@ -140,30 +140,29 @@ segments: - [0xc4488, .rodata, ov_SC03_001_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc449c, data, tail9] - [0xc44b4, .rodata, ov_SC03_001_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc4520, data, tail10] - [0xc4590, .rodata, ov_SC03_001_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc45d4, .rodata, ov_SC03_001_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc461c, data, tail11] + - [0xc461c, data, tail10] - [0xc467c, .rodata, ov_SC03_001_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc46b0, data, tail12] + - [0xc46b0, data, tail11] - [0xc46b4, .rodata, ov_SC03_001_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc46d0, data, tail13] + - [0xc46d0, data, tail12] - [0xc46d4, .rodata, ov_SC03_001_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc4710, data, tail14] + - [0xc4710, data, tail13] - [0xc4714, .rodata, ov_SC03_001_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc4730, data, tail15] + - [0xc4730, data, tail14] - [0xc4748, .rodata, ov_SC03_001_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc4788, data, tail16] + - [0xc4788, data, tail15] - [0xc47c8, .rodata, ov_SC03_001_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc47e8, .rodata, ov_SC03_001_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc47fc, data, tail17] + - [0xc47fc, data, tail16] - [0xc498c, .rodata, ov_SC03_001_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc49a4, .rodata, ov_SC03_001_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc4ba8, data, tail18] + - [0xc4ba8, data, tail17] - [0xc4bac, .rodata, ov_SC03_001_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc4c38, data, tail19] + - [0xc4c38, data, tail18] - [0xc4c3c, .rodata, ov_SC03_001_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc4c70, data, tail20] + - [0xc4c70, data, tail19] - [0xC730C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC730F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_002.yaml b/config/splat.ov_SC03_002.yaml index d0df1f6b23..a660663980 100644 --- a/config/splat.ov_SC03_002.yaml +++ b/config/splat.ov_SC03_002.yaml @@ -141,31 +141,30 @@ segments: - [0xa19e4, .rodata, ov_SC03_002_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa19f8, data, tail9] - [0xa1a10, .rodata, ov_SC03_002_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1a7c, data, tail10] - [0xa1aec, .rodata, ov_SC03_002_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa1b30, .rodata, ov_SC03_002_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1b78, data, tail11] + - [0xa1b78, data, tail10] - [0xa1bd8, .rodata, ov_SC03_002_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1c0c, data, tail12] + - [0xa1c0c, data, tail11] - [0xa1c10, .rodata, ov_SC03_002_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1c2c, data, tail13] + - [0xa1c2c, data, tail12] - [0xa1c30, .rodata, ov_SC03_002_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1c6c, data, tail14] + - [0xa1c6c, data, tail13] - [0xa1c70, .rodata, ov_SC03_002_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1c8c, data, tail15] + - [0xa1c8c, data, tail14] - [0xa1ca4, .rodata, ov_SC03_002_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1ce4, data, tail16] + - [0xa1ce4, data, tail15] - [0xa1d24, .rodata, ov_SC03_002_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa1d44, .rodata, ov_SC03_002_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1d58, data, tail17] + - [0xa1d58, data, tail16] - [0xa1ee8, .rodata, ov_SC03_002_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa1f00, .rodata, ov_SC03_002_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2104, data, tail18] + - [0xa2104, data, tail17] - [0xa2108, .rodata, ov_SC03_002_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2194, data, tail19] + - [0xa2194, data, tail18] - [0xa2198, .rodata, ov_SC03_002_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa21ac, .rodata, ov_SC03_002_jr_8017D604] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa21cc, data, tail20] + - [0xa21cc, data, tail19] - [0xA39F4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA39F7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_003.yaml b/config/splat.ov_SC03_003.yaml index 9916d90dcc..d1f6c5fb86 100644 --- a/config/splat.ov_SC03_003.yaml +++ b/config/splat.ov_SC03_003.yaml @@ -141,32 +141,31 @@ segments: - [0x65d64, .rodata, ov_SC03_003_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65d78, data, tail9] - [0x65d90, .rodata, ov_SC03_003_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65dfc, data, tail10] - [0x65e6c, .rodata, ov_SC03_003_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65eb0, .rodata, ov_SC03_003_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65ef8, data, tail11] + - [0x65ef8, data, tail10] - [0x65f58, .rodata, ov_SC03_003_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65f8c, data, tail12] + - [0x65f8c, data, tail11] - [0x65f90, .rodata, ov_SC03_003_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65fac, data, tail13] + - [0x65fac, data, tail12] - [0x65fb0, .rodata, ov_SC03_003_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65fec, data, tail14] + - [0x65fec, data, tail13] - [0x65ff0, .rodata, ov_SC03_003_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6600c, data, tail15] + - [0x6600c, data, tail14] - [0x66024, .rodata, ov_SC03_003_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66064, data, tail16] + - [0x66064, data, tail15] - [0x660a4, .rodata, ov_SC03_003_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x660c4, .rodata, ov_SC03_003_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x660d8, data, tail17] + - [0x660d8, data, tail16] - [0x66268, .rodata, ov_SC03_003_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66280, .rodata, ov_SC03_003_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66484, data, tail18] + - [0x66484, data, tail17] - [0x66488, .rodata, ov_SC03_003_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66514, data, tail19] + - [0x66514, data, tail18] - [0x66518, .rodata, ov_SC03_003_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6652c, data, tail20] + - [0x6652c, data, tail19] - [0x6654c, .rodata, ov_SC03_003_jr_8017D5C0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6656c, data, tail21] + - [0x6656c, data, tail20] - [0x67A24, bin, trailing] # final 1 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x67A25] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_006.yaml b/config/splat.ov_SC03_006.yaml index c4015520a6..3661b419ed 100644 --- a/config/splat.ov_SC03_006.yaml +++ b/config/splat.ov_SC03_006.yaml @@ -140,30 +140,29 @@ segments: - [0xcd620, .rodata, ov_SC03_006_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcd634, data, tail9] - [0xcd64c, .rodata, ov_SC03_006_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcd6b8, data, tail10] - [0xcd728, .rodata, ov_SC03_006_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcd76c, .rodata, ov_SC03_006_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcd7b4, data, tail11] + - [0xcd7b4, data, tail10] - [0xcd814, .rodata, ov_SC03_006_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcd848, data, tail12] + - [0xcd848, data, tail11] - [0xcd84c, .rodata, ov_SC03_006_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcd868, data, tail13] + - [0xcd868, data, tail12] - [0xcd86c, .rodata, ov_SC03_006_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcd8a8, data, tail14] + - [0xcd8a8, data, tail13] - [0xcd8ac, .rodata, ov_SC03_006_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcd8c8, data, tail15] + - [0xcd8c8, data, tail14] - [0xcd8e0, .rodata, ov_SC03_006_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcd920, data, tail16] + - [0xcd920, data, tail15] - [0xcd960, .rodata, ov_SC03_006_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcd980, .rodata, ov_SC03_006_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcd994, data, tail17] + - [0xcd994, data, tail16] - [0xcdb24, .rodata, ov_SC03_006_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcdb3c, .rodata, ov_SC03_006_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcdd40, data, tail18] + - [0xcdd40, data, tail17] - [0xcdd44, .rodata, ov_SC03_006_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcddd0, data, tail19] + - [0xcddd0, data, tail18] - [0xcddd4, .rodata, ov_SC03_006_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcdde8, data, tail20] + - [0xcdde8, data, tail19] - [0xCF75C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xCF75F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_007.yaml b/config/splat.ov_SC03_007.yaml index a0daa37af9..b4920ee746 100644 --- a/config/splat.ov_SC03_007.yaml +++ b/config/splat.ov_SC03_007.yaml @@ -140,30 +140,29 @@ segments: - [0xbffa8, .rodata, ov_SC03_007_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbffbc, data, tail9] - [0xbffd4, .rodata, ov_SC03_007_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0040, data, tail10] - [0xc00b0, .rodata, ov_SC03_007_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc00f4, .rodata, ov_SC03_007_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc013c, data, tail11] + - [0xc013c, data, tail10] - [0xc019c, .rodata, ov_SC03_007_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc01d0, data, tail12] + - [0xc01d0, data, tail11] - [0xc01d4, .rodata, ov_SC03_007_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc01f0, data, tail13] + - [0xc01f0, data, tail12] - [0xc01f4, .rodata, ov_SC03_007_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0230, data, tail14] + - [0xc0230, data, tail13] - [0xc0234, .rodata, ov_SC03_007_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0250, data, tail15] + - [0xc0250, data, tail14] - [0xc0268, .rodata, ov_SC03_007_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc02a8, data, tail16] + - [0xc02a8, data, tail15] - [0xc02e8, .rodata, ov_SC03_007_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0308, .rodata, ov_SC03_007_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc031c, data, tail17] + - [0xc031c, data, tail16] - [0xc04ac, .rodata, ov_SC03_007_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc04c4, .rodata, ov_SC03_007_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc06c8, data, tail18] + - [0xc06c8, data, tail17] - [0xc06cc, .rodata, ov_SC03_007_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0758, data, tail19] + - [0xc0758, data, tail18] - [0xc075c, .rodata, ov_SC03_007_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0770, data, tail20] + - [0xc0770, data, tail19] - [0xC316C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC316F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_010.yaml b/config/splat.ov_SC03_010.yaml index 1efda5c2bd..0cb7a0d45c 100644 --- a/config/splat.ov_SC03_010.yaml +++ b/config/splat.ov_SC03_010.yaml @@ -141,31 +141,30 @@ segments: - [0x76284, .rodata, ov_SC03_010_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76298, data, tail9] - [0x762b0, .rodata, ov_SC03_010_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7631c, data, tail10] - [0x7638c, .rodata, ov_SC03_010_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x763d0, .rodata, ov_SC03_010_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76418, data, tail11] + - [0x76418, data, tail10] - [0x76478, .rodata, ov_SC03_010_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x764ac, data, tail12] + - [0x764ac, data, tail11] - [0x764b0, .rodata, ov_SC03_010_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x764cc, data, tail13] + - [0x764cc, data, tail12] - [0x764d0, .rodata, ov_SC03_010_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7650c, data, tail14] + - [0x7650c, data, tail13] - [0x76510, .rodata, ov_SC03_010_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7652c, data, tail15] + - [0x7652c, data, tail14] - [0x76544, .rodata, ov_SC03_010_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76584, data, tail16] + - [0x76584, data, tail15] - [0x765c4, .rodata, ov_SC03_010_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x765e4, .rodata, ov_SC03_010_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x765f8, data, tail17] + - [0x765f8, data, tail16] - [0x76788, .rodata, ov_SC03_010_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x767a0, .rodata, ov_SC03_010_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x769a4, data, tail18] + - [0x769a4, data, tail17] - [0x769a8, .rodata, ov_SC03_010_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76a34, data, tail19] + - [0x76a34, data, tail18] - [0x76a38, .rodata, ov_SC03_010_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76a4c, .rodata, ov_SC03_010_jr_8017C730] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76a6c, data, tail20] + - [0x76a6c, data, tail19] - [0x78074, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x78077] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_011.yaml b/config/splat.ov_SC03_011.yaml index e0ea3ef0a3..f3bd570a05 100644 --- a/config/splat.ov_SC03_011.yaml +++ b/config/splat.ov_SC03_011.yaml @@ -141,31 +141,30 @@ segments: - [0x784f4, .rodata, ov_SC03_011_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78508, data, tail9] - [0x78520, .rodata, ov_SC03_011_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7858c, data, tail10] - [0x785fc, .rodata, ov_SC03_011_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78640, .rodata, ov_SC03_011_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78688, data, tail11] + - [0x78688, data, tail10] - [0x786e8, .rodata, ov_SC03_011_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7871c, data, tail12] + - [0x7871c, data, tail11] - [0x78720, .rodata, ov_SC03_011_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7873c, data, tail13] + - [0x7873c, data, tail12] - [0x78740, .rodata, ov_SC03_011_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7877c, data, tail14] + - [0x7877c, data, tail13] - [0x78780, .rodata, ov_SC03_011_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7879c, data, tail15] + - [0x7879c, data, tail14] - [0x787b4, .rodata, ov_SC03_011_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x787f4, data, tail16] + - [0x787f4, data, tail15] - [0x78834, .rodata, ov_SC03_011_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78854, .rodata, ov_SC03_011_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78868, data, tail17] + - [0x78868, data, tail16] - [0x789f8, .rodata, ov_SC03_011_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78a10, .rodata, ov_SC03_011_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78c14, data, tail18] + - [0x78c14, data, tail17] - [0x78c18, .rodata, ov_SC03_011_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78ca4, data, tail19] + - [0x78ca4, data, tail18] - [0x78ca8, .rodata, ov_SC03_011_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78cbc, .rodata, ov_SC03_011_jr_8017C730] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78cdc, data, tail20] + - [0x78cdc, data, tail19] - [0x7A2A8, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x7A2AB] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_012.yaml b/config/splat.ov_SC03_012.yaml index bd6b41a65f..05a0d76a4e 100644 --- a/config/splat.ov_SC03_012.yaml +++ b/config/splat.ov_SC03_012.yaml @@ -140,30 +140,29 @@ segments: - [0x6b350, .rodata, ov_SC03_012_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b364, data, tail9] - [0x6b37c, .rodata, ov_SC03_012_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b3e8, data, tail10] - [0x6b458, .rodata, ov_SC03_012_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b49c, .rodata, ov_SC03_012_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b4e4, data, tail11] + - [0x6b4e4, data, tail10] - [0x6b544, .rodata, ov_SC03_012_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b578, data, tail12] + - [0x6b578, data, tail11] - [0x6b57c, .rodata, ov_SC03_012_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b598, data, tail13] + - [0x6b598, data, tail12] - [0x6b59c, .rodata, ov_SC03_012_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b5d8, data, tail14] + - [0x6b5d8, data, tail13] - [0x6b5dc, .rodata, ov_SC03_012_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b5f8, data, tail15] + - [0x6b5f8, data, tail14] - [0x6b610, .rodata, ov_SC03_012_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b650, data, tail16] + - [0x6b650, data, tail15] - [0x6b690, .rodata, ov_SC03_012_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b6b0, .rodata, ov_SC03_012_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b6c4, data, tail17] + - [0x6b6c4, data, tail16] - [0x6b854, .rodata, ov_SC03_012_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b86c, .rodata, ov_SC03_012_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6ba70, data, tail18] + - [0x6ba70, data, tail17] - [0x6ba74, .rodata, ov_SC03_012_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6bb00, data, tail19] + - [0x6bb00, data, tail18] - [0x6bb04, .rodata, ov_SC03_012_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6bb18, data, tail20] + - [0x6bb18, data, tail19] - [0x6D004, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x6D007] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_013.yaml b/config/splat.ov_SC03_013.yaml index 2559daff36..b4d7b85869 100644 --- a/config/splat.ov_SC03_013.yaml +++ b/config/splat.ov_SC03_013.yaml @@ -141,31 +141,30 @@ segments: - [0x835e8, .rodata, ov_SC03_013_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x835fc, data, tail9] - [0x83614, .rodata, ov_SC03_013_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83680, data, tail10] - [0x836f0, .rodata, ov_SC03_013_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x83734, .rodata, ov_SC03_013_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8377c, data, tail11] + - [0x8377c, data, tail10] - [0x837dc, .rodata, ov_SC03_013_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83810, data, tail12] + - [0x83810, data, tail11] - [0x83814, .rodata, ov_SC03_013_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83830, data, tail13] + - [0x83830, data, tail12] - [0x83834, .rodata, ov_SC03_013_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83870, data, tail14] + - [0x83870, data, tail13] - [0x83874, .rodata, ov_SC03_013_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83890, data, tail15] + - [0x83890, data, tail14] - [0x838a8, .rodata, ov_SC03_013_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x838e8, data, tail16] + - [0x838e8, data, tail15] - [0x83928, .rodata, ov_SC03_013_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x83948, .rodata, ov_SC03_013_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8395c, data, tail17] + - [0x8395c, data, tail16] - [0x83aec, .rodata, ov_SC03_013_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x83b04, .rodata, ov_SC03_013_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83d08, data, tail18] + - [0x83d08, data, tail17] - [0x83d0c, .rodata, ov_SC03_013_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83d98, data, tail19] + - [0x83d98, data, tail18] - [0x83d9c, .rodata, ov_SC03_013_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x83db0, .rodata, ov_SC03_013_jr_8017C730] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83dd0, data, tail20] + - [0x83dd0, data, tail19] - [0x853FC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x853FF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_014.yaml b/config/splat.ov_SC03_014.yaml index 2470843dfe..3bd9eb861c 100644 --- a/config/splat.ov_SC03_014.yaml +++ b/config/splat.ov_SC03_014.yaml @@ -145,32 +145,31 @@ segments: - [0xc09bc, .rodata, ov_SC03_014_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc09d0, data, tail9] - [0xc09e8, .rodata, ov_SC03_014_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0a54, data, tail10] - [0xc0ac4, .rodata, ov_SC03_014_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0b08, .rodata, ov_SC03_014_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0b50, data, tail11] + - [0xc0b50, data, tail10] - [0xc0bb0, .rodata, ov_SC03_014_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0be4, data, tail12] + - [0xc0be4, data, tail11] - [0xc0be8, .rodata, ov_SC03_014_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0c04, data, tail13] + - [0xc0c04, data, tail12] - [0xc0c08, .rodata, ov_SC03_014_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0c44, data, tail14] + - [0xc0c44, data, tail13] - [0xc0c48, .rodata, ov_SC03_014_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0c64, data, tail15] + - [0xc0c64, data, tail14] - [0xc0c7c, .rodata, ov_SC03_014_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0cbc, data, tail16] + - [0xc0cbc, data, tail15] - [0xc0cfc, .rodata, ov_SC03_014_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0d1c, .rodata, ov_SC03_014_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0d30, data, tail17] + - [0xc0d30, data, tail16] - [0xc0ec0, .rodata, ov_SC03_014_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0ed8, .rodata, ov_SC03_014_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc10dc, data, tail18] + - [0xc10dc, data, tail17] - [0xc10e0, .rodata, ov_SC03_014_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc116c, data, tail19] + - [0xc116c, data, tail18] - [0xc1170, .rodata, ov_SC03_014_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1184, data, tail20] + - [0xc1184, data, tail19] - [0xc11b0, .rodata, ov_SC03_014_jr_8017EB7C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc11d0, data, tail21] + - [0xc11d0, data, tail20] - [0xC2EE4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC2EE7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_015.yaml b/config/splat.ov_SC03_015.yaml index 004171105f..d9f6e84fea 100644 --- a/config/splat.ov_SC03_015.yaml +++ b/config/splat.ov_SC03_015.yaml @@ -145,32 +145,31 @@ segments: - [0xc09bc, .rodata, ov_SC03_015_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc09d0, data, tail9] - [0xc09e8, .rodata, ov_SC03_015_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0a54, data, tail10] - [0xc0ac4, .rodata, ov_SC03_015_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0b08, .rodata, ov_SC03_015_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0b50, data, tail11] + - [0xc0b50, data, tail10] - [0xc0bb0, .rodata, ov_SC03_015_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0be4, data, tail12] + - [0xc0be4, data, tail11] - [0xc0be8, .rodata, ov_SC03_015_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0c04, data, tail13] + - [0xc0c04, data, tail12] - [0xc0c08, .rodata, ov_SC03_015_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0c44, data, tail14] + - [0xc0c44, data, tail13] - [0xc0c48, .rodata, ov_SC03_015_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0c64, data, tail15] + - [0xc0c64, data, tail14] - [0xc0c7c, .rodata, ov_SC03_015_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0cbc, data, tail16] + - [0xc0cbc, data, tail15] - [0xc0cfc, .rodata, ov_SC03_015_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0d1c, .rodata, ov_SC03_015_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0d30, data, tail17] + - [0xc0d30, data, tail16] - [0xc0ec0, .rodata, ov_SC03_015_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0ed8, .rodata, ov_SC03_015_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc10dc, data, tail18] + - [0xc10dc, data, tail17] - [0xc10e0, .rodata, ov_SC03_015_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc116c, data, tail19] + - [0xc116c, data, tail18] - [0xc1170, .rodata, ov_SC03_015_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1184, data, tail20] + - [0xc1184, data, tail19] - [0xc11b0, .rodata, ov_SC03_015_jr_8017EB7C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc11d0, data, tail21] + - [0xc11d0, data, tail20] - [0xC2EE4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC2EE7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_023.yaml b/config/splat.ov_SC03_023.yaml index 260db4b20a..8750dd29ef 100644 --- a/config/splat.ov_SC03_023.yaml +++ b/config/splat.ov_SC03_023.yaml @@ -140,30 +140,29 @@ segments: - [0x6ef94, .rodata, ov_SC03_023_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6efa8, data, tail9] - [0x6efc0, .rodata, ov_SC03_023_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f02c, data, tail10] - [0x6f09c, .rodata, ov_SC03_023_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6f0e0, .rodata, ov_SC03_023_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f128, data, tail11] + - [0x6f128, data, tail10] - [0x6f188, .rodata, ov_SC03_023_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f1bc, data, tail12] + - [0x6f1bc, data, tail11] - [0x6f1c0, .rodata, ov_SC03_023_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f1dc, data, tail13] + - [0x6f1dc, data, tail12] - [0x6f1e0, .rodata, ov_SC03_023_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f21c, data, tail14] + - [0x6f21c, data, tail13] - [0x6f220, .rodata, ov_SC03_023_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f23c, data, tail15] + - [0x6f23c, data, tail14] - [0x6f254, .rodata, ov_SC03_023_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f294, data, tail16] + - [0x6f294, data, tail15] - [0x6f2d4, .rodata, ov_SC03_023_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6f2f4, .rodata, ov_SC03_023_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f308, data, tail17] + - [0x6f308, data, tail16] - [0x6f498, .rodata, ov_SC03_023_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6f4b0, .rodata, ov_SC03_023_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f6b4, data, tail18] + - [0x6f6b4, data, tail17] - [0x6f6b8, .rodata, ov_SC03_023_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f744, data, tail19] + - [0x6f744, data, tail18] - [0x6f748, .rodata, ov_SC03_023_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6f75c, data, tail20] + - [0x6f75c, data, tail19] - [0x70C2C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x70C2F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_024.yaml b/config/splat.ov_SC03_024.yaml index bec43abf35..a9b7f2c6cc 100644 --- a/config/splat.ov_SC03_024.yaml +++ b/config/splat.ov_SC03_024.yaml @@ -141,32 +141,31 @@ segments: - [0x9741c, .rodata, ov_SC03_024_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x97430, data, tail9] - [0x97448, .rodata, ov_SC03_024_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x974b4, data, tail10] - [0x97524, .rodata, ov_SC03_024_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x97568, .rodata, ov_SC03_024_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x975b0, data, tail11] + - [0x975b0, data, tail10] - [0x97610, .rodata, ov_SC03_024_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97644, data, tail12] + - [0x97644, data, tail11] - [0x97648, .rodata, ov_SC03_024_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97664, data, tail13] + - [0x97664, data, tail12] - [0x97668, .rodata, ov_SC03_024_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x976a4, data, tail14] + - [0x976a4, data, tail13] - [0x976a8, .rodata, ov_SC03_024_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x976c4, data, tail15] + - [0x976c4, data, tail14] - [0x976dc, .rodata, ov_SC03_024_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9771c, data, tail16] + - [0x9771c, data, tail15] - [0x9775c, .rodata, ov_SC03_024_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9777c, .rodata, ov_SC03_024_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97790, data, tail17] + - [0x97790, data, tail16] - [0x97920, .rodata, ov_SC03_024_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x97938, .rodata, ov_SC03_024_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97b3c, data, tail18] + - [0x97b3c, data, tail17] - [0x97b40, .rodata, ov_SC03_024_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97bcc, data, tail19] + - [0x97bcc, data, tail18] - [0x97bd0, .rodata, ov_SC03_024_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97be4, data, tail20] + - [0x97be4, data, tail19] - [0x97c10, .rodata, ov_SC03_024_jr_8017DF84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97c30, data, tail21] + - [0x97c30, data, tail20] - [0x996F4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x996F7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_028.yaml b/config/splat.ov_SC03_028.yaml index 60b054ccbc..852d9d0279 100644 --- a/config/splat.ov_SC03_028.yaml +++ b/config/splat.ov_SC03_028.yaml @@ -140,30 +140,29 @@ segments: - [0xc15a4, .rodata, ov_SC03_028_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc15b8, data, tail9] - [0xc15d0, .rodata, ov_SC03_028_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc163c, data, tail10] - [0xc16ac, .rodata, ov_SC03_028_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc16f0, .rodata, ov_SC03_028_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1738, data, tail11] + - [0xc1738, data, tail10] - [0xc1798, .rodata, ov_SC03_028_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc17cc, data, tail12] + - [0xc17cc, data, tail11] - [0xc17d0, .rodata, ov_SC03_028_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc17ec, data, tail13] + - [0xc17ec, data, tail12] - [0xc17f0, .rodata, ov_SC03_028_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc182c, data, tail14] + - [0xc182c, data, tail13] - [0xc1830, .rodata, ov_SC03_028_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc184c, data, tail15] + - [0xc184c, data, tail14] - [0xc1864, .rodata, ov_SC03_028_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc18a4, data, tail16] + - [0xc18a4, data, tail15] - [0xc18e4, .rodata, ov_SC03_028_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc1904, .rodata, ov_SC03_028_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1918, data, tail17] + - [0xc1918, data, tail16] - [0xc1aa8, .rodata, ov_SC03_028_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc1ac0, .rodata, ov_SC03_028_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1cc4, data, tail18] + - [0xc1cc4, data, tail17] - [0xc1cc8, .rodata, ov_SC03_028_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1d54, data, tail19] + - [0xc1d54, data, tail18] - [0xc1d58, .rodata, ov_SC03_028_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1d6c, data, tail20] + - [0xc1d6c, data, tail19] - [0xC44AC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC44AF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_029.yaml b/config/splat.ov_SC03_029.yaml index 122c2a0db3..0cc52a7170 100644 --- a/config/splat.ov_SC03_029.yaml +++ b/config/splat.ov_SC03_029.yaml @@ -141,31 +141,30 @@ segments: - [0xaf6d8, .rodata, ov_SC03_029_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaf6ec, data, tail9] - [0xaf704, .rodata, ov_SC03_029_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaf770, data, tail10] - [0xaf7e0, .rodata, ov_SC03_029_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaf824, .rodata, ov_SC03_029_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaf86c, data, tail11] + - [0xaf86c, data, tail10] - [0xaf8cc, .rodata, ov_SC03_029_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaf900, data, tail12] + - [0xaf900, data, tail11] - [0xaf904, .rodata, ov_SC03_029_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaf920, data, tail13] + - [0xaf920, data, tail12] - [0xaf924, .rodata, ov_SC03_029_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaf960, data, tail14] + - [0xaf960, data, tail13] - [0xaf964, .rodata, ov_SC03_029_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaf980, data, tail15] + - [0xaf980, data, tail14] - [0xaf998, .rodata, ov_SC03_029_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaf9d8, data, tail16] + - [0xaf9d8, data, tail15] - [0xafa18, .rodata, ov_SC03_029_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xafa38, .rodata, ov_SC03_029_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xafa4c, data, tail17] + - [0xafa4c, data, tail16] - [0xafbdc, .rodata, ov_SC03_029_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xafbf4, .rodata, ov_SC03_029_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xafdf8, data, tail18] + - [0xafdf8, data, tail17] - [0xafdfc, .rodata, ov_SC03_029_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xafe88, data, tail19] + - [0xafe88, data, tail18] - [0xafe8c, .rodata, ov_SC03_029_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xafea0, .rodata, ov_SC03_029_jr_8017DC70] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xafec0, data, tail20] + - [0xafec0, data, tail19] - [0xB18EC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xB18EF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_030.yaml b/config/splat.ov_SC03_030.yaml index 25aa92b63b..239513b634 100644 --- a/config/splat.ov_SC03_030.yaml +++ b/config/splat.ov_SC03_030.yaml @@ -140,30 +140,29 @@ segments: - [0xb7d7c, .rodata, ov_SC03_030_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7d90, data, tail9] - [0xb7da8, .rodata, ov_SC03_030_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7e14, data, tail10] - [0xb7e84, .rodata, ov_SC03_030_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7ec8, .rodata, ov_SC03_030_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7f10, data, tail11] + - [0xb7f10, data, tail10] - [0xb7f70, .rodata, ov_SC03_030_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7fa4, data, tail12] + - [0xb7fa4, data, tail11] - [0xb7fa8, .rodata, ov_SC03_030_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7fc4, data, tail13] + - [0xb7fc4, data, tail12] - [0xb7fc8, .rodata, ov_SC03_030_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8004, data, tail14] + - [0xb8004, data, tail13] - [0xb8008, .rodata, ov_SC03_030_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8024, data, tail15] + - [0xb8024, data, tail14] - [0xb803c, .rodata, ov_SC03_030_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb807c, data, tail16] + - [0xb807c, data, tail15] - [0xb80bc, .rodata, ov_SC03_030_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb80dc, .rodata, ov_SC03_030_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb80f0, data, tail17] + - [0xb80f0, data, tail16] - [0xb8280, .rodata, ov_SC03_030_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb8298, .rodata, ov_SC03_030_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb849c, data, tail18] + - [0xb849c, data, tail17] - [0xb84a0, .rodata, ov_SC03_030_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb852c, data, tail19] + - [0xb852c, data, tail18] - [0xb8530, .rodata, ov_SC03_030_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8544, data, tail20] + - [0xb8544, data, tail19] - [0xB9AF0] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes # ` - [0x, bin, trailing]` (the final 1-3 bytes spimdisasm's data path drops); diff --git a/config/splat.ov_SC03_031.yaml b/config/splat.ov_SC03_031.yaml index f2689711d5..31dbf6dc7e 100644 --- a/config/splat.ov_SC03_031.yaml +++ b/config/splat.ov_SC03_031.yaml @@ -141,31 +141,30 @@ segments: - [0x9c220, .rodata, ov_SC03_031_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9c234, data, tail9] - [0x9c24c, .rodata, ov_SC03_031_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c2b8, data, tail10] - [0x9c328, .rodata, ov_SC03_031_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9c36c, .rodata, ov_SC03_031_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c3b4, data, tail11] + - [0x9c3b4, data, tail10] - [0x9c414, .rodata, ov_SC03_031_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c448, data, tail12] + - [0x9c448, data, tail11] - [0x9c44c, .rodata, ov_SC03_031_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c468, data, tail13] + - [0x9c468, data, tail12] - [0x9c46c, .rodata, ov_SC03_031_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c4a8, data, tail14] + - [0x9c4a8, data, tail13] - [0x9c4ac, .rodata, ov_SC03_031_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c4c8, data, tail15] + - [0x9c4c8, data, tail14] - [0x9c4e0, .rodata, ov_SC03_031_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c520, data, tail16] + - [0x9c520, data, tail15] - [0x9c560, .rodata, ov_SC03_031_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9c580, .rodata, ov_SC03_031_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c594, data, tail17] + - [0x9c594, data, tail16] - [0x9c724, .rodata, ov_SC03_031_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9c73c, .rodata, ov_SC03_031_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c940, data, tail18] + - [0x9c940, data, tail17] - [0x9c944, .rodata, ov_SC03_031_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c9d0, data, tail19] + - [0x9c9d0, data, tail18] - [0x9c9d4, .rodata, ov_SC03_031_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9c9e8, .rodata, ov_SC03_031_jr_8017DB5C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ca08, data, tail20] + - [0x9ca08, data, tail19] - [0x9E14C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9E14F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_089.yaml b/config/splat.ov_SC03_089.yaml index bbeafd6cc4..6786475b5b 100644 --- a/config/splat.ov_SC03_089.yaml +++ b/config/splat.ov_SC03_089.yaml @@ -141,31 +141,30 @@ segments: - [0x9ca8c, .rodata, ov_SC03_089_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9caa0, data, tail9] - [0x9cab8, .rodata, ov_SC03_089_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9cb24, data, tail10] - [0x9cb94, .rodata, ov_SC03_089_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9cbd8, .rodata, ov_SC03_089_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9cc20, data, tail11] + - [0x9cc20, data, tail10] - [0x9cc80, .rodata, ov_SC03_089_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ccb4, data, tail12] + - [0x9ccb4, data, tail11] - [0x9ccb8, .rodata, ov_SC03_089_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ccd4, data, tail13] + - [0x9ccd4, data, tail12] - [0x9ccd8, .rodata, ov_SC03_089_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9cd14, data, tail14] + - [0x9cd14, data, tail13] - [0x9cd18, .rodata, ov_SC03_089_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9cd34, data, tail15] + - [0x9cd34, data, tail14] - [0x9cd4c, .rodata, ov_SC03_089_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9cd8c, data, tail16] + - [0x9cd8c, data, tail15] - [0x9cdcc, .rodata, ov_SC03_089_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9cdec, .rodata, ov_SC03_089_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ce00, data, tail17] + - [0x9ce00, data, tail16] - [0x9cf90, .rodata, ov_SC03_089_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9cfa8, .rodata, ov_SC03_089_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d1ac, data, tail18] + - [0x9d1ac, data, tail17] - [0x9d1b0, .rodata, ov_SC03_089_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d23c, data, tail19] + - [0x9d23c, data, tail18] - [0x9d240, .rodata, ov_SC03_089_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9d254, .rodata, ov_SC03_089_jr_8017CA80] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d274, data, tail20] + - [0x9d274, data, tail19] - [0x9E7C4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9E7C7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_090.yaml b/config/splat.ov_SC03_090.yaml index aaed3bbffe..ff6f1dfe7c 100644 --- a/config/splat.ov_SC03_090.yaml +++ b/config/splat.ov_SC03_090.yaml @@ -141,31 +141,30 @@ segments: - [0xa1ef8, .rodata, ov_SC03_090_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa1f0c, data, tail9] - [0xa1f24, .rodata, ov_SC03_090_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1f90, data, tail10] - [0xa2000, .rodata, ov_SC03_090_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa2044, .rodata, ov_SC03_090_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa208c, data, tail11] + - [0xa208c, data, tail10] - [0xa20ec, .rodata, ov_SC03_090_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2120, data, tail12] + - [0xa2120, data, tail11] - [0xa2124, .rodata, ov_SC03_090_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2140, data, tail13] + - [0xa2140, data, tail12] - [0xa2144, .rodata, ov_SC03_090_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2180, data, tail14] + - [0xa2180, data, tail13] - [0xa2184, .rodata, ov_SC03_090_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa21a0, data, tail15] + - [0xa21a0, data, tail14] - [0xa21b8, .rodata, ov_SC03_090_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa21f8, data, tail16] + - [0xa21f8, data, tail15] - [0xa2238, .rodata, ov_SC03_090_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa2258, .rodata, ov_SC03_090_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa226c, data, tail17] + - [0xa226c, data, tail16] - [0xa23fc, .rodata, ov_SC03_090_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa2414, .rodata, ov_SC03_090_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2618, data, tail18] + - [0xa2618, data, tail17] - [0xa261c, .rodata, ov_SC03_090_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa26a8, data, tail19] + - [0xa26a8, data, tail18] - [0xa26ac, .rodata, ov_SC03_090_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa26c0, .rodata, ov_SC03_090_jr_8017CA80] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa26e0, data, tail20] + - [0xa26e0, data, tail19] - [0xA3C34, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA3C37] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_091.yaml b/config/splat.ov_SC03_091.yaml index 702ab17ec1..b61bcb614f 100644 --- a/config/splat.ov_SC03_091.yaml +++ b/config/splat.ov_SC03_091.yaml @@ -142,31 +142,30 @@ segments: - [0xa85c4, .rodata, ov_SC03_091_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa85d8, data, tail9] - [0xa85f0, .rodata, ov_SC03_091_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa865c, data, tail10] - [0xa86cc, .rodata, ov_SC03_091_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa8710, .rodata, ov_SC03_091_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa8758, data, tail11] + - [0xa8758, data, tail10] - [0xa87b8, .rodata, ov_SC03_091_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa87ec, data, tail12] + - [0xa87ec, data, tail11] - [0xa87f0, .rodata, ov_SC03_091_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa880c, data, tail13] + - [0xa880c, data, tail12] - [0xa8810, .rodata, ov_SC03_091_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa884c, data, tail14] + - [0xa884c, data, tail13] - [0xa8850, .rodata, ov_SC03_091_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa886c, data, tail15] + - [0xa886c, data, tail14] - [0xa8884, .rodata, ov_SC03_091_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa88c4, data, tail16] + - [0xa88c4, data, tail15] - [0xa8904, .rodata, ov_SC03_091_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa8924, .rodata, ov_SC03_091_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa8938, data, tail17] + - [0xa8938, data, tail16] - [0xa8ac8, .rodata, ov_SC03_091_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa8ae0, .rodata, ov_SC03_091_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa8ce4, data, tail18] + - [0xa8ce4, data, tail17] - [0xa8ce8, .rodata, ov_SC03_091_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa8d74, data, tail19] + - [0xa8d74, data, tail18] - [0xa8d78, .rodata, ov_SC03_091_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa8d8c, .rodata, ov_SC03_091_jr_8017D898] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa8dac, data, tail20] + - [0xa8dac, data, tail19] - [0xAA584, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xAA587] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_092.yaml b/config/splat.ov_SC03_092.yaml index 7daad22cb1..7aeb18f7f2 100644 --- a/config/splat.ov_SC03_092.yaml +++ b/config/splat.ov_SC03_092.yaml @@ -140,30 +140,29 @@ segments: - [0x8919c, .rodata, ov_SC03_092_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x891b0, data, tail9] - [0x891c8, .rodata, ov_SC03_092_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89234, data, tail10] - [0x892a4, .rodata, ov_SC03_092_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x892e8, .rodata, ov_SC03_092_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89330, data, tail11] + - [0x89330, data, tail10] - [0x89390, .rodata, ov_SC03_092_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x893c4, data, tail12] + - [0x893c4, data, tail11] - [0x893c8, .rodata, ov_SC03_092_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x893e4, data, tail13] + - [0x893e4, data, tail12] - [0x893e8, .rodata, ov_SC03_092_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89424, data, tail14] + - [0x89424, data, tail13] - [0x89428, .rodata, ov_SC03_092_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89444, data, tail15] + - [0x89444, data, tail14] - [0x8945c, .rodata, ov_SC03_092_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8949c, data, tail16] + - [0x8949c, data, tail15] - [0x894dc, .rodata, ov_SC03_092_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x894fc, .rodata, ov_SC03_092_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89510, data, tail17] + - [0x89510, data, tail16] - [0x896a0, .rodata, ov_SC03_092_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x896b8, .rodata, ov_SC03_092_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x898bc, data, tail18] + - [0x898bc, data, tail17] - [0x898c0, .rodata, ov_SC03_092_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8994c, data, tail19] + - [0x8994c, data, tail18] - [0x89950, .rodata, ov_SC03_092_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89964, data, tail20] + - [0x89964, data, tail19] - [0x8AF2C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x8AF2F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_093.yaml b/config/splat.ov_SC03_093.yaml index b3eaf54fd1..934bc4268e 100644 --- a/config/splat.ov_SC03_093.yaml +++ b/config/splat.ov_SC03_093.yaml @@ -141,31 +141,30 @@ segments: - [0xa25f0, .rodata, ov_SC03_093_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa2604, data, tail9] - [0xa261c, .rodata, ov_SC03_093_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2688, data, tail10] - [0xa26f8, .rodata, ov_SC03_093_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa273c, .rodata, ov_SC03_093_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2784, data, tail11] + - [0xa2784, data, tail10] - [0xa27e4, .rodata, ov_SC03_093_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2818, data, tail12] + - [0xa2818, data, tail11] - [0xa281c, .rodata, ov_SC03_093_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2838, data, tail13] + - [0xa2838, data, tail12] - [0xa283c, .rodata, ov_SC03_093_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2878, data, tail14] + - [0xa2878, data, tail13] - [0xa287c, .rodata, ov_SC03_093_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2898, data, tail15] + - [0xa2898, data, tail14] - [0xa28b0, .rodata, ov_SC03_093_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa28f0, data, tail16] + - [0xa28f0, data, tail15] - [0xa2930, .rodata, ov_SC03_093_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa2950, .rodata, ov_SC03_093_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2964, data, tail17] + - [0xa2964, data, tail16] - [0xa2af4, .rodata, ov_SC03_093_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa2b0c, .rodata, ov_SC03_093_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2d10, data, tail18] + - [0xa2d10, data, tail17] - [0xa2d14, .rodata, ov_SC03_093_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2da0, data, tail19] + - [0xa2da0, data, tail18] - [0xa2da4, .rodata, ov_SC03_093_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa2db8, .rodata, ov_SC03_093_jr_8017D898] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2dd8, data, tail20] + - [0xa2dd8, data, tail19] - [0xA4584, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA4587] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_094.yaml b/config/splat.ov_SC03_094.yaml index 5b0d81d0f0..cbb31cf4a8 100644 --- a/config/splat.ov_SC03_094.yaml +++ b/config/splat.ov_SC03_094.yaml @@ -141,31 +141,30 @@ segments: - [0xa942c, .rodata, ov_SC03_094_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa9440, data, tail9] - [0xa9458, .rodata, ov_SC03_094_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa94c4, data, tail10] - [0xa9534, .rodata, ov_SC03_094_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa9578, .rodata, ov_SC03_094_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa95c0, data, tail11] + - [0xa95c0, data, tail10] - [0xa9620, .rodata, ov_SC03_094_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa9654, data, tail12] + - [0xa9654, data, tail11] - [0xa9658, .rodata, ov_SC03_094_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa9674, data, tail13] + - [0xa9674, data, tail12] - [0xa9678, .rodata, ov_SC03_094_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa96b4, data, tail14] + - [0xa96b4, data, tail13] - [0xa96b8, .rodata, ov_SC03_094_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa96d4, data, tail15] + - [0xa96d4, data, tail14] - [0xa96ec, .rodata, ov_SC03_094_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa972c, data, tail16] + - [0xa972c, data, tail15] - [0xa976c, .rodata, ov_SC03_094_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa978c, .rodata, ov_SC03_094_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa97a0, data, tail17] + - [0xa97a0, data, tail16] - [0xa9930, .rodata, ov_SC03_094_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa9948, .rodata, ov_SC03_094_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa9b4c, data, tail18] + - [0xa9b4c, data, tail17] - [0xa9b50, .rodata, ov_SC03_094_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa9bdc, data, tail19] + - [0xa9bdc, data, tail18] - [0xa9be0, .rodata, ov_SC03_094_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa9bf4, .rodata, ov_SC03_094_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa9c14, data, tail20] + - [0xa9c14, data, tail19] - [0xAB13C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xAB13F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_095.yaml b/config/splat.ov_SC03_095.yaml index 72803b3f28..af6de49944 100644 --- a/config/splat.ov_SC03_095.yaml +++ b/config/splat.ov_SC03_095.yaml @@ -141,31 +141,30 @@ segments: - [0x72058, .rodata, ov_SC03_095_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7206c, data, tail9] - [0x72084, .rodata, ov_SC03_095_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x720f0, data, tail10] - [0x72160, .rodata, ov_SC03_095_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x721a4, .rodata, ov_SC03_095_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x721ec, data, tail11] + - [0x721ec, data, tail10] - [0x7224c, .rodata, ov_SC03_095_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72280, data, tail12] + - [0x72280, data, tail11] - [0x72284, .rodata, ov_SC03_095_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x722a0, data, tail13] + - [0x722a0, data, tail12] - [0x722a4, .rodata, ov_SC03_095_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x722e0, data, tail14] + - [0x722e0, data, tail13] - [0x722e4, .rodata, ov_SC03_095_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72300, data, tail15] + - [0x72300, data, tail14] - [0x72318, .rodata, ov_SC03_095_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72358, data, tail16] + - [0x72358, data, tail15] - [0x72398, .rodata, ov_SC03_095_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x723b8, .rodata, ov_SC03_095_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x723cc, data, tail17] + - [0x723cc, data, tail16] - [0x7255c, .rodata, ov_SC03_095_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x72574, .rodata, ov_SC03_095_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72778, data, tail18] + - [0x72778, data, tail17] - [0x7277c, .rodata, ov_SC03_095_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72808, data, tail19] + - [0x72808, data, tail18] - [0x7280c, .rodata, ov_SC03_095_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x72820, .rodata, ov_SC03_095_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72840, data, tail20] + - [0x72840, data, tail19] - [0x73D3C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x73D3F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_096.yaml b/config/splat.ov_SC03_096.yaml index 5b0503cf89..05f2597856 100644 --- a/config/splat.ov_SC03_096.yaml +++ b/config/splat.ov_SC03_096.yaml @@ -141,31 +141,30 @@ segments: - [0x70b0c, .rodata, ov_SC03_096_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70b20, data, tail9] - [0x70b38, .rodata, ov_SC03_096_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70ba4, data, tail10] - [0x70c14, .rodata, ov_SC03_096_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70c58, .rodata, ov_SC03_096_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70ca0, data, tail11] + - [0x70ca0, data, tail10] - [0x70d00, .rodata, ov_SC03_096_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70d34, data, tail12] + - [0x70d34, data, tail11] - [0x70d38, .rodata, ov_SC03_096_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70d54, data, tail13] + - [0x70d54, data, tail12] - [0x70d58, .rodata, ov_SC03_096_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70d94, data, tail14] + - [0x70d94, data, tail13] - [0x70d98, .rodata, ov_SC03_096_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70db4, data, tail15] + - [0x70db4, data, tail14] - [0x70dcc, .rodata, ov_SC03_096_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70e0c, data, tail16] + - [0x70e0c, data, tail15] - [0x70e4c, .rodata, ov_SC03_096_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70e6c, .rodata, ov_SC03_096_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70e80, data, tail17] + - [0x70e80, data, tail16] - [0x71010, .rodata, ov_SC03_096_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71028, .rodata, ov_SC03_096_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7122c, data, tail18] + - [0x7122c, data, tail17] - [0x71230, .rodata, ov_SC03_096_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x712bc, data, tail19] + - [0x712bc, data, tail18] - [0x712c0, .rodata, ov_SC03_096_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x712d4, .rodata, ov_SC03_096_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x712f4, data, tail20] + - [0x712f4, data, tail19] - [0x727F4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x727F7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_097.yaml b/config/splat.ov_SC03_097.yaml index 9380821ac4..0c12ff13e2 100644 --- a/config/splat.ov_SC03_097.yaml +++ b/config/splat.ov_SC03_097.yaml @@ -141,31 +141,30 @@ segments: - [0x80b7c, .rodata, ov_SC03_097_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x80b90, data, tail9] - [0x80ba8, .rodata, ov_SC03_097_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80c14, data, tail10] - [0x80c84, .rodata, ov_SC03_097_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x80cc8, .rodata, ov_SC03_097_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80d10, data, tail11] + - [0x80d10, data, tail10] - [0x80d70, .rodata, ov_SC03_097_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80da4, data, tail12] + - [0x80da4, data, tail11] - [0x80da8, .rodata, ov_SC03_097_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80dc4, data, tail13] + - [0x80dc4, data, tail12] - [0x80dc8, .rodata, ov_SC03_097_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80e04, data, tail14] + - [0x80e04, data, tail13] - [0x80e08, .rodata, ov_SC03_097_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80e24, data, tail15] + - [0x80e24, data, tail14] - [0x80e3c, .rodata, ov_SC03_097_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80e7c, data, tail16] + - [0x80e7c, data, tail15] - [0x80ebc, .rodata, ov_SC03_097_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x80edc, .rodata, ov_SC03_097_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80ef0, data, tail17] + - [0x80ef0, data, tail16] - [0x81080, .rodata, ov_SC03_097_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x81098, .rodata, ov_SC03_097_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8129c, data, tail18] + - [0x8129c, data, tail17] - [0x812a0, .rodata, ov_SC03_097_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8132c, data, tail19] + - [0x8132c, data, tail18] - [0x81330, .rodata, ov_SC03_097_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x81344, .rodata, ov_SC03_097_jr_8017D898] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x81364, data, tail20] + - [0x81364, data, tail19] - [0x82D74, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x82D77] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_098.yaml b/config/splat.ov_SC03_098.yaml index e56e832a67..45bd3b44b9 100644 --- a/config/splat.ov_SC03_098.yaml +++ b/config/splat.ov_SC03_098.yaml @@ -141,31 +141,30 @@ segments: - [0x9b800, .rodata, ov_SC03_098_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9b814, data, tail9] - [0x9b82c, .rodata, ov_SC03_098_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b898, data, tail10] - [0x9b908, .rodata, ov_SC03_098_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9b94c, .rodata, ov_SC03_098_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b994, data, tail11] + - [0x9b994, data, tail10] - [0x9b9f4, .rodata, ov_SC03_098_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ba28, data, tail12] + - [0x9ba28, data, tail11] - [0x9ba2c, .rodata, ov_SC03_098_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ba48, data, tail13] + - [0x9ba48, data, tail12] - [0x9ba4c, .rodata, ov_SC03_098_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ba88, data, tail14] + - [0x9ba88, data, tail13] - [0x9ba8c, .rodata, ov_SC03_098_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9baa8, data, tail15] + - [0x9baa8, data, tail14] - [0x9bac0, .rodata, ov_SC03_098_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9bb00, data, tail16] + - [0x9bb00, data, tail15] - [0x9bb40, .rodata, ov_SC03_098_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9bb60, .rodata, ov_SC03_098_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9bb74, data, tail17] + - [0x9bb74, data, tail16] - [0x9bd04, .rodata, ov_SC03_098_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9bd1c, .rodata, ov_SC03_098_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9bf20, data, tail18] + - [0x9bf20, data, tail17] - [0x9bf24, .rodata, ov_SC03_098_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9bfb0, data, tail19] + - [0x9bfb0, data, tail18] - [0x9bfb4, .rodata, ov_SC03_098_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9bfc8, .rodata, ov_SC03_098_jr_8017D898] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9bfe8, data, tail20] + - [0x9bfe8, data, tail19] - [0x9D75C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9D75F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_099.yaml b/config/splat.ov_SC03_099.yaml index 0f88433cd5..044da411cb 100644 --- a/config/splat.ov_SC03_099.yaml +++ b/config/splat.ov_SC03_099.yaml @@ -141,31 +141,30 @@ segments: - [0x954d4, .rodata, ov_SC03_099_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x954e8, data, tail9] - [0x95500, .rodata, ov_SC03_099_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9556c, data, tail10] - [0x955dc, .rodata, ov_SC03_099_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x95620, .rodata, ov_SC03_099_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x95668, data, tail11] + - [0x95668, data, tail10] - [0x956c8, .rodata, ov_SC03_099_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x956fc, data, tail12] + - [0x956fc, data, tail11] - [0x95700, .rodata, ov_SC03_099_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9571c, data, tail13] + - [0x9571c, data, tail12] - [0x95720, .rodata, ov_SC03_099_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9575c, data, tail14] + - [0x9575c, data, tail13] - [0x95760, .rodata, ov_SC03_099_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9577c, data, tail15] + - [0x9577c, data, tail14] - [0x95794, .rodata, ov_SC03_099_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x957d4, data, tail16] + - [0x957d4, data, tail15] - [0x95814, .rodata, ov_SC03_099_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x95834, .rodata, ov_SC03_099_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x95848, data, tail17] + - [0x95848, data, tail16] - [0x959d8, .rodata, ov_SC03_099_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x959f0, .rodata, ov_SC03_099_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x95bf4, data, tail18] + - [0x95bf4, data, tail17] - [0x95bf8, .rodata, ov_SC03_099_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x95c84, data, tail19] + - [0x95c84, data, tail18] - [0x95c88, .rodata, ov_SC03_099_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x95c9c, .rodata, ov_SC03_099_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x95cbc, data, tail20] + - [0x95cbc, data, tail19] - [0x97304, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x97307] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_100.yaml b/config/splat.ov_SC03_100.yaml index 4d6960da32..82896e1e36 100644 --- a/config/splat.ov_SC03_100.yaml +++ b/config/splat.ov_SC03_100.yaml @@ -141,31 +141,30 @@ segments: - [0x9e758, .rodata, ov_SC03_100_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9e76c, data, tail9] - [0x9e784, .rodata, ov_SC03_100_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9e7f0, data, tail10] - [0x9e860, .rodata, ov_SC03_100_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9e8a4, .rodata, ov_SC03_100_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9e8ec, data, tail11] + - [0x9e8ec, data, tail10] - [0x9e94c, .rodata, ov_SC03_100_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9e980, data, tail12] + - [0x9e980, data, tail11] - [0x9e984, .rodata, ov_SC03_100_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9e9a0, data, tail13] + - [0x9e9a0, data, tail12] - [0x9e9a4, .rodata, ov_SC03_100_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9e9e0, data, tail14] + - [0x9e9e0, data, tail13] - [0x9e9e4, .rodata, ov_SC03_100_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ea00, data, tail15] + - [0x9ea00, data, tail14] - [0x9ea18, .rodata, ov_SC03_100_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ea58, data, tail16] + - [0x9ea58, data, tail15] - [0x9ea98, .rodata, ov_SC03_100_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9eab8, .rodata, ov_SC03_100_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9eacc, data, tail17] + - [0x9eacc, data, tail16] - [0x9ec5c, .rodata, ov_SC03_100_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9ec74, .rodata, ov_SC03_100_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ee78, data, tail18] + - [0x9ee78, data, tail17] - [0x9ee7c, .rodata, ov_SC03_100_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ef08, data, tail19] + - [0x9ef08, data, tail18] - [0x9ef0c, .rodata, ov_SC03_100_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9ef20, .rodata, ov_SC03_100_jr_8017D898] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ef40, data, tail20] + - [0x9ef40, data, tail19] - [0xA080C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA080F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_101.yaml b/config/splat.ov_SC03_101.yaml index 062259c4df..c1cc2b06d3 100644 --- a/config/splat.ov_SC03_101.yaml +++ b/config/splat.ov_SC03_101.yaml @@ -141,31 +141,30 @@ segments: - [0x74020, .rodata, ov_SC03_101_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x74034, data, tail9] - [0x7404c, .rodata, ov_SC03_101_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x740b8, data, tail10] - [0x74128, .rodata, ov_SC03_101_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7416c, .rodata, ov_SC03_101_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x741b4, data, tail11] + - [0x741b4, data, tail10] - [0x74214, .rodata, ov_SC03_101_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74248, data, tail12] + - [0x74248, data, tail11] - [0x7424c, .rodata, ov_SC03_101_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74268, data, tail13] + - [0x74268, data, tail12] - [0x7426c, .rodata, ov_SC03_101_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x742a8, data, tail14] + - [0x742a8, data, tail13] - [0x742ac, .rodata, ov_SC03_101_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x742c8, data, tail15] + - [0x742c8, data, tail14] - [0x742e0, .rodata, ov_SC03_101_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74320, data, tail16] + - [0x74320, data, tail15] - [0x74360, .rodata, ov_SC03_101_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x74380, .rodata, ov_SC03_101_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74394, data, tail17] + - [0x74394, data, tail16] - [0x74524, .rodata, ov_SC03_101_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7453c, .rodata, ov_SC03_101_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74740, data, tail18] + - [0x74740, data, tail17] - [0x74744, .rodata, ov_SC03_101_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x747d0, data, tail19] + - [0x747d0, data, tail18] - [0x747d4, .rodata, ov_SC03_101_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x747e8, .rodata, ov_SC03_101_jr_8017CA80] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74808, data, tail20] + - [0x74808, data, tail19] - [0x760CC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x760CF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_102.yaml b/config/splat.ov_SC03_102.yaml index 3d1ae6c3e9..66b81c172d 100644 --- a/config/splat.ov_SC03_102.yaml +++ b/config/splat.ov_SC03_102.yaml @@ -141,31 +141,30 @@ segments: - [0x8fc9c, .rodata, ov_SC03_102_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8fcb0, data, tail9] - [0x8fcc8, .rodata, ov_SC03_102_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fd34, data, tail10] - [0x8fda4, .rodata, ov_SC03_102_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8fde8, .rodata, ov_SC03_102_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fe30, data, tail11] + - [0x8fe30, data, tail10] - [0x8fe90, .rodata, ov_SC03_102_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fec4, data, tail12] + - [0x8fec4, data, tail11] - [0x8fec8, .rodata, ov_SC03_102_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fee4, data, tail13] + - [0x8fee4, data, tail12] - [0x8fee8, .rodata, ov_SC03_102_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8ff24, data, tail14] + - [0x8ff24, data, tail13] - [0x8ff28, .rodata, ov_SC03_102_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8ff44, data, tail15] + - [0x8ff44, data, tail14] - [0x8ff5c, .rodata, ov_SC03_102_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8ff9c, data, tail16] + - [0x8ff9c, data, tail15] - [0x8ffdc, .rodata, ov_SC03_102_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8fffc, .rodata, ov_SC03_102_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90010, data, tail17] + - [0x90010, data, tail16] - [0x901a0, .rodata, ov_SC03_102_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x901b8, .rodata, ov_SC03_102_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x903bc, data, tail18] + - [0x903bc, data, tail17] - [0x903c0, .rodata, ov_SC03_102_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9044c, data, tail19] + - [0x9044c, data, tail18] - [0x90450, .rodata, ov_SC03_102_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x90464, .rodata, ov_SC03_102_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90484, data, tail20] + - [0x90484, data, tail19] - [0x91ACC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x91ACF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_103.yaml b/config/splat.ov_SC03_103.yaml index 83460e7549..7f6d81a4eb 100644 --- a/config/splat.ov_SC03_103.yaml +++ b/config/splat.ov_SC03_103.yaml @@ -141,31 +141,30 @@ segments: - [0x9ae50, .rodata, ov_SC03_103_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9ae64, data, tail9] - [0x9ae7c, .rodata, ov_SC03_103_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9aee8, data, tail10] - [0x9af58, .rodata, ov_SC03_103_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9af9c, .rodata, ov_SC03_103_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9afe4, data, tail11] + - [0x9afe4, data, tail10] - [0x9b044, .rodata, ov_SC03_103_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b078, data, tail12] + - [0x9b078, data, tail11] - [0x9b07c, .rodata, ov_SC03_103_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b098, data, tail13] + - [0x9b098, data, tail12] - [0x9b09c, .rodata, ov_SC03_103_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b0d8, data, tail14] + - [0x9b0d8, data, tail13] - [0x9b0dc, .rodata, ov_SC03_103_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b0f8, data, tail15] + - [0x9b0f8, data, tail14] - [0x9b110, .rodata, ov_SC03_103_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b150, data, tail16] + - [0x9b150, data, tail15] - [0x9b190, .rodata, ov_SC03_103_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9b1b0, .rodata, ov_SC03_103_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b1c4, data, tail17] + - [0x9b1c4, data, tail16] - [0x9b354, .rodata, ov_SC03_103_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9b36c, .rodata, ov_SC03_103_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b570, data, tail18] + - [0x9b570, data, tail17] - [0x9b574, .rodata, ov_SC03_103_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b600, data, tail19] + - [0x9b600, data, tail18] - [0x9b604, .rodata, ov_SC03_103_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9b618, .rodata, ov_SC03_103_jr_8017C294] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b638, data, tail20] + - [0x9b638, data, tail19] - [0x9CC7C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9CC7F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_104.yaml b/config/splat.ov_SC03_104.yaml index 66efac5652..029d860692 100644 --- a/config/splat.ov_SC03_104.yaml +++ b/config/splat.ov_SC03_104.yaml @@ -141,31 +141,30 @@ segments: - [0x963b0, .rodata, ov_SC03_104_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x963c4, data, tail9] - [0x963dc, .rodata, ov_SC03_104_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x96448, data, tail10] - [0x964b8, .rodata, ov_SC03_104_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x964fc, .rodata, ov_SC03_104_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x96544, data, tail11] + - [0x96544, data, tail10] - [0x965a4, .rodata, ov_SC03_104_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x965d8, data, tail12] + - [0x965d8, data, tail11] - [0x965dc, .rodata, ov_SC03_104_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x965f8, data, tail13] + - [0x965f8, data, tail12] - [0x965fc, .rodata, ov_SC03_104_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x96638, data, tail14] + - [0x96638, data, tail13] - [0x9663c, .rodata, ov_SC03_104_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x96658, data, tail15] + - [0x96658, data, tail14] - [0x96670, .rodata, ov_SC03_104_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x966b0, data, tail16] + - [0x966b0, data, tail15] - [0x966f0, .rodata, ov_SC03_104_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x96710, .rodata, ov_SC03_104_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x96724, data, tail17] + - [0x96724, data, tail16] - [0x968b4, .rodata, ov_SC03_104_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x968cc, .rodata, ov_SC03_104_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x96ad0, data, tail18] + - [0x96ad0, data, tail17] - [0x96ad4, .rodata, ov_SC03_104_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x96b60, data, tail19] + - [0x96b60, data, tail18] - [0x96b64, .rodata, ov_SC03_104_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x96b78, .rodata, ov_SC03_104_jr_8017CA80] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x96b98, data, tail20] + - [0x96b98, data, tail19] - [0x9833C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9833F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_105.yaml b/config/splat.ov_SC03_105.yaml index b90c994ca9..3ebc166bd5 100644 --- a/config/splat.ov_SC03_105.yaml +++ b/config/splat.ov_SC03_105.yaml @@ -141,32 +141,31 @@ segments: - [0x8f6a8, .rodata, ov_SC03_105_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f6bc, data, tail9] - [0x8f6d4, .rodata, ov_SC03_105_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f740, data, tail10] - [0x8f7b0, .rodata, ov_SC03_105_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f7f4, .rodata, ov_SC03_105_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f83c, data, tail11] + - [0x8f83c, data, tail10] - [0x8f89c, .rodata, ov_SC03_105_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f8d0, data, tail12] + - [0x8f8d0, data, tail11] - [0x8f8d4, .rodata, ov_SC03_105_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f8f0, data, tail13] + - [0x8f8f0, data, tail12] - [0x8f8f4, .rodata, ov_SC03_105_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f930, data, tail14] + - [0x8f930, data, tail13] - [0x8f934, .rodata, ov_SC03_105_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f950, data, tail15] + - [0x8f950, data, tail14] - [0x8f968, .rodata, ov_SC03_105_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f9a8, data, tail16] + - [0x8f9a8, data, tail15] - [0x8f9e8, .rodata, ov_SC03_105_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8fa08, .rodata, ov_SC03_105_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fa1c, data, tail17] + - [0x8fa1c, data, tail16] - [0x8fbac, .rodata, ov_SC03_105_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8fbc4, .rodata, ov_SC03_105_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fdc8, data, tail18] + - [0x8fdc8, data, tail17] - [0x8fdcc, .rodata, ov_SC03_105_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fe58, data, tail19] + - [0x8fe58, data, tail18] - [0x8fe5c, .rodata, ov_SC03_105_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fe70, data, tail20] + - [0x8fe70, data, tail19] - [0x8ffa8, .rodata, ov_SC03_105_jr_8017C8D0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8ffc8, data, tail21] + - [0x8ffc8, data, tail20] - [0x94BC4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x94BC7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_108.yaml b/config/splat.ov_SC03_108.yaml index dec293ddcb..b979af255b 100644 --- a/config/splat.ov_SC03_108.yaml +++ b/config/splat.ov_SC03_108.yaml @@ -141,31 +141,30 @@ segments: - [0x77bb0, .rodata, ov_SC03_108_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77bc4, data, tail9] - [0x77bdc, .rodata, ov_SC03_108_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77c48, data, tail10] - [0x77cb8, .rodata, ov_SC03_108_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77cfc, .rodata, ov_SC03_108_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77d44, data, tail11] + - [0x77d44, data, tail10] - [0x77da4, .rodata, ov_SC03_108_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77dd8, data, tail12] + - [0x77dd8, data, tail11] - [0x77ddc, .rodata, ov_SC03_108_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77df8, data, tail13] + - [0x77df8, data, tail12] - [0x77dfc, .rodata, ov_SC03_108_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77e38, data, tail14] + - [0x77e38, data, tail13] - [0x77e3c, .rodata, ov_SC03_108_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77e58, data, tail15] + - [0x77e58, data, tail14] - [0x77e70, .rodata, ov_SC03_108_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77e90, data, tail16] + - [0x77e90, data, tail15] - [0x77ef0, .rodata, ov_SC03_108_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77f10, .rodata, ov_SC03_108_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77f24, data, tail17] + - [0x77f24, data, tail16] - [0x780b4, .rodata, ov_SC03_108_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x780cc, .rodata, ov_SC03_108_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x782d0, data, tail18] + - [0x782d0, data, tail17] - [0x782d4, .rodata, ov_SC03_108_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78360, data, tail19] + - [0x78360, data, tail18] - [0x78364, .rodata, ov_SC03_108_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78378, .rodata, ov_SC03_108_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78398, data, tail20] + - [0x78398, data, tail19] - [0x7994C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x7994F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_109.yaml b/config/splat.ov_SC03_109.yaml index e497e010d4..75fa2d4a0a 100644 --- a/config/splat.ov_SC03_109.yaml +++ b/config/splat.ov_SC03_109.yaml @@ -141,31 +141,30 @@ segments: - [0x706c0, .rodata, ov_SC03_109_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x706d4, data, tail9] - [0x706ec, .rodata, ov_SC03_109_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70758, data, tail10] - [0x707c8, .rodata, ov_SC03_109_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7080c, .rodata, ov_SC03_109_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70854, data, tail11] + - [0x70854, data, tail10] - [0x708b4, .rodata, ov_SC03_109_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x708e8, data, tail12] + - [0x708e8, data, tail11] - [0x708ec, .rodata, ov_SC03_109_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70908, data, tail13] + - [0x70908, data, tail12] - [0x7090c, .rodata, ov_SC03_109_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70948, data, tail14] + - [0x70948, data, tail13] - [0x7094c, .rodata, ov_SC03_109_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70968, data, tail15] + - [0x70968, data, tail14] - [0x70980, .rodata, ov_SC03_109_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x709c0, data, tail16] + - [0x709c0, data, tail15] - [0x70a00, .rodata, ov_SC03_109_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70a20, .rodata, ov_SC03_109_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70a34, data, tail17] + - [0x70a34, data, tail16] - [0x70bc4, .rodata, ov_SC03_109_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70bdc, .rodata, ov_SC03_109_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70de0, data, tail18] + - [0x70de0, data, tail17] - [0x70de4, .rodata, ov_SC03_109_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70e70, data, tail19] + - [0x70e70, data, tail18] - [0x70e74, .rodata, ov_SC03_109_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70e88, .rodata, ov_SC03_109_jr_8017C180] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70ea8, data, tail20] + - [0x70ea8, data, tail19] - [0x72354, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x72357] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_110.yaml b/config/splat.ov_SC03_110.yaml index 0660e8d0b9..ac3a16febf 100644 --- a/config/splat.ov_SC03_110.yaml +++ b/config/splat.ov_SC03_110.yaml @@ -141,31 +141,30 @@ segments: - [0x7835c, .rodata, ov_SC03_110_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78370, data, tail9] - [0x78388, .rodata, ov_SC03_110_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x783f4, data, tail10] - [0x78464, .rodata, ov_SC03_110_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x784a8, .rodata, ov_SC03_110_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x784f0, data, tail11] + - [0x784f0, data, tail10] - [0x78550, .rodata, ov_SC03_110_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78584, data, tail12] + - [0x78584, data, tail11] - [0x78588, .rodata, ov_SC03_110_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x785a4, data, tail13] + - [0x785a4, data, tail12] - [0x785a8, .rodata, ov_SC03_110_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x785e4, data, tail14] + - [0x785e4, data, tail13] - [0x785e8, .rodata, ov_SC03_110_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78604, data, tail15] + - [0x78604, data, tail14] - [0x7861c, .rodata, ov_SC03_110_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7865c, data, tail16] + - [0x7865c, data, tail15] - [0x7869c, .rodata, ov_SC03_110_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x786bc, .rodata, ov_SC03_110_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x786d0, data, tail17] + - [0x786d0, data, tail16] - [0x78860, .rodata, ov_SC03_110_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78878, .rodata, ov_SC03_110_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78a7c, data, tail18] + - [0x78a7c, data, tail17] - [0x78a80, .rodata, ov_SC03_110_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78b0c, data, tail19] + - [0x78b0c, data, tail18] - [0x78b10, .rodata, ov_SC03_110_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78b24, .rodata, ov_SC03_110_jr_8017D898] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78b44, data, tail20] + - [0x78b44, data, tail19] - [0x7A384, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x7A387] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_111.yaml b/config/splat.ov_SC03_111.yaml index 6a7cff0283..9c60ecd212 100644 --- a/config/splat.ov_SC03_111.yaml +++ b/config/splat.ov_SC03_111.yaml @@ -141,31 +141,30 @@ segments: - [0x8f8dc, .rodata, ov_SC03_111_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f8f0, data, tail9] - [0x8f908, .rodata, ov_SC03_111_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f974, data, tail10] - [0x8f9e4, .rodata, ov_SC03_111_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8fa28, .rodata, ov_SC03_111_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fa70, data, tail11] + - [0x8fa70, data, tail10] - [0x8fad0, .rodata, ov_SC03_111_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fb04, data, tail12] + - [0x8fb04, data, tail11] - [0x8fb08, .rodata, ov_SC03_111_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fb24, data, tail13] + - [0x8fb24, data, tail12] - [0x8fb28, .rodata, ov_SC03_111_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fb64, data, tail14] + - [0x8fb64, data, tail13] - [0x8fb68, .rodata, ov_SC03_111_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fb84, data, tail15] + - [0x8fb84, data, tail14] - [0x8fb9c, .rodata, ov_SC03_111_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fbdc, data, tail16] + - [0x8fbdc, data, tail15] - [0x8fc1c, .rodata, ov_SC03_111_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8fc3c, .rodata, ov_SC03_111_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fc50, data, tail17] + - [0x8fc50, data, tail16] - [0x8fde0, .rodata, ov_SC03_111_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8fdf8, .rodata, ov_SC03_111_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fffc, data, tail18] + - [0x8fffc, data, tail17] - [0x90000, .rodata, ov_SC03_111_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9008c, data, tail19] + - [0x9008c, data, tail18] - [0x90090, .rodata, ov_SC03_111_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x900a4, .rodata, ov_SC03_111_jr_8017EC58] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x900c4, data, tail20] + - [0x900c4, data, tail19] - [0x91A2C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x91A2F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_112.yaml b/config/splat.ov_SC03_112.yaml index 4c2ed42ba8..376a822987 100644 --- a/config/splat.ov_SC03_112.yaml +++ b/config/splat.ov_SC03_112.yaml @@ -141,31 +141,30 @@ segments: - [0x83044, .rodata, ov_SC03_112_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x83058, data, tail9] - [0x83070, .rodata, ov_SC03_112_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x830dc, data, tail10] - [0x8314c, .rodata, ov_SC03_112_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x83190, .rodata, ov_SC03_112_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x831d8, data, tail11] + - [0x831d8, data, tail10] - [0x83238, .rodata, ov_SC03_112_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8326c, data, tail12] + - [0x8326c, data, tail11] - [0x83270, .rodata, ov_SC03_112_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8328c, data, tail13] + - [0x8328c, data, tail12] - [0x83290, .rodata, ov_SC03_112_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x832cc, data, tail14] + - [0x832cc, data, tail13] - [0x832d0, .rodata, ov_SC03_112_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x832ec, data, tail15] + - [0x832ec, data, tail14] - [0x83304, .rodata, ov_SC03_112_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83344, data, tail16] + - [0x83344, data, tail15] - [0x83384, .rodata, ov_SC03_112_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x833a4, .rodata, ov_SC03_112_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x833b8, data, tail17] + - [0x833b8, data, tail16] - [0x83548, .rodata, ov_SC03_112_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x83560, .rodata, ov_SC03_112_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83764, data, tail18] + - [0x83764, data, tail17] - [0x83768, .rodata, ov_SC03_112_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x837f4, data, tail19] + - [0x837f4, data, tail18] - [0x837f8, .rodata, ov_SC03_112_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8380c, .rodata, ov_SC03_112_jr_8017C294] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8382c, data, tail20] + - [0x8382c, data, tail19] - [0x84FF4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x84FF7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_113.yaml b/config/splat.ov_SC03_113.yaml index 36e65449e6..7836c5cc4b 100644 --- a/config/splat.ov_SC03_113.yaml +++ b/config/splat.ov_SC03_113.yaml @@ -141,31 +141,30 @@ segments: - [0x7bccc, .rodata, ov_SC03_113_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7bce0, data, tail9] - [0x7bcf8, .rodata, ov_SC03_113_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bd64, data, tail10] - [0x7bdd4, .rodata, ov_SC03_113_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7be18, .rodata, ov_SC03_113_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7be60, data, tail11] + - [0x7be60, data, tail10] - [0x7bec0, .rodata, ov_SC03_113_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bef4, data, tail12] + - [0x7bef4, data, tail11] - [0x7bef8, .rodata, ov_SC03_113_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bf14, data, tail13] + - [0x7bf14, data, tail12] - [0x7bf18, .rodata, ov_SC03_113_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bf54, data, tail14] + - [0x7bf54, data, tail13] - [0x7bf58, .rodata, ov_SC03_113_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bf74, data, tail15] + - [0x7bf74, data, tail14] - [0x7bf8c, .rodata, ov_SC03_113_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7bfcc, data, tail16] + - [0x7bfcc, data, tail15] - [0x7c00c, .rodata, ov_SC03_113_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7c02c, .rodata, ov_SC03_113_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7c040, data, tail17] + - [0x7c040, data, tail16] - [0x7c1d0, .rodata, ov_SC03_113_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7c1e8, .rodata, ov_SC03_113_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7c3ec, data, tail18] + - [0x7c3ec, data, tail17] - [0x7c3f0, .rodata, ov_SC03_113_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7c47c, data, tail19] + - [0x7c47c, data, tail18] - [0x7c480, .rodata, ov_SC03_113_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7c494, .rodata, ov_SC03_113_jr_8017C294] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7c4b4, data, tail20] + - [0x7c4b4, data, tail19] - [0x7DB94, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x7DB97] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_114.yaml b/config/splat.ov_SC03_114.yaml index 28c96d5b87..aa969fca9f 100644 --- a/config/splat.ov_SC03_114.yaml +++ b/config/splat.ov_SC03_114.yaml @@ -141,31 +141,30 @@ segments: - [0x7f9d8, .rodata, ov_SC03_114_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7f9ec, data, tail9] - [0x7fa04, .rodata, ov_SC03_114_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7fa70, data, tail10] - [0x7fae0, .rodata, ov_SC03_114_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7fb24, .rodata, ov_SC03_114_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7fb6c, data, tail11] + - [0x7fb6c, data, tail10] - [0x7fbcc, .rodata, ov_SC03_114_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7fc00, data, tail12] + - [0x7fc00, data, tail11] - [0x7fc04, .rodata, ov_SC03_114_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7fc20, data, tail13] + - [0x7fc20, data, tail12] - [0x7fc24, .rodata, ov_SC03_114_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7fc60, data, tail14] + - [0x7fc60, data, tail13] - [0x7fc64, .rodata, ov_SC03_114_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7fc80, data, tail15] + - [0x7fc80, data, tail14] - [0x7fc98, .rodata, ov_SC03_114_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7fcd8, data, tail16] + - [0x7fcd8, data, tail15] - [0x7fd18, .rodata, ov_SC03_114_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7fd38, .rodata, ov_SC03_114_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7fd4c, data, tail17] + - [0x7fd4c, data, tail16] - [0x7fedc, .rodata, ov_SC03_114_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7fef4, .rodata, ov_SC03_114_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x800f8, data, tail18] + - [0x800f8, data, tail17] - [0x800fc, .rodata, ov_SC03_114_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80188, data, tail19] + - [0x80188, data, tail18] - [0x8018c, .rodata, ov_SC03_114_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x801a0, .rodata, ov_SC03_114_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x801c0, data, tail20] + - [0x801c0, data, tail19] - [0x8170C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x8170F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_115.yaml b/config/splat.ov_SC03_115.yaml index ddb2938d25..97d9d1293c 100644 --- a/config/splat.ov_SC03_115.yaml +++ b/config/splat.ov_SC03_115.yaml @@ -141,31 +141,30 @@ segments: - [0x6b34c, .rodata, ov_SC03_115_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b360, data, tail9] - [0x6b378, .rodata, ov_SC03_115_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b3e4, data, tail10] - [0x6b454, .rodata, ov_SC03_115_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b498, .rodata, ov_SC03_115_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b4e0, data, tail11] + - [0x6b4e0, data, tail10] - [0x6b540, .rodata, ov_SC03_115_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b574, data, tail12] + - [0x6b574, data, tail11] - [0x6b578, .rodata, ov_SC03_115_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b594, data, tail13] + - [0x6b594, data, tail12] - [0x6b598, .rodata, ov_SC03_115_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b5d4, data, tail14] + - [0x6b5d4, data, tail13] - [0x6b5d8, .rodata, ov_SC03_115_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b5f4, data, tail15] + - [0x6b5f4, data, tail14] - [0x6b60c, .rodata, ov_SC03_115_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b64c, data, tail16] + - [0x6b64c, data, tail15] - [0x6b68c, .rodata, ov_SC03_115_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b6ac, .rodata, ov_SC03_115_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b6c0, data, tail17] + - [0x6b6c0, data, tail16] - [0x6b850, .rodata, ov_SC03_115_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b868, .rodata, ov_SC03_115_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6ba6c, data, tail18] + - [0x6ba6c, data, tail17] - [0x6ba70, .rodata, ov_SC03_115_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6bafc, data, tail19] + - [0x6bafc, data, tail18] - [0x6bb00, .rodata, ov_SC03_115_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6bb14, .rodata, ov_SC03_115_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6bb34, data, tail20] + - [0x6bb34, data, tail19] - [0x6CFE4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x6CFE7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_116.yaml b/config/splat.ov_SC03_116.yaml index 7031dca0df..4331ebb0ca 100644 --- a/config/splat.ov_SC03_116.yaml +++ b/config/splat.ov_SC03_116.yaml @@ -140,30 +140,29 @@ segments: - [0x6dee8, .rodata, ov_SC03_116_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6defc, data, tail9] - [0x6df14, .rodata, ov_SC03_116_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6df80, data, tail10] - [0x6dff0, .rodata, ov_SC03_116_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6e034, .rodata, ov_SC03_116_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e07c, data, tail11] + - [0x6e07c, data, tail10] - [0x6e0dc, .rodata, ov_SC03_116_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e110, data, tail12] + - [0x6e110, data, tail11] - [0x6e114, .rodata, ov_SC03_116_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e130, data, tail13] + - [0x6e130, data, tail12] - [0x6e134, .rodata, ov_SC03_116_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e170, data, tail14] + - [0x6e170, data, tail13] - [0x6e174, .rodata, ov_SC03_116_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e190, data, tail15] + - [0x6e190, data, tail14] - [0x6e1a8, .rodata, ov_SC03_116_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e1e8, data, tail16] + - [0x6e1e8, data, tail15] - [0x6e228, .rodata, ov_SC03_116_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6e248, .rodata, ov_SC03_116_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e25c, data, tail17] + - [0x6e25c, data, tail16] - [0x6e3ec, .rodata, ov_SC03_116_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6e404, .rodata, ov_SC03_116_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e608, data, tail18] + - [0x6e608, data, tail17] - [0x6e60c, .rodata, ov_SC03_116_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e698, data, tail19] + - [0x6e698, data, tail18] - [0x6e69c, .rodata, ov_SC03_116_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e6b0, data, tail20] + - [0x6e6b0, data, tail19] - [0x6FBF4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x6FBF7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_117.yaml b/config/splat.ov_SC03_117.yaml index 40e9ef85aa..c036323b58 100644 --- a/config/splat.ov_SC03_117.yaml +++ b/config/splat.ov_SC03_117.yaml @@ -141,31 +141,30 @@ segments: - [0xa4588, .rodata, ov_SC03_117_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa459c, data, tail9] - [0xa45b4, .rodata, ov_SC03_117_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa4620, data, tail10] - [0xa4690, .rodata, ov_SC03_117_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa46d4, .rodata, ov_SC03_117_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa471c, data, tail11] + - [0xa471c, data, tail10] - [0xa477c, .rodata, ov_SC03_117_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa47b0, data, tail12] + - [0xa47b0, data, tail11] - [0xa47b4, .rodata, ov_SC03_117_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa47d0, data, tail13] + - [0xa47d0, data, tail12] - [0xa47d4, .rodata, ov_SC03_117_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa4810, data, tail14] + - [0xa4810, data, tail13] - [0xa4814, .rodata, ov_SC03_117_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa4830, data, tail15] + - [0xa4830, data, tail14] - [0xa4848, .rodata, ov_SC03_117_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa4888, data, tail16] + - [0xa4888, data, tail15] - [0xa48c8, .rodata, ov_SC03_117_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa48e8, .rodata, ov_SC03_117_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa48fc, data, tail17] + - [0xa48fc, data, tail16] - [0xa4a8c, .rodata, ov_SC03_117_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa4aa4, .rodata, ov_SC03_117_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa4ca8, data, tail18] + - [0xa4ca8, data, tail17] - [0xa4cac, .rodata, ov_SC03_117_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa4d38, data, tail19] + - [0xa4d38, data, tail18] - [0xa4d3c, .rodata, ov_SC03_117_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa4d50, .rodata, ov_SC03_117_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa4d70, data, tail20] + - [0xa4d70, data, tail19] - [0xA67EC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA67EF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_118.yaml b/config/splat.ov_SC03_118.yaml index 00cc0f48c1..082090566e 100644 --- a/config/splat.ov_SC03_118.yaml +++ b/config/splat.ov_SC03_118.yaml @@ -141,32 +141,31 @@ segments: - [0xaa4e4, .rodata, ov_SC03_118_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaa4f8, data, tail9] - [0xaa510, .rodata, ov_SC03_118_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa57c, data, tail10] - [0xaa5ec, .rodata, ov_SC03_118_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaa630, .rodata, ov_SC03_118_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa678, data, tail11] + - [0xaa678, data, tail10] - [0xaa6d8, .rodata, ov_SC03_118_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa70c, data, tail12] + - [0xaa70c, data, tail11] - [0xaa710, .rodata, ov_SC03_118_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa72c, data, tail13] + - [0xaa72c, data, tail12] - [0xaa730, .rodata, ov_SC03_118_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa76c, data, tail14] + - [0xaa76c, data, tail13] - [0xaa770, .rodata, ov_SC03_118_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa78c, data, tail15] + - [0xaa78c, data, tail14] - [0xaa7a4, .rodata, ov_SC03_118_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa7e4, data, tail16] + - [0xaa7e4, data, tail15] - [0xaa824, .rodata, ov_SC03_118_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaa844, .rodata, ov_SC03_118_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa858, data, tail17] + - [0xaa858, data, tail16] - [0xaa9e8, .rodata, ov_SC03_118_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaaa00, .rodata, ov_SC03_118_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaac04, data, tail18] + - [0xaac04, data, tail17] - [0xaac08, .rodata, ov_SC03_118_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaac94, data, tail19] + - [0xaac94, data, tail18] - [0xaac98, .rodata, ov_SC03_118_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaacac, data, tail20] + - [0xaacac, data, tail19] - [0xaacd8, .rodata, ov_SC03_118_jr_8017FB84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaacf8, data, tail21] + - [0xaacf8, data, tail20] - [0xAC6F4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xAC6F7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_119.yaml b/config/splat.ov_SC03_119.yaml index edc8bc5b54..f899b6d08a 100644 --- a/config/splat.ov_SC03_119.yaml +++ b/config/splat.ov_SC03_119.yaml @@ -141,32 +141,31 @@ segments: - [0xaa4e4, .rodata, ov_SC03_119_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaa4f8, data, tail9] - [0xaa510, .rodata, ov_SC03_119_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa57c, data, tail10] - [0xaa5ec, .rodata, ov_SC03_119_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaa630, .rodata, ov_SC03_119_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa678, data, tail11] + - [0xaa678, data, tail10] - [0xaa6d8, .rodata, ov_SC03_119_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa70c, data, tail12] + - [0xaa70c, data, tail11] - [0xaa710, .rodata, ov_SC03_119_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa72c, data, tail13] + - [0xaa72c, data, tail12] - [0xaa730, .rodata, ov_SC03_119_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa76c, data, tail14] + - [0xaa76c, data, tail13] - [0xaa770, .rodata, ov_SC03_119_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa78c, data, tail15] + - [0xaa78c, data, tail14] - [0xaa7a4, .rodata, ov_SC03_119_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa7e4, data, tail16] + - [0xaa7e4, data, tail15] - [0xaa824, .rodata, ov_SC03_119_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaa844, .rodata, ov_SC03_119_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaa858, data, tail17] + - [0xaa858, data, tail16] - [0xaa9e8, .rodata, ov_SC03_119_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaaa00, .rodata, ov_SC03_119_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaac04, data, tail18] + - [0xaac04, data, tail17] - [0xaac08, .rodata, ov_SC03_119_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaac94, data, tail19] + - [0xaac94, data, tail18] - [0xaac98, .rodata, ov_SC03_119_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaacac, data, tail20] + - [0xaacac, data, tail19] - [0xaacd8, .rodata, ov_SC03_119_jr_8017FB84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaacf8, data, tail21] + - [0xaacf8, data, tail20] - [0xAC6F4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xAC6F7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_121.yaml b/config/splat.ov_SC03_121.yaml index ccf4390bf7..a57ae1e004 100644 --- a/config/splat.ov_SC03_121.yaml +++ b/config/splat.ov_SC03_121.yaml @@ -141,31 +141,30 @@ segments: - [0x84fec, .rodata, ov_SC03_121_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x85000, data, tail9] - [0x85018, .rodata, ov_SC03_121_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x85084, data, tail10] - [0x850f4, .rodata, ov_SC03_121_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x85138, .rodata, ov_SC03_121_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x85180, data, tail11] + - [0x85180, data, tail10] - [0x851e0, .rodata, ov_SC03_121_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x85214, data, tail12] + - [0x85214, data, tail11] - [0x85218, .rodata, ov_SC03_121_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x85234, data, tail13] + - [0x85234, data, tail12] - [0x85238, .rodata, ov_SC03_121_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x85274, data, tail14] + - [0x85274, data, tail13] - [0x85278, .rodata, ov_SC03_121_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x85294, data, tail15] + - [0x85294, data, tail14] - [0x852ac, .rodata, ov_SC03_121_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x852ec, data, tail16] + - [0x852ec, data, tail15] - [0x8532c, .rodata, ov_SC03_121_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8534c, .rodata, ov_SC03_121_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x85360, data, tail17] + - [0x85360, data, tail16] - [0x854f0, .rodata, ov_SC03_121_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x85508, .rodata, ov_SC03_121_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8570c, data, tail18] + - [0x8570c, data, tail17] - [0x85710, .rodata, ov_SC03_121_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8579c, data, tail19] + - [0x8579c, data, tail18] - [0x857a0, .rodata, ov_SC03_121_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x857b4, .rodata, ov_SC03_121_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x857d4, data, tail20] + - [0x857d4, data, tail19] - [0x86E54, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x86E57] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_124.yaml b/config/splat.ov_SC03_124.yaml index 8023489691..9a118b91e3 100644 --- a/config/splat.ov_SC03_124.yaml +++ b/config/splat.ov_SC03_124.yaml @@ -140,30 +140,29 @@ segments: - [0xb7740, .rodata, ov_SC03_124_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7754, data, tail9] - [0xb776c, .rodata, ov_SC03_124_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb77d8, data, tail10] - [0xb7848, .rodata, ov_SC03_124_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb788c, .rodata, ov_SC03_124_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb78d4, data, tail11] + - [0xb78d4, data, tail10] - [0xb7934, .rodata, ov_SC03_124_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7968, data, tail12] + - [0xb7968, data, tail11] - [0xb796c, .rodata, ov_SC03_124_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7988, data, tail13] + - [0xb7988, data, tail12] - [0xb798c, .rodata, ov_SC03_124_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb79c8, data, tail14] + - [0xb79c8, data, tail13] - [0xb79cc, .rodata, ov_SC03_124_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb79e8, data, tail15] + - [0xb79e8, data, tail14] - [0xb7a00, .rodata, ov_SC03_124_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7a40, data, tail16] + - [0xb7a40, data, tail15] - [0xb7a80, .rodata, ov_SC03_124_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7aa0, .rodata, ov_SC03_124_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7ab4, data, tail17] + - [0xb7ab4, data, tail16] - [0xb7c44, .rodata, ov_SC03_124_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7c5c, .rodata, ov_SC03_124_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7e60, data, tail18] + - [0xb7e60, data, tail17] - [0xb7e64, .rodata, ov_SC03_124_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7ef0, data, tail19] + - [0xb7ef0, data, tail18] - [0xb7ef4, .rodata, ov_SC03_124_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7f28, data, tail20] + - [0xb7f28, data, tail19] - [0xBA48C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xBA48F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_125.yaml b/config/splat.ov_SC03_125.yaml index e3c8ad6d00..2cfe29bc07 100644 --- a/config/splat.ov_SC03_125.yaml +++ b/config/splat.ov_SC03_125.yaml @@ -141,31 +141,30 @@ segments: - [0x9a42c, .rodata, ov_SC03_125_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9a440, data, tail9] - [0x9a458, .rodata, ov_SC03_125_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9a4c4, data, tail10] - [0x9a534, .rodata, ov_SC03_125_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9a578, .rodata, ov_SC03_125_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9a5c0, data, tail11] + - [0x9a5c0, data, tail10] - [0x9a620, .rodata, ov_SC03_125_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9a654, data, tail12] + - [0x9a654, data, tail11] - [0x9a658, .rodata, ov_SC03_125_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9a674, data, tail13] + - [0x9a674, data, tail12] - [0x9a678, .rodata, ov_SC03_125_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9a6b4, data, tail14] + - [0x9a6b4, data, tail13] - [0x9a6b8, .rodata, ov_SC03_125_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9a6d4, data, tail15] + - [0x9a6d4, data, tail14] - [0x9a6ec, .rodata, ov_SC03_125_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9a72c, data, tail16] + - [0x9a72c, data, tail15] - [0x9a76c, .rodata, ov_SC03_125_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9a78c, .rodata, ov_SC03_125_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9a7a0, data, tail17] + - [0x9a7a0, data, tail16] - [0x9a930, .rodata, ov_SC03_125_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9a948, .rodata, ov_SC03_125_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ab4c, data, tail18] + - [0x9ab4c, data, tail17] - [0x9ab50, .rodata, ov_SC03_125_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9abdc, data, tail19] + - [0x9abdc, data, tail18] - [0x9abe0, .rodata, ov_SC03_125_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9abf4, .rodata, ov_SC03_125_jr_8017D604] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ac14, data, tail20] + - [0x9ac14, data, tail19] - [0x9C3E4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9C3E7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_126.yaml b/config/splat.ov_SC03_126.yaml index 43d15dd9ad..b5ab2404ef 100644 --- a/config/splat.ov_SC03_126.yaml +++ b/config/splat.ov_SC03_126.yaml @@ -141,32 +141,31 @@ segments: - [0x65d18, .rodata, ov_SC03_126_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65d2c, data, tail9] - [0x65d44, .rodata, ov_SC03_126_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65db0, data, tail10] - [0x65e20, .rodata, ov_SC03_126_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65e64, .rodata, ov_SC03_126_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65eac, data, tail11] + - [0x65eac, data, tail10] - [0x65f0c, .rodata, ov_SC03_126_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65f40, data, tail12] + - [0x65f40, data, tail11] - [0x65f44, .rodata, ov_SC03_126_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65f60, data, tail13] + - [0x65f60, data, tail12] - [0x65f64, .rodata, ov_SC03_126_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65fa0, data, tail14] + - [0x65fa0, data, tail13] - [0x65fa4, .rodata, ov_SC03_126_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65fc0, data, tail15] + - [0x65fc0, data, tail14] - [0x65fd8, .rodata, ov_SC03_126_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66018, data, tail16] + - [0x66018, data, tail15] - [0x66058, .rodata, ov_SC03_126_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66078, .rodata, ov_SC03_126_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6608c, data, tail17] + - [0x6608c, data, tail16] - [0x6621c, .rodata, ov_SC03_126_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66234, .rodata, ov_SC03_126_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66438, data, tail18] + - [0x66438, data, tail17] - [0x6643c, .rodata, ov_SC03_126_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x664c8, data, tail19] + - [0x664c8, data, tail18] - [0x664cc, .rodata, ov_SC03_126_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x664e0, data, tail20] + - [0x664e0, data, tail19] - [0x66500, .rodata, ov_SC03_126_jr_8017D5C0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66520, data, tail21] + - [0x66520, data, tail20] - [0x679D4, bin, trailing] # final 1 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x679D5] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_000.yaml b/config/splat.ov_SC04_000.yaml index 13c908a2f8..15ada41b28 100644 --- a/config/splat.ov_SC04_000.yaml +++ b/config/splat.ov_SC04_000.yaml @@ -141,31 +141,30 @@ segments: - [0x7fd94, .rodata, ov_SC04_000_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7fda8, data, tail9] - [0x7fdc0, .rodata, ov_SC04_000_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7fe2c, data, tail10] - [0x7fe9c, .rodata, ov_SC04_000_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7fee0, .rodata, ov_SC04_000_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7ff28, data, tail11] + - [0x7ff28, data, tail10] - [0x7ff88, .rodata, ov_SC04_000_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7ffbc, data, tail12] + - [0x7ffbc, data, tail11] - [0x7ffc0, .rodata, ov_SC04_000_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7ffdc, data, tail13] + - [0x7ffdc, data, tail12] - [0x7ffe0, .rodata, ov_SC04_000_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8001c, data, tail14] + - [0x8001c, data, tail13] - [0x80020, .rodata, ov_SC04_000_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8003c, data, tail15] + - [0x8003c, data, tail14] - [0x80054, .rodata, ov_SC04_000_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80094, data, tail16] + - [0x80094, data, tail15] - [0x800d4, .rodata, ov_SC04_000_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x800f4, .rodata, ov_SC04_000_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80108, data, tail17] + - [0x80108, data, tail16] - [0x80298, .rodata, ov_SC04_000_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x802b0, .rodata, ov_SC04_000_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x804b4, data, tail18] + - [0x804b4, data, tail17] - [0x804b8, .rodata, ov_SC04_000_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80544, data, tail19] + - [0x80544, data, tail18] - [0x80548, .rodata, ov_SC04_000_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8055c, .rodata, ov_SC04_000_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8057c, data, tail20] + - [0x8057c, data, tail19] - [0x82EFC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x82EFF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_002.yaml b/config/splat.ov_SC04_002.yaml index 297c5c6743..b8d50fa522 100644 --- a/config/splat.ov_SC04_002.yaml +++ b/config/splat.ov_SC04_002.yaml @@ -141,31 +141,30 @@ segments: - [0x970e4, .rodata, ov_SC04_002_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x970f8, data, tail9] - [0x97110, .rodata, ov_SC04_002_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9717c, data, tail10] - [0x971ec, .rodata, ov_SC04_002_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x97230, .rodata, ov_SC04_002_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97278, data, tail11] + - [0x97278, data, tail10] - [0x972d8, .rodata, ov_SC04_002_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9730c, data, tail12] + - [0x9730c, data, tail11] - [0x97310, .rodata, ov_SC04_002_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9732c, data, tail13] + - [0x9732c, data, tail12] - [0x97330, .rodata, ov_SC04_002_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9736c, data, tail14] + - [0x9736c, data, tail13] - [0x97370, .rodata, ov_SC04_002_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9738c, data, tail15] + - [0x9738c, data, tail14] - [0x973a4, .rodata, ov_SC04_002_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x973e4, data, tail16] + - [0x973e4, data, tail15] - [0x97424, .rodata, ov_SC04_002_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x97444, .rodata, ov_SC04_002_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97458, data, tail17] + - [0x97458, data, tail16] - [0x975e8, .rodata, ov_SC04_002_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x97600, .rodata, ov_SC04_002_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97804, data, tail18] + - [0x97804, data, tail17] - [0x97808, .rodata, ov_SC04_002_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97894, data, tail19] + - [0x97894, data, tail18] - [0x97898, .rodata, ov_SC04_002_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x978ac, .rodata, ov_SC04_002_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x978cc, data, tail20] + - [0x978cc, data, tail19] - [0x995DC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x995DF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_003.yaml b/config/splat.ov_SC04_003.yaml index d831398567..a64b8e1427 100644 --- a/config/splat.ov_SC04_003.yaml +++ b/config/splat.ov_SC04_003.yaml @@ -141,31 +141,30 @@ segments: - [0x71d60, .rodata, ov_SC04_003_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71d74, data, tail9] - [0x71d8c, .rodata, ov_SC04_003_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71df8, data, tail10] - [0x71e68, .rodata, ov_SC04_003_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71eac, .rodata, ov_SC04_003_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71ef4, data, tail11] + - [0x71ef4, data, tail10] - [0x71f54, .rodata, ov_SC04_003_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71f88, data, tail12] + - [0x71f88, data, tail11] - [0x71f8c, .rodata, ov_SC04_003_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71fa8, data, tail13] + - [0x71fa8, data, tail12] - [0x71fac, .rodata, ov_SC04_003_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71fe8, data, tail14] + - [0x71fe8, data, tail13] - [0x71fec, .rodata, ov_SC04_003_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72008, data, tail15] + - [0x72008, data, tail14] - [0x72020, .rodata, ov_SC04_003_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72060, data, tail16] + - [0x72060, data, tail15] - [0x720a0, .rodata, ov_SC04_003_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x720c0, .rodata, ov_SC04_003_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x720d4, data, tail17] + - [0x720d4, data, tail16] - [0x72264, .rodata, ov_SC04_003_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7227c, .rodata, ov_SC04_003_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72480, data, tail18] + - [0x72480, data, tail17] - [0x72484, .rodata, ov_SC04_003_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72510, data, tail19] + - [0x72510, data, tail18] - [0x72514, .rodata, ov_SC04_003_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x72528, .rodata, ov_SC04_003_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72548, data, tail20] + - [0x72548, data, tail19] - [0x73A94, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x73A97] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_004.yaml b/config/splat.ov_SC04_004.yaml index 278fa185a5..413e883cd1 100644 --- a/config/splat.ov_SC04_004.yaml +++ b/config/splat.ov_SC04_004.yaml @@ -140,30 +140,29 @@ segments: - [0x89b5c, .rodata, ov_SC04_004_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x89b70, data, tail9] - [0x89b88, .rodata, ov_SC04_004_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89bf4, data, tail10] - [0x89c64, .rodata, ov_SC04_004_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x89ca8, .rodata, ov_SC04_004_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89cf0, data, tail11] + - [0x89cf0, data, tail10] - [0x89d50, .rodata, ov_SC04_004_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89d84, data, tail12] + - [0x89d84, data, tail11] - [0x89d88, .rodata, ov_SC04_004_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89da4, data, tail13] + - [0x89da4, data, tail12] - [0x89da8, .rodata, ov_SC04_004_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89de4, data, tail14] + - [0x89de4, data, tail13] - [0x89de8, .rodata, ov_SC04_004_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89e04, data, tail15] + - [0x89e04, data, tail14] - [0x89e1c, .rodata, ov_SC04_004_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89e5c, data, tail16] + - [0x89e5c, data, tail15] - [0x89e9c, .rodata, ov_SC04_004_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x89ebc, .rodata, ov_SC04_004_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89ed0, data, tail17] + - [0x89ed0, data, tail16] - [0x8a060, .rodata, ov_SC04_004_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8a078, .rodata, ov_SC04_004_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a27c, data, tail18] + - [0x8a27c, data, tail17] - [0x8a280, .rodata, ov_SC04_004_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a30c, data, tail19] + - [0x8a30c, data, tail18] - [0x8a310, .rodata, ov_SC04_004_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8a344, data, tail20] + - [0x8a344, data, tail19] - [0x8BAFC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x8BAFF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_005.yaml b/config/splat.ov_SC04_005.yaml index f58cbe544d..69daec1913 100644 --- a/config/splat.ov_SC04_005.yaml +++ b/config/splat.ov_SC04_005.yaml @@ -141,31 +141,30 @@ segments: - [0x97d20, .rodata, ov_SC04_005_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x97d34, data, tail9] - [0x97d4c, .rodata, ov_SC04_005_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97db8, data, tail10] - [0x97e28, .rodata, ov_SC04_005_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x97e6c, .rodata, ov_SC04_005_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97eb4, data, tail11] + - [0x97eb4, data, tail10] - [0x97f14, .rodata, ov_SC04_005_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97f48, data, tail12] + - [0x97f48, data, tail11] - [0x97f4c, .rodata, ov_SC04_005_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97f68, data, tail13] + - [0x97f68, data, tail12] - [0x97f6c, .rodata, ov_SC04_005_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97fa8, data, tail14] + - [0x97fa8, data, tail13] - [0x97fac, .rodata, ov_SC04_005_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97fc8, data, tail15] + - [0x97fc8, data, tail14] - [0x97fe0, .rodata, ov_SC04_005_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x98020, data, tail16] + - [0x98020, data, tail15] - [0x98060, .rodata, ov_SC04_005_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x98080, .rodata, ov_SC04_005_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x98094, data, tail17] + - [0x98094, data, tail16] - [0x98224, .rodata, ov_SC04_005_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9823c, .rodata, ov_SC04_005_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x98440, data, tail18] + - [0x98440, data, tail17] - [0x98444, .rodata, ov_SC04_005_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x984d0, data, tail19] + - [0x984d0, data, tail18] - [0x984d4, .rodata, ov_SC04_005_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x984e8, .rodata, ov_SC04_005_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x98508, data, tail20] + - [0x98508, data, tail19] - [0x9A1D4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9A1D7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_006.yaml b/config/splat.ov_SC04_006.yaml index b905b46efe..6d8bbbf096 100644 --- a/config/splat.ov_SC04_006.yaml +++ b/config/splat.ov_SC04_006.yaml @@ -141,31 +141,30 @@ segments: - [0x73fc8, .rodata, ov_SC04_006_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73fdc, data, tail9] - [0x73ff4, .rodata, ov_SC04_006_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74060, data, tail10] - [0x740d0, .rodata, ov_SC04_006_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x74114, .rodata, ov_SC04_006_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7415c, data, tail11] + - [0x7415c, data, tail10] - [0x741bc, .rodata, ov_SC04_006_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x741f0, data, tail12] + - [0x741f0, data, tail11] - [0x741f4, .rodata, ov_SC04_006_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74210, data, tail13] + - [0x74210, data, tail12] - [0x74214, .rodata, ov_SC04_006_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74250, data, tail14] + - [0x74250, data, tail13] - [0x74254, .rodata, ov_SC04_006_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74270, data, tail15] + - [0x74270, data, tail14] - [0x74288, .rodata, ov_SC04_006_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x742c8, data, tail16] + - [0x742c8, data, tail15] - [0x74308, .rodata, ov_SC04_006_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x74328, .rodata, ov_SC04_006_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7433c, data, tail17] + - [0x7433c, data, tail16] - [0x744cc, .rodata, ov_SC04_006_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x744e4, .rodata, ov_SC04_006_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x746e8, data, tail18] + - [0x746e8, data, tail17] - [0x746ec, .rodata, ov_SC04_006_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74778, data, tail19] + - [0x74778, data, tail18] - [0x7477c, .rodata, ov_SC04_006_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x74790, .rodata, ov_SC04_006_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x747b0, data, tail20] + - [0x747b0, data, tail19] - [0x75C74, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x75C77] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_007.yaml b/config/splat.ov_SC04_007.yaml index 11536844ae..b437837a0a 100644 --- a/config/splat.ov_SC04_007.yaml +++ b/config/splat.ov_SC04_007.yaml @@ -141,31 +141,30 @@ segments: - [0x8b584, .rodata, ov_SC04_007_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8b598, data, tail9] - [0x8b5b0, .rodata, ov_SC04_007_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8b61c, data, tail10] - [0x8b68c, .rodata, ov_SC04_007_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8b6d0, .rodata, ov_SC04_007_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8b718, data, tail11] + - [0x8b718, data, tail10] - [0x8b778, .rodata, ov_SC04_007_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8b7ac, data, tail12] + - [0x8b7ac, data, tail11] - [0x8b7b0, .rodata, ov_SC04_007_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8b7cc, data, tail13] + - [0x8b7cc, data, tail12] - [0x8b7d0, .rodata, ov_SC04_007_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8b80c, data, tail14] + - [0x8b80c, data, tail13] - [0x8b810, .rodata, ov_SC04_007_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8b82c, data, tail15] + - [0x8b82c, data, tail14] - [0x8b844, .rodata, ov_SC04_007_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8b884, data, tail16] + - [0x8b884, data, tail15] - [0x8b8c4, .rodata, ov_SC04_007_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8b8e4, .rodata, ov_SC04_007_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8b8f8, data, tail17] + - [0x8b8f8, data, tail16] - [0x8ba88, .rodata, ov_SC04_007_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8baa0, .rodata, ov_SC04_007_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8bca4, data, tail18] + - [0x8bca4, data, tail17] - [0x8bca8, .rodata, ov_SC04_007_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8bd34, data, tail19] + - [0x8bd34, data, tail18] - [0x8bd38, .rodata, ov_SC04_007_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8bd4c, .rodata, ov_SC04_007_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8bd6c, data, tail20] + - [0x8bd6c, data, tail19] - [0x8DA34, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x8DA37] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_008.yaml b/config/splat.ov_SC04_008.yaml index 8ee02ae8a0..64db7d1a8e 100644 --- a/config/splat.ov_SC04_008.yaml +++ b/config/splat.ov_SC04_008.yaml @@ -139,28 +139,27 @@ segments: - [0x6826c, .rodata, ov_SC04_008_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x68280, data, tail9] - [0x68298, .rodata, ov_SC04_008_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68304, data, tail10] - [0x68374, .rodata, ov_SC04_008_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x683b8, .rodata, ov_SC04_008_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68400, data, tail11] + - [0x68400, data, tail10] - [0x68460, .rodata, ov_SC04_008_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x684b4, data, tail12] + - [0x684b4, data, tail11] - [0x684b8, .rodata, ov_SC04_008_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x684f4, data, tail13] + - [0x684f4, data, tail12] - [0x684f8, .rodata, ov_SC04_008_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68514, data, tail14] + - [0x68514, data, tail13] - [0x6852c, .rodata, ov_SC04_008_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6856c, data, tail15] + - [0x6856c, data, tail14] - [0x685ac, .rodata, ov_SC04_008_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x685cc, .rodata, ov_SC04_008_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x685e0, data, tail16] + - [0x685e0, data, tail15] - [0x68770, .rodata, ov_SC04_008_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x68788, .rodata, ov_SC04_008_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6898c, data, tail17] + - [0x6898c, data, tail16] - [0x68990, .rodata, ov_SC04_008_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68a1c, data, tail18] + - [0x68a1c, data, tail17] - [0x68a20, .rodata, ov_SC04_008_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68a54, data, tail19] + - [0x68a54, data, tail18] - [0x6B364, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x6B367] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_009.yaml b/config/splat.ov_SC04_009.yaml index 1c27fa5d08..3a23f0575e 100644 --- a/config/splat.ov_SC04_009.yaml +++ b/config/splat.ov_SC04_009.yaml @@ -141,31 +141,30 @@ segments: - [0x6e480, .rodata, ov_SC04_009_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6e494, data, tail9] - [0x6e4ac, .rodata, ov_SC04_009_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e518, data, tail10] - [0x6e588, .rodata, ov_SC04_009_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6e5cc, .rodata, ov_SC04_009_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e614, data, tail11] + - [0x6e614, data, tail10] - [0x6e674, .rodata, ov_SC04_009_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e6a8, data, tail12] + - [0x6e6a8, data, tail11] - [0x6e6ac, .rodata, ov_SC04_009_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e6c8, data, tail13] + - [0x6e6c8, data, tail12] - [0x6e6cc, .rodata, ov_SC04_009_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e708, data, tail14] + - [0x6e708, data, tail13] - [0x6e70c, .rodata, ov_SC04_009_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e728, data, tail15] + - [0x6e728, data, tail14] - [0x6e740, .rodata, ov_SC04_009_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e780, data, tail16] + - [0x6e780, data, tail15] - [0x6e7c0, .rodata, ov_SC04_009_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6e7e0, .rodata, ov_SC04_009_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e7f4, data, tail17] + - [0x6e7f4, data, tail16] - [0x6e984, .rodata, ov_SC04_009_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6e99c, .rodata, ov_SC04_009_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6eba0, data, tail18] + - [0x6eba0, data, tail17] - [0x6eba4, .rodata, ov_SC04_009_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6ec30, data, tail19] + - [0x6ec30, data, tail18] - [0x6ec34, .rodata, ov_SC04_009_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6ec48, .rodata, ov_SC04_009_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6ec68, data, tail20] + - [0x6ec68, data, tail19] - [0x70114, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x70117] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_010.yaml b/config/splat.ov_SC04_010.yaml index 5c5e5a9eb4..7443c97fbe 100644 --- a/config/splat.ov_SC04_010.yaml +++ b/config/splat.ov_SC04_010.yaml @@ -141,31 +141,30 @@ segments: - [0x6590c, .rodata, ov_SC04_010_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65920, data, tail9] - [0x65938, .rodata, ov_SC04_010_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x659a4, data, tail10] - [0x65a14, .rodata, ov_SC04_010_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65a58, .rodata, ov_SC04_010_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65aa0, data, tail11] + - [0x65aa0, data, tail10] - [0x65b00, .rodata, ov_SC04_010_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65b34, data, tail12] + - [0x65b34, data, tail11] - [0x65b38, .rodata, ov_SC04_010_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65b54, data, tail13] + - [0x65b54, data, tail12] - [0x65b58, .rodata, ov_SC04_010_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65b94, data, tail14] + - [0x65b94, data, tail13] - [0x65b98, .rodata, ov_SC04_010_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65bb4, data, tail15] + - [0x65bb4, data, tail14] - [0x65bcc, .rodata, ov_SC04_010_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65c0c, data, tail16] + - [0x65c0c, data, tail15] - [0x65c4c, .rodata, ov_SC04_010_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65c6c, .rodata, ov_SC04_010_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65c80, data, tail17] + - [0x65c80, data, tail16] - [0x65e10, .rodata, ov_SC04_010_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65e28, .rodata, ov_SC04_010_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6602c, data, tail18] + - [0x6602c, data, tail17] - [0x66030, .rodata, ov_SC04_010_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x660bc, data, tail19] + - [0x660bc, data, tail18] - [0x660c0, .rodata, ov_SC04_010_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x660d4, .rodata, ov_SC04_010_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x660f4, data, tail20] + - [0x660f4, data, tail19] - [0x675EC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x675EF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_011.yaml b/config/splat.ov_SC04_011.yaml index e3f614cd1a..36ab3930e0 100644 --- a/config/splat.ov_SC04_011.yaml +++ b/config/splat.ov_SC04_011.yaml @@ -141,32 +141,31 @@ segments: - [0xc4ea8, .rodata, ov_SC04_011_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc4ebc, data, tail9] - [0xc4ed4, .rodata, ov_SC04_011_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc4f40, data, tail10] - [0xc4fb0, .rodata, ov_SC04_011_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc4ff4, .rodata, ov_SC04_011_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc503c, data, tail11] + - [0xc503c, data, tail10] - [0xc509c, .rodata, ov_SC04_011_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc50d0, data, tail12] + - [0xc50d0, data, tail11] - [0xc50d4, .rodata, ov_SC04_011_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc50f0, data, tail13] + - [0xc50f0, data, tail12] - [0xc50f4, .rodata, ov_SC04_011_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5130, data, tail14] + - [0xc5130, data, tail13] - [0xc5134, .rodata, ov_SC04_011_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5150, data, tail15] + - [0xc5150, data, tail14] - [0xc5168, .rodata, ov_SC04_011_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc51a8, data, tail16] + - [0xc51a8, data, tail15] - [0xc51e8, .rodata, ov_SC04_011_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc5208, .rodata, ov_SC04_011_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc521c, data, tail17] + - [0xc521c, data, tail16] - [0xc53ac, .rodata, ov_SC04_011_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc53c4, .rodata, ov_SC04_011_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc55c8, data, tail18] + - [0xc55c8, data, tail17] - [0xc55cc, .rodata, ov_SC04_011_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5658, data, tail19] + - [0xc5658, data, tail18] - [0xc565c, .rodata, ov_SC04_011_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5670, data, tail20] + - [0xc5670, data, tail19] - [0xc57a8, .rodata, ov_SC04_011_jr_8017D494] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc57c8, data, tail21] + - [0xc57c8, data, tail20] - [0xC9554, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC9557] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_012.yaml b/config/splat.ov_SC04_012.yaml index ddfe5b1cef..9af4d869b2 100644 --- a/config/splat.ov_SC04_012.yaml +++ b/config/splat.ov_SC04_012.yaml @@ -140,30 +140,29 @@ segments: - [0x67fec, .rodata, ov_SC04_012_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x68000, data, tail9] - [0x68018, .rodata, ov_SC04_012_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68084, data, tail10] - [0x680f4, .rodata, ov_SC04_012_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x68138, .rodata, ov_SC04_012_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68180, data, tail11] + - [0x68180, data, tail10] - [0x681e0, .rodata, ov_SC04_012_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68214, data, tail12] + - [0x68214, data, tail11] - [0x68218, .rodata, ov_SC04_012_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68234, data, tail13] + - [0x68234, data, tail12] - [0x68238, .rodata, ov_SC04_012_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68274, data, tail14] + - [0x68274, data, tail13] - [0x68278, .rodata, ov_SC04_012_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68294, data, tail15] + - [0x68294, data, tail14] - [0x682ac, .rodata, ov_SC04_012_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x682ec, data, tail16] + - [0x682ec, data, tail15] - [0x6832c, .rodata, ov_SC04_012_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6834c, .rodata, ov_SC04_012_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68360, data, tail17] + - [0x68360, data, tail16] - [0x684f0, .rodata, ov_SC04_012_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x68508, .rodata, ov_SC04_012_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6870c, data, tail18] + - [0x6870c, data, tail17] - [0x68710, .rodata, ov_SC04_012_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6879c, data, tail19] + - [0x6879c, data, tail18] - [0x687a0, .rodata, ov_SC04_012_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x687d4, data, tail20] + - [0x687d4, data, tail19] - [0x6B0E4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x6B0E7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_015.yaml b/config/splat.ov_SC04_015.yaml index 81c42f8506..b7e218b7fb 100644 --- a/config/splat.ov_SC04_015.yaml +++ b/config/splat.ov_SC04_015.yaml @@ -140,30 +140,29 @@ segments: - [0x9ec84, .rodata, ov_SC04_015_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9ec98, data, tail9] - [0x9ecb0, .rodata, ov_SC04_015_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ed1c, data, tail10] - [0x9ed8c, .rodata, ov_SC04_015_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9edd0, .rodata, ov_SC04_015_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ee18, data, tail11] + - [0x9ee18, data, tail10] - [0x9ee78, .rodata, ov_SC04_015_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9eeac, data, tail12] + - [0x9eeac, data, tail11] - [0x9eeb0, .rodata, ov_SC04_015_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9eecc, data, tail13] + - [0x9eecc, data, tail12] - [0x9eed0, .rodata, ov_SC04_015_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ef0c, data, tail14] + - [0x9ef0c, data, tail13] - [0x9ef10, .rodata, ov_SC04_015_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ef2c, data, tail15] + - [0x9ef2c, data, tail14] - [0x9ef44, .rodata, ov_SC04_015_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ef84, data, tail16] + - [0x9ef84, data, tail15] - [0x9efc4, .rodata, ov_SC04_015_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9efe4, .rodata, ov_SC04_015_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9eff8, data, tail17] + - [0x9eff8, data, tail16] - [0x9f188, .rodata, ov_SC04_015_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9f1a0, .rodata, ov_SC04_015_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9f3a4, data, tail18] + - [0x9f3a4, data, tail17] - [0x9f3a8, .rodata, ov_SC04_015_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9f434, data, tail19] + - [0x9f434, data, tail18] - [0x9f438, .rodata, ov_SC04_015_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9f46c, data, tail20] + - [0x9f46c, data, tail19] - [0xA1284, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA1287] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_016.yaml b/config/splat.ov_SC04_016.yaml index 31aa6141e7..d92e3490e9 100644 --- a/config/splat.ov_SC04_016.yaml +++ b/config/splat.ov_SC04_016.yaml @@ -141,31 +141,30 @@ segments: - [0x7ce3c, .rodata, ov_SC04_016_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7ce50, data, tail9] - [0x7ce68, .rodata, ov_SC04_016_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7ced4, data, tail10] - [0x7cf44, .rodata, ov_SC04_016_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7cf88, .rodata, ov_SC04_016_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7cfd0, data, tail11] + - [0x7cfd0, data, tail10] - [0x7d030, .rodata, ov_SC04_016_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7d064, data, tail12] + - [0x7d064, data, tail11] - [0x7d068, .rodata, ov_SC04_016_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7d084, data, tail13] + - [0x7d084, data, tail12] - [0x7d088, .rodata, ov_SC04_016_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7d0c4, data, tail14] + - [0x7d0c4, data, tail13] - [0x7d0c8, .rodata, ov_SC04_016_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7d0e4, data, tail15] + - [0x7d0e4, data, tail14] - [0x7d0fc, .rodata, ov_SC04_016_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7d13c, data, tail16] + - [0x7d13c, data, tail15] - [0x7d17c, .rodata, ov_SC04_016_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7d19c, .rodata, ov_SC04_016_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7d1b0, data, tail17] + - [0x7d1b0, data, tail16] - [0x7d340, .rodata, ov_SC04_016_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7d358, .rodata, ov_SC04_016_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7d55c, data, tail18] + - [0x7d55c, data, tail17] - [0x7d560, .rodata, ov_SC04_016_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7d5ec, data, tail19] + - [0x7d5ec, data, tail18] - [0x7d5f0, .rodata, ov_SC04_016_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7d604, .rodata, ov_SC04_016_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7d624, data, tail20] + - [0x7d624, data, tail19] - [0x84184, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x84187] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_018.yaml b/config/splat.ov_SC04_018.yaml index 38cd0162d1..6df38f0c3d 100644 --- a/config/splat.ov_SC04_018.yaml +++ b/config/splat.ov_SC04_018.yaml @@ -140,30 +140,29 @@ segments: - [0xbcc54, .rodata, ov_SC04_018_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbcc68, data, tail9] - [0xbcc80, .rodata, ov_SC04_018_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbccec, data, tail10] - [0xbcd5c, .rodata, ov_SC04_018_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbcda0, .rodata, ov_SC04_018_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcde8, data, tail11] + - [0xbcde8, data, tail10] - [0xbce48, .rodata, ov_SC04_018_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbce7c, data, tail12] + - [0xbce7c, data, tail11] - [0xbce80, .rodata, ov_SC04_018_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbce9c, data, tail13] + - [0xbce9c, data, tail12] - [0xbcea0, .rodata, ov_SC04_018_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcedc, data, tail14] + - [0xbcedc, data, tail13] - [0xbcee0, .rodata, ov_SC04_018_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcefc, data, tail15] + - [0xbcefc, data, tail14] - [0xbcf14, .rodata, ov_SC04_018_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcf54, data, tail16] + - [0xbcf54, data, tail15] - [0xbcf94, .rodata, ov_SC04_018_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbcfb4, .rodata, ov_SC04_018_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcfc8, data, tail17] + - [0xbcfc8, data, tail16] - [0xbd158, .rodata, ov_SC04_018_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbd170, .rodata, ov_SC04_018_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbd374, data, tail18] + - [0xbd374, data, tail17] - [0xbd378, .rodata, ov_SC04_018_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbd404, data, tail19] + - [0xbd404, data, tail18] - [0xbd408, .rodata, ov_SC04_018_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbd43c, data, tail20] + - [0xbd43c, data, tail19] - [0xBF9CC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xBF9CF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_019.yaml b/config/splat.ov_SC04_019.yaml index edeaac89e9..6dad95aa7b 100644 --- a/config/splat.ov_SC04_019.yaml +++ b/config/splat.ov_SC04_019.yaml @@ -140,30 +140,29 @@ segments: - [0xbcc54, .rodata, ov_SC04_019_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbcc68, data, tail9] - [0xbcc80, .rodata, ov_SC04_019_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbccec, data, tail10] - [0xbcd5c, .rodata, ov_SC04_019_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbcda0, .rodata, ov_SC04_019_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcde8, data, tail11] + - [0xbcde8, data, tail10] - [0xbce48, .rodata, ov_SC04_019_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbce7c, data, tail12] + - [0xbce7c, data, tail11] - [0xbce80, .rodata, ov_SC04_019_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbce9c, data, tail13] + - [0xbce9c, data, tail12] - [0xbcea0, .rodata, ov_SC04_019_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcedc, data, tail14] + - [0xbcedc, data, tail13] - [0xbcee0, .rodata, ov_SC04_019_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcefc, data, tail15] + - [0xbcefc, data, tail14] - [0xbcf14, .rodata, ov_SC04_019_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcf54, data, tail16] + - [0xbcf54, data, tail15] - [0xbcf94, .rodata, ov_SC04_019_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbcfb4, .rodata, ov_SC04_019_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcfc8, data, tail17] + - [0xbcfc8, data, tail16] - [0xbd158, .rodata, ov_SC04_019_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbd170, .rodata, ov_SC04_019_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbd374, data, tail18] + - [0xbd374, data, tail17] - [0xbd378, .rodata, ov_SC04_019_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbd404, data, tail19] + - [0xbd404, data, tail18] - [0xbd408, .rodata, ov_SC04_019_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbd43c, data, tail20] + - [0xbd43c, data, tail19] - [0xBF9CC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xBF9CF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_020.yaml b/config/splat.ov_SC04_020.yaml index 3c402f851d..106325e4b1 100644 --- a/config/splat.ov_SC04_020.yaml +++ b/config/splat.ov_SC04_020.yaml @@ -141,31 +141,30 @@ segments: - [0x9267c, .rodata, ov_SC04_020_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x92690, data, tail9] - [0x926a8, .rodata, ov_SC04_020_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x92714, data, tail10] - [0x92784, .rodata, ov_SC04_020_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x927c8, .rodata, ov_SC04_020_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x92810, data, tail11] + - [0x92810, data, tail10] - [0x92870, .rodata, ov_SC04_020_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x928a4, data, tail12] + - [0x928a4, data, tail11] - [0x928a8, .rodata, ov_SC04_020_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x928c4, data, tail13] + - [0x928c4, data, tail12] - [0x928c8, .rodata, ov_SC04_020_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x92904, data, tail14] + - [0x92904, data, tail13] - [0x92908, .rodata, ov_SC04_020_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x92924, data, tail15] + - [0x92924, data, tail14] - [0x9293c, .rodata, ov_SC04_020_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9297c, data, tail16] + - [0x9297c, data, tail15] - [0x929bc, .rodata, ov_SC04_020_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x929dc, .rodata, ov_SC04_020_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x929f0, data, tail17] + - [0x929f0, data, tail16] - [0x92b80, .rodata, ov_SC04_020_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x92b98, .rodata, ov_SC04_020_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x92d9c, data, tail18] + - [0x92d9c, data, tail17] - [0x92da0, .rodata, ov_SC04_020_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x92e2c, data, tail19] + - [0x92e2c, data, tail18] - [0x92e30, .rodata, ov_SC04_020_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x92e44, .rodata, ov_SC04_020_jr_8017D604] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x92e64, data, tail20] + - [0x92e64, data, tail19] - [0x94654, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x94657] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_021.yaml b/config/splat.ov_SC04_021.yaml index f9fd94b6ca..9bd5376ad9 100644 --- a/config/splat.ov_SC04_021.yaml +++ b/config/splat.ov_SC04_021.yaml @@ -141,32 +141,31 @@ segments: - [0x65d18, .rodata, ov_SC04_021_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65d2c, data, tail9] - [0x65d44, .rodata, ov_SC04_021_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65db0, data, tail10] - [0x65e20, .rodata, ov_SC04_021_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65e64, .rodata, ov_SC04_021_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65eac, data, tail11] + - [0x65eac, data, tail10] - [0x65f0c, .rodata, ov_SC04_021_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65f40, data, tail12] + - [0x65f40, data, tail11] - [0x65f44, .rodata, ov_SC04_021_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65f60, data, tail13] + - [0x65f60, data, tail12] - [0x65f64, .rodata, ov_SC04_021_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65fa0, data, tail14] + - [0x65fa0, data, tail13] - [0x65fa4, .rodata, ov_SC04_021_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65fc0, data, tail15] + - [0x65fc0, data, tail14] - [0x65fd8, .rodata, ov_SC04_021_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66018, data, tail16] + - [0x66018, data, tail15] - [0x66058, .rodata, ov_SC04_021_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66078, .rodata, ov_SC04_021_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6608c, data, tail17] + - [0x6608c, data, tail16] - [0x6621c, .rodata, ov_SC04_021_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66234, .rodata, ov_SC04_021_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66438, data, tail18] + - [0x66438, data, tail17] - [0x6643c, .rodata, ov_SC04_021_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x664c8, data, tail19] + - [0x664c8, data, tail18] - [0x664cc, .rodata, ov_SC04_021_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x664e0, data, tail20] + - [0x664e0, data, tail19] - [0x66500, .rodata, ov_SC04_021_jr_8017D5C0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66520, data, tail21] + - [0x66520, data, tail20] - [0x679D4, bin, trailing] # final 1 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x679D5] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_000.yaml b/config/splat.ov_SC05_000.yaml index 220436c39a..ffb5d28ef5 100644 --- a/config/splat.ov_SC05_000.yaml +++ b/config/splat.ov_SC05_000.yaml @@ -141,31 +141,30 @@ segments: - [0x70e68, .rodata, ov_SC05_000_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70e7c, data, tail9] - [0x70e94, .rodata, ov_SC05_000_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70f00, data, tail10] - [0x70f70, .rodata, ov_SC05_000_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70fb4, .rodata, ov_SC05_000_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70ffc, data, tail11] + - [0x70ffc, data, tail10] - [0x7105c, .rodata, ov_SC05_000_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71090, data, tail12] + - [0x71090, data, tail11] - [0x71094, .rodata, ov_SC05_000_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x710b0, data, tail13] + - [0x710b0, data, tail12] - [0x710b4, .rodata, ov_SC05_000_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x710f0, data, tail14] + - [0x710f0, data, tail13] - [0x710f4, .rodata, ov_SC05_000_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71110, data, tail15] + - [0x71110, data, tail14] - [0x71128, .rodata, ov_SC05_000_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71168, data, tail16] + - [0x71168, data, tail15] - [0x711a8, .rodata, ov_SC05_000_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x711c8, .rodata, ov_SC05_000_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x711dc, data, tail17] + - [0x711dc, data, tail16] - [0x7136c, .rodata, ov_SC05_000_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71384, .rodata, ov_SC05_000_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71588, data, tail18] + - [0x71588, data, tail17] - [0x7158c, .rodata, ov_SC05_000_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71618, data, tail19] + - [0x71618, data, tail18] - [0x7161c, .rodata, ov_SC05_000_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71630, .rodata, ov_SC05_000_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71650, data, tail20] + - [0x71650, data, tail19] - [0x72AFC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x72AFF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_001.yaml b/config/splat.ov_SC05_001.yaml index c874cc73eb..efd09fc9ea 100644 --- a/config/splat.ov_SC05_001.yaml +++ b/config/splat.ov_SC05_001.yaml @@ -141,31 +141,30 @@ segments: - [0x8be1c, .rodata, ov_SC05_001_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8be30, data, tail9] - [0x8be48, .rodata, ov_SC05_001_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8beb4, data, tail10] - [0x8bf24, .rodata, ov_SC05_001_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8bf68, .rodata, ov_SC05_001_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8bfb0, data, tail11] + - [0x8bfb0, data, tail10] - [0x8c010, .rodata, ov_SC05_001_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8c044, data, tail12] + - [0x8c044, data, tail11] - [0x8c048, .rodata, ov_SC05_001_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8c064, data, tail13] + - [0x8c064, data, tail12] - [0x8c068, .rodata, ov_SC05_001_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8c0a4, data, tail14] + - [0x8c0a4, data, tail13] - [0x8c0a8, .rodata, ov_SC05_001_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8c0c4, data, tail15] + - [0x8c0c4, data, tail14] - [0x8c0dc, .rodata, ov_SC05_001_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8c11c, data, tail16] + - [0x8c11c, data, tail15] - [0x8c15c, .rodata, ov_SC05_001_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8c17c, .rodata, ov_SC05_001_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8c190, data, tail17] + - [0x8c190, data, tail16] - [0x8c320, .rodata, ov_SC05_001_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8c338, .rodata, ov_SC05_001_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8c53c, data, tail18] + - [0x8c53c, data, tail17] - [0x8c540, .rodata, ov_SC05_001_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8c5cc, data, tail19] + - [0x8c5cc, data, tail18] - [0x8c5d0, .rodata, ov_SC05_001_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8c5e4, .rodata, ov_SC05_001_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8c604, data, tail20] + - [0x8c604, data, tail19] - [0x8DEAC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x8DEAF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_002.yaml b/config/splat.ov_SC05_002.yaml index 811dd180eb..8851703766 100644 --- a/config/splat.ov_SC05_002.yaml +++ b/config/splat.ov_SC05_002.yaml @@ -141,31 +141,30 @@ segments: - [0x761c8, .rodata, ov_SC05_002_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x761dc, data, tail9] - [0x761f4, .rodata, ov_SC05_002_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76260, data, tail10] - [0x762d0, .rodata, ov_SC05_002_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76314, .rodata, ov_SC05_002_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7635c, data, tail11] + - [0x7635c, data, tail10] - [0x763bc, .rodata, ov_SC05_002_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x763f0, data, tail12] + - [0x763f0, data, tail11] - [0x763f4, .rodata, ov_SC05_002_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76410, data, tail13] + - [0x76410, data, tail12] - [0x76414, .rodata, ov_SC05_002_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76450, data, tail14] + - [0x76450, data, tail13] - [0x76454, .rodata, ov_SC05_002_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76470, data, tail15] + - [0x76470, data, tail14] - [0x76488, .rodata, ov_SC05_002_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x764c8, data, tail16] + - [0x764c8, data, tail15] - [0x76508, .rodata, ov_SC05_002_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76528, .rodata, ov_SC05_002_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7653c, data, tail17] + - [0x7653c, data, tail16] - [0x766cc, .rodata, ov_SC05_002_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x766e4, .rodata, ov_SC05_002_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x768e8, data, tail18] + - [0x768e8, data, tail17] - [0x768ec, .rodata, ov_SC05_002_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76978, data, tail19] + - [0x76978, data, tail18] - [0x7697c, .rodata, ov_SC05_002_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76990, .rodata, ov_SC05_002_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x769b0, data, tail20] + - [0x769b0, data, tail19] - [0x77E64, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x77E67] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_003.yaml b/config/splat.ov_SC05_003.yaml index f2466ce39f..ece9910505 100644 --- a/config/splat.ov_SC05_003.yaml +++ b/config/splat.ov_SC05_003.yaml @@ -141,31 +141,30 @@ segments: - [0x82cc4, .rodata, ov_SC05_003_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x82cd8, data, tail9] - [0x82cf0, .rodata, ov_SC05_003_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82d5c, data, tail10] - [0x82dcc, .rodata, ov_SC05_003_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x82e10, .rodata, ov_SC05_003_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82e58, data, tail11] + - [0x82e58, data, tail10] - [0x82eb8, .rodata, ov_SC05_003_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82eec, data, tail12] + - [0x82eec, data, tail11] - [0x82ef0, .rodata, ov_SC05_003_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82f0c, data, tail13] + - [0x82f0c, data, tail12] - [0x82f10, .rodata, ov_SC05_003_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82f4c, data, tail14] + - [0x82f4c, data, tail13] - [0x82f50, .rodata, ov_SC05_003_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82f6c, data, tail15] + - [0x82f6c, data, tail14] - [0x82f84, .rodata, ov_SC05_003_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82fc4, data, tail16] + - [0x82fc4, data, tail15] - [0x83004, .rodata, ov_SC05_003_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x83024, .rodata, ov_SC05_003_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83038, data, tail17] + - [0x83038, data, tail16] - [0x831c8, .rodata, ov_SC05_003_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x831e0, .rodata, ov_SC05_003_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x833e4, data, tail18] + - [0x833e4, data, tail17] - [0x833e8, .rodata, ov_SC05_003_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83474, data, tail19] + - [0x83474, data, tail18] - [0x83478, .rodata, ov_SC05_003_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8348c, .rodata, ov_SC05_003_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x834ac, data, tail20] + - [0x834ac, data, tail19] - [0x84974, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x84977] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_004.yaml b/config/splat.ov_SC05_004.yaml index ac8ee0d63c..6dd3004a23 100644 --- a/config/splat.ov_SC05_004.yaml +++ b/config/splat.ov_SC05_004.yaml @@ -141,31 +141,30 @@ segments: - [0x752b8, .rodata, ov_SC05_004_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x752cc, data, tail9] - [0x752e4, .rodata, ov_SC05_004_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75350, data, tail10] - [0x753c0, .rodata, ov_SC05_004_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x75404, .rodata, ov_SC05_004_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7544c, data, tail11] + - [0x7544c, data, tail10] - [0x754ac, .rodata, ov_SC05_004_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x754e0, data, tail12] + - [0x754e0, data, tail11] - [0x754e4, .rodata, ov_SC05_004_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75500, data, tail13] + - [0x75500, data, tail12] - [0x75504, .rodata, ov_SC05_004_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75540, data, tail14] + - [0x75540, data, tail13] - [0x75544, .rodata, ov_SC05_004_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75560, data, tail15] + - [0x75560, data, tail14] - [0x75578, .rodata, ov_SC05_004_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x755b8, data, tail16] + - [0x755b8, data, tail15] - [0x755f8, .rodata, ov_SC05_004_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x75618, .rodata, ov_SC05_004_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7562c, data, tail17] + - [0x7562c, data, tail16] - [0x757bc, .rodata, ov_SC05_004_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x757d4, .rodata, ov_SC05_004_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x759d8, data, tail18] + - [0x759d8, data, tail17] - [0x759dc, .rodata, ov_SC05_004_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75a68, data, tail19] + - [0x75a68, data, tail18] - [0x75a6c, .rodata, ov_SC05_004_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x75a80, .rodata, ov_SC05_004_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75aa0, data, tail20] + - [0x75aa0, data, tail19] - [0x771CC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x771CF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_005.yaml b/config/splat.ov_SC05_005.yaml index ec774b6f40..d2fdd6a69b 100644 --- a/config/splat.ov_SC05_005.yaml +++ b/config/splat.ov_SC05_005.yaml @@ -141,31 +141,30 @@ segments: - [0x87fa0, .rodata, ov_SC05_005_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x87fb4, data, tail9] - [0x87fcc, .rodata, ov_SC05_005_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88038, data, tail10] - [0x880a8, .rodata, ov_SC05_005_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x880ec, .rodata, ov_SC05_005_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88134, data, tail11] + - [0x88134, data, tail10] - [0x88194, .rodata, ov_SC05_005_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x881c8, data, tail12] + - [0x881c8, data, tail11] - [0x881cc, .rodata, ov_SC05_005_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x881e8, data, tail13] + - [0x881e8, data, tail12] - [0x881ec, .rodata, ov_SC05_005_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88228, data, tail14] + - [0x88228, data, tail13] - [0x8822c, .rodata, ov_SC05_005_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88248, data, tail15] + - [0x88248, data, tail14] - [0x88260, .rodata, ov_SC05_005_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x882a0, data, tail16] + - [0x882a0, data, tail15] - [0x882e0, .rodata, ov_SC05_005_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x88300, .rodata, ov_SC05_005_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88314, data, tail17] + - [0x88314, data, tail16] - [0x884a4, .rodata, ov_SC05_005_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x884bc, .rodata, ov_SC05_005_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x886c0, data, tail18] + - [0x886c0, data, tail17] - [0x886c4, .rodata, ov_SC05_005_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88750, data, tail19] + - [0x88750, data, tail18] - [0x88754, .rodata, ov_SC05_005_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x88768, .rodata, ov_SC05_005_jr_8017D898] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88788, data, tail20] + - [0x88788, data, tail19] - [0x89ED4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x89ED7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_006.yaml b/config/splat.ov_SC05_006.yaml index 3bac94842b..75d41fb81e 100644 --- a/config/splat.ov_SC05_006.yaml +++ b/config/splat.ov_SC05_006.yaml @@ -141,31 +141,30 @@ segments: - [0x660f0, .rodata, ov_SC05_006_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66104, data, tail9] - [0x6611c, .rodata, ov_SC05_006_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66188, data, tail10] - [0x661f8, .rodata, ov_SC05_006_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6623c, .rodata, ov_SC05_006_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66284, data, tail11] + - [0x66284, data, tail10] - [0x662e4, .rodata, ov_SC05_006_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66318, data, tail12] + - [0x66318, data, tail11] - [0x6631c, .rodata, ov_SC05_006_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66338, data, tail13] + - [0x66338, data, tail12] - [0x6633c, .rodata, ov_SC05_006_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66378, data, tail14] + - [0x66378, data, tail13] - [0x6637c, .rodata, ov_SC05_006_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66398, data, tail15] + - [0x66398, data, tail14] - [0x663b0, .rodata, ov_SC05_006_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x663f0, data, tail16] + - [0x663f0, data, tail15] - [0x66430, .rodata, ov_SC05_006_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66450, .rodata, ov_SC05_006_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66464, data, tail17] + - [0x66464, data, tail16] - [0x665f4, .rodata, ov_SC05_006_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6660c, .rodata, ov_SC05_006_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66810, data, tail18] + - [0x66810, data, tail17] - [0x66814, .rodata, ov_SC05_006_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x668a0, data, tail19] + - [0x668a0, data, tail18] - [0x668a4, .rodata, ov_SC05_006_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x668b8, .rodata, ov_SC05_006_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x668d8, data, tail20] + - [0x668d8, data, tail19] - [0x68004, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x68007] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_007.yaml b/config/splat.ov_SC05_007.yaml index ea798a90c0..5813420683 100644 --- a/config/splat.ov_SC05_007.yaml +++ b/config/splat.ov_SC05_007.yaml @@ -141,31 +141,30 @@ segments: - [0x730c8, .rodata, ov_SC05_007_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x730dc, data, tail9] - [0x730f4, .rodata, ov_SC05_007_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73160, data, tail10] - [0x731d0, .rodata, ov_SC05_007_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73214, .rodata, ov_SC05_007_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7325c, data, tail11] + - [0x7325c, data, tail10] - [0x732bc, .rodata, ov_SC05_007_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x732f0, data, tail12] + - [0x732f0, data, tail11] - [0x732f4, .rodata, ov_SC05_007_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73310, data, tail13] + - [0x73310, data, tail12] - [0x73314, .rodata, ov_SC05_007_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73350, data, tail14] + - [0x73350, data, tail13] - [0x73354, .rodata, ov_SC05_007_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73370, data, tail15] + - [0x73370, data, tail14] - [0x73388, .rodata, ov_SC05_007_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x733c8, data, tail16] + - [0x733c8, data, tail15] - [0x73408, .rodata, ov_SC05_007_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73428, .rodata, ov_SC05_007_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7343c, data, tail17] + - [0x7343c, data, tail16] - [0x735cc, .rodata, ov_SC05_007_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x735e4, .rodata, ov_SC05_007_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x737e8, data, tail18] + - [0x737e8, data, tail17] - [0x737ec, .rodata, ov_SC05_007_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73878, data, tail19] + - [0x73878, data, tail18] - [0x7387c, .rodata, ov_SC05_007_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73890, .rodata, ov_SC05_007_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x738b0, data, tail20] + - [0x738b0, data, tail19] - [0x74DA4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x74DA7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_008.yaml b/config/splat.ov_SC05_008.yaml index ac34ac99bc..acdad220ea 100644 --- a/config/splat.ov_SC05_008.yaml +++ b/config/splat.ov_SC05_008.yaml @@ -140,30 +140,29 @@ segments: - [0x773fc, .rodata, ov_SC05_008_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77410, data, tail9] - [0x77428, .rodata, ov_SC05_008_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77494, data, tail10] - [0x77504, .rodata, ov_SC05_008_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77548, .rodata, ov_SC05_008_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77590, data, tail11] + - [0x77590, data, tail10] - [0x775f0, .rodata, ov_SC05_008_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77624, data, tail12] + - [0x77624, data, tail11] - [0x77628, .rodata, ov_SC05_008_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77644, data, tail13] + - [0x77644, data, tail12] - [0x77648, .rodata, ov_SC05_008_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77684, data, tail14] + - [0x77684, data, tail13] - [0x77688, .rodata, ov_SC05_008_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x776a4, data, tail15] + - [0x776a4, data, tail14] - [0x776bc, .rodata, ov_SC05_008_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x776fc, data, tail16] + - [0x776fc, data, tail15] - [0x7773c, .rodata, ov_SC05_008_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7775c, .rodata, ov_SC05_008_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77770, data, tail17] + - [0x77770, data, tail16] - [0x77900, .rodata, ov_SC05_008_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77918, .rodata, ov_SC05_008_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77b1c, data, tail18] + - [0x77b1c, data, tail17] - [0x77b20, .rodata, ov_SC05_008_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77bac, data, tail19] + - [0x77bac, data, tail18] - [0x77bb0, .rodata, ov_SC05_008_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77be4, data, tail20] + - [0x77be4, data, tail19] - [0x79190, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x79193] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_009.yaml b/config/splat.ov_SC05_009.yaml index e0373ffb50..57da8be3f2 100644 --- a/config/splat.ov_SC05_009.yaml +++ b/config/splat.ov_SC05_009.yaml @@ -140,29 +140,28 @@ segments: - [0x6ce10, .rodata, ov_SC05_009_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6ce24, data, tail9] - [0x6ce3c, .rodata, ov_SC05_009_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cea8, data, tail10] - [0x6cf18, .rodata, ov_SC05_009_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6cf5c, .rodata, ov_SC05_009_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cfa4, data, tail11] + - [0x6cfa4, data, tail10] - [0x6d004, .rodata, ov_SC05_009_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d058, data, tail12] + - [0x6d058, data, tail11] - [0x6d05c, .rodata, ov_SC05_009_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d098, data, tail13] + - [0x6d098, data, tail12] - [0x6d09c, .rodata, ov_SC05_009_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d0b8, data, tail14] + - [0x6d0b8, data, tail13] - [0x6d0d0, .rodata, ov_SC05_009_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d110, data, tail15] + - [0x6d110, data, tail14] - [0x6d150, .rodata, ov_SC05_009_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6d170, .rodata, ov_SC05_009_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d184, data, tail16] + - [0x6d184, data, tail15] - [0x6d314, .rodata, ov_SC05_009_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6d32c, .rodata, ov_SC05_009_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d530, data, tail17] + - [0x6d530, data, tail16] - [0x6d534, .rodata, ov_SC05_009_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d5c0, data, tail18] + - [0x6d5c0, data, tail17] - [0x6d5c4, .rodata, ov_SC05_009_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6d5d8, .rodata, ov_SC05_009_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d5f8, data, tail19] + - [0x6d5f8, data, tail18] - [0x6EAEC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x6EAEF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_010.yaml b/config/splat.ov_SC05_010.yaml index 12217143cc..365d5f302d 100644 --- a/config/splat.ov_SC05_010.yaml +++ b/config/splat.ov_SC05_010.yaml @@ -142,34 +142,33 @@ segments: - [0x9d044, .rodata, ov_SC05_010_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9d058, data, tail9] - [0x9d070, .rodata, ov_SC05_010_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d0dc, data, tail10] - [0x9d14c, .rodata, ov_SC05_010_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9d190, .rodata, ov_SC05_010_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d1d8, data, tail11] + - [0x9d1d8, data, tail10] - [0x9d238, .rodata, ov_SC05_010_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d26c, data, tail12] + - [0x9d26c, data, tail11] - [0x9d270, .rodata, ov_SC05_010_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d28c, data, tail13] + - [0x9d28c, data, tail12] - [0x9d290, .rodata, ov_SC05_010_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d2cc, data, tail14] + - [0x9d2cc, data, tail13] - [0x9d2d0, .rodata, ov_SC05_010_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d2ec, data, tail15] + - [0x9d2ec, data, tail14] - [0x9d304, .rodata, ov_SC05_010_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d344, data, tail16] + - [0x9d344, data, tail15] - [0x9d384, .rodata, ov_SC05_010_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9d3a4, .rodata, ov_SC05_010_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d3b8, data, tail17] + - [0x9d3b8, data, tail16] - [0x9d548, .rodata, ov_SC05_010_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9d560, .rodata, ov_SC05_010_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d764, data, tail18] + - [0x9d764, data, tail17] - [0x9d768, .rodata, ov_SC05_010_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d7f4, data, tail19] + - [0x9d7f4, data, tail18] - [0x9d7f8, .rodata, ov_SC05_010_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d80c, data, tail20] + - [0x9d80c, data, tail19] - [0x9d944, .rodata, ov_SC05_010_jr_8017C8D0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d964, data, tail21] + - [0x9d964, data, tail20] - [0x9d9f4, .rodata, ov_SC05_010_jr_80181CDC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9da0c, data, tail22] + - [0x9da0c, data, tail21] - [0x9FED4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9FED7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_011.yaml b/config/splat.ov_SC05_011.yaml index bd45ccf237..97d3d140a0 100644 --- a/config/splat.ov_SC05_011.yaml +++ b/config/splat.ov_SC05_011.yaml @@ -141,31 +141,30 @@ segments: - [0x733a8, .rodata, ov_SC05_011_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x733bc, data, tail9] - [0x733d4, .rodata, ov_SC05_011_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73440, data, tail10] - [0x734b0, .rodata, ov_SC05_011_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x734f4, .rodata, ov_SC05_011_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7353c, data, tail11] + - [0x7353c, data, tail10] - [0x7359c, .rodata, ov_SC05_011_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x735d0, data, tail12] + - [0x735d0, data, tail11] - [0x735d4, .rodata, ov_SC05_011_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x735f0, data, tail13] + - [0x735f0, data, tail12] - [0x735f4, .rodata, ov_SC05_011_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73630, data, tail14] + - [0x73630, data, tail13] - [0x73634, .rodata, ov_SC05_011_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73650, data, tail15] + - [0x73650, data, tail14] - [0x73668, .rodata, ov_SC05_011_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x736a8, data, tail16] + - [0x736a8, data, tail15] - [0x736e8, .rodata, ov_SC05_011_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73708, .rodata, ov_SC05_011_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7371c, data, tail17] + - [0x7371c, data, tail16] - [0x738ac, .rodata, ov_SC05_011_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x738c4, .rodata, ov_SC05_011_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73ac8, data, tail18] + - [0x73ac8, data, tail17] - [0x73acc, .rodata, ov_SC05_011_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73b58, data, tail19] + - [0x73b58, data, tail18] - [0x73b5c, .rodata, ov_SC05_011_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73b70, .rodata, ov_SC05_011_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73b90, data, tail20] + - [0x73b90, data, tail19] - [0x75084, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x75087] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_017.yaml b/config/splat.ov_SC05_017.yaml index 3248897bcd..cccf58ece7 100644 --- a/config/splat.ov_SC05_017.yaml +++ b/config/splat.ov_SC05_017.yaml @@ -140,30 +140,29 @@ segments: - [0xc2a90, .rodata, ov_SC05_017_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc2aa4, data, tail9] - [0xc2abc, .rodata, ov_SC05_017_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc2b28, data, tail10] - [0xc2b98, .rodata, ov_SC05_017_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc2bdc, .rodata, ov_SC05_017_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc2c24, data, tail11] + - [0xc2c24, data, tail10] - [0xc2c84, .rodata, ov_SC05_017_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc2cb8, data, tail12] + - [0xc2cb8, data, tail11] - [0xc2cbc, .rodata, ov_SC05_017_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc2cd8, data, tail13] + - [0xc2cd8, data, tail12] - [0xc2cdc, .rodata, ov_SC05_017_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc2d18, data, tail14] + - [0xc2d18, data, tail13] - [0xc2d1c, .rodata, ov_SC05_017_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc2d38, data, tail15] + - [0xc2d38, data, tail14] - [0xc2d50, .rodata, ov_SC05_017_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc2d90, data, tail16] + - [0xc2d90, data, tail15] - [0xc2dd0, .rodata, ov_SC05_017_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc2df0, .rodata, ov_SC05_017_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc2e04, data, tail17] + - [0xc2e04, data, tail16] - [0xc2f94, .rodata, ov_SC05_017_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc2fac, .rodata, ov_SC05_017_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc31b0, data, tail18] + - [0xc31b0, data, tail17] - [0xc31b4, .rodata, ov_SC05_017_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3240, data, tail19] + - [0xc3240, data, tail18] - [0xc3244, .rodata, ov_SC05_017_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3278, data, tail20] + - [0xc3278, data, tail19] - [0xC582C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC582F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_018.yaml b/config/splat.ov_SC05_018.yaml index 221ddb1cd0..6c9d053416 100644 --- a/config/splat.ov_SC05_018.yaml +++ b/config/splat.ov_SC05_018.yaml @@ -141,31 +141,30 @@ segments: - [0xbc604, .rodata, ov_SC05_018_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbc618, data, tail9] - [0xbc630, .rodata, ov_SC05_018_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc69c, data, tail10] - [0xbc70c, .rodata, ov_SC05_018_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbc750, .rodata, ov_SC05_018_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc798, data, tail11] + - [0xbc798, data, tail10] - [0xbc7f8, .rodata, ov_SC05_018_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc82c, data, tail12] + - [0xbc82c, data, tail11] - [0xbc830, .rodata, ov_SC05_018_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc84c, data, tail13] + - [0xbc84c, data, tail12] - [0xbc850, .rodata, ov_SC05_018_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc88c, data, tail14] + - [0xbc88c, data, tail13] - [0xbc890, .rodata, ov_SC05_018_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc8ac, data, tail15] + - [0xbc8ac, data, tail14] - [0xbc8c4, .rodata, ov_SC05_018_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc904, data, tail16] + - [0xbc904, data, tail15] - [0xbc944, .rodata, ov_SC05_018_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbc964, .rodata, ov_SC05_018_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc978, data, tail17] + - [0xbc978, data, tail16] - [0xbcb08, .rodata, ov_SC05_018_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbcb20, .rodata, ov_SC05_018_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcd24, data, tail18] + - [0xbcd24, data, tail17] - [0xbcd28, .rodata, ov_SC05_018_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcdb4, data, tail19] + - [0xbcdb4, data, tail18] - [0xbcdb8, .rodata, ov_SC05_018_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbcdcc, .rodata, ov_SC05_018_jr_8017D604] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbcdec, data, tail20] + - [0xbcdec, data, tail19] - [0xBE734, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xBE737] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_019.yaml b/config/splat.ov_SC05_019.yaml index 1a389001ec..fdcffa6d12 100644 --- a/config/splat.ov_SC05_019.yaml +++ b/config/splat.ov_SC05_019.yaml @@ -141,32 +141,31 @@ segments: - [0x65d18, .rodata, ov_SC05_019_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65d2c, data, tail9] - [0x65d44, .rodata, ov_SC05_019_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65db0, data, tail10] - [0x65e20, .rodata, ov_SC05_019_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65e64, .rodata, ov_SC05_019_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65eac, data, tail11] + - [0x65eac, data, tail10] - [0x65f0c, .rodata, ov_SC05_019_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65f40, data, tail12] + - [0x65f40, data, tail11] - [0x65f44, .rodata, ov_SC05_019_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65f60, data, tail13] + - [0x65f60, data, tail12] - [0x65f64, .rodata, ov_SC05_019_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65fa0, data, tail14] + - [0x65fa0, data, tail13] - [0x65fa4, .rodata, ov_SC05_019_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65fc0, data, tail15] + - [0x65fc0, data, tail14] - [0x65fd8, .rodata, ov_SC05_019_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66018, data, tail16] + - [0x66018, data, tail15] - [0x66058, .rodata, ov_SC05_019_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66078, .rodata, ov_SC05_019_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6608c, data, tail17] + - [0x6608c, data, tail16] - [0x6621c, .rodata, ov_SC05_019_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66234, .rodata, ov_SC05_019_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66438, data, tail18] + - [0x66438, data, tail17] - [0x6643c, .rodata, ov_SC05_019_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x664c8, data, tail19] + - [0x664c8, data, tail18] - [0x664cc, .rodata, ov_SC05_019_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x664e0, data, tail20] + - [0x664e0, data, tail19] - [0x66500, .rodata, ov_SC05_019_jr_8017D5C0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66520, data, tail21] + - [0x66520, data, tail20] - [0x679D4, bin, trailing] # final 1 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x679D5] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_000.yaml b/config/splat.ov_SC06_000.yaml index 52e9af3ae5..3756695088 100644 --- a/config/splat.ov_SC06_000.yaml +++ b/config/splat.ov_SC06_000.yaml @@ -140,30 +140,29 @@ segments: - [0x84990, .rodata, ov_SC06_000_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x849a4, data, tail9] - [0x849bc, .rodata, ov_SC06_000_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x84a28, data, tail10] - [0x84a98, .rodata, ov_SC06_000_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x84adc, .rodata, ov_SC06_000_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x84b24, data, tail11] + - [0x84b24, data, tail10] - [0x84b84, .rodata, ov_SC06_000_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x84bb8, data, tail12] + - [0x84bb8, data, tail11] - [0x84bbc, .rodata, ov_SC06_000_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x84bd8, data, tail13] + - [0x84bd8, data, tail12] - [0x84bdc, .rodata, ov_SC06_000_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x84c18, data, tail14] + - [0x84c18, data, tail13] - [0x84c1c, .rodata, ov_SC06_000_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x84c38, data, tail15] + - [0x84c38, data, tail14] - [0x84c50, .rodata, ov_SC06_000_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x84c90, data, tail16] + - [0x84c90, data, tail15] - [0x84cd0, .rodata, ov_SC06_000_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x84cf0, .rodata, ov_SC06_000_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x84d04, data, tail17] + - [0x84d04, data, tail16] - [0x84e94, .rodata, ov_SC06_000_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x84eac, .rodata, ov_SC06_000_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x850b0, data, tail18] + - [0x850b0, data, tail17] - [0x850b4, .rodata, ov_SC06_000_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x85140, data, tail19] + - [0x85140, data, tail18] - [0x85144, .rodata, ov_SC06_000_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x85158, data, tail20] + - [0x85158, data, tail19] - [0x8A02C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x8A02F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_006.yaml b/config/splat.ov_SC06_006.yaml index 89e837c95e..bdb8d3422c 100644 --- a/config/splat.ov_SC06_006.yaml +++ b/config/splat.ov_SC06_006.yaml @@ -141,31 +141,30 @@ segments: - [0xce298, .rodata, ov_SC06_006_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xce2ac, data, tail9] - [0xce2c4, .rodata, ov_SC06_006_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xce330, data, tail10] - [0xce3a0, .rodata, ov_SC06_006_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xce3e4, .rodata, ov_SC06_006_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xce42c, data, tail11] + - [0xce42c, data, tail10] - [0xce48c, .rodata, ov_SC06_006_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xce4c0, data, tail12] + - [0xce4c0, data, tail11] - [0xce4c4, .rodata, ov_SC06_006_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xce4e0, data, tail13] + - [0xce4e0, data, tail12] - [0xce4e4, .rodata, ov_SC06_006_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xce520, data, tail14] + - [0xce520, data, tail13] - [0xce524, .rodata, ov_SC06_006_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xce540, data, tail15] + - [0xce540, data, tail14] - [0xce558, .rodata, ov_SC06_006_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xce598, data, tail16] + - [0xce598, data, tail15] - [0xce5d8, .rodata, ov_SC06_006_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xce5f8, .rodata, ov_SC06_006_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xce60c, data, tail17] + - [0xce60c, data, tail16] - [0xce79c, .rodata, ov_SC06_006_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xce7b4, .rodata, ov_SC06_006_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xce9b8, data, tail18] + - [0xce9b8, data, tail17] - [0xce9bc, .rodata, ov_SC06_006_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcea48, data, tail19] + - [0xcea48, data, tail18] - [0xcea4c, .rodata, ov_SC06_006_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcea60, .rodata, ov_SC06_006_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcea80, data, tail20] + - [0xcea80, data, tail19] - [0xD0A0C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xD0A0F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_008.yaml b/config/splat.ov_SC06_008.yaml index 4462734178..a3b96e5884 100644 --- a/config/splat.ov_SC06_008.yaml +++ b/config/splat.ov_SC06_008.yaml @@ -141,31 +141,30 @@ segments: - [0x80370, .rodata, ov_SC06_008_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x80384, data, tail9] - [0x8039c, .rodata, ov_SC06_008_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80408, data, tail10] - [0x80478, .rodata, ov_SC06_008_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x804bc, .rodata, ov_SC06_008_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80504, data, tail11] + - [0x80504, data, tail10] - [0x80564, .rodata, ov_SC06_008_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80598, data, tail12] + - [0x80598, data, tail11] - [0x8059c, .rodata, ov_SC06_008_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x805b8, data, tail13] + - [0x805b8, data, tail12] - [0x805bc, .rodata, ov_SC06_008_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x805f8, data, tail14] + - [0x805f8, data, tail13] - [0x805fc, .rodata, ov_SC06_008_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80618, data, tail15] + - [0x80618, data, tail14] - [0x80630, .rodata, ov_SC06_008_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80670, data, tail16] + - [0x80670, data, tail15] - [0x806b0, .rodata, ov_SC06_008_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x806d0, .rodata, ov_SC06_008_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x806e4, data, tail17] + - [0x806e4, data, tail16] - [0x80874, .rodata, ov_SC06_008_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8088c, .rodata, ov_SC06_008_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80a90, data, tail18] + - [0x80a90, data, tail17] - [0x80a94, .rodata, ov_SC06_008_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80b20, data, tail19] + - [0x80b20, data, tail18] - [0x80b24, .rodata, ov_SC06_008_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x80b38, .rodata, ov_SC06_008_jr_8017C294] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80b58, data, tail20] + - [0x80b58, data, tail19] - [0x826DC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x826DF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_010.yaml b/config/splat.ov_SC06_010.yaml index 447dd4d60e..5cd66e6f9f 100644 --- a/config/splat.ov_SC06_010.yaml +++ b/config/splat.ov_SC06_010.yaml @@ -139,28 +139,27 @@ segments: - [0x883c4, .rodata, ov_SC06_010_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x883d8, data, tail9] - [0x883f0, .rodata, ov_SC06_010_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8845c, data, tail10] - [0x884cc, .rodata, ov_SC06_010_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x88510, .rodata, ov_SC06_010_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88558, data, tail11] + - [0x88558, data, tail10] - [0x885b8, .rodata, ov_SC06_010_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x885ec, data, tail12] + - [0x885ec, data, tail11] - [0x885f0, .rodata, ov_SC06_010_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8860c, data, tail13] + - [0x8860c, data, tail12] - [0x88610, .rodata, ov_SC06_010_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8864c, data, tail14] + - [0x8864c, data, tail13] - [0x88650, .rodata, ov_SC06_010_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8866c, data, tail15] + - [0x8866c, data, tail14] - [0x88684, .rodata, ov_SC06_010_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x886c4, data, tail16] + - [0x886c4, data, tail15] - [0x88704, .rodata, ov_SC06_010_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x88724, .rodata, ov_SC06_010_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88738, data, tail17] + - [0x88738, data, tail16] - [0x888c8, .rodata, ov_SC06_010_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x888e0, .rodata, ov_SC06_010_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88ae4, data, tail18] + - [0x88ae4, data, tail17] - [0x88ae8, .rodata, ov_SC06_010_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88b8c, data, tail19] + - [0x88b8c, data, tail18] - [0x8AB24, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x8AB27] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_011.yaml b/config/splat.ov_SC06_011.yaml index 8f6e8e09ae..df5772a519 100644 --- a/config/splat.ov_SC06_011.yaml +++ b/config/splat.ov_SC06_011.yaml @@ -141,31 +141,30 @@ segments: - [0x81f24, .rodata, ov_SC06_011_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x81f38, data, tail9] - [0x81f50, .rodata, ov_SC06_011_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x81fbc, data, tail10] - [0x8202c, .rodata, ov_SC06_011_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x82070, .rodata, ov_SC06_011_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x820b8, data, tail11] + - [0x820b8, data, tail10] - [0x82118, .rodata, ov_SC06_011_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8214c, data, tail12] + - [0x8214c, data, tail11] - [0x82150, .rodata, ov_SC06_011_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8216c, data, tail13] + - [0x8216c, data, tail12] - [0x82170, .rodata, ov_SC06_011_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x821ac, data, tail14] + - [0x821ac, data, tail13] - [0x821b0, .rodata, ov_SC06_011_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x821cc, data, tail15] + - [0x821cc, data, tail14] - [0x821e4, .rodata, ov_SC06_011_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82224, data, tail16] + - [0x82224, data, tail15] - [0x82264, .rodata, ov_SC06_011_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x82284, .rodata, ov_SC06_011_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82298, data, tail17] + - [0x82298, data, tail16] - [0x82428, .rodata, ov_SC06_011_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x82440, .rodata, ov_SC06_011_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82644, data, tail18] + - [0x82644, data, tail17] - [0x82648, .rodata, ov_SC06_011_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x826d4, data, tail19] + - [0x826d4, data, tail18] - [0x826d8, .rodata, ov_SC06_011_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x826ec, .rodata, ov_SC06_011_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8270c, data, tail20] + - [0x8270c, data, tail19] - [0x83BFC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x83BFF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_013.yaml b/config/splat.ov_SC06_013.yaml index 9961a5a6f4..0e18a3af10 100644 --- a/config/splat.ov_SC06_013.yaml +++ b/config/splat.ov_SC06_013.yaml @@ -141,31 +141,30 @@ segments: - [0x70df8, .rodata, ov_SC06_013_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70e0c, data, tail9] - [0x70e24, .rodata, ov_SC06_013_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70e90, data, tail10] - [0x70f00, .rodata, ov_SC06_013_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70f44, .rodata, ov_SC06_013_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70f8c, data, tail11] + - [0x70f8c, data, tail10] - [0x70fec, .rodata, ov_SC06_013_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71020, data, tail12] + - [0x71020, data, tail11] - [0x71024, .rodata, ov_SC06_013_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71040, data, tail13] + - [0x71040, data, tail12] - [0x71044, .rodata, ov_SC06_013_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71080, data, tail14] + - [0x71080, data, tail13] - [0x71084, .rodata, ov_SC06_013_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x710a0, data, tail15] + - [0x710a0, data, tail14] - [0x710b8, .rodata, ov_SC06_013_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x710f8, data, tail16] + - [0x710f8, data, tail15] - [0x71138, .rodata, ov_SC06_013_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71158, .rodata, ov_SC06_013_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7116c, data, tail17] + - [0x7116c, data, tail16] - [0x712fc, .rodata, ov_SC06_013_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71314, .rodata, ov_SC06_013_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71518, data, tail18] + - [0x71518, data, tail17] - [0x7151c, .rodata, ov_SC06_013_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x715a8, data, tail19] + - [0x715a8, data, tail18] - [0x715ac, .rodata, ov_SC06_013_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x715c0, .rodata, ov_SC06_013_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x715e0, data, tail20] + - [0x715e0, data, tail19] - [0x72AAC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x72AAF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_014.yaml b/config/splat.ov_SC06_014.yaml index 99816b3577..40375314c4 100644 --- a/config/splat.ov_SC06_014.yaml +++ b/config/splat.ov_SC06_014.yaml @@ -141,31 +141,30 @@ segments: - [0x777e8, .rodata, ov_SC06_014_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x777fc, data, tail9] - [0x77814, .rodata, ov_SC06_014_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77880, data, tail10] - [0x778f0, .rodata, ov_SC06_014_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77934, .rodata, ov_SC06_014_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7797c, data, tail11] + - [0x7797c, data, tail10] - [0x779dc, .rodata, ov_SC06_014_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77a10, data, tail12] + - [0x77a10, data, tail11] - [0x77a14, .rodata, ov_SC06_014_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77a30, data, tail13] + - [0x77a30, data, tail12] - [0x77a34, .rodata, ov_SC06_014_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77a70, data, tail14] + - [0x77a70, data, tail13] - [0x77a74, .rodata, ov_SC06_014_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77a90, data, tail15] + - [0x77a90, data, tail14] - [0x77aa8, .rodata, ov_SC06_014_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77ae8, data, tail16] + - [0x77ae8, data, tail15] - [0x77b28, .rodata, ov_SC06_014_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77b48, .rodata, ov_SC06_014_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77b5c, data, tail17] + - [0x77b5c, data, tail16] - [0x77cec, .rodata, ov_SC06_014_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77d04, .rodata, ov_SC06_014_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77f08, data, tail18] + - [0x77f08, data, tail17] - [0x77f0c, .rodata, ov_SC06_014_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77f98, data, tail19] + - [0x77f98, data, tail18] - [0x77f9c, .rodata, ov_SC06_014_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77fb0, .rodata, ov_SC06_014_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77fd0, data, tail20] + - [0x77fd0, data, tail19] - [0x794C4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x794C7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_015.yaml b/config/splat.ov_SC06_015.yaml index ca528d40e5..0dd895007e 100644 --- a/config/splat.ov_SC06_015.yaml +++ b/config/splat.ov_SC06_015.yaml @@ -141,31 +141,30 @@ segments: - [0x6abc8, .rodata, ov_SC06_015_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6abdc, data, tail9] - [0x6abf4, .rodata, ov_SC06_015_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6ac60, data, tail10] - [0x6acd0, .rodata, ov_SC06_015_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6ad14, .rodata, ov_SC06_015_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6ad5c, data, tail11] + - [0x6ad5c, data, tail10] - [0x6adbc, .rodata, ov_SC06_015_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6adf0, data, tail12] + - [0x6adf0, data, tail11] - [0x6adf4, .rodata, ov_SC06_015_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6ae10, data, tail13] + - [0x6ae10, data, tail12] - [0x6ae14, .rodata, ov_SC06_015_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6ae50, data, tail14] + - [0x6ae50, data, tail13] - [0x6ae54, .rodata, ov_SC06_015_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6ae70, data, tail15] + - [0x6ae70, data, tail14] - [0x6ae88, .rodata, ov_SC06_015_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6aec8, data, tail16] + - [0x6aec8, data, tail15] - [0x6af08, .rodata, ov_SC06_015_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6af28, .rodata, ov_SC06_015_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6af3c, data, tail17] + - [0x6af3c, data, tail16] - [0x6b0cc, .rodata, ov_SC06_015_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b0e4, .rodata, ov_SC06_015_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b2e8, data, tail18] + - [0x6b2e8, data, tail17] - [0x6b2ec, .rodata, ov_SC06_015_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b378, data, tail19] + - [0x6b378, data, tail18] - [0x6b37c, .rodata, ov_SC06_015_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b390, .rodata, ov_SC06_015_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6b3b0, data, tail20] + - [0x6b3b0, data, tail19] - [0x6C8A4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x6C8A7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_016.yaml b/config/splat.ov_SC06_016.yaml index a2a92fb38f..7761827589 100644 --- a/config/splat.ov_SC06_016.yaml +++ b/config/splat.ov_SC06_016.yaml @@ -141,32 +141,31 @@ segments: - [0x75810, .rodata, ov_SC06_016_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x75824, data, tail9] - [0x7583c, .rodata, ov_SC06_016_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x758a8, data, tail10] - [0x75918, .rodata, ov_SC06_016_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7595c, .rodata, ov_SC06_016_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x759a4, data, tail11] + - [0x759a4, data, tail10] - [0x75a04, .rodata, ov_SC06_016_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75a38, data, tail12] + - [0x75a38, data, tail11] - [0x75a3c, .rodata, ov_SC06_016_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75a58, data, tail13] + - [0x75a58, data, tail12] - [0x75a5c, .rodata, ov_SC06_016_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75a98, data, tail14] + - [0x75a98, data, tail13] - [0x75a9c, .rodata, ov_SC06_016_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75ab8, data, tail15] + - [0x75ab8, data, tail14] - [0x75ad0, .rodata, ov_SC06_016_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75b10, data, tail16] + - [0x75b10, data, tail15] - [0x75b50, .rodata, ov_SC06_016_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x75b70, .rodata, ov_SC06_016_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75b84, data, tail17] + - [0x75b84, data, tail16] - [0x75d14, .rodata, ov_SC06_016_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x75d2c, .rodata, ov_SC06_016_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75f30, data, tail18] + - [0x75f30, data, tail17] - [0x75f34, .rodata, ov_SC06_016_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75fc0, data, tail19] + - [0x75fc0, data, tail18] - [0x75fc4, .rodata, ov_SC06_016_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75fd8, data, tail20] + - [0x75fd8, data, tail19] - [0x76110, .rodata, ov_SC06_016_jr_8017C8D0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76130, data, tail21] + - [0x76130, data, tail20] - [0x78114, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x78117] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_018.yaml b/config/splat.ov_SC06_018.yaml index 5a89539298..094ff1bde7 100644 --- a/config/splat.ov_SC06_018.yaml +++ b/config/splat.ov_SC06_018.yaml @@ -143,35 +143,34 @@ segments: - [0xab0a0, .rodata, ov_SC06_018_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xab0b4, data, tail9] - [0xab0cc, .rodata, ov_SC06_018_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab138, data, tail10] - [0xab1a8, .rodata, ov_SC06_018_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xab1ec, .rodata, ov_SC06_018_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab234, data, tail11] + - [0xab234, data, tail10] - [0xab294, .rodata, ov_SC06_018_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab2c8, data, tail12] + - [0xab2c8, data, tail11] - [0xab2cc, .rodata, ov_SC06_018_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab2e8, data, tail13] + - [0xab2e8, data, tail12] - [0xab2ec, .rodata, ov_SC06_018_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab328, data, tail14] + - [0xab328, data, tail13] - [0xab32c, .rodata, ov_SC06_018_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab348, data, tail15] + - [0xab348, data, tail14] - [0xab360, .rodata, ov_SC06_018_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab3a0, data, tail16] + - [0xab3a0, data, tail15] - [0xab3e0, .rodata, ov_SC06_018_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xab400, .rodata, ov_SC06_018_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab414, data, tail17] + - [0xab414, data, tail16] - [0xab5a4, .rodata, ov_SC06_018_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xab5bc, .rodata, ov_SC06_018_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab7c0, data, tail18] + - [0xab7c0, data, tail17] - [0xab7c4, .rodata, ov_SC06_018_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab850, data, tail19] + - [0xab850, data, tail18] - [0xab854, .rodata, ov_SC06_018_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xab868, .rodata, ov_SC06_018_jr_8017C24C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xab888, data, tail20] + - [0xab888, data, tail19] - [0xab9f4, .rodata, ov_SC06_018_jr_8019059C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaba1c, data, tail21] + - [0xaba1c, data, tail20] - [0xaba4c, .rodata, ov_SC06_018_jr_80191C50] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaba7c, data, tail22] + - [0xaba7c, data, tail21] - [0xADA44, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xADA47] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_020.yaml b/config/splat.ov_SC06_020.yaml index 21f526b527..bcf11a1f5c 100644 --- a/config/splat.ov_SC06_020.yaml +++ b/config/splat.ov_SC06_020.yaml @@ -141,31 +141,30 @@ segments: - [0x90988, .rodata, ov_SC06_020_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9099c, data, tail9] - [0x909b4, .rodata, ov_SC06_020_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90a20, data, tail10] - [0x90a90, .rodata, ov_SC06_020_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x90ad4, .rodata, ov_SC06_020_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90b1c, data, tail11] + - [0x90b1c, data, tail10] - [0x90b7c, .rodata, ov_SC06_020_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90bb0, data, tail12] + - [0x90bb0, data, tail11] - [0x90bb4, .rodata, ov_SC06_020_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90bd0, data, tail13] + - [0x90bd0, data, tail12] - [0x90bd4, .rodata, ov_SC06_020_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90c10, data, tail14] + - [0x90c10, data, tail13] - [0x90c14, .rodata, ov_SC06_020_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90c30, data, tail15] + - [0x90c30, data, tail14] - [0x90c48, .rodata, ov_SC06_020_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90c88, data, tail16] + - [0x90c88, data, tail15] - [0x90cc8, .rodata, ov_SC06_020_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x90ce8, .rodata, ov_SC06_020_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90cfc, data, tail17] + - [0x90cfc, data, tail16] - [0x90e8c, .rodata, ov_SC06_020_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x90ea4, .rodata, ov_SC06_020_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x910a8, data, tail18] + - [0x910a8, data, tail17] - [0x910ac, .rodata, ov_SC06_020_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x91138, data, tail19] + - [0x91138, data, tail18] - [0x9113c, .rodata, ov_SC06_020_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x91150, .rodata, ov_SC06_020_jr_8017C24C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x91170, data, tail20] + - [0x91170, data, tail19] - [0x92894, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x92897] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_022.yaml b/config/splat.ov_SC06_022.yaml index 4564b9bf64..e4a574cbc8 100644 --- a/config/splat.ov_SC06_022.yaml +++ b/config/splat.ov_SC06_022.yaml @@ -141,31 +141,30 @@ segments: - [0xb8198, .rodata, ov_SC06_022_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb81ac, data, tail9] - [0xb81c4, .rodata, ov_SC06_022_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8230, data, tail10] - [0xb82a0, .rodata, ov_SC06_022_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb82e4, .rodata, ov_SC06_022_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb832c, data, tail11] + - [0xb832c, data, tail10] - [0xb838c, .rodata, ov_SC06_022_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb83c0, data, tail12] + - [0xb83c0, data, tail11] - [0xb83c4, .rodata, ov_SC06_022_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb83e0, data, tail13] + - [0xb83e0, data, tail12] - [0xb83e4, .rodata, ov_SC06_022_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8420, data, tail14] + - [0xb8420, data, tail13] - [0xb8424, .rodata, ov_SC06_022_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8440, data, tail15] + - [0xb8440, data, tail14] - [0xb8458, .rodata, ov_SC06_022_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8498, data, tail16] + - [0xb8498, data, tail15] - [0xb84d8, .rodata, ov_SC06_022_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb84f8, .rodata, ov_SC06_022_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb850c, data, tail17] + - [0xb850c, data, tail16] - [0xb869c, .rodata, ov_SC06_022_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb86b4, .rodata, ov_SC06_022_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb88b8, data, tail18] + - [0xb88b8, data, tail17] - [0xb88bc, .rodata, ov_SC06_022_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8948, data, tail19] + - [0xb8948, data, tail18] - [0xb894c, .rodata, ov_SC06_022_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb8960, .rodata, ov_SC06_022_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8980, data, tail20] + - [0xb8980, data, tail19] - [0xBA114, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xBA117] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_024.yaml b/config/splat.ov_SC06_024.yaml index 2640601ac4..cf45e58ac3 100644 --- a/config/splat.ov_SC06_024.yaml +++ b/config/splat.ov_SC06_024.yaml @@ -141,31 +141,30 @@ segments: - [0xb72dc, .rodata, ov_SC06_024_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb72f0, data, tail9] - [0xb7308, .rodata, ov_SC06_024_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7374, data, tail10] - [0xb73e4, .rodata, ov_SC06_024_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7428, .rodata, ov_SC06_024_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7470, data, tail11] + - [0xb7470, data, tail10] - [0xb74d0, .rodata, ov_SC06_024_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7504, data, tail12] + - [0xb7504, data, tail11] - [0xb7508, .rodata, ov_SC06_024_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7524, data, tail13] + - [0xb7524, data, tail12] - [0xb7528, .rodata, ov_SC06_024_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7564, data, tail14] + - [0xb7564, data, tail13] - [0xb7568, .rodata, ov_SC06_024_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7584, data, tail15] + - [0xb7584, data, tail14] - [0xb759c, .rodata, ov_SC06_024_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb75dc, data, tail16] + - [0xb75dc, data, tail15] - [0xb761c, .rodata, ov_SC06_024_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb763c, .rodata, ov_SC06_024_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7650, data, tail17] + - [0xb7650, data, tail16] - [0xb77e0, .rodata, ov_SC06_024_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb77f8, .rodata, ov_SC06_024_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb79fc, data, tail18] + - [0xb79fc, data, tail17] - [0xb7a00, .rodata, ov_SC06_024_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7a8c, data, tail19] + - [0xb7a8c, data, tail18] - [0xb7a90, .rodata, ov_SC06_024_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7aa4, .rodata, ov_SC06_024_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7ac4, data, tail20] + - [0xb7ac4, data, tail19] - [0xB980C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xB980F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_025.yaml b/config/splat.ov_SC06_025.yaml index 3a515e77e3..bda2725601 100644 --- a/config/splat.ov_SC06_025.yaml +++ b/config/splat.ov_SC06_025.yaml @@ -141,31 +141,30 @@ segments: - [0x875fc, .rodata, ov_SC06_025_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x87610, data, tail9] - [0x87628, .rodata, ov_SC06_025_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87694, data, tail10] - [0x87704, .rodata, ov_SC06_025_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x87748, .rodata, ov_SC06_025_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87790, data, tail11] + - [0x87790, data, tail10] - [0x877f0, .rodata, ov_SC06_025_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87824, data, tail12] + - [0x87824, data, tail11] - [0x87828, .rodata, ov_SC06_025_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87844, data, tail13] + - [0x87844, data, tail12] - [0x87848, .rodata, ov_SC06_025_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87884, data, tail14] + - [0x87884, data, tail13] - [0x87888, .rodata, ov_SC06_025_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x878a4, data, tail15] + - [0x878a4, data, tail14] - [0x878bc, .rodata, ov_SC06_025_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x878fc, data, tail16] + - [0x878fc, data, tail15] - [0x8793c, .rodata, ov_SC06_025_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8795c, .rodata, ov_SC06_025_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87970, data, tail17] + - [0x87970, data, tail16] - [0x87b00, .rodata, ov_SC06_025_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x87b18, .rodata, ov_SC06_025_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87d1c, data, tail18] + - [0x87d1c, data, tail17] - [0x87d20, .rodata, ov_SC06_025_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87dac, data, tail19] + - [0x87dac, data, tail18] - [0x87db0, .rodata, ov_SC06_025_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x87dc4, .rodata, ov_SC06_025_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87de4, data, tail20] + - [0x87de4, data, tail19] - [0x8A12C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x8A12F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_027.yaml b/config/splat.ov_SC06_027.yaml index 1f946b3520..58ba49ce6c 100644 --- a/config/splat.ov_SC06_027.yaml +++ b/config/splat.ov_SC06_027.yaml @@ -141,31 +141,30 @@ segments: - [0x73638, .rodata, ov_SC06_027_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7364c, data, tail9] - [0x73664, .rodata, ov_SC06_027_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x736d0, data, tail10] - [0x73740, .rodata, ov_SC06_027_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73784, .rodata, ov_SC06_027_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x737cc, data, tail11] + - [0x737cc, data, tail10] - [0x7382c, .rodata, ov_SC06_027_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73860, data, tail12] + - [0x73860, data, tail11] - [0x73864, .rodata, ov_SC06_027_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73880, data, tail13] + - [0x73880, data, tail12] - [0x73884, .rodata, ov_SC06_027_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x738c0, data, tail14] + - [0x738c0, data, tail13] - [0x738c4, .rodata, ov_SC06_027_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x738e0, data, tail15] + - [0x738e0, data, tail14] - [0x738f8, .rodata, ov_SC06_027_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73938, data, tail16] + - [0x73938, data, tail15] - [0x73978, .rodata, ov_SC06_027_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73998, .rodata, ov_SC06_027_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x739ac, data, tail17] + - [0x739ac, data, tail16] - [0x73b3c, .rodata, ov_SC06_027_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73b54, .rodata, ov_SC06_027_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73d58, data, tail18] + - [0x73d58, data, tail17] - [0x73d5c, .rodata, ov_SC06_027_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73de8, data, tail19] + - [0x73de8, data, tail18] - [0x73dec, .rodata, ov_SC06_027_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73e00, .rodata, ov_SC06_027_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73e20, data, tail20] + - [0x73e20, data, tail19] - [0x752D4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x752D7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_029.yaml b/config/splat.ov_SC06_029.yaml index 1e2bfe997e..af612aef1d 100644 --- a/config/splat.ov_SC06_029.yaml +++ b/config/splat.ov_SC06_029.yaml @@ -141,32 +141,31 @@ segments: - [0xb2cb4, .rodata, ov_SC06_029_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb2cc8, data, tail9] - [0xb2ce0, .rodata, ov_SC06_029_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb2d4c, data, tail10] - [0xb2dbc, .rodata, ov_SC06_029_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb2e00, .rodata, ov_SC06_029_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb2e48, data, tail11] + - [0xb2e48, data, tail10] - [0xb2ea8, .rodata, ov_SC06_029_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb2edc, data, tail12] + - [0xb2edc, data, tail11] - [0xb2ee0, .rodata, ov_SC06_029_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb2efc, data, tail13] + - [0xb2efc, data, tail12] - [0xb2f00, .rodata, ov_SC06_029_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb2f3c, data, tail14] + - [0xb2f3c, data, tail13] - [0xb2f40, .rodata, ov_SC06_029_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb2f5c, data, tail15] + - [0xb2f5c, data, tail14] - [0xb2f74, .rodata, ov_SC06_029_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb2fb4, data, tail16] + - [0xb2fb4, data, tail15] - [0xb2ff4, .rodata, ov_SC06_029_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb3014, .rodata, ov_SC06_029_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb3028, data, tail17] + - [0xb3028, data, tail16] - [0xb31b8, .rodata, ov_SC06_029_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb31d0, .rodata, ov_SC06_029_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb33d4, data, tail18] + - [0xb33d4, data, tail17] - [0xb33d8, .rodata, ov_SC06_029_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb3464, data, tail19] + - [0xb3464, data, tail18] - [0xb3468, .rodata, ov_SC06_029_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb347c, data, tail20] + - [0xb347c, data, tail19] - [0xb35b4, .rodata, ov_SC06_029_jr_8017C954] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb35d4, data, tail21] + - [0xb35d4, data, tail20] - [0xBA034, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xBA037] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_030.yaml b/config/splat.ov_SC06_030.yaml index d0a116d83b..8b5b9ecc86 100644 --- a/config/splat.ov_SC06_030.yaml +++ b/config/splat.ov_SC06_030.yaml @@ -141,32 +141,31 @@ segments: - [0x90018, .rodata, ov_SC06_030_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9002c, data, tail9] - [0x90044, .rodata, ov_SC06_030_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x900b0, data, tail10] - [0x90120, .rodata, ov_SC06_030_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x90164, .rodata, ov_SC06_030_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x901ac, data, tail11] + - [0x901ac, data, tail10] - [0x9020c, .rodata, ov_SC06_030_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90240, data, tail12] + - [0x90240, data, tail11] - [0x90244, .rodata, ov_SC06_030_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90260, data, tail13] + - [0x90260, data, tail12] - [0x90264, .rodata, ov_SC06_030_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x902a0, data, tail14] + - [0x902a0, data, tail13] - [0x902a4, .rodata, ov_SC06_030_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x902c0, data, tail15] + - [0x902c0, data, tail14] - [0x902d8, .rodata, ov_SC06_030_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90318, data, tail16] + - [0x90318, data, tail15] - [0x90358, .rodata, ov_SC06_030_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x90378, .rodata, ov_SC06_030_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9038c, data, tail17] + - [0x9038c, data, tail16] - [0x9051c, .rodata, ov_SC06_030_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x90534, .rodata, ov_SC06_030_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90738, data, tail18] + - [0x90738, data, tail17] - [0x9073c, .rodata, ov_SC06_030_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x907c8, data, tail19] + - [0x907c8, data, tail18] - [0x907cc, .rodata, ov_SC06_030_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x907e0, data, tail20] + - [0x907e0, data, tail19] - [0x90918, .rodata, ov_SC06_030_jr_8017C8D0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x90958, data, tail21] + - [0x90958, data, tail20] - [0x91F2C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x91F2F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_032.yaml b/config/splat.ov_SC06_032.yaml index 1473a441f4..a9d35023d0 100644 --- a/config/splat.ov_SC06_032.yaml +++ b/config/splat.ov_SC06_032.yaml @@ -141,31 +141,30 @@ segments: - [0xa6674, .rodata, ov_SC06_032_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6688, data, tail9] - [0xa66a0, .rodata, ov_SC06_032_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa670c, data, tail10] - [0xa677c, .rodata, ov_SC06_032_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa67c0, .rodata, ov_SC06_032_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6808, data, tail11] + - [0xa6808, data, tail10] - [0xa6868, .rodata, ov_SC06_032_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa689c, data, tail12] + - [0xa689c, data, tail11] - [0xa68a0, .rodata, ov_SC06_032_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa68bc, data, tail13] + - [0xa68bc, data, tail12] - [0xa68c0, .rodata, ov_SC06_032_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa68fc, data, tail14] + - [0xa68fc, data, tail13] - [0xa6900, .rodata, ov_SC06_032_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa691c, data, tail15] + - [0xa691c, data, tail14] - [0xa6934, .rodata, ov_SC06_032_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6974, data, tail16] + - [0xa6974, data, tail15] - [0xa69b4, .rodata, ov_SC06_032_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa69d4, .rodata, ov_SC06_032_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa69e8, data, tail17] + - [0xa69e8, data, tail16] - [0xa6b78, .rodata, ov_SC06_032_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6b90, .rodata, ov_SC06_032_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6d94, data, tail18] + - [0xa6d94, data, tail17] - [0xa6d98, .rodata, ov_SC06_032_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6e24, data, tail19] + - [0xa6e24, data, tail18] - [0xa6e28, .rodata, ov_SC06_032_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6e3c, .rodata, ov_SC06_032_jr_8017C24C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6e5c, data, tail20] + - [0xa6e5c, data, tail19] - [0xA9014, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA9017] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_033.yaml b/config/splat.ov_SC06_033.yaml index 299ba76122..634f66f07f 100644 --- a/config/splat.ov_SC06_033.yaml +++ b/config/splat.ov_SC06_033.yaml @@ -141,31 +141,30 @@ segments: - [0xa6728, .rodata, ov_SC06_033_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa673c, data, tail9] - [0xa6754, .rodata, ov_SC06_033_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa67c0, data, tail10] - [0xa6830, .rodata, ov_SC06_033_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6874, .rodata, ov_SC06_033_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa68bc, data, tail11] + - [0xa68bc, data, tail10] - [0xa691c, .rodata, ov_SC06_033_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6950, data, tail12] + - [0xa6950, data, tail11] - [0xa6954, .rodata, ov_SC06_033_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6970, data, tail13] + - [0xa6970, data, tail12] - [0xa6974, .rodata, ov_SC06_033_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa69b0, data, tail14] + - [0xa69b0, data, tail13] - [0xa69b4, .rodata, ov_SC06_033_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa69d0, data, tail15] + - [0xa69d0, data, tail14] - [0xa69e8, .rodata, ov_SC06_033_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6a28, data, tail16] + - [0xa6a28, data, tail15] - [0xa6a68, .rodata, ov_SC06_033_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6a88, .rodata, ov_SC06_033_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6a9c, data, tail17] + - [0xa6a9c, data, tail16] - [0xa6c2c, .rodata, ov_SC06_033_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6c44, .rodata, ov_SC06_033_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6e48, data, tail18] + - [0xa6e48, data, tail17] - [0xa6e4c, .rodata, ov_SC06_033_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6ed8, data, tail19] + - [0xa6ed8, data, tail18] - [0xa6edc, .rodata, ov_SC06_033_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6ef0, .rodata, ov_SC06_033_jr_8017C24C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6f10, data, tail20] + - [0xa6f10, data, tail19] - [0xA8E94, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA8E97] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC07_000.yaml b/config/splat.ov_SC07_000.yaml index 661bc66226..88e7286c52 100644 --- a/config/splat.ov_SC07_000.yaml +++ b/config/splat.ov_SC07_000.yaml @@ -141,31 +141,30 @@ segments: - [0xa5d84, .rodata, ov_SC07_000_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa5d98, data, tail9] - [0xa5db0, .rodata, ov_SC07_000_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa5e1c, data, tail10] - [0xa5e8c, .rodata, ov_SC07_000_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa5ed0, .rodata, ov_SC07_000_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa5f18, data, tail11] + - [0xa5f18, data, tail10] - [0xa5f78, .rodata, ov_SC07_000_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa5fac, data, tail12] + - [0xa5fac, data, tail11] - [0xa5fb0, .rodata, ov_SC07_000_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa5fcc, data, tail13] + - [0xa5fcc, data, tail12] - [0xa5fd0, .rodata, ov_SC07_000_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa600c, data, tail14] + - [0xa600c, data, tail13] - [0xa6010, .rodata, ov_SC07_000_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa602c, data, tail15] + - [0xa602c, data, tail14] - [0xa6044, .rodata, ov_SC07_000_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6084, data, tail16] + - [0xa6084, data, tail15] - [0xa60c4, .rodata, ov_SC07_000_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa60e4, .rodata, ov_SC07_000_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa60f8, data, tail17] + - [0xa60f8, data, tail16] - [0xa6288, .rodata, ov_SC07_000_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa62a0, .rodata, ov_SC07_000_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa64a4, data, tail18] + - [0xa64a4, data, tail17] - [0xa64a8, .rodata, ov_SC07_000_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6534, data, tail19] + - [0xa6534, data, tail18] - [0xa6538, .rodata, ov_SC07_000_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa654c, .rodata, ov_SC07_000_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa656c, data, tail20] + - [0xa656c, data, tail19] - [0xA8B8C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA8B8F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC07_001.yaml b/config/splat.ov_SC07_001.yaml index a0494c3d44..1abe22b47b 100644 --- a/config/splat.ov_SC07_001.yaml +++ b/config/splat.ov_SC07_001.yaml @@ -141,31 +141,30 @@ segments: - [0x80f20, .rodata, ov_SC07_001_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x80f34, data, tail9] - [0x80f4c, .rodata, ov_SC07_001_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80fb8, data, tail10] - [0x81028, .rodata, ov_SC07_001_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8106c, .rodata, ov_SC07_001_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x810b4, data, tail11] + - [0x810b4, data, tail10] - [0x81114, .rodata, ov_SC07_001_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x81148, data, tail12] + - [0x81148, data, tail11] - [0x8114c, .rodata, ov_SC07_001_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x81168, data, tail13] + - [0x81168, data, tail12] - [0x8116c, .rodata, ov_SC07_001_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x811a8, data, tail14] + - [0x811a8, data, tail13] - [0x811ac, .rodata, ov_SC07_001_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x811c8, data, tail15] + - [0x811c8, data, tail14] - [0x811e0, .rodata, ov_SC07_001_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x81220, data, tail16] + - [0x81220, data, tail15] - [0x81260, .rodata, ov_SC07_001_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x81280, .rodata, ov_SC07_001_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x81294, data, tail17] + - [0x81294, data, tail16] - [0x81424, .rodata, ov_SC07_001_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8143c, .rodata, ov_SC07_001_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x81640, data, tail18] + - [0x81640, data, tail17] - [0x81644, .rodata, ov_SC07_001_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x816d0, data, tail19] + - [0x816d0, data, tail18] - [0x816d4, .rodata, ov_SC07_001_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x816e8, .rodata, ov_SC07_001_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x81708, data, tail20] + - [0x81708, data, tail19] - [0x82DB4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x82DB7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC07_002.yaml b/config/splat.ov_SC07_002.yaml index 3b3869eecd..ea65ceb424 100644 --- a/config/splat.ov_SC07_002.yaml +++ b/config/splat.ov_SC07_002.yaml @@ -141,32 +141,31 @@ segments: - [0x71908, .rodata, ov_SC07_002_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7191c, data, tail9] - [0x71934, .rodata, ov_SC07_002_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x719a0, data, tail10] - [0x71a10, .rodata, ov_SC07_002_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71a54, .rodata, ov_SC07_002_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71a9c, data, tail11] + - [0x71a9c, data, tail10] - [0x71afc, .rodata, ov_SC07_002_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71b30, data, tail12] + - [0x71b30, data, tail11] - [0x71b34, .rodata, ov_SC07_002_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71b50, data, tail13] + - [0x71b50, data, tail12] - [0x71b54, .rodata, ov_SC07_002_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71b90, data, tail14] + - [0x71b90, data, tail13] - [0x71b94, .rodata, ov_SC07_002_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71bb0, data, tail15] + - [0x71bb0, data, tail14] - [0x71bc8, .rodata, ov_SC07_002_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71c08, data, tail16] + - [0x71c08, data, tail15] - [0x71c48, .rodata, ov_SC07_002_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71c68, .rodata, ov_SC07_002_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71c7c, data, tail17] + - [0x71c7c, data, tail16] - [0x71e0c, .rodata, ov_SC07_002_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71e24, .rodata, ov_SC07_002_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72028, data, tail18] + - [0x72028, data, tail17] - [0x7202c, .rodata, ov_SC07_002_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x720b8, data, tail19] + - [0x720b8, data, tail18] - [0x720bc, .rodata, ov_SC07_002_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x720d0, data, tail20] + - [0x720d0, data, tail19] - [0x72208, .rodata, ov_SC07_002_jr_8017C8D0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72228, data, tail21] + - [0x72228, data, tail20] - [0x77F7C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x77F7F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC07_006.yaml b/config/splat.ov_SC07_006.yaml index 32aa5b3ac9..f8b2a2e726 100644 --- a/config/splat.ov_SC07_006.yaml +++ b/config/splat.ov_SC07_006.yaml @@ -137,31 +137,30 @@ segments: - [0xcc38c, .rodata, ov_SC07_006_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcc3a0, data, tail10] - [0xcc3b8, .rodata, ov_SC07_006_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcc424, data, tail11] - [0xcc494, .rodata, ov_SC07_006_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcc4d8, .rodata, ov_SC07_006_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcc520, data, tail12] + - [0xcc520, data, tail11] - [0xcc580, .rodata, ov_SC07_006_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcc5b4, data, tail13] + - [0xcc5b4, data, tail12] - [0xcc5b8, .rodata, ov_SC07_006_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcc5f4, data, tail14] + - [0xcc5f4, data, tail13] - [0xcc5f8, .rodata, ov_SC07_006_jr_8015B950] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcc614, data, tail15] + - [0xcc614, data, tail14] - [0xcc618, .rodata, ov_SC07_006_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcc634, data, tail16] + - [0xcc634, data, tail15] - [0xcc66c, .rodata, ov_SC07_006_jr_8016AE5C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcc68c, data, tail17] + - [0xcc68c, data, tail16] - [0xcc6cc, .rodata, ov_SC07_006_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcc6ec, data, tail18] + - [0xcc6ec, data, tail17] - [0xcc890, .rodata, ov_SC07_006_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcc8a8, data, tail19] + - [0xcc8a8, data, tail18] - [0xcca20, .rodata, ov_SC07_006_jr_80179B74] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xccb3c, data, tail20] + - [0xccb3c, data, tail19] - [0xccb40, .rodata, ov_SC07_006_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xccb54, .rodata, ov_SC07_006_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xccb74, data, tail21] + - [0xccb74, data, tail20] - [0xccb8c, .rodata, ov_SC07_006_jr_80183814] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xccbe0, data, tail22] + - [0xccbe0, data, tail21] - [0xCE214, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xCE217] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC07_007.yaml b/config/splat.ov_SC07_007.yaml index 2393cd0352..8c9d6ab7cc 100644 --- a/config/splat.ov_SC07_007.yaml +++ b/config/splat.ov_SC07_007.yaml @@ -136,29 +136,28 @@ segments: - [0x9db68, .rodata, ov_SC07_007_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9db7c, data, tail10] - [0x9db94, .rodata, ov_SC07_007_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9dc00, data, tail11] - [0x9dc70, .rodata, ov_SC07_007_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9dcb4, .rodata, ov_SC07_007_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9dcfc, data, tail12] + - [0x9dcfc, data, tail11] - [0x9dd5c, .rodata, ov_SC07_007_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9dd90, data, tail13] + - [0x9dd90, data, tail12] - [0x9dd94, .rodata, ov_SC07_007_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ddd0, data, tail14] + - [0x9ddd0, data, tail13] - [0x9ddd4, .rodata, ov_SC07_007_jr_8015B950] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9ddf0, data, tail15] + - [0x9ddf0, data, tail14] - [0x9ddf4, .rodata, ov_SC07_007_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9de10, data, tail16] + - [0x9de10, data, tail15] - [0x9de48, .rodata, ov_SC07_007_jr_8016AE5C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9de68, data, tail17] + - [0x9de68, data, tail16] - [0x9dea8, .rodata, ov_SC07_007_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9dec8, data, tail18] + - [0x9dec8, data, tail17] - [0x9e06c, .rodata, ov_SC07_007_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9e084, data, tail19] + - [0x9e084, data, tail18] - [0x9e1fc, .rodata, ov_SC07_007_jr_80179B74] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9e318, data, tail20] + - [0x9e318, data, tail19] - [0x9e31c, .rodata, ov_SC07_007_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9e330, .rodata, ov_SC07_007_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9e350, data, tail21] + - [0x9e350, data, tail20] - [0x9F9DC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x9F9DF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC07_008.yaml b/config/splat.ov_SC07_008.yaml index d7f391de96..f9063c4527 100644 --- a/config/splat.ov_SC07_008.yaml +++ b/config/splat.ov_SC07_008.yaml @@ -141,31 +141,30 @@ segments: - [0x6c958, .rodata, ov_SC07_008_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6c96c, data, tail9] - [0x6c984, .rodata, ov_SC07_008_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c9f0, data, tail10] - [0x6ca60, .rodata, ov_SC07_008_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6caa4, .rodata, ov_SC07_008_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6caec, data, tail11] + - [0x6caec, data, tail10] - [0x6cb4c, .rodata, ov_SC07_008_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cb80, data, tail12] + - [0x6cb80, data, tail11] - [0x6cb84, .rodata, ov_SC07_008_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cba0, data, tail13] + - [0x6cba0, data, tail12] - [0x6cba4, .rodata, ov_SC07_008_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cbe0, data, tail14] + - [0x6cbe0, data, tail13] - [0x6cbe4, .rodata, ov_SC07_008_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cc00, data, tail15] + - [0x6cc00, data, tail14] - [0x6cc18, .rodata, ov_SC07_008_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cc58, data, tail16] + - [0x6cc58, data, tail15] - [0x6cc98, .rodata, ov_SC07_008_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6ccb8, .rodata, ov_SC07_008_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6cccc, data, tail17] + - [0x6cccc, data, tail16] - [0x6ce5c, .rodata, ov_SC07_008_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6ce74, .rodata, ov_SC07_008_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d078, data, tail18] + - [0x6d078, data, tail17] - [0x6d07c, .rodata, ov_SC07_008_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d108, data, tail19] + - [0x6d108, data, tail18] - [0x6d10c, .rodata, ov_SC07_008_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6d120, .rodata, ov_SC07_008_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d140, data, tail20] + - [0x6d140, data, tail19] - [0x6E5EC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x6E5EF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC07_009.yaml b/config/splat.ov_SC07_009.yaml index 821fc398a4..ca9afba014 100644 --- a/config/splat.ov_SC07_009.yaml +++ b/config/splat.ov_SC07_009.yaml @@ -140,30 +140,29 @@ segments: - [0x79fe4, .rodata, ov_SC07_009_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x79ff8, data, tail9] - [0x7a010, .rodata, ov_SC07_009_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a07c, data, tail10] - [0x7a0ec, .rodata, ov_SC07_009_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7a130, .rodata, ov_SC07_009_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a178, data, tail11] + - [0x7a178, data, tail10] - [0x7a1d8, .rodata, ov_SC07_009_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a20c, data, tail12] + - [0x7a20c, data, tail11] - [0x7a210, .rodata, ov_SC07_009_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a22c, data, tail13] + - [0x7a22c, data, tail12] - [0x7a230, .rodata, ov_SC07_009_jr_8015AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a26c, data, tail14] + - [0x7a26c, data, tail13] - [0x7a270, .rodata, ov_SC07_009_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a28c, data, tail15] + - [0x7a28c, data, tail14] - [0x7a2a4, .rodata, ov_SC07_009_jr_8016AB6C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a2e4, data, tail16] + - [0x7a2e4, data, tail15] - [0x7a324, .rodata, ov_SC07_009_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7a344, .rodata, ov_SC07_009_jr_801734BC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a358, data, tail17] + - [0x7a358, data, tail16] - [0x7a4e8, .rodata, ov_SC07_009_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7a500, .rodata, ov_SC07_009_jr_80178D40] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a704, data, tail18] + - [0x7a704, data, tail17] - [0x7a708, .rodata, ov_SC07_009_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a794, data, tail19] + - [0x7a794, data, tail18] - [0x7a798, .rodata, ov_SC07_009_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7a7cc, data, tail20] + - [0x7a7cc, data, tail19] - [0x7BC7C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x7BC7F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC07_010.yaml b/config/splat.ov_SC07_010.yaml index 24850b1f26..5b98d4d490 100644 --- a/config/splat.ov_SC07_010.yaml +++ b/config/splat.ov_SC07_010.yaml @@ -135,28 +135,27 @@ segments: - [0x7e048, .rodata, ov_SC07_010_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7e05c, data, tail10] - [0x7e074, .rodata, ov_SC07_010_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e0e0, data, tail11] - [0x7e150, .rodata, ov_SC07_010_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7e194, .rodata, ov_SC07_010_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e1dc, data, tail12] + - [0x7e1dc, data, tail11] - [0x7e23c, .rodata, ov_SC07_010_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e270, data, tail13] + - [0x7e270, data, tail12] - [0x7e274, .rodata, ov_SC07_010_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e2b0, data, tail14] + - [0x7e2b0, data, tail13] - [0x7e2b4, .rodata, ov_SC07_010_jr_8015B950] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e2d0, data, tail15] + - [0x7e2d0, data, tail14] - [0x7e2d4, .rodata, ov_SC07_010_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e2f0, data, tail16] + - [0x7e2f0, data, tail15] - [0x7e328, .rodata, ov_SC07_010_jr_8016AE5C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e348, data, tail17] + - [0x7e348, data, tail16] - [0x7e388, .rodata, ov_SC07_010_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e3a8, data, tail18] + - [0x7e3a8, data, tail17] - [0x7e54c, .rodata, ov_SC07_010_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e564, data, tail19] + - [0x7e564, data, tail18] - [0x7e6dc, .rodata, ov_SC07_010_jr_80179B74] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e7f8, data, tail20] + - [0x7e7f8, data, tail19] - [0x7e7fc, .rodata, ov_SC07_010_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7e810, data, tail21] + - [0x7e810, data, tail20] - [0x813EC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x813EF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC07_011.yaml b/config/splat.ov_SC07_011.yaml index e70d8b3274..27742f3c28 100644 --- a/config/splat.ov_SC07_011.yaml +++ b/config/splat.ov_SC07_011.yaml @@ -136,29 +136,28 @@ segments: - [0x66710, .rodata, ov_SC07_011_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66724, data, tail10] - [0x6673c, .rodata, ov_SC07_011_jr_8015444C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x667a8, data, tail11] - [0x66818, .rodata, ov_SC07_011_jr_80154C24] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6685c, .rodata, ov_SC07_011_jr_801588CC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x668a4, data, tail12] + - [0x668a4, data, tail11] - [0x66904, .rodata, ov_SC07_011_jr_80159C84] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66938, data, tail13] + - [0x66938, data, tail12] - [0x6693c, .rodata, ov_SC07_011_jr_8015A3C8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66978, data, tail14] + - [0x66978, data, tail13] - [0x6697c, .rodata, ov_SC07_011_jr_8015B950] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66998, data, tail15] + - [0x66998, data, tail14] - [0x6699c, .rodata, ov_SC07_011_jr_8015C32C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x669b8, data, tail16] + - [0x669b8, data, tail15] - [0x669f0, .rodata, ov_SC07_011_jr_8016AE5C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66a10, data, tail17] + - [0x66a10, data, tail16] - [0x66a50, .rodata, ov_SC07_011_jr_80171B4C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66a70, data, tail18] + - [0x66a70, data, tail17] - [0x66c14, .rodata, ov_SC07_011_jr_801789AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66c2c, data, tail19] + - [0x66c2c, data, tail18] - [0x66da4, .rodata, ov_SC07_011_jr_80179B74] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66ec0, data, tail20] + - [0x66ec0, data, tail19] - [0x66ec4, .rodata, ov_SC07_011_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66ed8, .rodata, ov_SC07_011_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66ef8, data, tail21] + - [0x66ef8, data, tail20] - [0x683A4, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x683A7] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/src/ov_SC01_000/ov_SC01_000_jr_8015444C.c b/src/ov_SC01_000/ov_SC01_000_jr_8015444C.c index fc5fe1d878..1e7d491349 100644 --- a/src/ov_SC01_000/ov_SC01_000_jr_8015444C.c +++ b/src/ov_SC01_000/ov_SC01_000_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC01_000/nonmatchings/ov_SC01_000_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC01_001/ov_SC01_001_jr_8015444C.c b/src/ov_SC01_001/ov_SC01_001_jr_8015444C.c index e3d86b682c..f94965d778 100644 --- a/src/ov_SC01_001/ov_SC01_001_jr_8015444C.c +++ b/src/ov_SC01_001/ov_SC01_001_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC01_001/nonmatchings/ov_SC01_001_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC01_004/ov_SC01_004_jr_8015444C.c b/src/ov_SC01_004/ov_SC01_004_jr_8015444C.c index 1d88edec8c..a0898b2e41 100644 --- a/src/ov_SC01_004/ov_SC01_004_jr_8015444C.c +++ b/src/ov_SC01_004/ov_SC01_004_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC01_004/nonmatchings/ov_SC01_004_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC01_005/ov_SC01_005_jr_8015444C.c b/src/ov_SC01_005/ov_SC01_005_jr_8015444C.c index d3535c7fd9..f9bced102f 100644 --- a/src/ov_SC01_005/ov_SC01_005_jr_8015444C.c +++ b/src/ov_SC01_005/ov_SC01_005_jr_8015444C.c @@ -1172,7 +1172,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC01_005/nonmatchings/ov_SC01_005_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC01_006/ov_SC01_006_jr_8015444C.c b/src/ov_SC01_006/ov_SC01_006_jr_8015444C.c index 35fae5cceb..f9bced102f 100644 --- a/src/ov_SC01_006/ov_SC01_006_jr_8015444C.c +++ b/src/ov_SC01_006/ov_SC01_006_jr_8015444C.c @@ -1172,7 +1172,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC01_006/nonmatchings/ov_SC01_006_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC01_008/ov_SC01_008_jr_8015444C.c b/src/ov_SC01_008/ov_SC01_008_jr_8015444C.c index f776584928..7061b95259 100644 --- a/src/ov_SC01_008/ov_SC01_008_jr_8015444C.c +++ b/src/ov_SC01_008/ov_SC01_008_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC01_008/nonmatchings/ov_SC01_008_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC01_009/ov_SC01_009_jr_8015444C.c b/src/ov_SC01_009/ov_SC01_009_jr_8015444C.c index 40e9c438e8..4e6d82df09 100644 --- a/src/ov_SC01_009/ov_SC01_009_jr_8015444C.c +++ b/src/ov_SC01_009/ov_SC01_009_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC01_009/nonmatchings/ov_SC01_009_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC01_074/ov_SC01_074_jr_8015444C.c b/src/ov_SC01_074/ov_SC01_074_jr_8015444C.c index d70ad1ce0e..cd06684968 100644 --- a/src/ov_SC01_074/ov_SC01_074_jr_8015444C.c +++ b/src/ov_SC01_074/ov_SC01_074_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC01_074/nonmatchings/ov_SC01_074_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC01_080/ov_SC01_080_jr_8015444C.c b/src/ov_SC01_080/ov_SC01_080_jr_8015444C.c index 411fc7ecee..57ab40ca40 100644 --- a/src/ov_SC01_080/ov_SC01_080_jr_8015444C.c +++ b/src/ov_SC01_080/ov_SC01_080_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC01_080/nonmatchings/ov_SC01_080_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC01_084/ov_SC01_084_jr_8015444C.c b/src/ov_SC01_084/ov_SC01_084_jr_8015444C.c index c6d0999bd1..7211230bdb 100644 --- a/src/ov_SC01_084/ov_SC01_084_jr_8015444C.c +++ b/src/ov_SC01_084/ov_SC01_084_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC01_084/nonmatchings/ov_SC01_084_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_000/ov_SC02_000_jr_8015444C.c b/src/ov_SC02_000/ov_SC02_000_jr_8015444C.c index 03e2098f80..6875894d53 100644 --- a/src/ov_SC02_000/ov_SC02_000_jr_8015444C.c +++ b/src/ov_SC02_000/ov_SC02_000_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_000/nonmatchings/ov_SC02_000_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_003/ov_SC02_003_jr_8015444C.c b/src/ov_SC02_003/ov_SC02_003_jr_8015444C.c index 21beebf7f9..6875894d53 100644 --- a/src/ov_SC02_003/ov_SC02_003_jr_8015444C.c +++ b/src/ov_SC02_003/ov_SC02_003_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_003/nonmatchings/ov_SC02_003_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_004/ov_SC02_004_jr_8015444C.c b/src/ov_SC02_004/ov_SC02_004_jr_8015444C.c index 94b7292f87..4c2f5cb8aa 100644 --- a/src/ov_SC02_004/ov_SC02_004_jr_8015444C.c +++ b/src/ov_SC02_004/ov_SC02_004_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_004/nonmatchings/ov_SC02_004_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_005/ov_SC02_005_jr_8015444C.c b/src/ov_SC02_005/ov_SC02_005_jr_8015444C.c index cccecb6066..6dcffd1c03 100644 --- a/src/ov_SC02_005/ov_SC02_005_jr_8015444C.c +++ b/src/ov_SC02_005/ov_SC02_005_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_005/nonmatchings/ov_SC02_005_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_011/ov_SC02_011_jr_8015444C.c b/src/ov_SC02_011/ov_SC02_011_jr_8015444C.c index c7d2f6680d..24ee0d462d 100644 --- a/src/ov_SC02_011/ov_SC02_011_jr_8015444C.c +++ b/src/ov_SC02_011/ov_SC02_011_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_011/nonmatchings/ov_SC02_011_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_015/ov_SC02_015_jr_8015444C.c b/src/ov_SC02_015/ov_SC02_015_jr_8015444C.c index 3876755892..97d64ae492 100644 --- a/src/ov_SC02_015/ov_SC02_015_jr_8015444C.c +++ b/src/ov_SC02_015/ov_SC02_015_jr_8015444C.c @@ -1169,7 +1169,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_015/nonmatchings/ov_SC02_015_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_016/ov_SC02_016_jr_8015444C.c b/src/ov_SC02_016/ov_SC02_016_jr_8015444C.c index a898c60661..8fb6d26c0a 100644 --- a/src/ov_SC02_016/ov_SC02_016_jr_8015444C.c +++ b/src/ov_SC02_016/ov_SC02_016_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_016/nonmatchings/ov_SC02_016_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_017/ov_SC02_017_jr_8015444C.c b/src/ov_SC02_017/ov_SC02_017_jr_8015444C.c index 19728fd3e1..173c03c430 100644 --- a/src/ov_SC02_017/ov_SC02_017_jr_8015444C.c +++ b/src/ov_SC02_017/ov_SC02_017_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_017/nonmatchings/ov_SC02_017_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_021/ov_SC02_021_jr_8015444C.c b/src/ov_SC02_021/ov_SC02_021_jr_8015444C.c index 39a1a48571..3a3f8471c5 100644 --- a/src/ov_SC02_021/ov_SC02_021_jr_8015444C.c +++ b/src/ov_SC02_021/ov_SC02_021_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_021/nonmatchings/ov_SC02_021_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_026/ov_SC02_026_jr_8015444C.c b/src/ov_SC02_026/ov_SC02_026_jr_8015444C.c index db639424d8..a9fbd232eb 100644 --- a/src/ov_SC02_026/ov_SC02_026_jr_8015444C.c +++ b/src/ov_SC02_026/ov_SC02_026_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_026/nonmatchings/ov_SC02_026_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_027/ov_SC02_027_jr_8015444C.c b/src/ov_SC02_027/ov_SC02_027_jr_8015444C.c index 664febf336..67c46ee567 100644 --- a/src/ov_SC02_027/ov_SC02_027_jr_8015444C.c +++ b/src/ov_SC02_027/ov_SC02_027_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_027/nonmatchings/ov_SC02_027_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_028/ov_SC02_028_jr_8015444C.c b/src/ov_SC02_028/ov_SC02_028_jr_8015444C.c index 633fc9ea28..7a3f1fa392 100644 --- a/src/ov_SC02_028/ov_SC02_028_jr_8015444C.c +++ b/src/ov_SC02_028/ov_SC02_028_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_028/nonmatchings/ov_SC02_028_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_031/ov_SC02_031_jr_8015444C.c b/src/ov_SC02_031/ov_SC02_031_jr_8015444C.c index 4f3c330e28..be20c38943 100644 --- a/src/ov_SC02_031/ov_SC02_031_jr_8015444C.c +++ b/src/ov_SC02_031/ov_SC02_031_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_031/nonmatchings/ov_SC02_031_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_035/ov_SC02_035_jr_8015444C.c b/src/ov_SC02_035/ov_SC02_035_jr_8015444C.c index c7ffb2e4a5..902c0bdd60 100644 --- a/src/ov_SC02_035/ov_SC02_035_jr_8015444C.c +++ b/src/ov_SC02_035/ov_SC02_035_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_035/nonmatchings/ov_SC02_035_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_039/ov_SC02_039_jr_8015444C.c b/src/ov_SC02_039/ov_SC02_039_jr_8015444C.c index 0ff32caed1..32ce357dfa 100644 --- a/src/ov_SC02_039/ov_SC02_039_jr_8015444C.c +++ b/src/ov_SC02_039/ov_SC02_039_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_039/nonmatchings/ov_SC02_039_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC02_041/ov_SC02_041_jr_8015444C.c b/src/ov_SC02_041/ov_SC02_041_jr_8015444C.c index 8c701fb451..8759b182d6 100644 --- a/src/ov_SC02_041/ov_SC02_041_jr_8015444C.c +++ b/src/ov_SC02_041/ov_SC02_041_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC02_041/nonmatchings/ov_SC02_041_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_001/ov_SC03_001_jr_8015444C.c b/src/ov_SC03_001/ov_SC03_001_jr_8015444C.c index 1131e8a04b..50bd2c7134 100644 --- a/src/ov_SC03_001/ov_SC03_001_jr_8015444C.c +++ b/src/ov_SC03_001/ov_SC03_001_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_002/ov_SC03_002_jr_8015444C.c b/src/ov_SC03_002/ov_SC03_002_jr_8015444C.c index 4583600fcf..f5b2936acb 100644 --- a/src/ov_SC03_002/ov_SC03_002_jr_8015444C.c +++ b/src/ov_SC03_002/ov_SC03_002_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_002/nonmatchings/ov_SC03_002_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_003/ov_SC03_003_jr_8015444C.c b/src/ov_SC03_003/ov_SC03_003_jr_8015444C.c index beea77486e..1c5a5e541f 100644 --- a/src/ov_SC03_003/ov_SC03_003_jr_8015444C.c +++ b/src/ov_SC03_003/ov_SC03_003_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_003/nonmatchings/ov_SC03_003_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_006/ov_SC03_006_jr_8015444C.c b/src/ov_SC03_006/ov_SC03_006_jr_8015444C.c index 63e9b00086..13ae11b6f3 100644 --- a/src/ov_SC03_006/ov_SC03_006_jr_8015444C.c +++ b/src/ov_SC03_006/ov_SC03_006_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_006/nonmatchings/ov_SC03_006_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_007/ov_SC03_007_jr_8015444C.c b/src/ov_SC03_007/ov_SC03_007_jr_8015444C.c index 773b085f46..b5b6180779 100644 --- a/src/ov_SC03_007/ov_SC03_007_jr_8015444C.c +++ b/src/ov_SC03_007/ov_SC03_007_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_007/nonmatchings/ov_SC03_007_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_010/ov_SC03_010_jr_8015444C.c b/src/ov_SC03_010/ov_SC03_010_jr_8015444C.c index 70d3fb1db7..ae07675f55 100644 --- a/src/ov_SC03_010/ov_SC03_010_jr_8015444C.c +++ b/src/ov_SC03_010/ov_SC03_010_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_010/nonmatchings/ov_SC03_010_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_011/ov_SC03_011_jr_8015444C.c b/src/ov_SC03_011/ov_SC03_011_jr_8015444C.c index e77ce4aa62..579738c85b 100644 --- a/src/ov_SC03_011/ov_SC03_011_jr_8015444C.c +++ b/src/ov_SC03_011/ov_SC03_011_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_011/nonmatchings/ov_SC03_011_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_012/ov_SC03_012_jr_8015444C.c b/src/ov_SC03_012/ov_SC03_012_jr_8015444C.c index f4eb7b8a98..fadf1066d8 100644 --- a/src/ov_SC03_012/ov_SC03_012_jr_8015444C.c +++ b/src/ov_SC03_012/ov_SC03_012_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_012/nonmatchings/ov_SC03_012_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_013/ov_SC03_013_jr_8015444C.c b/src/ov_SC03_013/ov_SC03_013_jr_8015444C.c index 97e3e20acc..22a474ffee 100644 --- a/src/ov_SC03_013/ov_SC03_013_jr_8015444C.c +++ b/src/ov_SC03_013/ov_SC03_013_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_013/nonmatchings/ov_SC03_013_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_014/ov_SC03_014_jr_8015444C.c b/src/ov_SC03_014/ov_SC03_014_jr_8015444C.c index 9e1863ff1d..33f3e4261c 100644 --- a/src/ov_SC03_014/ov_SC03_014_jr_8015444C.c +++ b/src/ov_SC03_014/ov_SC03_014_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_014/nonmatchings/ov_SC03_014_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_015/ov_SC03_015_jr_8015444C.c b/src/ov_SC03_015/ov_SC03_015_jr_8015444C.c index 7b65956c90..33f3e4261c 100644 --- a/src/ov_SC03_015/ov_SC03_015_jr_8015444C.c +++ b/src/ov_SC03_015/ov_SC03_015_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_015/nonmatchings/ov_SC03_015_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_023/ov_SC03_023_jr_8015444C.c b/src/ov_SC03_023/ov_SC03_023_jr_8015444C.c index 20955ef420..9f743e2479 100644 --- a/src/ov_SC03_023/ov_SC03_023_jr_8015444C.c +++ b/src/ov_SC03_023/ov_SC03_023_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_023/nonmatchings/ov_SC03_023_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_024/ov_SC03_024_jr_8015444C.c b/src/ov_SC03_024/ov_SC03_024_jr_8015444C.c index 690721df20..99925b85f3 100644 --- a/src/ov_SC03_024/ov_SC03_024_jr_8015444C.c +++ b/src/ov_SC03_024/ov_SC03_024_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_028/ov_SC03_028_jr_8015444C.c b/src/ov_SC03_028/ov_SC03_028_jr_8015444C.c index 0b46295f8f..d61af1cf03 100644 --- a/src/ov_SC03_028/ov_SC03_028_jr_8015444C.c +++ b/src/ov_SC03_028/ov_SC03_028_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_028/nonmatchings/ov_SC03_028_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_029/ov_SC03_029_jr_8015444C.c b/src/ov_SC03_029/ov_SC03_029_jr_8015444C.c index 2b4aa5dbb1..57d679f257 100644 --- a/src/ov_SC03_029/ov_SC03_029_jr_8015444C.c +++ b/src/ov_SC03_029/ov_SC03_029_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_029/nonmatchings/ov_SC03_029_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_030/ov_SC03_030_jr_8015444C.c b/src/ov_SC03_030/ov_SC03_030_jr_8015444C.c index 34d518b233..336578f4b4 100644 --- a/src/ov_SC03_030/ov_SC03_030_jr_8015444C.c +++ b/src/ov_SC03_030/ov_SC03_030_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_030/nonmatchings/ov_SC03_030_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_031/ov_SC03_031_jr_8015444C.c b/src/ov_SC03_031/ov_SC03_031_jr_8015444C.c index 08ff46dc56..773b3ce634 100644 --- a/src/ov_SC03_031/ov_SC03_031_jr_8015444C.c +++ b/src/ov_SC03_031/ov_SC03_031_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_031/nonmatchings/ov_SC03_031_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_089/ov_SC03_089_jr_8015444C.c b/src/ov_SC03_089/ov_SC03_089_jr_8015444C.c index 2d409bd69d..7bae8d6fa7 100644 --- a/src/ov_SC03_089/ov_SC03_089_jr_8015444C.c +++ b/src/ov_SC03_089/ov_SC03_089_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_089/nonmatchings/ov_SC03_089_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_090/ov_SC03_090_jr_8015444C.c b/src/ov_SC03_090/ov_SC03_090_jr_8015444C.c index 359ede31da..ef35aceb69 100644 --- a/src/ov_SC03_090/ov_SC03_090_jr_8015444C.c +++ b/src/ov_SC03_090/ov_SC03_090_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_090/nonmatchings/ov_SC03_090_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_091/ov_SC03_091_jr_8015444C.c b/src/ov_SC03_091/ov_SC03_091_jr_8015444C.c index cfa4b213b7..d52bb7d14b 100644 --- a/src/ov_SC03_091/ov_SC03_091_jr_8015444C.c +++ b/src/ov_SC03_091/ov_SC03_091_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_091/nonmatchings/ov_SC03_091_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_092/ov_SC03_092_jr_8015444C.c b/src/ov_SC03_092/ov_SC03_092_jr_8015444C.c index 6b8e16e210..c9006bc15d 100644 --- a/src/ov_SC03_092/ov_SC03_092_jr_8015444C.c +++ b/src/ov_SC03_092/ov_SC03_092_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_092/nonmatchings/ov_SC03_092_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_093/ov_SC03_093_jr_8015444C.c b/src/ov_SC03_093/ov_SC03_093_jr_8015444C.c index e0325cae00..089ae5444b 100644 --- a/src/ov_SC03_093/ov_SC03_093_jr_8015444C.c +++ b/src/ov_SC03_093/ov_SC03_093_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_093/nonmatchings/ov_SC03_093_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_094/ov_SC03_094_jr_8015444C.c b/src/ov_SC03_094/ov_SC03_094_jr_8015444C.c index 8dc3db7fa8..08ff363874 100644 --- a/src/ov_SC03_094/ov_SC03_094_jr_8015444C.c +++ b/src/ov_SC03_094/ov_SC03_094_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_094/nonmatchings/ov_SC03_094_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_095/ov_SC03_095_jr_8015444C.c b/src/ov_SC03_095/ov_SC03_095_jr_8015444C.c index 97f7e8029c..a07b9b4f9e 100644 --- a/src/ov_SC03_095/ov_SC03_095_jr_8015444C.c +++ b/src/ov_SC03_095/ov_SC03_095_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_095/nonmatchings/ov_SC03_095_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_096/ov_SC03_096_jr_8015444C.c b/src/ov_SC03_096/ov_SC03_096_jr_8015444C.c index 2568424a71..610a97d179 100644 --- a/src/ov_SC03_096/ov_SC03_096_jr_8015444C.c +++ b/src/ov_SC03_096/ov_SC03_096_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_096/nonmatchings/ov_SC03_096_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_097/ov_SC03_097_jr_8015444C.c b/src/ov_SC03_097/ov_SC03_097_jr_8015444C.c index 1b9e21dccf..21d31f3268 100644 --- a/src/ov_SC03_097/ov_SC03_097_jr_8015444C.c +++ b/src/ov_SC03_097/ov_SC03_097_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_097/nonmatchings/ov_SC03_097_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_098/ov_SC03_098_jr_8015444C.c b/src/ov_SC03_098/ov_SC03_098_jr_8015444C.c index 183a92afe8..8cb3eed2a6 100644 --- a/src/ov_SC03_098/ov_SC03_098_jr_8015444C.c +++ b/src/ov_SC03_098/ov_SC03_098_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_098/nonmatchings/ov_SC03_098_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_099/ov_SC03_099_jr_8015444C.c b/src/ov_SC03_099/ov_SC03_099_jr_8015444C.c index 4230b334c2..50e72c1385 100644 --- a/src/ov_SC03_099/ov_SC03_099_jr_8015444C.c +++ b/src/ov_SC03_099/ov_SC03_099_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_099/nonmatchings/ov_SC03_099_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_100/ov_SC03_100_jr_8015444C.c b/src/ov_SC03_100/ov_SC03_100_jr_8015444C.c index 4c23361f91..487d0f647c 100644 --- a/src/ov_SC03_100/ov_SC03_100_jr_8015444C.c +++ b/src/ov_SC03_100/ov_SC03_100_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_100/nonmatchings/ov_SC03_100_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_101/ov_SC03_101_jr_8015444C.c b/src/ov_SC03_101/ov_SC03_101_jr_8015444C.c index c6557468b4..43edbd0b3c 100644 --- a/src/ov_SC03_101/ov_SC03_101_jr_8015444C.c +++ b/src/ov_SC03_101/ov_SC03_101_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_102/ov_SC03_102_jr_8015444C.c b/src/ov_SC03_102/ov_SC03_102_jr_8015444C.c index ccc19e3cd2..a7af8b52ce 100644 --- a/src/ov_SC03_102/ov_SC03_102_jr_8015444C.c +++ b/src/ov_SC03_102/ov_SC03_102_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_102/nonmatchings/ov_SC03_102_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_103/ov_SC03_103_jr_8015444C.c b/src/ov_SC03_103/ov_SC03_103_jr_8015444C.c index a1ca7fc633..0f2ff88175 100644 --- a/src/ov_SC03_103/ov_SC03_103_jr_8015444C.c +++ b/src/ov_SC03_103/ov_SC03_103_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_103/nonmatchings/ov_SC03_103_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_104/ov_SC03_104_jr_8015444C.c b/src/ov_SC03_104/ov_SC03_104_jr_8015444C.c index 2585f92d35..94a5f20c11 100644 --- a/src/ov_SC03_104/ov_SC03_104_jr_8015444C.c +++ b/src/ov_SC03_104/ov_SC03_104_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_105/ov_SC03_105_jr_8015444C.c b/src/ov_SC03_105/ov_SC03_105_jr_8015444C.c index 538f89b5b4..d298eca5bc 100644 --- a/src/ov_SC03_105/ov_SC03_105_jr_8015444C.c +++ b/src/ov_SC03_105/ov_SC03_105_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_105/nonmatchings/ov_SC03_105_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_108/ov_SC03_108_jr_8015444C.c b/src/ov_SC03_108/ov_SC03_108_jr_8015444C.c index 436fbc885d..f225c1d6ac 100644 --- a/src/ov_SC03_108/ov_SC03_108_jr_8015444C.c +++ b/src/ov_SC03_108/ov_SC03_108_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_108/nonmatchings/ov_SC03_108_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_109/ov_SC03_109_jr_8015444C.c b/src/ov_SC03_109/ov_SC03_109_jr_8015444C.c index a3e7baf0cd..636303cce5 100644 --- a/src/ov_SC03_109/ov_SC03_109_jr_8015444C.c +++ b/src/ov_SC03_109/ov_SC03_109_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_109/nonmatchings/ov_SC03_109_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_110/ov_SC03_110_jr_8015444C.c b/src/ov_SC03_110/ov_SC03_110_jr_8015444C.c index f034868202..a756b16c93 100644 --- a/src/ov_SC03_110/ov_SC03_110_jr_8015444C.c +++ b/src/ov_SC03_110/ov_SC03_110_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_110/nonmatchings/ov_SC03_110_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_111/ov_SC03_111_jr_8015444C.c b/src/ov_SC03_111/ov_SC03_111_jr_8015444C.c index 5ff3d526e4..638634ba86 100644 --- a/src/ov_SC03_111/ov_SC03_111_jr_8015444C.c +++ b/src/ov_SC03_111/ov_SC03_111_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_111/nonmatchings/ov_SC03_111_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_112/ov_SC03_112_jr_8015444C.c b/src/ov_SC03_112/ov_SC03_112_jr_8015444C.c index 24a8ecff8e..722535df4f 100644 --- a/src/ov_SC03_112/ov_SC03_112_jr_8015444C.c +++ b/src/ov_SC03_112/ov_SC03_112_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_112/nonmatchings/ov_SC03_112_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_113/ov_SC03_113_jr_8015444C.c b/src/ov_SC03_113/ov_SC03_113_jr_8015444C.c index af1ac9ab23..82c3feb42c 100644 --- a/src/ov_SC03_113/ov_SC03_113_jr_8015444C.c +++ b/src/ov_SC03_113/ov_SC03_113_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_113/nonmatchings/ov_SC03_113_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_114/ov_SC03_114_jr_8015444C.c b/src/ov_SC03_114/ov_SC03_114_jr_8015444C.c index 7e335f24d7..7a2d3315d6 100644 --- a/src/ov_SC03_114/ov_SC03_114_jr_8015444C.c +++ b/src/ov_SC03_114/ov_SC03_114_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_114/nonmatchings/ov_SC03_114_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_115/ov_SC03_115_jr_8015444C.c b/src/ov_SC03_115/ov_SC03_115_jr_8015444C.c index 09ece2d707..5398ca60c9 100644 --- a/src/ov_SC03_115/ov_SC03_115_jr_8015444C.c +++ b/src/ov_SC03_115/ov_SC03_115_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_115/nonmatchings/ov_SC03_115_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_116/ov_SC03_116_jr_8015444C.c b/src/ov_SC03_116/ov_SC03_116_jr_8015444C.c index b7cfc97211..40283502d2 100644 --- a/src/ov_SC03_116/ov_SC03_116_jr_8015444C.c +++ b/src/ov_SC03_116/ov_SC03_116_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_116/nonmatchings/ov_SC03_116_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_117/ov_SC03_117_jr_8015444C.c b/src/ov_SC03_117/ov_SC03_117_jr_8015444C.c index d158d061b3..dc358754c9 100644 --- a/src/ov_SC03_117/ov_SC03_117_jr_8015444C.c +++ b/src/ov_SC03_117/ov_SC03_117_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_117/nonmatchings/ov_SC03_117_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_118/ov_SC03_118_jr_8015444C.c b/src/ov_SC03_118/ov_SC03_118_jr_8015444C.c index 6ef7a86cbc..64e8a08485 100644 --- a/src/ov_SC03_118/ov_SC03_118_jr_8015444C.c +++ b/src/ov_SC03_118/ov_SC03_118_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_118/nonmatchings/ov_SC03_118_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_119/ov_SC03_119_jr_8015444C.c b/src/ov_SC03_119/ov_SC03_119_jr_8015444C.c index aef803a261..64e8a08485 100644 --- a/src/ov_SC03_119/ov_SC03_119_jr_8015444C.c +++ b/src/ov_SC03_119/ov_SC03_119_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_119/nonmatchings/ov_SC03_119_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_121/ov_SC03_121_jr_8015444C.c b/src/ov_SC03_121/ov_SC03_121_jr_8015444C.c index 6a4d864c3f..f786185015 100644 --- a/src/ov_SC03_121/ov_SC03_121_jr_8015444C.c +++ b/src/ov_SC03_121/ov_SC03_121_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_121/nonmatchings/ov_SC03_121_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_124/ov_SC03_124_jr_8015444C.c b/src/ov_SC03_124/ov_SC03_124_jr_8015444C.c index 1310fd2a3b..d6d5b1d824 100644 --- a/src/ov_SC03_124/ov_SC03_124_jr_8015444C.c +++ b/src/ov_SC03_124/ov_SC03_124_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_125/ov_SC03_125_jr_8015444C.c b/src/ov_SC03_125/ov_SC03_125_jr_8015444C.c index 282bc78e75..18f2ddba25 100644 --- a/src/ov_SC03_125/ov_SC03_125_jr_8015444C.c +++ b/src/ov_SC03_125/ov_SC03_125_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_125/nonmatchings/ov_SC03_125_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC03_126/ov_SC03_126_jr_8015444C.c b/src/ov_SC03_126/ov_SC03_126_jr_8015444C.c index 4930023890..e3e0a9b7a9 100644 --- a/src/ov_SC03_126/ov_SC03_126_jr_8015444C.c +++ b/src/ov_SC03_126/ov_SC03_126_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC03_126/nonmatchings/ov_SC03_126_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_000/ov_SC04_000_jr_8015444C.c b/src/ov_SC04_000/ov_SC04_000_jr_8015444C.c index 40baf23af1..f61bd640e8 100644 --- a/src/ov_SC04_000/ov_SC04_000_jr_8015444C.c +++ b/src/ov_SC04_000/ov_SC04_000_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_000/nonmatchings/ov_SC04_000_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_002/ov_SC04_002_jr_8015444C.c b/src/ov_SC04_002/ov_SC04_002_jr_8015444C.c index 4361ab169c..d644e8b828 100644 --- a/src/ov_SC04_002/ov_SC04_002_jr_8015444C.c +++ b/src/ov_SC04_002/ov_SC04_002_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_002/nonmatchings/ov_SC04_002_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_003/ov_SC04_003_jr_8015444C.c b/src/ov_SC04_003/ov_SC04_003_jr_8015444C.c index 31bfe3670a..9a32baf970 100644 --- a/src/ov_SC04_003/ov_SC04_003_jr_8015444C.c +++ b/src/ov_SC04_003/ov_SC04_003_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_004/ov_SC04_004_jr_8015444C.c b/src/ov_SC04_004/ov_SC04_004_jr_8015444C.c index 0adf805cb9..709bf08599 100644 --- a/src/ov_SC04_004/ov_SC04_004_jr_8015444C.c +++ b/src/ov_SC04_004/ov_SC04_004_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_004/nonmatchings/ov_SC04_004_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_005/ov_SC04_005_jr_8015444C.c b/src/ov_SC04_005/ov_SC04_005_jr_8015444C.c index ea1c5988ba..e9118b444f 100644 --- a/src/ov_SC04_005/ov_SC04_005_jr_8015444C.c +++ b/src/ov_SC04_005/ov_SC04_005_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_006/ov_SC04_006_jr_8015444C.c b/src/ov_SC04_006/ov_SC04_006_jr_8015444C.c index e39b77d84f..aecfc36766 100644 --- a/src/ov_SC04_006/ov_SC04_006_jr_8015444C.c +++ b/src/ov_SC04_006/ov_SC04_006_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_006/nonmatchings/ov_SC04_006_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_007/ov_SC04_007_jr_8015444C.c b/src/ov_SC04_007/ov_SC04_007_jr_8015444C.c index 5a0fbbf828..63d64a6d4e 100644 --- a/src/ov_SC04_007/ov_SC04_007_jr_8015444C.c +++ b/src/ov_SC04_007/ov_SC04_007_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_008/ov_SC04_008_jr_8015444C.c b/src/ov_SC04_008/ov_SC04_008_jr_8015444C.c index a8e58d9f3f..fb0f80b014 100644 --- a/src/ov_SC04_008/ov_SC04_008_jr_8015444C.c +++ b/src/ov_SC04_008/ov_SC04_008_jr_8015444C.c @@ -1193,7 +1193,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_008/nonmatchings/ov_SC04_008_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_009/ov_SC04_009_jr_8015444C.c b/src/ov_SC04_009/ov_SC04_009_jr_8015444C.c index bb48a496f2..aa7c48f743 100644 --- a/src/ov_SC04_009/ov_SC04_009_jr_8015444C.c +++ b/src/ov_SC04_009/ov_SC04_009_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_009/nonmatchings/ov_SC04_009_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_010/ov_SC04_010_jr_8015444C.c b/src/ov_SC04_010/ov_SC04_010_jr_8015444C.c index b09ae77c1e..3de4cde614 100644 --- a/src/ov_SC04_010/ov_SC04_010_jr_8015444C.c +++ b/src/ov_SC04_010/ov_SC04_010_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_010/nonmatchings/ov_SC04_010_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_011/ov_SC04_011_jr_8015444C.c b/src/ov_SC04_011/ov_SC04_011_jr_8015444C.c index 1e79240b07..5683b84b60 100644 --- a/src/ov_SC04_011/ov_SC04_011_jr_8015444C.c +++ b/src/ov_SC04_011/ov_SC04_011_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_011/nonmatchings/ov_SC04_011_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_012/ov_SC04_012_jr_8015444C.c b/src/ov_SC04_012/ov_SC04_012_jr_8015444C.c index c166f23772..2584186ad0 100644 --- a/src/ov_SC04_012/ov_SC04_012_jr_8015444C.c +++ b/src/ov_SC04_012/ov_SC04_012_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_012/nonmatchings/ov_SC04_012_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_015/ov_SC04_015_jr_8015444C.c b/src/ov_SC04_015/ov_SC04_015_jr_8015444C.c index 37d1c4297c..e521f34daa 100644 --- a/src/ov_SC04_015/ov_SC04_015_jr_8015444C.c +++ b/src/ov_SC04_015/ov_SC04_015_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_015/nonmatchings/ov_SC04_015_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_016/ov_SC04_016_jr_8015444C.c b/src/ov_SC04_016/ov_SC04_016_jr_8015444C.c index a73583c8d0..a94a898c58 100644 --- a/src/ov_SC04_016/ov_SC04_016_jr_8015444C.c +++ b/src/ov_SC04_016/ov_SC04_016_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_016/nonmatchings/ov_SC04_016_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_018/ov_SC04_018_jr_8015444C.c b/src/ov_SC04_018/ov_SC04_018_jr_8015444C.c index f6c4ba3a9d..f9b0877465 100644 --- a/src/ov_SC04_018/ov_SC04_018_jr_8015444C.c +++ b/src/ov_SC04_018/ov_SC04_018_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_018/nonmatchings/ov_SC04_018_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_019/ov_SC04_019_jr_8015444C.c b/src/ov_SC04_019/ov_SC04_019_jr_8015444C.c index db638bacc5..f9b0877465 100644 --- a/src/ov_SC04_019/ov_SC04_019_jr_8015444C.c +++ b/src/ov_SC04_019/ov_SC04_019_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_019/nonmatchings/ov_SC04_019_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_020/ov_SC04_020_jr_8015444C.c b/src/ov_SC04_020/ov_SC04_020_jr_8015444C.c index 4ef8adfbe4..9bb0679334 100644 --- a/src/ov_SC04_020/ov_SC04_020_jr_8015444C.c +++ b/src/ov_SC04_020/ov_SC04_020_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_020/nonmatchings/ov_SC04_020_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC04_021/ov_SC04_021_jr_8015444C.c b/src/ov_SC04_021/ov_SC04_021_jr_8015444C.c index 0891929da2..e3e0a9b7a9 100644 --- a/src/ov_SC04_021/ov_SC04_021_jr_8015444C.c +++ b/src/ov_SC04_021/ov_SC04_021_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC04_021/nonmatchings/ov_SC04_021_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_000/ov_SC05_000_jr_8015444C.c b/src/ov_SC05_000/ov_SC05_000_jr_8015444C.c index d4e72e4f4b..7a6b925628 100644 --- a/src/ov_SC05_000/ov_SC05_000_jr_8015444C.c +++ b/src/ov_SC05_000/ov_SC05_000_jr_8015444C.c @@ -1169,7 +1169,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_000/nonmatchings/ov_SC05_000_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_001/ov_SC05_001_jr_8015444C.c b/src/ov_SC05_001/ov_SC05_001_jr_8015444C.c index 28aec74685..ac4f962c58 100644 --- a/src/ov_SC05_001/ov_SC05_001_jr_8015444C.c +++ b/src/ov_SC05_001/ov_SC05_001_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_001/nonmatchings/ov_SC05_001_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_002/ov_SC05_002_jr_8015444C.c b/src/ov_SC05_002/ov_SC05_002_jr_8015444C.c index 9b2fdeca8c..6895c764a4 100644 --- a/src/ov_SC05_002/ov_SC05_002_jr_8015444C.c +++ b/src/ov_SC05_002/ov_SC05_002_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_002/nonmatchings/ov_SC05_002_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_003/ov_SC05_003_jr_8015444C.c b/src/ov_SC05_003/ov_SC05_003_jr_8015444C.c index 5b66d17353..0fe84e5700 100644 --- a/src/ov_SC05_003/ov_SC05_003_jr_8015444C.c +++ b/src/ov_SC05_003/ov_SC05_003_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_003/nonmatchings/ov_SC05_003_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_004/ov_SC05_004_jr_8015444C.c b/src/ov_SC05_004/ov_SC05_004_jr_8015444C.c index 38ed827111..6696bc6707 100644 --- a/src/ov_SC05_004/ov_SC05_004_jr_8015444C.c +++ b/src/ov_SC05_004/ov_SC05_004_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_004/nonmatchings/ov_SC05_004_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_005/ov_SC05_005_jr_8015444C.c b/src/ov_SC05_005/ov_SC05_005_jr_8015444C.c index 909cb741b4..6339ba670f 100644 --- a/src/ov_SC05_005/ov_SC05_005_jr_8015444C.c +++ b/src/ov_SC05_005/ov_SC05_005_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_005/nonmatchings/ov_SC05_005_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_006/ov_SC05_006_jr_8015444C.c b/src/ov_SC05_006/ov_SC05_006_jr_8015444C.c index c8d5057558..6fef748e20 100644 --- a/src/ov_SC05_006/ov_SC05_006_jr_8015444C.c +++ b/src/ov_SC05_006/ov_SC05_006_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_006/nonmatchings/ov_SC05_006_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_007/ov_SC05_007_jr_8015444C.c b/src/ov_SC05_007/ov_SC05_007_jr_8015444C.c index 1a279dcec0..03f913e18c 100644 --- a/src/ov_SC05_007/ov_SC05_007_jr_8015444C.c +++ b/src/ov_SC05_007/ov_SC05_007_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_007/nonmatchings/ov_SC05_007_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_008/ov_SC05_008_jr_8015444C.c b/src/ov_SC05_008/ov_SC05_008_jr_8015444C.c index 876dedfa06..84765d12d9 100644 --- a/src/ov_SC05_008/ov_SC05_008_jr_8015444C.c +++ b/src/ov_SC05_008/ov_SC05_008_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_008/nonmatchings/ov_SC05_008_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_009/ov_SC05_009_jr_8015444C.c b/src/ov_SC05_009/ov_SC05_009_jr_8015444C.c index 6beca8c139..d44d63f3f3 100644 --- a/src/ov_SC05_009/ov_SC05_009_jr_8015444C.c +++ b/src/ov_SC05_009/ov_SC05_009_jr_8015444C.c @@ -1193,7 +1193,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_009/nonmatchings/ov_SC05_009_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_010/ov_SC05_010_jr_8015444C.c b/src/ov_SC05_010/ov_SC05_010_jr_8015444C.c index 5eff04f29a..0f20767af4 100644 --- a/src/ov_SC05_010/ov_SC05_010_jr_8015444C.c +++ b/src/ov_SC05_010/ov_SC05_010_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_010/nonmatchings/ov_SC05_010_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_011/ov_SC05_011_jr_8015444C.c b/src/ov_SC05_011/ov_SC05_011_jr_8015444C.c index a95cd90c98..fd753b2472 100644 --- a/src/ov_SC05_011/ov_SC05_011_jr_8015444C.c +++ b/src/ov_SC05_011/ov_SC05_011_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_011/nonmatchings/ov_SC05_011_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_017/ov_SC05_017_jr_8015444C.c b/src/ov_SC05_017/ov_SC05_017_jr_8015444C.c index c5b4b3cf79..a98e19d85f 100644 --- a/src/ov_SC05_017/ov_SC05_017_jr_8015444C.c +++ b/src/ov_SC05_017/ov_SC05_017_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_017/nonmatchings/ov_SC05_017_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_018/ov_SC05_018_jr_8015444C.c b/src/ov_SC05_018/ov_SC05_018_jr_8015444C.c index b367e38926..bb322fa4e8 100644 --- a/src/ov_SC05_018/ov_SC05_018_jr_8015444C.c +++ b/src/ov_SC05_018/ov_SC05_018_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_018/nonmatchings/ov_SC05_018_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC05_019/ov_SC05_019_jr_8015444C.c b/src/ov_SC05_019/ov_SC05_019_jr_8015444C.c index 47718141f0..e3e0a9b7a9 100644 --- a/src/ov_SC05_019/ov_SC05_019_jr_8015444C.c +++ b/src/ov_SC05_019/ov_SC05_019_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC05_019/nonmatchings/ov_SC05_019_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_000/ov_SC06_000_jr_8015444C.c b/src/ov_SC06_000/ov_SC06_000_jr_8015444C.c index 20f9a8088e..875cd6827b 100644 --- a/src/ov_SC06_000/ov_SC06_000_jr_8015444C.c +++ b/src/ov_SC06_000/ov_SC06_000_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_000/nonmatchings/ov_SC06_000_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_006/ov_SC06_006_jr_8015444C.c b/src/ov_SC06_006/ov_SC06_006_jr_8015444C.c index 9e90e19b50..a0d995fda9 100644 --- a/src/ov_SC06_006/ov_SC06_006_jr_8015444C.c +++ b/src/ov_SC06_006/ov_SC06_006_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_006/nonmatchings/ov_SC06_006_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_008/ov_SC06_008_jr_8015444C.c b/src/ov_SC06_008/ov_SC06_008_jr_8015444C.c index 2aea05f370..8fa4c0a574 100644 --- a/src/ov_SC06_008/ov_SC06_008_jr_8015444C.c +++ b/src/ov_SC06_008/ov_SC06_008_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_010/ov_SC06_010_jr_8015444C.c b/src/ov_SC06_010/ov_SC06_010_jr_8015444C.c index 7c644ed2c0..8bdc29aae2 100644 --- a/src/ov_SC06_010/ov_SC06_010_jr_8015444C.c +++ b/src/ov_SC06_010/ov_SC06_010_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_011/ov_SC06_011_jr_8015444C.c b/src/ov_SC06_011/ov_SC06_011_jr_8015444C.c index 3919620b71..91e65096e1 100644 --- a/src/ov_SC06_011/ov_SC06_011_jr_8015444C.c +++ b/src/ov_SC06_011/ov_SC06_011_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_011/nonmatchings/ov_SC06_011_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_013/ov_SC06_013_jr_8015444C.c b/src/ov_SC06_013/ov_SC06_013_jr_8015444C.c index 7c614d34eb..9d064d65d1 100644 --- a/src/ov_SC06_013/ov_SC06_013_jr_8015444C.c +++ b/src/ov_SC06_013/ov_SC06_013_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_013/nonmatchings/ov_SC06_013_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_014/ov_SC06_014_jr_8015444C.c b/src/ov_SC06_014/ov_SC06_014_jr_8015444C.c index 1cf4c7c754..b173b20d08 100644 --- a/src/ov_SC06_014/ov_SC06_014_jr_8015444C.c +++ b/src/ov_SC06_014/ov_SC06_014_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_014/nonmatchings/ov_SC06_014_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_015/ov_SC06_015_jr_8015444C.c b/src/ov_SC06_015/ov_SC06_015_jr_8015444C.c index d1613b6cf8..c412178b97 100644 --- a/src/ov_SC06_015/ov_SC06_015_jr_8015444C.c +++ b/src/ov_SC06_015/ov_SC06_015_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_015/nonmatchings/ov_SC06_015_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_016/ov_SC06_016_jr_8015444C.c b/src/ov_SC06_016/ov_SC06_016_jr_8015444C.c index fafbf66c59..ba788b23c5 100644 --- a/src/ov_SC06_016/ov_SC06_016_jr_8015444C.c +++ b/src/ov_SC06_016/ov_SC06_016_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_016/nonmatchings/ov_SC06_016_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_018/ov_SC06_018_jr_8015444C.c b/src/ov_SC06_018/ov_SC06_018_jr_8015444C.c index 2d88748cde..bd0c9f4434 100644 --- a/src/ov_SC06_018/ov_SC06_018_jr_8015444C.c +++ b/src/ov_SC06_018/ov_SC06_018_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_020/ov_SC06_020_jr_8015444C.c b/src/ov_SC06_020/ov_SC06_020_jr_8015444C.c index dac0471b1b..a7d4b9337f 100644 --- a/src/ov_SC06_020/ov_SC06_020_jr_8015444C.c +++ b/src/ov_SC06_020/ov_SC06_020_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_020/nonmatchings/ov_SC06_020_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_022/ov_SC06_022_jr_8015444C.c b/src/ov_SC06_022/ov_SC06_022_jr_8015444C.c index 135bc61490..49227131f8 100644 --- a/src/ov_SC06_022/ov_SC06_022_jr_8015444C.c +++ b/src/ov_SC06_022/ov_SC06_022_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_024/ov_SC06_024_jr_8015444C.c b/src/ov_SC06_024/ov_SC06_024_jr_8015444C.c index d57a5b1ca8..f72e45212f 100644 --- a/src/ov_SC06_024/ov_SC06_024_jr_8015444C.c +++ b/src/ov_SC06_024/ov_SC06_024_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_025/ov_SC06_025_jr_8015444C.c b/src/ov_SC06_025/ov_SC06_025_jr_8015444C.c index 9bf34180d2..ce9c738d92 100644 --- a/src/ov_SC06_025/ov_SC06_025_jr_8015444C.c +++ b/src/ov_SC06_025/ov_SC06_025_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_025/nonmatchings/ov_SC06_025_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_027/ov_SC06_027_jr_8015444C.c b/src/ov_SC06_027/ov_SC06_027_jr_8015444C.c index 46c7e3e618..9a15d1f023 100644 --- a/src/ov_SC06_027/ov_SC06_027_jr_8015444C.c +++ b/src/ov_SC06_027/ov_SC06_027_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_027/nonmatchings/ov_SC06_027_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_029/ov_SC06_029_jr_8015444C.c b/src/ov_SC06_029/ov_SC06_029_jr_8015444C.c index 6f6e2be4cf..0fa4516baa 100644 --- a/src/ov_SC06_029/ov_SC06_029_jr_8015444C.c +++ b/src/ov_SC06_029/ov_SC06_029_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_029/nonmatchings/ov_SC06_029_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_030/ov_SC06_030_jr_8015444C.c b/src/ov_SC06_030/ov_SC06_030_jr_8015444C.c index 891fb89aef..a53a559d3e 100644 --- a/src/ov_SC06_030/ov_SC06_030_jr_8015444C.c +++ b/src/ov_SC06_030/ov_SC06_030_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_030/nonmatchings/ov_SC06_030_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_032/ov_SC06_032_jr_8015444C.c b/src/ov_SC06_032/ov_SC06_032_jr_8015444C.c index 1182f52a4e..523325ed37 100644 --- a/src/ov_SC06_032/ov_SC06_032_jr_8015444C.c +++ b/src/ov_SC06_032/ov_SC06_032_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC06_033/ov_SC06_033_jr_8015444C.c b/src/ov_SC06_033/ov_SC06_033_jr_8015444C.c index 1d457f0116..0eac05c7fa 100644 --- a/src/ov_SC06_033/ov_SC06_033_jr_8015444C.c +++ b/src/ov_SC06_033/ov_SC06_033_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC07_000/ov_SC07_000_jr_8015444C.c b/src/ov_SC07_000/ov_SC07_000_jr_8015444C.c index 918ca69ed9..b7c65e9279 100644 --- a/src/ov_SC07_000/ov_SC07_000_jr_8015444C.c +++ b/src/ov_SC07_000/ov_SC07_000_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC07_000/nonmatchings/ov_SC07_000_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC07_001/ov_SC07_001_jr_8015444C.c b/src/ov_SC07_001/ov_SC07_001_jr_8015444C.c index c23a2e3f69..75bb99e761 100644 --- a/src/ov_SC07_001/ov_SC07_001_jr_8015444C.c +++ b/src/ov_SC07_001/ov_SC07_001_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC07_001/nonmatchings/ov_SC07_001_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC07_002/ov_SC07_002_jr_8015444C.c b/src/ov_SC07_002/ov_SC07_002_jr_8015444C.c index 5c48eef2a2..ea4226c4b3 100644 --- a/src/ov_SC07_002/ov_SC07_002_jr_8015444C.c +++ b/src/ov_SC07_002/ov_SC07_002_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC07_002/nonmatchings/ov_SC07_002_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC07_006/ov_SC07_006_jr_8015444C.c b/src/ov_SC07_006/ov_SC07_006_jr_8015444C.c index e1abbf0dc2..8d105f064f 100644 --- a/src/ov_SC07_006/ov_SC07_006_jr_8015444C.c +++ b/src/ov_SC07_006/ov_SC07_006_jr_8015444C.c @@ -2174,7 +2174,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } } -INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154a74 (src/shared) */ diff --git a/src/ov_SC07_007/ov_SC07_007_jr_8015444C.c b/src/ov_SC07_007/ov_SC07_007_jr_8015444C.c index 3b2ca2437c..c9b64f5e10 100644 --- a/src/ov_SC07_007/ov_SC07_007_jr_8015444C.c +++ b/src/ov_SC07_007/ov_SC07_007_jr_8015444C.c @@ -2159,7 +2159,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } } -INCLUDE_ASM("asm/ov_SC07_007/nonmatchings/ov_SC07_007_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154a74 (src/shared) */ diff --git a/src/ov_SC07_008/ov_SC07_008_jr_8015444C.c b/src/ov_SC07_008/ov_SC07_008_jr_8015444C.c index 429fb8fc31..c1c2e2fa23 100644 --- a/src/ov_SC07_008/ov_SC07_008_jr_8015444C.c +++ b/src/ov_SC07_008/ov_SC07_008_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC07_008/nonmatchings/ov_SC07_008_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC07_009/ov_SC07_009_jr_8015444C.c b/src/ov_SC07_009/ov_SC07_009_jr_8015444C.c index 771ba92e6b..1d0c06ef71 100644 --- a/src/ov_SC07_009/ov_SC07_009_jr_8015444C.c +++ b/src/ov_SC07_009/ov_SC07_009_jr_8015444C.c @@ -1171,7 +1171,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } -INCLUDE_ASM("asm/ov_SC07_009/nonmatchings/ov_SC07_009_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154A74 (src/shared) */ diff --git a/src/ov_SC07_010/ov_SC07_010_jr_8015444C.c b/src/ov_SC07_010/ov_SC07_010_jr_8015444C.c index 2e9c894899..fbac07f0c7 100644 --- a/src/ov_SC07_010/ov_SC07_010_jr_8015444C.c +++ b/src/ov_SC07_010/ov_SC07_010_jr_8015444C.c @@ -1594,7 +1594,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } } -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154a74 (src/shared) */ diff --git a/src/ov_SC07_011/ov_SC07_011_jr_8015444C.c b/src/ov_SC07_011/ov_SC07_011_jr_8015444C.c index d9b9383182..0f0674916a 100644 --- a/src/ov_SC07_011/ov_SC07_011_jr_8015444C.c +++ b/src/ov_SC07_011/ov_SC07_011_jr_8015444C.c @@ -2160,7 +2160,78 @@ void func_8015444C(void *a0v, s32 *arg1x, s32 *arg2x, s32 *arg3x) { } } -INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011_jr_8015444C", func_801549F8); + + +/* + * func_801549F8 — scan param->b4[] (s32[], length = the u8 at param->bc), + * stepping the index by 1 or 2 per entry via the 27-entry jump table + * jtbl_801D89A4; count the default/out-of-range entries. Returns (u8) count. + * + * REDRAFT NOTE (the decay fix, 2 levers — both required, both source-level): + * + * 1. `u8 n` (NOT `s32 n`) — THE fix for the stored draft's 3-off residual. + * The stored draft's whole residual was the position of the loop-bound + * keep-alive copy `addu $a3,$v0,$zero` among the three preheader insns: + * draft emitted [lw base][copy][lui/addiu jtbl], target wants + * [lw base][lui/addiu jtbl][copy]. The loop-invariant jtbl address is + * moved by loop.c and lands AFTER every preheader source statement, so as + * long as the copy is an ordinary preheader statement it can never follow + * the hoist. Making `n` a u8 changes the RTL for `n = *(u8*)(p+0xBC)`: + * cse1 no longer converts it into a plain reg-reg copy in place, and the + * copy that ultimately feeds the exit test is emitted at loop_start AFTER + * move_movables (post-loop pass), i.e. after the hoisted lui/addiu — the + * target order. Nothing else in the function changes. + * + * 2. The `j = i` / `i = j + k` index form BLOCKS strength reduction, which + * is what the stored draft's `register s32 i __asm__("$3")` pin was for. + * Unblocked, -O2 turns base[i] into a walking pointer (2nd biv, 33 ins); + * the target keeps the INDEX form (sll $v0,$v1,2; addu $v0,$v0,$a0; lw). + * `j` is a mult=1/add=0 giv of the biv `i`, so SR declines and i/j get + * coalesced into $v1 — no extra insn. This replaces the hard-register + * pin, so the match is pin-free and safe to travel to sibling overlays. + * (The pinned form — keep `register s32 i __asm__("$3")` + `i += 1/2` and + * just change `n` to u8 — also MATCHes, 31 ins, if a pin is ever wanted.) + * + * OPT LEVEL: plain -O2. The unfilled load-delay nops are this psx gcc's + * default, not an -O1 tell. + * + * VERIFIED: python3 tools/match_one.py func_801549F8 --c .run/uc/func_801549F8.c + * --asm-subdir asm/ov_SC01_077/nonmatchings/ov_SC01_077_jr_8015444C + * -> MATCH (31 ins) + */ +s32 func_801549F8(s32 param_1, s32 _arg1, s32 _arg2) +{ + s32 i, j; + u8 n; + u8 count; + s32 *base; + + count = 0; + i = 0; + if (*(u8 *)(param_1 + 0xBC) != 0) { + base = *(s32 **)(param_1 + 0xB4); + n = *(u8 *)(param_1 + 0xBC); + do { + j = i; + switch (base[j]) { + case 0: case 2: case 7: case 8: case 9: case 10: + case 0xd: case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x19: case 0x1a: + i = j + 1; + break; + case 3: case 4: case 5: case 6: case 0xb: case 0xc: + case 0xe: case 0xf: case 0x15: case 0x16: + i = j + 2; + break; + default: + i = j + 1; + count += 1; + break; + } + } while (i != n); + } + return count; +} DEFINE_func_80154A74() /* dedup: shared engine-core @0x80154a74 (src/shared) */