From 2ae8a5a6ae34457da228e53ce83376bded7a721b Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 11 Sep 2026 00:44:20 -0600 Subject: [PATCH] =?UTF-8?q?phase-36:=20S104=20log=20=E2=80=94=20the=20fift?= =?UTF-8?q?h=20wave,=20the=20widened=20generators,=20the=20interrupted=20p?= =?UTF-8?q?art-3=20bank=20(R22-verified),=20e1=20(func=5F801AB818=20banked?= =?UTF-8?q?;=20two=20signature=20closes=20parked;=20~158=20'$4=20pin=20=3D?= =?UTF-8?q?=20missing=20parameter'=20functions=20for=20the=20structs=20pha?= =?UTF-8?q?se)=20|=20=F0=9F=9B=91=20T7=20RUNNING?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .run/P36/agents/ORDER.tsv | 18 +- .../ov_SC03_006__func_8017E710/body_free.c | 52 +++++ .../ov_SC03_006__func_8017E710/body_tree.c | 52 +++++ .../ov_SC03_006__func_8017E710/history.txt | 14 ++ .../ov_SC03_006__func_8017E710/neighbours.txt | 76 +++++++ .../ov_SC03_006__func_8017E710/related.txt | 192 ++++++++++++++++++ .../ov_SC03_006__func_8017E710/residual.txt | 15 ++ .../ov_SC03_006__func_8017E710/sites.txt | 1 + .../agents/ov_SC03_006__func_8017E710/tu.txt | 2 + .../ov_SC03_006__func_80182F4C/body_free.c | 62 ++++++ .../ov_SC03_006__func_80182F4C/body_tree.c | 62 ++++++ .../ov_SC03_006__func_80182F4C/history.txt | 14 ++ .../ov_SC03_006__func_80182F4C/neighbours.txt | 57 ++++++ .../ov_SC03_006__func_80182F4C/related.txt | 1 + .../ov_SC03_006__func_80182F4C/residual.txt | 45 ++++ .../ov_SC03_006__func_80182F4C/sites.txt | 4 + .../agents/ov_SC03_006__func_80182F4C/tu.txt | 2 + .../ov_SC03_006__func_80189A84/body_free.c | 29 +++ .../ov_SC03_006__func_80189A84/body_tree.c | 29 +++ .../ov_SC03_006__func_80189A84/history.txt | 14 ++ .../ov_SC03_006__func_80189A84/neighbours.txt | 57 ++++++ .../ov_SC03_006__func_80189A84/related.txt | 150 ++++++++++++++ .../ov_SC03_006__func_80189A84/residual.txt | 39 ++++ .../ov_SC03_006__func_80189A84/sites.txt | 2 + .../agents/ov_SC03_006__func_80189A84/tu.txt | 2 + .run/P36/census/lever_census.json | 162 ++++++++------- .run/P36/census/lever_census.txt | 28 +-- phase-ends/CURRENT_PHASE.md | 14 ++ 28 files changed, 1095 insertions(+), 100 deletions(-) create mode 100644 .run/P36/agents/ov_SC03_006__func_8017E710/body_free.c create mode 100644 .run/P36/agents/ov_SC03_006__func_8017E710/body_tree.c create mode 100644 .run/P36/agents/ov_SC03_006__func_8017E710/history.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_8017E710/neighbours.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_8017E710/related.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_8017E710/residual.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_8017E710/sites.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_8017E710/tu.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80182F4C/body_free.c create mode 100644 .run/P36/agents/ov_SC03_006__func_80182F4C/body_tree.c create mode 100644 .run/P36/agents/ov_SC03_006__func_80182F4C/history.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80182F4C/neighbours.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80182F4C/related.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80182F4C/residual.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80182F4C/sites.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80182F4C/tu.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80189A84/body_free.c create mode 100644 .run/P36/agents/ov_SC03_006__func_80189A84/body_tree.c create mode 100644 .run/P36/agents/ov_SC03_006__func_80189A84/history.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80189A84/neighbours.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80189A84/related.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80189A84/residual.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80189A84/sites.txt create mode 100644 .run/P36/agents/ov_SC03_006__func_80189A84/tu.txt diff --git a/.run/P36/agents/ORDER.tsv b/.run/P36/agents/ORDER.tsv index 8acd74a507..e06c5620e7 100644 --- a/.run/P36/agents/ORDER.tsv +++ b/.run/P36/agents/ORDER.tsv @@ -1,16 +1,4 @@ rank fn alias copies best needed kinds regs tu -60 func_8018B9D4 ov_SC06_018 2 1 1 pin $0 src/ov_SC06_018/ov_SC06_018_jr_80187AEC.c -23 func_801A1E94 md_SC07_004 1 1 1 pin $4 src/md_SC07_004/md_SC07_004.c -101 func_801A5C44 md_SC07_004 1 1 1 pin $4 src/md_SC07_004/md_SC07_004.c -232 func_801AB818 md_SC07_004 1 1 1 barrier src/md_SC07_004/md_SC07_004.c -20 func_80037144 main 1 2 1 barrier src/800_c.c -41 func_800384A8 main 1 2 1 pin $4 src/800_c.c -4 func_80187DD0 ov_SC06_018 1 2 1 pin $2 src/ov_SC06_018/ov_SC06_018_jr_80187AEC.c -47 func_8018AD74 ov_SC06_018 1 2 1 launder src/ov_SC06_018/ov_SC06_018_jr_80187AEC.c -127 func_80035210 main 1 4 1 pin $3 src/800_b_2.c -18 func_80036FB0 main 1 4 1 keepalive src/800_c.c -141 func_80183B9C ov_SC02_017 1 4 1 barrier src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c -200 func_80186770 ov_SC02_017 1 4 1 pin $6 src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c -85 func_80030F80 main 1 5 1 barrier src/800_b_2.c -163 func_80184754 ov_SC02_017 1 8 1 launder src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c -118 func_800348A8 main 1 9 1 keepalive src/800_b_2.c +286 func_80189A84 ov_SC03_006 2 3 2 pin $2,$3 src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c +51 func_8017E710 ov_SC03_006 1 7 1 pin $2 src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c +128 func_80182F4C ov_SC03_006 1 13 1 pin $4 src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c diff --git a/.run/P36/agents/ov_SC03_006__func_8017E710/body_free.c b/.run/P36/agents/ov_SC03_006__func_8017E710/body_free.c new file mode 100644 index 0000000000..c7e9a4fb42 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_8017E710/body_free.c @@ -0,0 +1,52 @@ +void func_8017E710(s32 a0) { + extern void ApplyMatrixSV(void *a0, void *a1, void *a2); + extern s32 ratan2(s32 a0, s32 a1); + extern s16 D_801152B0; + extern s16 D_801152B4; + extern s32 func_80133784(s32 a0, void *a1, s32 a2); + extern s32 func_8012CEB0(s32 a0, s32 a1, s32 a2); + extern void RotMatrixY(s32 a0, void *a1); + extern Mtx8_8017DE10_8017E710 D_800AE620; + + u8 in[8]; + u8 out[8]; + Mtx8_8017DE10_8017E710 m; + s32 base; + s32 ang; + s16 arg; + + *(s16 *)(in + 0) = *(u16 *)(a0 + 0x6) + *(u16 *)(a0 + 0x12); + *(s16 *)(in + 2) = *(u16 *)(a0 + 0xA) + 8; + *(s16 *)(in + 4) = *(u16 *)(a0 + 0xE) + *(u16 *)(a0 + 0x1A); + *(s16 *)(out + 0) = *(u16 *)(a0 + 0x6); + *(s16 *)(out + 2) = *(u16 *)(a0 + 0xA) + 8; + *(s16 *)(out + 4) = *(u16 *)(a0 + 0xE); + if ((func_80133784(1, &in[0], (s32)&out[0]) & 0xC000) != 0) { + base = ratan2(D_801152B0, D_801152B4) & 0xFFF; + ang = ratan2(*(s32 *)(a0 + 0x10), *(s32 *)(a0 + 0x18)) & 0xFFF; + if ((s16)(ang - base) < 0) { + ang += 0x480; + } else { + ang -= 0x480; + } + arg = base - ang; + ang = *(u16 *)(a0 + 0x6); + *(s16 *)(in + 0) = ang; + *(s16 *)(in + 2) = *(u16 *)(a0 + 0xA); + *(s16 *)(in + 4) = *(u16 *)(a0 + 0xE); + m = D_800AE620; + RotMatrixY(arg, &m); + *(s16 *)(out + 0) = *(u16 *)(a0 + 0x12); + *(s16 *)(out + 2) = *(u16 *)(a0 + 0x16); + *(s16 *)(out + 4) = *(u16 *)(a0 + 0x1A); + ApplyMatrixSV(&m, &out[0], &out[0]); + *(s16 *)(out + 0) = *(u16 *)(a0 + 0x6) + ((s16)*(u16 *)(out + 0) >> 1); + *(s16 *)(out + 2) = *(u16 *)(a0 + 0xA) + ((s16)*(u16 *)(out + 2) >> 1); + *(s16 *)(out + 4) = *(u16 *)(a0 + 0xE) + ((s16)*(u16 *)(out + 4) >> 1); + if ((func_8012CEB0((s32)&in[0], (s32)&out[0], 0) & 0x2000) != 0) { + *(s16 *)(a0 + 0x6) = *(u16 *)(out + 0); + *(s16 *)(a0 + 0xA) = *(u16 *)(out + 2); + *(s16 *)(a0 + 0xE) = *(u16 *)(out + 4); + } + } +} diff --git a/.run/P36/agents/ov_SC03_006__func_8017E710/body_tree.c b/.run/P36/agents/ov_SC03_006__func_8017E710/body_tree.c new file mode 100644 index 0000000000..eaf1b0665b --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_8017E710/body_tree.c @@ -0,0 +1,52 @@ +void func_8017E710(s32 a0) { + extern void ApplyMatrixSV(void *a0, void *a1, void *a2); + extern s32 ratan2(s32 a0, s32 a1); + extern s16 D_801152B0; + extern s16 D_801152B4; + extern s32 func_80133784(s32 a0, void *a1, s32 a2); + extern s32 func_8012CEB0(s32 a0, s32 a1, s32 a2); + extern void RotMatrixY(s32 a0, void *a1); + extern Mtx8_8017DE10_8017E710 D_800AE620; + + u8 in[8]; + u8 out[8]; + Mtx8_8017DE10_8017E710 m; + s32 base; + register s32 ang __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus7) + s16 arg; + + *(s16 *)(in + 0) = *(u16 *)(a0 + 0x6) + *(u16 *)(a0 + 0x12); + *(s16 *)(in + 2) = *(u16 *)(a0 + 0xA) + 8; + *(s16 *)(in + 4) = *(u16 *)(a0 + 0xE) + *(u16 *)(a0 + 0x1A); + *(s16 *)(out + 0) = *(u16 *)(a0 + 0x6); + *(s16 *)(out + 2) = *(u16 *)(a0 + 0xA) + 8; + *(s16 *)(out + 4) = *(u16 *)(a0 + 0xE); + if ((func_80133784(1, &in[0], (s32)&out[0]) & 0xC000) != 0) { + base = ratan2(D_801152B0, D_801152B4) & 0xFFF; + ang = ratan2(*(s32 *)(a0 + 0x10), *(s32 *)(a0 + 0x18)) & 0xFFF; + if ((s16)(ang - base) < 0) { + ang += 0x480; + } else { + ang -= 0x480; + } + arg = base - ang; + ang = *(u16 *)(a0 + 0x6); + *(s16 *)(in + 0) = ang; + *(s16 *)(in + 2) = *(u16 *)(a0 + 0xA); + *(s16 *)(in + 4) = *(u16 *)(a0 + 0xE); + m = D_800AE620; + RotMatrixY(arg, &m); + *(s16 *)(out + 0) = *(u16 *)(a0 + 0x12); + *(s16 *)(out + 2) = *(u16 *)(a0 + 0x16); + *(s16 *)(out + 4) = *(u16 *)(a0 + 0x1A); + ApplyMatrixSV(&m, &out[0], &out[0]); + *(s16 *)(out + 0) = *(u16 *)(a0 + 0x6) + ((s16)*(u16 *)(out + 0) >> 1); + *(s16 *)(out + 2) = *(u16 *)(a0 + 0xA) + ((s16)*(u16 *)(out + 2) >> 1); + *(s16 *)(out + 4) = *(u16 *)(a0 + 0xE) + ((s16)*(u16 *)(out + 4) >> 1); + if ((func_8012CEB0((s32)&in[0], (s32)&out[0], 0) & 0x2000) != 0) { + *(s16 *)(a0 + 0x6) = *(u16 *)(out + 0); + *(s16 *)(a0 + 0xA) = *(u16 *)(out + 2); + *(s16 *)(a0 + 0xE) = *(u16 *)(out + 4); + } + } +} diff --git a/.run/P36/agents/ov_SC03_006__func_8017E710/history.txt b/.run/P36/agents/ov_SC03_006__func_8017E710/history.txt new file mode 100644 index 0000000000..b051a32e00 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_8017E710/history.txt @@ -0,0 +1,14 @@ +s5: verdict NO-MATCH start 9 best 7 compiles 189 path R6 inline ang @4934 +best-scoring single candidates of the last trace (move -> score [residual class]): + R6 inline ang @4934 -> 7 [REG] (from 9) + R8 temp tmp0 @4919 -> 7 [REG] (from 7) + R18 bystander @4933->4936 -> 7 [REG] (from 7) + R10 param-copy a0 @4918 -> 7 [REG] (from 7) + R7 block @4919 -> 7 [REG] (from 7) + R4 decl-move ang 7->0 -> 7 [REG] (from 7) + R8 base tmp0 @4919 -> 7 [REG] (from 7) + R18 bystander @4933->4937 -> 7 [REG] (from 7) + R7 do-while @4919 -> 7 [REG] (from 7) + R4 decl-move ang 7->1 -> 7 [REG] (from 7) + R5 swap + @4943 -> 7 [REG] (from 7) + R7 block @4921 -> 7 [REG] (from 7) diff --git a/.run/P36/agents/ov_SC03_006__func_8017E710/neighbours.txt b/.run/P36/agents/ov_SC03_006__func_8017E710/neighbours.txt new file mode 100644 index 0000000000..de2cb2d31a --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_8017E710/neighbours.txt @@ -0,0 +1,76 @@ +=== THIS FUNCTION'S OWN HEADER (func_8017E710, line 4871) — read it in full === +/* func_8017E710 -- ov_SC02_011 / ov_SC02_011_jr_8017AE2C [target: 133 ins] + * + * Structural twin of func_8017D0BC (ov_SC03_002/ov_SC03_002_jr_8017AE2C.c), + * banked [MATCH, 133 ins] this session -- same jr_8017AE2C shared layout, + * identical struct-offset chain (a0+0x6/0xA/0xE/0x10/0x12/0x16/0x18/0x1A) and + * identical call sequence (func_80133784 -> ratan2 x2 -> angle-wrap -> + * RotMatrixY -> ApplyMatrixSV -> func_8012CEB0). Reused verbatim per §136c + * sibling-first (declaration + expression forms are already byte-proven for + * this exact body). + * + * §136 L1/RC-5 note carried from the twin: `ang` (second ratan2 result) is a + * GLOBAL allocno spanning the +/-0x480 arms, while the `ang - base` compare + * temp is a LOCAL allocno in the same block; unpinned gcc hands the local + * temp $v0 and pushes `ang` to $v1 (REGALLOC-PERM). Pinning `ang` to $v0 + * fixes the swap, and reusing the now-dead `ang` as the a0[0x6] scratch + * (instead of a fresh local) avoids stealing back the $v0 slot. + */ + +--- every @class/@stuck/@crack note in this translation unit --- +// @class: plumbing +// @stuck: none — MATCH +// @class: regalloc-order — simplified sibling of matched func_8017B614. +// @stuck: none. Block-moves are align-1 struct-assigns (u8[8]) -> emit_block_move +// @class: struct +// @stuck: none — MATCH (74 ins) +// @class: regalloc-order + T1 memcpy-builtin→call re-crack +// @stuck: 0 (iso). Register lever = $16 pin + in-place re-tie on the memcpy-branch src (keeps +// @class: plumbing +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH (63 ins) +// @class: struct +// @stuck: none — MATCH (62 ins) +// @class: struct +// @stuck: none — MATCH (65 ins) +// @class: regalloc-order +// @stuck: pending self-check — register order param=$s2 counter=$s1 ptr=$s0 +// @class: plumbing +// @stuck: none — MATCH (expected); short-typed global increment + signed compare, store-2 on overflow +// @class: plumbing +// @stuck: none — MATCH expected (simple short-increment + guarded call) +// @class: regalloc-order +// @stuck: none — MATCH (branch-polarity invert: fn-ptr non-zero call is the fall-through arm) +// @class: plumbing +// @stuck: none — MATCH (41 ins, relocation-masked); frame needed a 0x30 address-taken local +// @class: plumbing +// @stuck: none — signed s32 counter at 0x1C, delay-slot store is the unconditional bump +// @class: struct +// @stuck: none — MATCH (array-of-fnptr %lo-fold + signed-halfword guard) +// @class: regalloc-order +// @stuck: none — MATCH +// @class: structural (STRENGTH/mflo!=lw -> MATCH) +// @stuck: none - MATCH (41 ins), match_one + rtu_match. +// @class: straight-derive +// @stuck: none — MATCH (52 ins) on iteration 1, confirmed by rtu_match. +// @class: structural (STRENGTH/mflo!=lw -> MATCH) +// @stuck: none - MATCH (41 ins), match_one + rtu_match. +// @class: regalloc (WIDTH/li!=addu -> MATCH) +// @stuck: none — MATCH (58 ins), match_one + rtu_match. PIN-FREE (no register __asm__). +// @class: structural (STRENGTH/mflo!=lw -> MATCH) +// @stuck: none - MATCH (41 ins), match_one + rtu_match. +// @class: plumbing +// @stuck: none — MATCH (18 ins): if((b&1) && p!=&sym) call(param,&sym); $a0 live, $a1=&sym fall out +// @class: schedule +// @stuck: none — MATCH (44 ins). Two §3-T4 branch-polarity inversions: outer if(param_2>=iVar2) makes the func_8018B1B4 else-block fall-through; inner if(param_3>=iVar2) return 0 makes the func_8012A828 body fall-through. No pins needed — natural $s1/$s0/$s2 alloc matched. +// @class: plumbing +// @stuck: none — MATCH (straightforward; callee sigs canonical from overlay) +// @class: plumbing +// @stuck: none — MATCH (clean if/else, sh into delay slot of func_8001CA88 call) +// @class: plumbing +// @stuck: none — MATCH expected (single call-crossing local pins to $s0 naturally; lhu via unsigned short) diff --git a/.run/P36/agents/ov_SC03_006__func_8017E710/related.txt b/.run/P36/agents/ov_SC03_006__func_8017E710/related.txt new file mode 100644 index 0000000000..28257cf8dd --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_8017E710/related.txt @@ -0,0 +1,192 @@ +=== lever-free bodies in ov_SC03_006 sharing a callee or global with func_8017E710 (37 found; top 6 by shared symbols) — read them for the SHAPE === +--- func_8015C0C4 (src/shared/ov/func_8015C0C4.h:8) shares 2: D_801152B0 D_801152B4 --- +void func_8015C0C4(s32 a0) { + s32 t = D_801152B0 << 6; + *(s32 *)(a0 + 0x238) = 0x80000; + *(s32 *)(a0 + 0x234) = t; + *(s32 *)(a0 + 0x23C) = D_801152B4 << 6; + func_80154150(a0, 0x11); + func_801553A8((s32 *)a0); + func_80146CA0((void *)a0); +} + +--- func_8014A3E0 (src/shared/ov/func_8014A3E0.h:5) shares 2: D_801152B0 D_801152B4 --- +s32 func_8014A3E0(struct S_8014A3E0 *a0) { + s32 sp[4]; + sp[0] = a0->h12 * D_801152B0; + sp[2] = a0->h1A * D_801152B4; + if (sp[0] >= 0 && sp[2] >= 0) { + return 1; + } + *(s16 *)((char *)a0 + 0x6) = a0->h88; + *(s16 *)((char *)a0 + 0xA) = a0->h8A; + *(s16 *)((char *)a0 + 0xE) = a0->h8C; + return 0; +} + +--- func_8014FA70 (src/shared/ov/func_8014FA70.h:8) shares 2: D_801152B0 func_80133784 --- +s32 func_8014FA70(s32 a0) { + s32 s1; + s32 v0; + u8 in[8]; + u8 out[8]; + *(s16 *)(in + 0x0) = *(u16 *)(a0 + 0x88); + *(s16 *)(in + 0x2) = *(u16 *)(a0 + 0x8A); + *(s16 *)(in + 0x4) = *(u16 *)(a0 + 0x8C); + *(s16 *)(out + 0x0) = *(u16 *)(a0 + 0x6); + *(s16 *)(out + 0x2) = *(u16 *)(a0 + 0xA); + *(s16 *)(out + 0x4) = *(u16 *)(a0 + 0xE); + s1 = func_80133784(1, &in[0], (s32)&out[0]); + if (s1 != 0) { + *(s16 *)(a0 + 0x6) = *(u16 *)(out + 0x0); + *(s16 *)(a0 + 0xA) = *(u16 *)(out + 0x2); + *(s16 *)(a0 + 0xE) = *(u16 *)(out + 0x4); + v0 = *(u8 *)(out + 0x6); + if (v0 != 0) { + *(s16 *)(a0 + 0x16C) = v0; + } + *(s16 *)(a0 + 0x16E) = *(u16 *)(out + 0x6) >> 13; + if (*(u16 *)(a0 + 0x16C) == 0x1D) { + if ((func_80029178(0x21) & 0xFF) == 0) { + s1 &= ~0x2000; + s1 |= 0x4000; + __builtin_memcpy(&D_801152B0, &D_801152A8[0], 8); + D_801152BC = 1; + } + } + return s1; + } + v0 = *(u8 *)(out + 0x6); + if (v0 != 0) { + *(s16 *)(a0 + 0x16C) = v0; + } + return 0; +} + +--- func_8016163C (src/shared/ov/func_8016163C.h:13) shares 2: D_801152B0 D_801152B4 --- +s32 func_8016163C(s32 a0, u32 a1) +{ + s32 result; + if ((a1 & 1) != 0) { + func_801599A4(a0); + func_80159B3C(a0); + func_8014C010((s32)a0, 1); + func_80161D20((s32)a0, *(u16 *)((s32)a0 + 0x16E)); + return 1; + } + if ((a1 & 0x4000) != 0) { + func_801599A4(a0); + func_8015BF48((s32 *)a0); + func_8014C010((s32)a0, 1); + func_80161D20((s32)a0, *(u16 *)((s32)a0 + 0x16E)); + return 2; + } + if ((a1 & 0x2000) != 0) { + func_801599A4(a0); + func_80159B3C(a0); + func_8014C010((s32)a0, 1); + func_80161D20((s32)a0, *(u16 *)((s32)a0 + 0x16E)); + return 4; + } + if ((a1 & 0x8000) != 0) { + if (*(u16 *)((s32)a0 + 0x16C) != 0x15) { + return 0; + } + if (func_8014A6C4((s32)a0) == 0) { + return 0; + } + func_801599A4(a0); + func_8015F2F0(a0); + result = ratan2(D_801152B0, D_801152B4); + *(s16 *)(*(s32 *)((s32)a0 + 0x20) + 0x12) = (s16)result; + return 8; + } + return 0; +} + +--- func_80161774 (src/shared/ov/func_80161774.h:11) shares 2: D_801152B0 D_801152B4 --- +s32 func_80161774(int a0, u32 a1) +{ + s32 v1; + s16 v2; + if ((a1 & 1) != 0) { + func_8014C010((s32)a0, 1); + v1 = *(u16 *)((s32)a0 + 0x16E); + func_80161D20((s32)a0, v1); + return 1; + } + if ((a1 & 0x4000) != 0) { + func_801599A4(a0); + func_8015BF48((s32 *)a0); + func_8014C010((s32)a0, 1); + v1 = *(u16 *)((s32)a0 + 0x16E); + func_80161D20((s32)a0, v1); + return 2; + } + if ((a1 & 0x2000) != 0) { + func_8014C010((s32)a0, 1); + v1 = *(u16 *)((s32)a0 + 0x16E); + func_80161D20((s32)a0, v1); + return 4; + } + if ((a1 & 0x8000) != 0) { + v1 = *(u16 *)((s32)a0 + 0x16C); + if (v1 != 0x15) { + return 0; + } + v1 = func_8014A6C4((s32)a0); + if (v1 == 0) { + return 0; + } + func_801599A4(a0); + func_8015F2F0((s32 *)a0); + v2 = ratan2(D_801152B0, D_801152B4); + *(s16 *)(*(s32 *)((s32)a0 + 0x20) + 0x12) = v2; + return 8; + } + return 0; +} + +--- func_80188AF4 (src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c:12079) shares 2: D_800AE620 func_8012CEB0 --- +void func_80188AF4(s32 a0, s32 a1) { + extern s32 func_8012B864(s32 a0); + extern void RotMatrixY(s32 a0, void *a1); + extern void func_800484EC(s32 a0, s32 a1, s32 a2); + extern s32 func_8012CEB0(s32 a0, s32 a1, s32 a2); + extern Mtx8_8017DE10_8017E710 D_800AE620; + + u32 pos[3]; + Vec32_80188AF4 out; + u8 rotIn[8]; + u8 rotOut[8]; + Blk20_80188AF4 m; + + m = (*(Blk20_80188AF4 *)&D_800AE620); + RotMatrixY(func_8012B864(a0), &m); + func_800484EC((s32)&m, a1, (s32)&out); + + pos[0] = *(s32 *)(a0 + 0x4) + out.vx; + pos[1] = *(s32 *)(a0 + 0x8) + out.vy; + pos[2] = *(s32 *)(a0 + 0xC) + out.vz; + + { + u16 rix; + u16 roy; + u16 roz; + u16 riz; + + rix = *(u16 *)(a0 + 0x3A); + roy = *((u16 *)&pos[1] + 1); + roz = *((u16 *)&pos[2] + 1); + *(u16 *)(rotIn + 0) = rix; + *(u16 *)(rotIn + 2) = *(u16 *)(a0 + 0x3E); + riz = *(u16 *)(a0 + 0x42); + *(u16 *)(rotOut + 0) = *((u16 *)&pos[0] + 1); + *(u16 *)(rotOut + 2) = roy; + *(u16 *)(rotOut + 4) = roz; + *(u16 *)(rotIn + 4) = riz; + } + + func_8012CEB0((s32)&rotIn[0], (s32)&rotOut[0], 0); +} + diff --git a/.run/P36/agents/ov_SC03_006__func_8017E710/residual.txt b/.run/P36/agents/ov_SC03_006__func_8017E710/residual.txt new file mode 100644 index 0000000000..b7f83d49ec --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_8017E710/residual.txt @@ -0,0 +1,15 @@ +src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c:func_8017E710: score 9 (REG-caller; mine 133 ins, target 133) — not yet + register pairs (mine -> target, count): v1->v0 x9, v0->v1 x4 + replace mine[43:47] target[43:47] + 43 andi v1,v0,0xfff | andi v0,v0,0xfff + 44 subu v0,v1,s0 | subu v1,v0,s0 + 45 sll v0,v0,0x10 | sll v1,v1,0x10 + 46 bgez v0,39ac | bgez v1,39ac + replace mine[49:52] target[49:52] + 49 addiu v1,v1,1152 | addiu v0,v0,1152 + 50 addiu v1,v1,-1152 | addiu v0,v0,-1152 + 51 subu a0,s0,v1 | subu a0,s0,v0 + replace mine[53:54] target[53:54] + 53 lhu v1,6(s1) | lhu v0,6(s1) + replace mine[55:56] target[55:56] + 55 sh v1,16(sp) | sh v0,16(sp) diff --git a/.run/P36/agents/ov_SC03_006__func_8017E710/sites.txt b/.run/P36/agents/ov_SC03_006__func_8017E710/sites.txt new file mode 100644 index 0000000000..50da3d979d --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_8017E710/sites.txt @@ -0,0 +1 @@ +NEEDED pin $2 line 4916 diff --git a/.run/P36/agents/ov_SC03_006__func_8017E710/tu.txt b/.run/P36/agents/ov_SC03_006__func_8017E710/tu.txt new file mode 100644 index 0000000000..9327c6cf9d --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_8017E710/tu.txt @@ -0,0 +1,2 @@ +src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c +func_8017E710 diff --git a/.run/P36/agents/ov_SC03_006__func_80182F4C/body_free.c b/.run/P36/agents/ov_SC03_006__func_80182F4C/body_free.c new file mode 100644 index 0000000000..78863213f4 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80182F4C/body_free.c @@ -0,0 +1,62 @@ +s32 func_80182F4C(s32 a0, s16 a1) +{ + u8 *base; + s16 val; + u16 c0; + u16 c1; + u16 outerIdx; + u16 innerIdx; + u16 diff; + s32 prod; + u16 temp2; + u16 idx2; + u16 *tbl; + s32 p1; + s32 p2; + s32 p3; + u16 dx; + u16 n; + u16 sample; + s32 addr; + s16 cur; + u16 v; + + base = D_801AD31C; + c0 = 0xF800; + val = (s16)a0; + + do { + c1 = 0xFA00; + outerIdx = (c0 + 0x8000) >> 7 & 0x1FF; + do { + innerIdx = (c1 + 0x8000) >> 7 & 0x1FF; + diff = innerIdx - *(u16 *)(base + 2); + prod = diff * *(u16 *)(base + 4); + p1 = *(s32 *)(base + 0x14); + p2 = *(s32 *)(base + 0x18); + p3 = *(s32 *)(base + 0x1C); + temp2 = outerIdx - *(u16 *)(base + 0); + tbl = *(u16 **)(base + 0x8); + idx2 = (prod + temp2) * 2; + dx = tbl[idx2]; + n = tbl[idx2 + 1]; + p1 += dx; + while (n--) { + sample = *(u16 *)p1; + if (!(sample & 0x8000)) { + addr = p2 + sample * 18; + } else { + v = sample & 0x7FFF; + addr = p3 + v * 22; + } + cur = *(s16 *)addr; + if (cur == val) { + *(s16 *)addr = a1; + } + p1 += 2; + } + c1 += 0x80; + } while (c1 <= 0xFDFF); + c0 += 0x80; + } while (c0 <= 0xFBFF); +} diff --git a/.run/P36/agents/ov_SC03_006__func_80182F4C/body_tree.c b/.run/P36/agents/ov_SC03_006__func_80182F4C/body_tree.c new file mode 100644 index 0000000000..aa860cc8bd --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80182F4C/body_tree.c @@ -0,0 +1,62 @@ +s32 func_80182F4C(s32 a0, s16 a1) +{ + u8 *base; + s16 val; + u16 c0; + u16 c1; + u16 outerIdx; + u16 innerIdx; + u16 diff; + s32 prod; + u16 temp2; + u16 idx2; + u16 *tbl; + register s32 p1 __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus7) + s32 p2; + s32 p3; + u16 dx; + u16 n; + u16 sample; + s32 addr; + s16 cur; + u16 v; + + base = D_801AD31C; + c0 = 0xF800; + val = (s16)a0; + + do { + c1 = 0xFA00; + outerIdx = (c0 + 0x8000) >> 7 & 0x1FF; + do { + innerIdx = (c1 + 0x8000) >> 7 & 0x1FF; + diff = innerIdx - *(u16 *)(base + 2); + prod = diff * *(u16 *)(base + 4); + p1 = *(s32 *)(base + 0x14); + p2 = *(s32 *)(base + 0x18); + p3 = *(s32 *)(base + 0x1C); + temp2 = outerIdx - *(u16 *)(base + 0); + tbl = *(u16 **)(base + 0x8); + idx2 = (prod + temp2) * 2; + dx = tbl[idx2]; + n = tbl[idx2 + 1]; + p1 += dx; + while (n--) { + sample = *(u16 *)p1; + if (!(sample & 0x8000)) { + addr = p2 + sample * 18; + } else { + v = sample & 0x7FFF; + addr = p3 + v * 22; + } + cur = *(s16 *)addr; + if (cur == val) { + *(s16 *)addr = a1; + } + p1 += 2; + } + c1 += 0x80; + } while (c1 <= 0xFDFF); + c0 += 0x80; + } while (c0 <= 0xFBFF); +} diff --git a/.run/P36/agents/ov_SC03_006__func_80182F4C/history.txt b/.run/P36/agents/ov_SC03_006__func_80182F4C/history.txt new file mode 100644 index 0000000000..60347b1026 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80182F4C/history.txt @@ -0,0 +1,14 @@ +s5: verdict NO-MATCH start 29 best 13 compiles 189 path R6 inline diff @7683 + R12 width p1 s32->u16 @7663 +best-scoring single candidates of the last trace (move -> score [residual class]): + R12 width p1 s32->u16 @7663 -> 13 [COUNT] (from 18) + R12 width p1 s32->u8 @7663 -> 14 [COUNT] (from 18) + R12 width p1 s32->s16 @7663 -> 17 [COUNT] (from 18) + R6 inline diff @7683 -> 18 [COUNT] (from 29) + R6 inline outerIdx @7679 -> 18 [COUNT] (from 18) + R18 bystander @7675->7673 -> 18 [COUNT] (from 18) + R7 block @7679 -> 18 [COUNT] (from 18) + R5 swap * @7682 -> 18 [COUNT] (from 18) + R4 decl-move p1 10->0 -> 18 [COUNT] (from 18) + R6 inline v @7697 -> 18 [COUNT] (from 18) + R8 temp tmp0 @7686 -> 18 [COUNT] (from 18) + R7 do-while @7679 -> 18 [COUNT] (from 18) diff --git a/.run/P36/agents/ov_SC03_006__func_80182F4C/neighbours.txt b/.run/P36/agents/ov_SC03_006__func_80182F4C/neighbours.txt new file mode 100644 index 0000000000..38fe5e1209 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80182F4C/neighbours.txt @@ -0,0 +1,57 @@ +--- every @class/@stuck/@crack note in this translation unit --- +// @class: plumbing +// @stuck: none — MATCH +// @class: regalloc-order — simplified sibling of matched func_8017B614. +// @stuck: none. Block-moves are align-1 struct-assigns (u8[8]) -> emit_block_move +// @class: struct +// @stuck: none — MATCH (74 ins) +// @class: regalloc-order + T1 memcpy-builtin→call re-crack +// @stuck: 0 (iso). Register lever = $16 pin + in-place re-tie on the memcpy-branch src (keeps +// @class: plumbing +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH (63 ins) +// @class: struct +// @stuck: none — MATCH (62 ins) +// @class: struct +// @stuck: none — MATCH (65 ins) +// @class: regalloc-order +// @stuck: pending self-check — register order param=$s2 counter=$s1 ptr=$s0 +// @class: plumbing +// @stuck: none — MATCH (expected); short-typed global increment + signed compare, store-2 on overflow +// @class: plumbing +// @stuck: none — MATCH expected (simple short-increment + guarded call) +// @class: regalloc-order +// @stuck: none — MATCH (branch-polarity invert: fn-ptr non-zero call is the fall-through arm) +// @class: plumbing +// @stuck: none — MATCH (41 ins, relocation-masked); frame needed a 0x30 address-taken local +// @class: plumbing +// @stuck: none — signed s32 counter at 0x1C, delay-slot store is the unconditional bump +// @class: struct +// @stuck: none — MATCH (array-of-fnptr %lo-fold + signed-halfword guard) +// @class: regalloc-order +// @stuck: none — MATCH +// @class: structural (STRENGTH/mflo!=lw -> MATCH) +// @stuck: none - MATCH (41 ins), match_one + rtu_match. +// @class: straight-derive +// @stuck: none — MATCH (52 ins) on iteration 1, confirmed by rtu_match. +// @class: structural (STRENGTH/mflo!=lw -> MATCH) +// @stuck: none - MATCH (41 ins), match_one + rtu_match. +// @class: regalloc (WIDTH/li!=addu -> MATCH) +// @stuck: none — MATCH (58 ins), match_one + rtu_match. PIN-FREE (no register __asm__). +// @class: structural (STRENGTH/mflo!=lw -> MATCH) +// @stuck: none - MATCH (41 ins), match_one + rtu_match. +// @class: plumbing +// @stuck: none — MATCH (18 ins): if((b&1) && p!=&sym) call(param,&sym); $a0 live, $a1=&sym fall out +// @class: schedule +// @stuck: none — MATCH (44 ins). Two §3-T4 branch-polarity inversions: outer if(param_2>=iVar2) makes the func_8018B1B4 else-block fall-through; inner if(param_3>=iVar2) return 0 makes the func_8012A828 body fall-through. No pins needed — natural $s1/$s0/$s2 alloc matched. +// @class: plumbing +// @stuck: none — MATCH (straightforward; callee sigs canonical from overlay) +// @class: plumbing +// @stuck: none — MATCH (clean if/else, sh into delay slot of func_8001CA88 call) +// @class: plumbing +// @stuck: none — MATCH expected (single call-crossing local pins to $s0 naturally; lhu via unsigned short) diff --git a/.run/P36/agents/ov_SC03_006__func_80182F4C/related.txt b/.run/P36/agents/ov_SC03_006__func_80182F4C/related.txt new file mode 100644 index 0000000000..f10713ac22 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80182F4C/related.txt @@ -0,0 +1 @@ +=== lever-free bodies in ov_SC03_006 sharing a callee or global with func_80182F4C (0 found; top 6 by shared symbols) — read them for the SHAPE === diff --git a/.run/P36/agents/ov_SC03_006__func_80182F4C/residual.txt b/.run/P36/agents/ov_SC03_006__func_80182F4C/residual.txt new file mode 100644 index 0000000000..31ab35ec72 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80182F4C/residual.txt @@ -0,0 +1,45 @@ +src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c:func_80182F4C: score 29 (REG-caller; mine 81 ins, target 81) — not yet + register pairs (mine -> target, count): t1->t0 x10, t0->a3 x6, a3->a0 x6, t4->t3 x5, a0->t6 x2, t6->t5 x2, t3->t2 x2, t2->t1 x2 + replace mine[0:3] target[0:3] + 0 lui t1,0x0 | lui t0,0x0 + 1 addiu t1,t1,0 | addiu t0,t0,0 + 2 li t4,0xf800 | li t3,0xf800 + replace mine[5:8] target[5:8] + 5 sra a0,a0,0x10 | sra t6,a0,0x10 + 6 li t0,0xfa00 | li a3,0xfa00 + 7 andi v0,t4,0xffff | andi v0,t3,0xffff + replace mine[10:12] target[10:12] + 10 andi t6,v0,0x1ff | andi t5,v0,0x1ff + 11 andi v0,t0,0xffff | andi v0,a3,0xffff + replace mine[14:15] target[14:15] + 14 lhu v1,2(t1) | lhu v1,2(t0) + replace mine[17:18] target[17:18] + 17 lhu v1,4(t1) | lhu v1,4(t0) + replace mine[20:26] target[20:26] + 20 lw a3,20(t1) | lw a0,20(t0) + 21 lw t3,24(t1) | lw t2,24(t0) + 22 lw t2,28(t1) | lw t1,28(t0) + 23 lhu v0,0(t1) | lhu v0,0(t0) + 24 lw v1,8(t1) | lw v1,8(t0) + 25 subu v0,t6,v0 | subu v0,t5,v0 + replace mine[35:36] target[35:36] + 35 addu a3,a3,v1 | addu a0,a0,v1 + replace mine[40:42] target[40:42] + 40 li t5,0xffff | li t4,0xffff + 41 lhu v1,0(a3) | lhu v1,0(a0) + replace mine[49:50] target[49:50] + 49 addu v1,t3,v0 | addu v1,t2,v0 + replace mine[56:57] target[56:57] + 56 addu v1,t2,v0 | addu v1,t1,v0 + replace mine[59:60] target[59:60] + 59 bne v0,a0,8218 | bne v0,t6,8218 + replace mine[62:63] target[62:63] + 62 addiu a3,a3,2 | addiu a0,a0,2 + replace mine[66:69] target[66:69] + 66 addu a2,a2,t5 | addu a2,a2,t4 + 67 addiu t0,t0,128 | addiu a3,a3,128 + 68 andi v1,t0,0xffff | andi v1,a3,0xffff + replace mine[72:75] target[72:75] + 72 andi v0,t0,0xffff | andi v0,a3,0xffff + 73 addiu t4,t4,128 | addiu t3,t3,128 + 74 andi v1,t4,0xffff | andi v1,t3,0xffff diff --git a/.run/P36/agents/ov_SC03_006__func_80182F4C/sites.txt b/.run/P36/agents/ov_SC03_006__func_80182F4C/sites.txt new file mode 100644 index 0000000000..d23af18031 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80182F4C/sites.txt @@ -0,0 +1,4 @@ +REMOVED pin $8 line 7734 +REMOVED pin $11 line 7736 +REMOVED pin $7 line 7737 +NEEDED pin $4 line 7745 diff --git a/.run/P36/agents/ov_SC03_006__func_80182F4C/tu.txt b/.run/P36/agents/ov_SC03_006__func_80182F4C/tu.txt new file mode 100644 index 0000000000..add4ffed28 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80182F4C/tu.txt @@ -0,0 +1,2 @@ +src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c +func_80182F4C diff --git a/.run/P36/agents/ov_SC03_006__func_80189A84/body_free.c b/.run/P36/agents/ov_SC03_006__func_80189A84/body_free.c new file mode 100644 index 0000000000..70c2791418 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80189A84/body_free.c @@ -0,0 +1,29 @@ +void func_80189A84(s32 a0) +{ + s32 v0; + s32 v1; + + v0 = *(s32 *)(a0 + 0xDC); + if ((v0 & 0x2) != 0) { + v0 = *(s32 *)(a0 + 0x1C); + if (v0 >= 0x15) { + v1 = *(s32 *)(a0 + 0x20); + v0 = *(u16 *)(v1 + 0x10); + *(s16 *)(v1 + 0x10) = v0 - 0x28; + } + } + + v0 = *(s32 *)(a0 + 0x1C); + if (v0 < 0x11) { + v0 = *(s32 *)(a0 + 0x20); + v1 = *(s32 *)(v0 + 0x4); + v1 = v1 ^ 0x80000000; + *(s32 *)(v0 + 0x4) = v1; + } + + if (func_8012BEE8(a0) != 0) { + func_8002AC00(0xB); + func_80130D48(a0); + func_8018A05C(a0); + } +} diff --git a/.run/P36/agents/ov_SC03_006__func_80189A84/body_tree.c b/.run/P36/agents/ov_SC03_006__func_80189A84/body_tree.c new file mode 100644 index 0000000000..0be94ad9ed --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80189A84/body_tree.c @@ -0,0 +1,29 @@ +void func_80189A84(s32 a0) +{ + register s32 v0 __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus7) + register s32 v1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus7) + + v0 = *(s32 *)(a0 + 0xDC); + if ((v0 & 0x2) != 0) { + v0 = *(s32 *)(a0 + 0x1C); + if (v0 >= 0x15) { + v1 = *(s32 *)(a0 + 0x20); + v0 = *(u16 *)(v1 + 0x10); + *(s16 *)(v1 + 0x10) = v0 - 0x28; + } + } + + v0 = *(s32 *)(a0 + 0x1C); + if (v0 < 0x11) { + v0 = *(s32 *)(a0 + 0x20); + v1 = *(s32 *)(v0 + 0x4); + v1 = v1 ^ 0x80000000; + *(s32 *)(v0 + 0x4) = v1; + } + + if (func_8012BEE8(a0) != 0) { + func_8002AC00(0xB); + func_80130D48(a0); + func_8018A05C(a0); + } +} diff --git a/.run/P36/agents/ov_SC03_006__func_80189A84/history.txt b/.run/P36/agents/ov_SC03_006__func_80189A84/history.txt new file mode 100644 index 0000000000..0af64250ee --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80189A84/history.txt @@ -0,0 +1,14 @@ +g6b: verdict NO-MATCH start 30 best 3 compiles 323 path R9 swap-stmts @12944 +best-scoring single candidates of the last trace (move -> score [residual class]): + R9 swap-stmts @12944 -> 3 [COUNT] (from 30) + R9 swap-stmts @12945 -> 3 [COUNT] (from 30) + R8 temp tmp0 @12941 -> 3 [COUNT] (from 3) + R7 block @12944 -> 3 [COUNT] (from 3) + R10 param-copy a0 @12930 -> 3 [COUNT] (from 3) + R2 decl-order 1,0 -> 3 [COUNT] (from 3) + R6 inline v0 @12941 -> 3 [COUNT] (from 3) + R8 base tmp0 @12941 -> 3 [COUNT] (from 3) + R7 do-while @12944 -> 3 [COUNT] (from 3) + R8 temp tmp0 @12945 -> 3 [COUNT] (from 3) + R7 block @12941 -> 3 [COUNT] (from 3) + R9 swap-stmts @12943 -> 3 [COUNT] (from 3) diff --git a/.run/P36/agents/ov_SC03_006__func_80189A84/neighbours.txt b/.run/P36/agents/ov_SC03_006__func_80189A84/neighbours.txt new file mode 100644 index 0000000000..38fe5e1209 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80189A84/neighbours.txt @@ -0,0 +1,57 @@ +--- every @class/@stuck/@crack note in this translation unit --- +// @class: plumbing +// @stuck: none — MATCH +// @class: regalloc-order — simplified sibling of matched func_8017B614. +// @stuck: none. Block-moves are align-1 struct-assigns (u8[8]) -> emit_block_move +// @class: struct +// @stuck: none — MATCH (74 ins) +// @class: regalloc-order + T1 memcpy-builtin→call re-crack +// @stuck: 0 (iso). Register lever = $16 pin + in-place re-tie on the memcpy-branch src (keeps +// @class: plumbing +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH (63 ins) +// @class: struct +// @stuck: none — MATCH (62 ins) +// @class: struct +// @stuck: none — MATCH (65 ins) +// @class: regalloc-order +// @stuck: pending self-check — register order param=$s2 counter=$s1 ptr=$s0 +// @class: plumbing +// @stuck: none — MATCH (expected); short-typed global increment + signed compare, store-2 on overflow +// @class: plumbing +// @stuck: none — MATCH expected (simple short-increment + guarded call) +// @class: regalloc-order +// @stuck: none — MATCH (branch-polarity invert: fn-ptr non-zero call is the fall-through arm) +// @class: plumbing +// @stuck: none — MATCH (41 ins, relocation-masked); frame needed a 0x30 address-taken local +// @class: plumbing +// @stuck: none — signed s32 counter at 0x1C, delay-slot store is the unconditional bump +// @class: struct +// @stuck: none — MATCH (array-of-fnptr %lo-fold + signed-halfword guard) +// @class: regalloc-order +// @stuck: none — MATCH +// @class: structural (STRENGTH/mflo!=lw -> MATCH) +// @stuck: none - MATCH (41 ins), match_one + rtu_match. +// @class: straight-derive +// @stuck: none — MATCH (52 ins) on iteration 1, confirmed by rtu_match. +// @class: structural (STRENGTH/mflo!=lw -> MATCH) +// @stuck: none - MATCH (41 ins), match_one + rtu_match. +// @class: regalloc (WIDTH/li!=addu -> MATCH) +// @stuck: none — MATCH (58 ins), match_one + rtu_match. PIN-FREE (no register __asm__). +// @class: structural (STRENGTH/mflo!=lw -> MATCH) +// @stuck: none - MATCH (41 ins), match_one + rtu_match. +// @class: plumbing +// @stuck: none — MATCH (18 ins): if((b&1) && p!=&sym) call(param,&sym); $a0 live, $a1=&sym fall out +// @class: schedule +// @stuck: none — MATCH (44 ins). Two §3-T4 branch-polarity inversions: outer if(param_2>=iVar2) makes the func_8018B1B4 else-block fall-through; inner if(param_3>=iVar2) return 0 makes the func_8012A828 body fall-through. No pins needed — natural $s1/$s0/$s2 alloc matched. +// @class: plumbing +// @stuck: none — MATCH (straightforward; callee sigs canonical from overlay) +// @class: plumbing +// @stuck: none — MATCH (clean if/else, sh into delay slot of func_8001CA88 call) +// @class: plumbing +// @stuck: none — MATCH expected (single call-crossing local pins to $s0 naturally; lhu via unsigned short) diff --git a/.run/P36/agents/ov_SC03_006__func_80189A84/related.txt b/.run/P36/agents/ov_SC03_006__func_80189A84/related.txt new file mode 100644 index 0000000000..e61b853372 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80189A84/related.txt @@ -0,0 +1,150 @@ +=== lever-free bodies in ov_SC03_006 sharing a callee or global with func_80189A84 (60 found; top 6 by shared symbols) — read them for the SHAPE === +--- func_8018993C (src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c:12809) shares 4: func_8002AC00 func_8012BEE8 func_80130D48 func_8018A05C --- +void func_8018993C(s32 a0) { + if (*(s32 *)(a0 + 0x1C) < 0x11) { + s32 mask; + s32 ptr; + s32 val; + + mask = 0x80000000; + ptr = *(s32 *)(a0 + 0x20); + val = *(s32 *)(ptr + 0x4); + val ^= mask; + *(s32 *)(ptr + 0x4) = val; + } + + if (func_8012BEE8(a0) != 0) { + func_8002AC00(0xB); + func_80130D48(a0); + func_8018A05C(a0); + } +} + +--- func_801856A0 (src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c:9601) shares 3: func_8002AC00 func_8012BEE8 func_80130D48 --- +void func_801856A0(s32 a0) { + s32 obj; + s32 i; + s32 t4; + s32 tmp; + s32 q1; + unsigned int *pbuf; + s32 r1, r2, r4; + s32 ang1, dist; + s32 base, v3; + s32 buf; + u16 pos[3]; + + obj = a0; + + if (*(u16 *)(obj + 0x34) != 0) { + if (func_8012BEE8(a0) != 0) { + func_8002AC00(0xA); + func_80130D48(obj); + func_80185D20(obj); + } + return; + } + + i = 0; + pbuf = (unsigned int *)&buf; + for (; i < 10;) { + r1 = rand(); + tmp = (r1 >= 0) ? r1 : (r1 + 0xFFF); + ang1 = r1 - ((tmp >> 12) << 12); + + r2 = rand(); + q1 = r2 / 48; + dist = r2 - q1 * 48; + + func_8012B0B4(pbuf, ang1, dist); + t4 = buf; + + pos[0] = *(u16 *)(obj + 0x6) + t4; + + v3 = rand() % 24; + + base = *(s16 *)(obj + 0xA) - 0x34; + + r4 = rand(); + { + s32 t1 = (r4 & 1) ? (base + v3) : (base - v3); + pos[1] = t1; + + { + s32 hi4; + hi4 = t4 >> 16; + pos[2] = *(u16 *)(obj + 0xE) + hi4; + } + func_80143BDC(pos); + i++; + } + } + + *(s32 *)(obj + 0x1C) = 0x10; + *(u16 *)(obj + 0x34) += 1; + + for (i = 0; i < 3; i++) { + func_8012C658(0x240, i, obj); + } +} + +--- func_8012FF98 (src/shared/ov/func_8012FF98.h:7) shares 2: func_8012BEE8 func_80130D48 --- +void func_8012FF98(u8 *a0) { + if (*(s32 *)(a0 + 0xB4) & 0x20) { + s32 p = *(s32 *)(a0 + 0x20); + if (p != 0) { + *(u32 *)(p + 4) ^= 0x80000000; + } + if (func_8012BEE8((s32)a0)) { + func_80130D48((s32)a0); + func_801319E0((s32)a0); + } + } + func_80131CA8((int)a0, 0x10); +} + +--- func_801301E8 (src/shared/ov/func_801301E8.h:7) shares 2: func_8012BEE8 func_80130D48 --- +void func_801301E8(u8 *a0) { + if (*(s32 *)(a0 + 0xB4) & 0x2000) { + if (*(u8 *)(a0 + 0xC3) != 0) { + if (*(u16 *)(a0 + 0x72) & 0x4000) { + func_80130D48((s32)a0); + func_801319E0((s32)a0); + } + } else if (func_8012BEE8((s32)a0) != 0) { + func_80130D48((s32)a0); + func_801319E0((s32)a0); + } + } + func_80131CA8((int)a0, 0x26); +} + +--- func_80184034 (src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c:8418) shares 2: func_8012BEE8 func_80130D48 --- +void func_80184034(s32 a0) { + if (*(s32 *)(a0 + 0x1C) < 0xC) { + s32 mask; + s32 ptr; + s32 val; + + mask = 0x80000000; + ptr = *(s32 *)(a0 + 0x20); + val = *(s32 *)(ptr + 0x4); + val ^= mask; + *(s32 *)(ptr + 0x4) = val; + } + + if (func_8012BEE8(a0) != 0) { + func_80130D48(a0); + *(s32 *)(a0 + 0x1C) = 0x3C; + *(s32 *)(*(s32 *)(a0 + 0x20) + 4) = 0x80000000; + func_801846D0(a0); + } +} + +--- func_80188F14 (src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c:12280) shares 1: func_8012BEE8 --- + void func_80188F14(void *a0) { + if (func_8012BEE8((s32)a0)) { + *(s16 *)((s32)a0 + 0x2) = 0x5; + } + } + diff --git a/.run/P36/agents/ov_SC03_006__func_80189A84/residual.txt b/.run/P36/agents/ov_SC03_006__func_80189A84/residual.txt new file mode 100644 index 0000000000..5aee72e35e --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80189A84/residual.txt @@ -0,0 +1,39 @@ +src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c:func_80189A84: score 30 (COUNT; mine 46 ins, target 46) — not yet + register pairs (mine -> target, count): v1->v0 x3 + replace mine[4:5] target[4:5] + 4 lw v1,220(s0) | lw v0,220(s0) + replace mine[6:7] target[6:7] + 6 andi v0,v1,0x2 | andi v0,v0,0x2 + replace mine[9:10] target[9:10] + 9 lw v1,28(s0) | lw v0,28(s0) + replace mine[11:15] target[11:13] + 11 slti v0,v1,21 | slti v0,v0,21 + 12 bnez v0,ecb4 | bnez v0,eca8 + 13 slti v0,v1,17 | -- + 14 lw a0,32(s0) | -- + delete mine[16:25] target[14:14] + 16 lhu v1,16(a0) | -- + 17 nop | -- + 18 addiu v0,v1,-40 | -- + 19 sh v0,16(a0) | -- + 20 lw v1,28(s0) | -- + 21 nop | -- + 22 slti v0,v1,17 | -- + 23 beqz v0,ecd4 | -- + 24 lui v0,0x8000 | -- + replace mine[27:28] target[16:17] + 27 lw a0,4(v1) | lhu v0,16(v1) + replace mine[29:31] target[18:31] + 29 xor a0,a0,v0 | addiu v0,v0,-40 + 30 sw a0,4(v1) | sh v0,16(v1) + 31 -- | lw v0,28(s0) + 32 -- | nop + 33 -- | slti v0,v0,17 + 34 -- | beqz v0,ecd4 + 35 -- | lui a0,0x8000 + 36 -- | lw v0,32(s0) + 37 -- | nop + 38 -- | lw v1,4(v0) + 39 -- | nop + 40 -- | xor v1,v1,a0 + 41 -- | sw v1,4(v0) diff --git a/.run/P36/agents/ov_SC03_006__func_80189A84/sites.txt b/.run/P36/agents/ov_SC03_006__func_80189A84/sites.txt new file mode 100644 index 0000000000..3e91b32cf7 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80189A84/sites.txt @@ -0,0 +1,2 @@ +NEEDED pin $2 line 13113 +NEEDED pin $3 line 13114 diff --git a/.run/P36/agents/ov_SC03_006__func_80189A84/tu.txt b/.run/P36/agents/ov_SC03_006__func_80189A84/tu.txt new file mode 100644 index 0000000000..045c159360 --- /dev/null +++ b/.run/P36/agents/ov_SC03_006__func_80189A84/tu.txt @@ -0,0 +1,2 @@ +src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c +func_80189A84 diff --git a/.run/P36/census/lever_census.json b/.run/P36/census/lever_census.json index 604639ab9c..f44979be71 100644 --- a/.run/P36/census/lever_census.json +++ b/.run/P36/census/lever_census.json @@ -53,7 +53,7 @@ }, "kinds": { "asm-body/direct": 13, - "barrier/direct": 345, + "barrier/direct": 329, "barrier/via-macro": 2, "gte-lever/direct": 362, "gte-lever/via-macro": 94, @@ -62,64 +62,84 @@ "gte/via-macro": 6128, "instruction/direct": 210, "instruction/via-macro": 22, - "keepalive/direct": 349, - "launder/direct": 686, + "keepalive/direct": 346, + "launder/direct": 664, "launder/via-macro": 42, "verbatim-body/direct": 2682 } }, "binaries": 218, "cfake_markers": { - "count": 13, + "count": 33, "sample": [ - "src/md_SC07_003/md_SC07_003.c:3577", "src/md_SC07_004/md_SC07_004.c:280", + "src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c:4815", + "src/ov_SC05_005/ov_SC05_005_jr_8017D898.c:4026", + "src/800.c:12748", + "src/md_SC07_003/md_SC07_003.c:3577", + "src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c:3570", "src/ov_SC01_009/ov_SC01_009_jr_8017E590.c:4271", + "src/ov_SC01_077/ov_SC01_077_jr_80183CF4.c:3979", "src/ov_SC01_080/ov_SC01_080_jr_8017AE2C.c:5178", - "src/ov_SC02_028/ov_SC02_028_jr_8017D898.c:5475", + "src/ov_SC02_011/ov_SC02_011_jr_80183178.c:2139", + "src/ov_SC02_027/ov_SC02_027_jr_8017D898.c:4534", + "src/ov_SC02_028/ov_SC02_028_jr_8017D898.c:5464", "src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c:7554", + "src/ov_SC03_014/ov_SC03_014_jr_801848E4.c:5080", + "src/ov_SC03_024/ov_SC03_024_jr_8017DF84.c:5530", + "src/ov_SC03_024/ov_SC03_024_jr_80183BF8.c:3108", + "src/ov_SC03_118/ov_SC03_118_jr_8017FB84.c:3796", + "src/ov_SC03_121/ov_SC03_121_jr_8017E1D0.c:4568", + "src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c:6575", + "src/ov_SC03_124/ov_SC03_124_jr_80188544.c:4422", "src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c:10069", "src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c:9323", "src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c:6630", + "src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:7487", + "src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:10290", "src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c:5814", - "src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c:4815", - "src/ov_SC05_005/ov_SC05_005_jr_8017D898.c:4026", - "src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c:3335" + "src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c:3335", + "src/ov_SC05_018/ov_SC05_018_jr_8017D604.c:4942", + "src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c:8485", + "src/ov_SC06_016/ov_SC06_016_jr_801816DC.c:3082", + "src/ov_SC06_024/ov_SC06_024_jr_80186F00.c:5419", + "src/ov_SC06_029/ov_SC06_029_jr_8017C954.c:6669", + "src/shared/ov/func_80169584.h:42" ] }, "classes": { "A": { - "bodies": 1559, - "distinct_bodies": 712, + "bodies": 1520, + "distinct_bodies": 681, "file_scope": 0, - "in_bodies": 2478, + "in_bodies": 2424, "kinds": { - "pin": 2478 + "pin": 2424 }, - "marked": 2478, - "sites": 2478, - "tus": 1097, + "marked": 2424, + "sites": 2424, + "tus": 1091, "unmarked": 0 }, "B": { - "bodies": 4749, - "distinct_bodies": 803, + "bodies": 4720, + "distinct_bodies": 779, "file_scope": 13, - "in_bodies": 11393, + "in_bodies": 11352, "kinds": { "asm-body": 13, - "barrier": 347, + "barrier": 331, "gte": 6328, "gte-lever": 456, "gte-unsigned": 271, "instruction": 232, - "keepalive": 349, - "launder": 728, + "keepalive": 346, + "launder": 706, "verbatim-body": 2682 }, - "marked": 2615, - "sites": 11406, - "tus": 1431, + "marked": 2574, + "sites": 11365, + "tus": 1428, "unmarked": 8791 }, "C": { @@ -152,17 +172,17 @@ "unmarked": 50 }, "E": { - "bodies": 1089, - "distinct_bodies": 153, + "bodies": 1096, + "distinct_bodies": 157, "file_scope": 6423, - "in_bodies": 1357, + "in_bodies": 1364, "kinds": { - "asm-label": 7780 + "asm-label": 7787 }, "marked": 0, - "sites": 7780, + "sites": 7787, "tus": 2090, - "unmarked": 7780 + "unmarked": 7787 }, "F": { "bodies": 428, @@ -224,9 +244,9 @@ "coverage": { "asm": { "comment_dead": 6782, - "live": 15538, + "live": 15450, "macro_block": 194, - "raw": 22514 + "raw": 22426 }, "attribute": { "comment_dead": 0, @@ -242,20 +262,20 @@ }, "register": { "comment_dead": 8576, - "live": 2528, + "live": 2474, "macro_block": 18, - "raw": 11122 + "raw": 11068 }, "volatile": { - "comment_dead": 2607, - "live": 1700, + "comment_dead": 2606, + "live": 1699, "macro_block": 82, - "raw": 4389 + "raw": 4387 } }, "coverage_ok": true, - "elapsed_s": 30.7, - "generated": "2026-09-10", + "elapsed_s": 35.3, + "generated": "2026-09-11", "gte_levers": { "direct": 362, "marked": 456, @@ -265,15 +285,15 @@ "via_macro": 94, "what": "GTE ops whose clobbers exceed the canonical macro's (a scheduling steer): class-B levers INSIDE the headline number since T5 (2026-09-09), marked, 0 at the close" }, - "head": "93e2a9170", + "head": "2e7bc0947", "headers": 3181, "levers_AB": { - "asm": 2125, - "bodies": 2301, - "distinct_bodies": 973, - "marked": 4603, - "pins": 2478, - "sites": 4603, + "asm": 2084, + "bodies": 2238, + "distinct_bodies": 921, + "marked": 4508, + "pins": 2424, + "sites": 4508, "unmarked": 0, "what": "register pins + asm statements excluding GTE ops: the classes the phase drives to 0" }, @@ -407,28 +427,28 @@ }, "pins": { "bare_name": 15, - "init": 239, + "init": 221, "registers": { - "$0": 72, + "$0": 70, "$10": 10, "$11": 5, "$12": 9, "$13": 6, "$14": 5, "$15": 1, - "$16": 105, - "$17": 48, - "$18": 33, - "$19": 26, - "$2": 857, - "$20": 8, + "$16": 98, + "$17": 41, + "$18": 32, + "$19": 22, + "$2": 844, + "$20": 7, "$21": 6, - "$22": 7, - "$23": 10, + "$22": 3, + "$23": 6, "$25": 1, "$29": 13, - "$3": 203, - "$4": 514, + "$3": 199, + "$4": 507, "$5": 387, "$6": 63, "$7": 27, @@ -440,30 +460,30 @@ "v0": 2, "v1": 3 }, - "sites": 2478, + "sites": 2424, "sp": 13, "spelling": { - "__asm__": 2448, + "__asm__": 2394, "asm": 30 }, "volatile_qualified": 0, - "zero": 72 + "zero": 70 }, - "src_stamp": "1dcece0f1969b9d6", + "src_stamp": "16c906a24b01d57d", "tus": 4121, "unclassified": 0, "union_AD": { - "bodies": 6039, + "bodies": 5982, "by_kind": { - "main": 162, - "md": 120, - "ov": 5580, + "main": 161, + "md": 119, + "ov": 5530, "resident": 10, - "shared": 167 + "shared": 162 }, - "copies_in_multi": 4886, - "distinct_bodies": 1279, - "multi_copy_classes": 126 + "copies_in_multi": 4871, + "distinct_bodies": 1232, + "multi_copy_classes": 121 }, "verbatim_excluded": { "functions": 13, diff --git a/.run/P36/census/lever_census.txt b/.run/P36/census/lever_census.txt index 4c3813963d..adc0473dcf 100644 --- a/.run/P36/census/lever_census.txt +++ b/.run/P36/census/lever_census.txt @@ -1,32 +1,32 @@ lever_census: 218 binaries · 4,121 TUs + 3,181 headers · coverage OK · unclassified 0 · verbatim excluded 13 fn / 14 sites (manifest 13) - coverage asm raw 22514 = live 15538 + macro-block 194 + comment/dead 6782 - coverage register raw 11122 = live 2528 + macro-block 18 + comment/dead 8576 - coverage volatile raw 4389 = live 1700 + macro-block 82 + comment/dead 2607 + coverage asm raw 22426 = live 15450 + macro-block 194 + comment/dead 6782 + coverage register raw 11068 = live 2474 + macro-block 18 + comment/dead 8576 + coverage volatile raw 4387 = live 1699 + macro-block 82 + comment/dead 2606 coverage builtin raw 599 = live 445 + macro-block 0 + comment/dead 154 coverage attribute raw 76 = live 76 + macro-block 0 + comment/dead 0 class sites in-bodies file-scope bodies distinct TUs marked unmarked kinds - A pins 2478 2478 0 1559 712 1097 2478 0 {'pin': 2478} - B asm 11406 11393 13 4749 803 1431 2615 8791 {'gte': 6328, 'barrier': 347, 'gte-lever': 456, 'gte-unsigned': 271, 'launder': 728, 'instruction': 232, 'asm-body': 13, 'keepalive': 349, 'verbatim-body': 2682} - C volatile 1590 1438 152 496 95 610 14 1576 {'decl-body': 58, 'decl-file': 152, 'cast': 1378, 'param': 2} + A pins 2424 2424 0 1520 681 1091 2424 0 {'pin': 2424} + B asm 11365 11352 13 4720 779 1428 2574 8791 {'barrier': 331, 'keepalive': 346, 'instruction': 232, 'gte-lever': 456, 'launder': 706, 'gte': 6328, 'gte-unsigned': 271, 'asm-body': 13, 'verbatim-body': 2682} + C volatile 1590 1438 152 496 95 610 14 1576 {'cast': 1378, 'decl-body': 58, 'decl-file': 152, 'param': 2} D register 50 50 0 47 47 6 0 50 {'register': 50} - E asm-label 7780 1357 6423 1089 153 2090 0 7780 {'asm-label': 7780} + E asm-label 7787 1364 6423 1096 157 2090 0 7787 {'asm-label': 7787} F builtin 445 445 0 428 27 302 0 445 {'builtin': 445} G attribute 76 1 75 1 1 40 0 76 {'attribute': 76} - UNION A–D: 6,039 bodies · 1,279 distinct (addresses normalized) · 126 multi-copy classes holding 4,886 bodies · by kind {'ov': 5580, 'main': 162, 'md': 120, 'resident': 10, 'shared': 167} - THE PHASE'S NUMBER (pins + asm statements, GTE excluded): 4,603 sites in 2,301 bodies (973 distinct) · marked !FAKE 4,603 · UNMARKED 0 + UNION A–D: 5,982 bodies · 1,232 distinct (addresses normalized) · 121 multi-copy classes holding 4,871 bodies · by kind {'ov': 5530, 'main': 161, 'md': 119, 'shared': 162, 'resident': 10} + THE PHASE'S NUMBER (pins + asm statements, GTE excluded): 4,508 sites in 2,238 bodies (921 distinct) · marked !FAKE 4,508 · UNMARKED 0 orphan !FAKE markers (no pin/asm site on the line nor below): 0 - marked ordinary-C fakes kept by Drew's S104 ruling (a) (`do { } while (0)`, dead initialisers; NOT levers): 13 + marked ordinary-C fakes kept by Drew's S104 ruling (a) (`do { } while (0)`, dead initialisers; NOT levers): 33 GTE levers (clobbers beyond the canonical macro's): 456 sites (94 via a variant macro, 362 direct) · marked 456 · UNMARKED 0 · unsigned GTE statements 271 per-TU asm macro definitions outside the GTE header: 314 {'gte': 150, 'launder': 154, 'instruction': 9, 'barrier': 1} (GTE variants 64) - pins: 2,478 · $0 72 · $sp 13 · with initializer 239 · volatile-qualified 0 · bare-name 15 · spellings {'__asm__': 2448, 'asm': 30} + pins: 2,424 · $0 70 · $sp 13 · with initializer 221 · volatile-qualified 0 · bare-name 15 · spellings {'__asm__': 2394, 'asm': 30} whole-body asm routines in C shells, manifest PERMANENT (hand asm, NOT levers): 22 routines · 2,682 sites (2,660 private copies + 22 shared headers); asm-bodies NOT permanent (levers): 13 site(s) ['func_8001E378:DECOMPILE-NOW', 'func_80020F34:DECOMPILE-NOW', 'func_800249F0:DECOMPILE-NOW', 'func_80025CBC:DECOMPILE-NOW', 'func_80026514:UNCERTAIN', 'func_800268D0:UNCERTAIN', 'func_80027058:DECOMPILE-NOW', 'func_80027200:DECOMPILE-NOW', 'func_800CBA44:DECOMPILE-NOW', 'func_8017D810:DECOMPILE-NOW', 'func_8017E26C:UNCERTAIN', 'func_80184440:DECOMPILE-NOW', 'func_801A3BCC:DECOMPILE-NOW'] - asm kinds: {'asm-body/direct': 13, 'barrier/direct': 345, 'barrier/via-macro': 2, 'gte/direct': 200, 'gte/via-macro': 6128, 'gte-lever/direct': 362, 'gte-lever/via-macro': 94, 'gte-unsigned/direct': 271, 'instruction/direct': 210, 'instruction/via-macro': 22, 'keepalive/direct': 349, 'launder/direct': 686, 'launder/via-macro': 42, 'verbatim-body/direct': 2682} + asm kinds: {'asm-body/direct': 13, 'barrier/direct': 329, 'barrier/via-macro': 2, 'gte/direct': 200, 'gte/via-macro': 6128, 'gte-lever/direct': 362, 'gte-lever/via-macro': 94, 'gte-unsigned/direct': 271, 'instruction/direct': 210, 'instruction/via-macro': 22, 'keepalive/direct': 346, 'launder/direct': 664, 'launder/via-macro': 42, 'verbatim-body/direct': 2682} instruction mnemonics: {'la': 142, 'addu': 23, 'addiu': 22, 'RTP_SND': 22, '.section': 7, 'lui': 4, 'lh': 3, 'and': 2, 'mult': 1, 'mfhi': 1, 'sll': 1, 'li': 1, 'lw': 1, 'nop': 1, 'srl': 1} - gte mnemonics: {'gte_ldv0': 757, 'gte_stlvnl': 593, 'gte_stsxy': 447, 'gte_rtps': 437, 'gte_stflg': 415, 'gte_rtpt': 352, 'gte_SetRotMatrix': 249, 'gte_stsxy3': 236, 'gte_SetTransMatrix': 229, 'gte_rtv0tr': 228, 'gte_ldv3c': 184, 'gte_ldv3': 177, 'gte_stsv': 161, 'lwc2': 159, 'gte_stsz4': 149, 'gte_stsz3': 147, 'gte_stszotz': 134, 'gte_dpcl': 134, 'gte_stsxy3_f3': 111, 'gte_stclmv': 108, 'gte_nclip': 108, 'gte_stopz': 108, 'gte_stsxy3c': 108, 'gte_stsxy3_ft3': 79, 'gte_rtir': 75, 'gte_ldclmv': 72, 'gte_avsz4': 56, 'gte_stotz': 52, 'gte_ldrgb': 30, 'gte_nccs': 25} + gte mnemonics: {'gte_ldv0': 757, 'gte_stlvnl': 593, 'gte_stsxy': 447, 'gte_rtps': 437, 'gte_stflg': 415, 'gte_rtpt': 352, 'gte_SetRotMatrix': 249, 'gte_stsxy3': 236, 'gte_SetTransMatrix': 229, 'gte_rtv0tr': 228, 'gte_ldv3c': 184, 'gte_ldv3': 177, 'gte_stsv': 161, 'lwc2': 159, 'gte_stsz4': 149, 'gte_stsz3': 147, 'gte_stszotz': 134, 'gte_dpcl': 134, 'gte_stsxy3_f3': 111, 'gte_nclip': 108, 'gte_stopz': 108, 'gte_stsxy3c': 108, 'gte_stclmv': 108, 'gte_stsxy3_ft3': 79, 'gte_rtir': 75, 'gte_ldclmv': 72, 'gte_avsz4': 56, 'gte_stotz': 52, 'gte_ldrgb': 30, 'gte_nccs': 25} asm-bearing macro definitions: 314 (20 names, 3 with >1 text) kinds {'gte': 150, 'launder': 154, 'instruction': 9, 'barrier': 1} controls (R39): src/800.c func_800226C0 pins got 14 expected 45 N-A src/shared/ov/func_80178004.h pins got 8 expected 26 N-A ov_SC03_006 func_80184034 bare-name pins got 0 expected 3 N-A engine_prelude.h asm sites (a macro definition only) got 0 expected 0 OK - elapsed 30.7 s + elapsed 35.3 s diff --git a/phase-ends/CURRENT_PHASE.md b/phase-ends/CURRENT_PHASE.md index c1ea5e1555..721558fc18 100644 --- a/phase-ends/CURRENT_PHASE.md +++ b/phase-ends/CURRENT_PHASE.md @@ -1891,6 +1891,20 @@ accumulate here as the phase produces them.** 218 passed, 0 failed of 218` (r22_d); census **4,661** (exit 0). The R23/R34/R35/R36 pass `s104_new4` is running (16 MATCH at 650/915); agents d20, d30–d33 in flight. +- **S104 — the fifth wave and the TU batches.** d30–d39 + d34: d30 `func_80183884` (7), d31 `func_80182FB4` (4), d32 + `func_80181744` (3), d33 `func_8017DD70` (4), d34 `func_80181408` (7), d35 `func_8018486C` (4), d37 `func_8017DAB8` (4), d38 + `func_801818A4` (2 + 4 siblings de-do-while'd), d39 `func_80185484` (3) — all 0 with ZERO levers; **d36 `func_80183CC4` ×5 + PARKED** (a `void` → `s32` signature, like d29). Generators widened: R31 all-shifts, R35 cast copies, `named_definitions` sees + `func_X_body` asm-label definitions, R37 `return_constants`; `tools/localalloc_sim.py` models the three-quantity switch (the old + tool mispredicted 387/16/228 blocks on d5's dumps, the new 0/0/0). Regen passes banked: R23/R34–R36 16/16, R37 4, part 3 (the + all-families pass's rows on the live residue) 38 rows — **a 590 s tool timeout killed that bank mid-run; the 30 files it had + written were verified by R22 `check-all: 218 passed` before committing (`c5786dac6`), the rest resumed (6 more)** — and R31/R35 + 4 + 1. TU batches from here (the residue's copies are 1–2): e1 `md_SC07_004` → `func_801AB818` 0 zero levers; + `func_801A1E94`/`func_801A5C44` close only as a SIGNATURE change (a `(void)` function that reads a pinned `$a0` takes a parameter; + five externs and the callers change) — PARKED; e1 estimates **~158 such "`$4` pin = a missing parameter" functions in `src/` (a + rough regex, unverified), ~110 of them `func_80157D20` copies** — the structs phase's signature population. R22 after every + batch (r22_e/f/g): `check-all: 218 passed, 0 failed of 218`; census **4,517** → (after e1) exit 0. + ## 🛑 SESSION CHECKPOINT — S104 (2026-09-10, refreshed ~23:55): T0–T6 ☑, **T7 RUNNING**. 5,097 → **4,603 sites** this session; 38 agent draws, **32 closed at 0** (31 with zero levers, d4 one marked do-while), d29 PARKED (a void→s32 signature — structs phase), d20 PARKED (a minimum-lever body with two invented always-false C branches — **Drew's call**); generators **R27–R37**; the census counts kept ordinary-C fakes apart; R22 `check-all: 218 passed, 0 failed of 218` after every batch | `lever_census --check` exit 0 (4,603 marked, 0 UNMARKED, 0 orphans) ### 0. How to use this block