mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-09-26 13:33:34 -04:00
phase-36: S105 s105_f8 — func_8018CA74 banked at 0 through the whole-object gate + propagated — f8 plain C (copy-first after the call + a store straddle; 3 pins → 0)
This commit is contained in:
Drew T
+174
-174
@@ -1,5 +1,5 @@
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},
|
||||
"ok": true,
|
||||
"seconds": 2.1
|
||||
"seconds": 2.2
|
||||
}
|
||||
|
||||
@@ -29626,3 +29626,4 @@
|
||||
{"ts": "2026-09-11 18:18:14", "label": "s105_f8", "rung": "E", "calib": {"head": "7069f8c3d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_80185E80.c", "fn": "func_80186424", "addr": 2149082148, "aliases": null, "header": false, "includers": 0, "nhash_before": "5653916b57bfa254ee44e38a2b3dd2a5f8ca90fb", "nhash_after": "c363e38222fd4dd72c0fa7ed1c7b8b9e2a110e17", "source": ".run/P36/agents/ov_SC02_005__func_80186424/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.183, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_80185E80.o"], "before_text": "void func_80186424(s32 arg0)\n{\n if (*(u8 *)(arg0 + 0x74) != 0) {\n extern s32 gVecX __asm__(\"D_80126B5C\");\n s32 in[4];\n s32 out[4];\n s32 tmp[4];\n u16 h;\n\n in[0] = gVecX;\n in[1] = D_80126B60;\n in[2] = D_80126B64;\n func_8012F0BC((s32 *)(*(s32 *)(arg0 + 0x20) + 0x34), in, tmp);\n func_80132784(arg0, *(s32 *)(arg0 + 0x64), *(u16 *)(arg0 + 0xFC));\n func_8012F1A4((s32 *)(*(s32 *)(arg0 + 0x20) + 0x34), (s32)tmp, out);\n gVecX = out[0];\n D_80126B60 = out[1];\n D_80126B64 = out[2];\n h = *((u16 *)&gVecX + 1);\n *(u16 *)((s32)D_80126B78 + 8) = h;\n *(s32 *)((s32)D_80126B78 + 0x48) = (s32)(s16)h;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus10)\n *(u16 *)((s32)D_80126B78 + 0xA) = D_80126B62;\n *(s32 *)((s32)D_80126B78 + 0x4C) = (s32)(s16)D_80126B62;\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus10)\n *(u16 *)((s32)D_80126B78 + 0xC) = D_80126B66;\n *(s32 *)((s32)D_80126B78 + 0x50) = (s32)(s16)D_80126B66;\n } else {\n func_80132784(arg0, *(s32 *)(arg0 + 0x64), *(u16 *)(arg0 + 0xFC));\n }\n}\n", "after_text": "void func_80186424(s32 arg0)\n{\n if (*(u8 *)(arg0 + 0x74) != 0) {\n extern s32 gVecX __asm__(\"D_80126B5C\");\n extern s32 *aCam[] __asm__(\"D_80126B78\");\n s32 in[4];\n s32 out[4];\n s32 tmp[4];\n\n in[0] = gVecX;\n in[1] = D_80126B60;\n in[2] = D_80126B64;\n func_8012F0BC((s32 *)(*(s32 *)(arg0 + 0x20) + 0x34), in, tmp);\n func_80132784(arg0, *(s32 *)(arg0 + 0x64), *(u16 *)(arg0 + 0xFC));\n func_8012F1A4((s32 *)(*(s32 *)(arg0 + 0x20) + 0x34), (s32)tmp, out);\n gVecX = out[0];\n D_80126B60 = out[1];\n D_80126B64 = out[2];\n *(s32 *)((s32)aCam[0] + 0x48) = *(s16 *)((s32)aCam[0] + 8) = *((u16 *)&gVecX + 1);\n *(s32 *)((s32)aCam[0] + 0x4C) = *(s16 *)((s32)aCam[0] + 0xA) = D_80126B62;\n *(s32 *)((s32)aCam[0] + 0x50) = *(s16 *)((s32)aCam[0] + 0xC) = D_80126B66;\n } else {\n func_80132784(arg0, *(s32 *)(arg0 + 0x64), *(u16 *)(arg0 + 0xFC));\n }\n}\n"}
|
||||
{"ts": "2026-09-11 18:18:31", "label": "s105_f8", "rung": "E", "calib": {"head": "21f2fd8e4", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_80185E80.c", "fn": "func_8018622C", "addr": 2149081644, "aliases": null, "header": false, "includers": 0, "nhash_before": "3273b305758c8bd2a33b7b916a2ca19fda10a321", "nhash_after": "661cbcef9e85fb64f7bdd4c69ef35db07e9c91c0", "source": ".run/P36/agents/ov_SC02_005__func_8018622C/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.185, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_80185E80.o"], "before_text": "void func_8018622C(MainStruct *a0) {\n register MainStruct *a1 __asm__(\"$5\"); // !FAKE: pin $5 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n register SubStruct *v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n register s32 v0 __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n s32 a2;\n\n a1 = a0;\n a2 = 0x7FFFFFFF;\n\n v1 = a1->f_20;\n v0 = v1->field_4;\n v0 &= a2;\n v1->field_4 = v0;\n\n v0 = (s32)a1->f_CC;\n v1 = ((MainStruct *)v0)->f_20;\n v0 = v1->field_4;\n v0 &= a2;\n v1->field_4 = v0;\n\n v0 = (s32)a1->f_D0;\n v1 = ((MainStruct *)v0)->f_20;\n v0 = v1->field_4;\n\n a0 = D_801E43A4;\n v0 &= a2;\n v1->field_4 = v0;\n\n v1 = (SubStruct *)a0->f_CC;\n v0 = v1->field_4;\n v0 &= a2;\n v1->field_4 = v0;\n\n v0 = a1->f_E8;\n if ((v0 & 0x2) == 0) {\n v0 = (s32)a1->f_D4;\n v1 = ((MainStruct *)v0)->f_20;\n v0 = v1->field_4;\n v0 &= a2;\n v1->field_4 = v0;\n }\n}\n", "after_text": "void func_8018622C(MainStruct *a0) {\n MainStruct *a1 = a0;\n s32 a2 = 0x7FFFFFFF;\n MainStruct *a0_reg;\n MainStruct *v0;\n SubStruct *v1;\n s32 v2;\n\n v1 = a1->f_20;\n v1->field_4 &= a2;\n\n v0 = (MainStruct *)a1->f_CC;\n v1 = v0->f_20;\n v1->field_4 &= a2;\n\n a0_reg = D_801E43A4;\n\n v0 = (MainStruct *)a1->f_D0;\n v0->f_20->field_4 &= a2;\n\n v1 = (SubStruct *)a0_reg->f_CC;\n v1->field_4 &= a2;\n\n v2 = a1->f_E8;\n if ((v2 & 0x2) == 0) {\n v0 = (MainStruct *)a1->f_D4;\n v0->f_20->field_4 &= a2;\n }\n}\n"}
|
||||
{"ts": "2026-09-11 18:18:48", "label": "s105_f8", "rung": "E", "calib": {"head": "4d96e472c", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_80185E80.c", "fn": "func_8018D270", "addr": 2149110384, "aliases": null, "header": false, "includers": 0, "nhash_before": "3a10c68a7ee40b87c51f17efc49095c2c5870a86", "nhash_after": "456b64ee2f9d8491ad3c1ee805b33b89cc6bd07a", "source": ".run/P36/agents/ov_SC02_005__func_8018D270/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.185, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_80185E80.o"], "before_text": "void func_8018D270(void *a0) {\n register s32 v0 __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n s32 v1;\n\n v0 = ((s32 (*)(void))func_8012C1B8)();\n *(s32 *)((s32)a0 + 0x20) = v0;\n\n if (!v0) {\n func_8012CAE4(a0);\n } else {\n func_8001C214(v0, (s32)&D_801BDCD0);\n\n v0 = *(s32 *)((s32)a0 + 0x20);\n *(s32 *)((s32)v0 + 0x20) = (s32)a0 + 0xDC;\n\n {\n register s32 a1_val __asm__(\"$5\") = *(s32 *)((s32)*(s32 *)((s32)a0 + 0x64) + 0x20); // !FAKE: pin $5 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n if (a1_val) {\n func_8001C1E4(*(s32 *)((s32)a0 + 0x20));\n *(s16 *)((s32)a0 + 0xE) = 0;\n *(s16 *)((s32)a0 + 0xA) = 0;\n *(s16 *)((s32)a0 + 0x6) = 0;\n }\n }\n\n v0 = *(s32 *)((s32)a0 + 0x20);\n *(s32 *)((s32)v0 + 0x4) |= 0x80000000;\n func_8012AD50(a0);\n }\n}\n", "after_text": "void func_8018D270(void *a0) {\n s32 v0;\n s32 v;\n\n v0 = ((s32 (*)(void))func_8012C1B8)();\n *(s32 *)((s32)a0 + 0x20) = v0;\n\n if (v0 == 0) {\n func_8012CAE4(a0);\n } else {\n func_8001C214(v0, (s32)&D_801BDCD0);\n *(s32 *)(*(s32 *)((s32)a0 + 0x20) + 0x20) = (s32)a0 + 0xDC;\n v = *(s32 *)(*(s32 *)((s32)a0 + 0x64) + 0x20);\n if (v != 0) {\n ((void (*)(s32, s32))func_8001C1E4)(*(s32 *)((s32)a0 + 0x20), v);\n *(s16 *)((s32)a0 + 0xE) = 0;\n *(s16 *)((s32)a0 + 0xA) = 0;\n *(s16 *)((s32)a0 + 0x6) = 0;\n }\n *(s32 *)(*(s32 *)((s32)a0 + 0x20) + 0x4) |= 0x80000000;\n func_8012AD50(a0);\n }\n}\n"}
|
||||
{"ts": "2026-09-11 18:19:05", "label": "s105_f8", "rung": "E", "calib": {"head": "d21cd5616", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_80185E80.c", "fn": "func_8018CA74", "addr": 2149108340, "aliases": null, "header": false, "includers": 0, "nhash_before": "7745691fdaf5e5121272c2f09f8895e736785a34", "nhash_after": "19e95f0256de239541f93b1bca96caf4da093f98", "source": ".run/P36/agents/ov_SC02_005__func_8018CA74/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.185, "objects": ["build/src/ov_SC02_005/ov_SC02_005_jr_80185E80.o"], "before_text": "void func_8018CA74(s32 param_1)\n{\n register s32 d __asm__(\"$16\") = param_1; // !FAKE: pin $16 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n register s32 obj __asm__(\"$17\"); // !FAKE: pin $17 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n /* $a1 pin on the shared `1`: without it the const-1 pseudo and the 0xC4\n * pseudo both land in $v0 (disjoint ranges after sched1), which pins the\n * 0xC4 load below the two sb's in sched2. See notes in the wave report. */\n register u8 one __asm__(\"$5\"); // !FAKE: pin $5 \u2014 NEEDED DIFFERS (P36 rung B tus10)\n s32 ret;\n s32 c4v;\n u16 aev;\n u16 f70v;\n\n ret = ((s32 (*)(void))func_8012C1B8)();\n *(s32 *)(d + 0x20) = ret;\n obj = ret;\n if (ret == 0) {\n func_8012CAE4((void *)d);\n return;\n }\n func_8001CA1C(obj, (s32)&D_80196910);\n *(s16 *)(obj + 0x1c) = 0x2800;\n *(s16 *)(obj + 0x1a) = 0x2800;\n *(s16 *)(obj + 0x18) = 0x2800;\n *(s32 *)(d + 0xbc) = (s32)&D_80196B68;\n *(s32 *)(d + 0x58) = (s32)&D_80196B58 | 0x20000000;\n c4v = *(s32 *)(d + 0xc4);\n one = 1;\n *(u8 *)(d + 0xc0) = one;\n *(u8 *)(d + 0x75) = one;\n *(s32 *)(d + 0xb4) = 0;\n *(u8 *)(d + 0xc1) = 0;\n *(s32 *)(d + 0xc4) = c4v | 2;\n *(s32 *)(*(s32 *)(d + 0x20) + 4) |= 0x50000000;\n aev = *(u16 *)(d + 0xae);\n *(s16 *)(d + 0x5c) = 0;\n aev |= 0xfffd;\n *(s16 *)(d + 0xae) = (s16)aev;\n func_8012A828(d, &D_80196A60);\n f70v = *(u16 *)(d + 0x70);\n *(s16 *)(d + 0x98) = 1;\n f70v &= 7;\n *(s32 *)(d + 0x94) = f70v;\n func_8012AD50((void *)d);\n}\n", "after_text": "void func_8018CA74(s32 d)\n{\n s32 obj;\n s32 ret;\n\n ret = ((s32 (*)(void))func_8012C1B8)();\n obj = ret;\n *(s32 *)(d + 0x20) = ret;\n if (ret == 0) {\n func_8012CAE4((void *)d);\n return;\n }\n func_8001CA1C(obj, (s32)&D_80196910);\n *(s16 *)(obj + 0x1c) = 0x2800;\n *(s16 *)(obj + 0x1a) = 0x2800;\n *(s16 *)(obj + 0x18) = 0x2800;\n *(s32 *)(d + 0xbc) = (s32)&D_80196B68;\n *(u8 *)(d + 0xc0) = 1;\n *(s32 *)(d + 0x58) = (s32)&D_80196B58 | 0x20000000;\n *(u8 *)(d + 0x75) = 1;\n *(s32 *)(d + 0xb4) = 0;\n *(u8 *)(d + 0xc1) = 0;\n *(s32 *)(d + 0xc4) |= 2;\n *(s32 *)(*(s32 *)(d + 0x20) + 4) |= 0x50000000;\n *(s16 *)(d + 0x5c) = 0;\n *(u16 *)(d + 0xae) |= 0xfffd;\n func_8012A828(d, &D_80196A60);\n *(s16 *)(d + 0x98) = 1;\n *(s32 *)(d + 0x94) = *(u16 *)(d + 0x70) & 7;\n func_8012AD50((void *)d);\n}\n"}
|
||||
|
||||
@@ -4991,22 +4991,14 @@ extern s32 D_80196B68;
|
||||
extern s32 D_80196B58;
|
||||
extern s32 D_80196A60;
|
||||
|
||||
void func_8018CA74(s32 param_1)
|
||||
void func_8018CA74(s32 d)
|
||||
{
|
||||
register s32 d __asm__("$16") = param_1; // !FAKE: pin $16 — NEEDED DIFFERS (P36 rung B tus10)
|
||||
register s32 obj __asm__("$17"); // !FAKE: pin $17 — NEEDED DIFFERS (P36 rung B tus10)
|
||||
/* $a1 pin on the shared `1`: without it the const-1 pseudo and the 0xC4
|
||||
* pseudo both land in $v0 (disjoint ranges after sched1), which pins the
|
||||
* 0xC4 load below the two sb's in sched2. See notes in the wave report. */
|
||||
register u8 one __asm__("$5"); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B tus10)
|
||||
s32 obj;
|
||||
s32 ret;
|
||||
s32 c4v;
|
||||
u16 aev;
|
||||
u16 f70v;
|
||||
|
||||
ret = ((s32 (*)(void))func_8012C1B8)();
|
||||
*(s32 *)(d + 0x20) = ret;
|
||||
obj = ret;
|
||||
*(s32 *)(d + 0x20) = ret;
|
||||
if (ret == 0) {
|
||||
func_8012CAE4((void *)d);
|
||||
return;
|
||||
@@ -5016,24 +5008,18 @@ void func_8018CA74(s32 param_1)
|
||||
*(s16 *)(obj + 0x1a) = 0x2800;
|
||||
*(s16 *)(obj + 0x18) = 0x2800;
|
||||
*(s32 *)(d + 0xbc) = (s32)&D_80196B68;
|
||||
*(u8 *)(d + 0xc0) = 1;
|
||||
*(s32 *)(d + 0x58) = (s32)&D_80196B58 | 0x20000000;
|
||||
c4v = *(s32 *)(d + 0xc4);
|
||||
one = 1;
|
||||
*(u8 *)(d + 0xc0) = one;
|
||||
*(u8 *)(d + 0x75) = one;
|
||||
*(u8 *)(d + 0x75) = 1;
|
||||
*(s32 *)(d + 0xb4) = 0;
|
||||
*(u8 *)(d + 0xc1) = 0;
|
||||
*(s32 *)(d + 0xc4) = c4v | 2;
|
||||
*(s32 *)(d + 0xc4) |= 2;
|
||||
*(s32 *)(*(s32 *)(d + 0x20) + 4) |= 0x50000000;
|
||||
aev = *(u16 *)(d + 0xae);
|
||||
*(s16 *)(d + 0x5c) = 0;
|
||||
aev |= 0xfffd;
|
||||
*(s16 *)(d + 0xae) = (s16)aev;
|
||||
*(u16 *)(d + 0xae) |= 0xfffd;
|
||||
func_8012A828(d, &D_80196A60);
|
||||
f70v = *(u16 *)(d + 0x70);
|
||||
*(s16 *)(d + 0x98) = 1;
|
||||
f70v &= 7;
|
||||
*(s32 *)(d + 0x94) = f70v;
|
||||
*(s32 *)(d + 0x94) = *(u16 *)(d + 0x70) & 7;
|
||||
func_8012AD50((void *)d);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user