diff --git a/src/800.c b/src/800.c
index 9992e2b0b..66e6b1baf 100644
--- a/src/800.c
+++ b/src/800.c
@@ -6368,7 +6368,110 @@ void func_8001D3FC(s32 arg0)
     }
 }
 
-INCLUDE_ASM("asm/nonmatchings/800", func_8001D70C);
+void func_8001D70C(s32 param_1)
+{
+    s32 matrix[8];  /* sp+0x10 */
+    s16 sc[20];     /* sp+0x30 */
+
+    func_8004978C((s16 *)(param_1 + 0x10), (void *)matrix);
+
+    /* build the diagonal scale matrix at sp+0x30 */
+    sc[0] = *(u16 *)(param_1 + 0x18);
+    sc[1] = 0;
+    sc[2] = 0;
+    sc[3] = 0;
+    sc[4] = *(u16 *)(param_1 + 0x1A);
+    sc[5] = 0;
+    sc[6] = 0;
+    sc[7] = 0;
+    sc[8] = 0x1000;
+
+    __asm__ volatile (
+        "lw $12, 0(%0);"
+        "lw $13, 4(%0);"
+        "ctc2 $12, $0;"
+        "ctc2 $13, $1;"
+        "lw $12, 8(%0);"
+        "lw $13, 12(%0);"
+        "lw $14, 16(%0);"
+        "ctc2 $12, $2;"
+        "ctc2 $13, $3;"
+        "ctc2 $14, $4;"
+        "addiu $2, $sp, 0x30;"
+        "lhu $12, 0($2);"
+        "lhu $13, 6($2);"
+        "lhu $14, 12($2);"
+        "mtc2 $12, $9;"
+        "mtc2 $13, $10;"
+        "mtc2 $14, $11;"
+        "nop;"
+        "nop;"
+        "mvmva 1, 0, 3, 3, 0;"
+        "mfc2 $12, $9;"
+        "mfc2 $13, $10;"
+        "mfc2 $14, $11;"
+        "sh $12, 0(%0);"
+        "sh $13, 6(%0);"
+        "sh $14, 12(%0);"
+        "addiu $2, $sp, 0x32;"
+        "lhu $12, 0($2);"
+        "lhu $13, 6($2);"
+        "lhu $14, 12($2);"
+        "mtc2 $12, $9;"
+        "mtc2 $13, $10;"
+        "mtc2 $14, $11;"
+        "nop;"
+        "nop;"
+        "mvmva 1, 0, 3, 3, 0;"
+        "addiu $2, $sp, 0x12;"
+        "mfc2 $12, $9;"
+        "mfc2 $13, $10;"
+        "mfc2 $14, $11;"
+        "sh $12, 0($2);"
+        "sh $13, 6($2);"
+        "sh $14, 12($2);"
+        "addiu $2, $sp, 0x34;"
+        "lhu $12, 0($2);"
+        "lhu $13, 6($2);"
+        "lhu $14, 12($2);"
+        "mtc2 $12, $9;"
+        "mtc2 $13, $10;"
+        "mtc2 $14, $11;"
+        "nop;"
+        "nop;"
+        "mvmva 1, 0, 3, 3, 0;"
+        "addiu $2, $sp, 0x14;"
+        "mfc2 $12, $9;"
+        "mfc2 $13, $10;"
+        "mfc2 $14, $11;"
+        "sh $12, 0($2);"
+        "sh $13, 6($2);"
+        "sh $14, 12($2);"
+        : : "r"((s32)matrix) : "$12", "$13", "$14", "$2", "memory");
+
+    *(s32 *)((u8 *)matrix + 0x14) = *(s16 *)(param_1 + 8);
+    *(s32 *)((u8 *)matrix + 0x18) = *(s16 *)(param_1 + 10);
+    *(s32 *)((u8 *)matrix + 0x1C) = *(s16 *)(param_1 + 12);
+
+    __asm__ volatile (
+        "lw $12, 0(%0);"
+        "lw $13, 4(%0);"
+        "ctc2 $12, $0;"
+        "ctc2 $13, $1;"
+        "lw $12, 8(%0);"
+        "lw $13, 12(%0);"
+        "lw $14, 16(%0);"
+        "ctc2 $12, $2;"
+        "ctc2 $13, $3;"
+        "ctc2 $14, $4;"
+        "lw $12, 20(%0);"
+        "lw $13, 24(%0);"
+        "ctc2 $12, $5;"
+        "lw $14, 28(%0);"
+        "ctc2 $13, $6;"
+        "ctc2 $14, $7"
+        : : "r"((s32)matrix) : "$12", "$13", "$14", "$2");
+}
 
 
 /* ---- PsyQ GTE inline macros (same spelling as func_8001F730 / ov_SC03_* / 800.c gte_ldv0) ---- */
diff --git a/src/800c.c b/src/800c.c
index f004e833c..68ff90a77 100644
--- a/src/800c.c
+++ b/src/800c.c
@@ -563,7 +563,69 @@ __asm__(
     ".end\tfunc_80059FC0\n"
 );
 
-INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_E34);
+__asm__(
+    ".text\n"
+    ".align\t2\n"
+    ".globl\tSYS_OBJ_E34\n"
+    ".ent\tSYS_OBJ_E34\n"
+    "SYS_OBJ_E34:\n"
+    ".set\tnoreorder\n"
+    "or    $4, $2, $3\n"
+    "lui   $2, %hi(D_80072780)\n"
+    "lw    $2, %lo(D_80072780)($2)\n"
+    "nop\n"
+    "lw    $2, 16($2)\n"
+    "nop\n"
+    "jalr  $2\n"
+    "nop\n"
+    "lui   $2, %hi(D_800727FC)\n"
+    "addiu $2, $2, %lo(D_800727FC)\n"
+    "lhu   $2, 0($2)\n"
+    "lh    $3, 8($16)\n"
+    "sll   $2, $2, 16\n"
+    "sra   $2, $2, 16\n"
+    "bne   $2, $3, .L8005A0FC\n"
+    "nop\n"
+    "lui   $2, %hi(D_800727FE)\n"
+    "lhu   $2, %lo(D_800727FE)($2)\n"
+    "lh    $3, 10($16)\n"
+    "sll   $2, $2, 16\n"
+    "sra   $2, $2, 16\n"
+    "bne   $2, $3, .L8005A0FC\n"
+    "nop\n"
+    "lui   $2, %hi(D_80072800)\n"
+    "lhu   $2, %lo(D_80072800)($2)\n"
+    "lh    $3, 12($16)\n"
+    "sll   $2, $2, 16\n"
+    "sra   $2, $2, 16\n"
+    "bne   $2, $3, .L8005A0FC\n"
+    "nop\n"
+    "lui   $2, %hi(D_80072802)\n"
+    "lhu   $2, %lo(D_80072802)($2)\n"
+    "lh    $3, 14($16)\n"
+    "sll   $2, $2, 16\n"
+    "sra   $2, $2, 16\n"
+    "beq   $2, $3, .L8005A2C4\n"
+    "nop\n"
+    ".L8005A0FC:\n"
+    "jal   func_80043078\n"
+    "nop\n"
+    "lh    $4, 8($16)\n"
+    "sb    $2, 18($16)\n"
+    "andi  $2, $2, 0xFF\n"
+    "sll   $3, $4, 2\n"
+    "addu  $3, $3, $4\n"
+    "sll   $3, $3, 1\n"
+    "lh    $4, 10($16)\n"
+    "beqz  $2, .L8005A130\n"
+    "addiu $3, $3, 0x260\n"
+    "j     SYS_OBJ_F00\n"
+    "addiu $17, $4, 0x13\n"
+    ".L8005A130:\n"
+    "addiu $17, $4, 0x10\n"
+    ".set\treorder\n"
+    ".end\tSYS_OBJ_E34\n"
+);
 
 INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_F00);
 
diff --git a/src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c b/src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c
index 2bb5e3659..7db789fff 100644
--- a/src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c
+++ b/src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c
@@ -4927,7 +4927,36 @@ void func_8017F10C(s32 a0) {
 
 INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_jr_8017AE2C", func_8017F1CC);
 
-INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_jr_8017AE2C", func_8017F214);
+extern s32 func_8012AD50(void*);
+extern void func_8017DCB8(s32 a0);
+extern void func_8017F2BC(void);
+
+void func_8017F214(s32 a0) {
+    u8 *s0;
+    u16 val16;
+
+    s0 = *(u8 **)(a0 + 0x20);
+    func_8017F2BC();
+
+    val16 = *(u16 *)(s0 + 0x18);
+    val16 += 0x80;
+    *(u16 *)(s0 + 0x18) = val16;
+
+    {
+        s16 temp = (s16)val16;
+        if (temp >= 0x4001) {
+            *(u16 *)(s0 + 0x18) = 0x4000;
+        }
+    }
+
+    *(u16 *)(s0 + 0x1A) = *(u16 *)(s0 + 0x18);
+
+    if (*(s16 *)(s0 + 0x18) == 0x4000) {
+        func_8017DCB8(0x5);
+        ((void (*)(s32))func_8012AD50)(a0);
+    }
+}
+
 
 extern void func_8017F2BC();
 void func_8017F29C(void) {