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"s105_f11_minlever", "rung": "E", "calib": {"head": "a4a244c7f", "stamp": "e34b6679685f"}, "tu": "src/ov_SC06_018/ov_SC06_018_jr_80187AEC.c", "fn": "func_8018F060", "addr": 2149118048, "aliases": null, "header": false, "includers": 0, "nhash_before": "2b679154c8c09c465eaad0f7b76788a55666edaa", "nhash_after": "863f58f5d4dc16037ea65ce8906d7f5f669b5fc4", "source": ".run/P36/agents/ov_SC06_018__func_8018F060/body.c", "verdict": "LEVER-FREE", "sites": [{"ord": 0, "kind": "launder", "cls": "B", "detail": "", "via": "", "line": 8374, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 1, "kind": "launder", "cls": "B", "detail": "", "via": "", "line": 8409, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 2, "kind": "launder", "cls": "B", "detail": "", "via": "", "line": 8444, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}], "compiles": 1, "seconds": 0.2, "objects": ["build/src/ov_SC06_018/ov_SC06_018_jr_80187AEC.o"], "before_text": "void func_8018F060(s32 param_1, u32 param_2, u16 *param_3, u32 param_4) {\n u8 dead[0x20]; /* 0x10 : reserved, never referenced (holds the frame at 0xC8) */\n SVECTOR_8018F060 scratch; /* 0x30 */\n B8_8018F060 out[6]; /* 0x38 */\n u32 pkt[10]; /* 0x68 : v0..v3 + color(0x88) + code(0x8C) */\n SVECTOR_8018F060 rtflag; /* 0x90 (8 bytes -> 0x94 gap) */\n s32 flag1; /* 0x98 */\n s32 flag2; /* 0x9C */\n s32 otz; /* 0xA0 */\n SVEC_8018F060 *src;\n s32 i, oz;\n long *p0, *p1, *p2, *p3, *pfl;\n u8 *mb;\n register long *pc __asm__(\"$16\"); // !FAKE: pin $16 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8004914C((void *)(((s32 *)param_1)[8] + 0x34));\n func_800491AC((void *)(((s32 *)param_1)[8] + 0x34));\n\n src = &D_801D1228[(param_2 & 1) * 3];\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[0];\n RotTransSV(&scratch, &out[i], &rtflag);\n }\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[1];\n RotTransSV(&scratch, &out[3 + i], &rtflag);\n }\n\n *(B4_8018F060 *)&pkt[8] = *(B4_8018F060 *)¶m_4;\n pkt[9] = 0x50000000;\n\n /* face 0: verts 0,1,3,4 */\n *(B8_8018F060 *)&pkt[0] = out[0];\n *(B8_8018F060 *)&pkt[2] = out[1];\n *(B8_8018F060 *)&pkt[4] = out[3];\n *(B8_8018F060 *)&pkt[6] = out[4];\n DRAW(); // !FAKE: launder via DRAW \u2014 REFUSED macro-carried launder: the lever is inside `#define DRAW` with real code around it (T5) (P36 rung B tus9)\n\n /* face 1: verts 1,2,4,5 */\n *(B8_8018F060 *)&pkt[0] = out[1];\n *(B8_8018F060 *)&pkt[2] = out[2];\n *(B8_8018F060 *)&pkt[4] = out[4];\n *(B8_8018F060 *)&pkt[6] = out[5];\n DRAW(); // !FAKE: launder via DRAW \u2014 REFUSED macro-carried launder: the lever is inside `#define DRAW` with real code around it (T5) (P36 rung B tus9)\n\n /* face 2: verts 2,0,5,3 */\n *(B8_8018F060 *)&pkt[0] = out[2];\n *(B8_8018F060 *)&pkt[2] = out[0];\n *(B8_8018F060 *)&pkt[4] = out[5];\n *(B8_8018F060 *)&pkt[6] = out[3];\n DRAW(); // !FAKE: launder via DRAW \u2014 REFUSED macro-carried launder: the lever is inside `#define DRAW` with real code around it (T5) (P36 rung B tus9)\n}\n", "after_text": "void func_8018F060(s32 param_1, u32 param_2, u16 *param_3, u32 param_4) {\n u8 dead[0x20]; /* 0x10 : reserved, never referenced (holds the frame at 0xC8) */\n SVECTOR_8018F060 scratch; /* 0x30 */\n B8_8018F060 out[6]; /* 0x38 */\n u32 pkt[10]; /* 0x68 : v0..v3 + color(0x88) + code(0x8C) */\n SVECTOR_8018F060 rtflag; /* 0x90 (8 bytes -> 0x94 gap) */\n s32 flag1; /* 0x98 */\n s32 flag2; /* 0x9C */\n s32 otz; /* 0xA0 */\n SVEC_8018F060 *src;\n s32 i, oz;\n u8 *mb;\n\n func_8004914C((void *)(((s32 *)param_1)[8] + 0x34));\n func_800491AC((void *)(((s32 *)param_1)[8] + 0x34));\n\n src = &D_801D1228[(param_2 & 1) * 3];\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[0];\n RotTransSV(&scratch, &out[i], &rtflag);\n }\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[1];\n RotTransSV(&scratch, &out[3 + i], &rtflag);\n }\n\n *(B4_8018F060 *)&pkt[8] = *(B4_8018F060 *)¶m_4;\n pkt[9] = 0x50000000;\n\n /* face 0: verts 0,1,3,4 */\n *(B8_8018F060 *)&pkt[0] = out[0];\n *(B8_8018F060 *)&pkt[2] = out[1];\n *(B8_8018F060 *)&pkt[4] = out[3];\n *(B8_8018F060 *)&pkt[6] = out[4];\n mb = (u8 *)&D_800AF630;\n func_8004914C(mb + 0x18);\n __asm__(\"\" : \"=r\"(mb) : \"0\"(mb)); // !FAKE: launder mb between the two matrix calls \u2014 cse unifies the second `mb + 0x18` through the class of its constant value `(const (plus D_800AF630 24))`, cse.c:6766-6850 + :7195-7225, and combine then folds the symbol into the lone survivor; an unknown value after the first call keeps two adds off one call-crossing base (P36 S105 f11 minimum-lever)\n func_800491AC(mb + 0x18);\n {\n long *p1 = (long *)&pkt[2];\n long *p2 = (long *)&pkt[4];\n long *p3 = (long *)&pkt[6];\n long *pfl = &flag1;\n long *p0 = (long *)&pkt[0];\n gte_ldv3(p0, p1, p2);\n gte_rtpt();\n gte_stflg(pfl);\n gte_stsxy3(p0, p1, p2);\n gte_ldv0(p3);\n gte_rtps();\n gte_stflg(&flag2);\n flag1 |= flag2;\n gte_stsxy(p3);\n }\n gte_avsz4();\n gte_stotz(&otz);\n oz = otz;\n *(s16 *)((u8 *)pkt + 4) = (s16)oz;\n if (oz > 0 && flag1 >= 0 &&\n !((u32)&D_800AE610 < (u32)(*(s32 *)((u8 *)&D_800A651C\n + (*(u16 *)&D_800B9A02) * 0x14) + oz * 4))) {\n func_80017254(&pkt[0]);\n }\n\n /* face 1: verts 1,2,4,5 */\n *(B8_8018F060 *)&pkt[0] = out[1];\n *(B8_8018F060 *)&pkt[2] = out[2];\n *(B8_8018F060 *)&pkt[4] = out[4];\n *(B8_8018F060 *)&pkt[6] = out[5];\n mb = (u8 *)&D_800AF630;\n func_8004914C(mb + 0x18);\n __asm__(\"\" : \"=r\"(mb) : \"0\"(mb)); // !FAKE: launder mb between the two matrix calls \u2014 cse unifies the second `mb + 0x18` through the class of its constant value `(const (plus D_800AF630 24))`, cse.c:6766-6850 + :7195-7225, and combine then folds the symbol into the lone survivor; an unknown value after the first call keeps two adds off one call-crossing base (P36 S105 f11 minimum-lever)\n func_800491AC(mb + 0x18);\n {\n long *p1 = (long *)&pkt[2];\n long *p2 = (long *)&pkt[4];\n long *p3 = (long *)&pkt[6];\n long *pfl = &flag1;\n long *p0 = (long *)&pkt[0];\n gte_ldv3(p0, p1, p2);\n gte_rtpt();\n gte_stflg(pfl);\n gte_stsxy3(p0, p1, p2);\n gte_ldv0(p3);\n gte_rtps();\n gte_stflg(&flag2);\n flag1 |= flag2;\n gte_stsxy(p3);\n }\n gte_avsz4();\n gte_stotz(&otz);\n oz = otz;\n *(s16 *)((u8 *)pkt + 4) = (s16)oz;\n if (oz > 0 && flag1 >= 0 &&\n !((u32)&D_800AE610 < (u32)(*(s32 *)((u8 *)&D_800A651C\n + (*(u16 *)&D_800B9A02) * 0x14) + oz * 4))) {\n func_80017254(&pkt[0]);\n }\n\n /* face 2: verts 2,0,5,3 */\n *(B8_8018F060 *)&pkt[0] = out[2];\n *(B8_8018F060 *)&pkt[2] = out[0];\n *(B8_8018F060 *)&pkt[4] = out[5];\n *(B8_8018F060 *)&pkt[6] = out[3];\n mb = (u8 *)&D_800AF630;\n func_8004914C(mb + 0x18);\n __asm__(\"\" : \"=r\"(mb) : \"0\"(mb)); // !FAKE: launder mb between the two matrix calls \u2014 cse unifies the second `mb + 0x18` through the class of its constant value `(const (plus D_800AF630 24))`, cse.c:6766-6850 + :7195-7225, and combine then folds the symbol into the lone survivor; an unknown value after the first call keeps two adds off one call-crossing base (P36 S105 f11 minimum-lever)\n func_800491AC(mb + 0x18);\n {\n long *p1 = (long *)&pkt[2];\n long *p2 = (long *)&pkt[4];\n long *p3 = (long *)&pkt[6];\n long *pfl = &flag1;\n long *p0 = (long *)&pkt[0];\n gte_ldv3(p0, p1, p2);\n gte_rtpt();\n gte_stflg(pfl);\n gte_stsxy3(p0, p1, p2);\n gte_ldv0(p3);\n gte_rtps();\n gte_stflg(&flag2);\n flag1 |= flag2;\n gte_stsxy(p3);\n }\n gte_avsz4();\n gte_stotz(&otz);\n oz = otz;\n *(s16 *)((u8 *)pkt + 4) = (s16)oz;\n if (oz > 0 && flag1 >= 0 &&\n !((u32)&D_800AE610 < (u32)(*(s32 *)((u8 *)&D_800A651C\n + (*(u16 *)&D_800B9A02) * 0x14) + oz * 4))) {\n func_80017254(&pkt[0]);\n }\n}\n"} {"ts": "2026-09-11 20:44:21", "label": "s105_f11_minlever", "rung": "E", "calib": {"head": "389e4d068", "stamp": "e34b6679685f"}, "tu": "src/ov_SC06_032/ov_SC06_032_jr_80182890.c", "fn": "func_8018EDB0", "addr": 2149117360, "aliases": null, "header": false, "includers": 0, "nhash_before": "2f44135c9f7aed99d8731c643eb13aa93aee61ef", "nhash_after": "4ee7d94f8530cf578cf4f589dee1fff57c43b747", "source": ".run/P36/agents/ov_SC06_018__func_8018F060/scratch/copy_func_8018EDB0.c", "verdict": "LEVER-FREE", "sites": [{"ord": 0, "kind": "launder", "cls": "B", "detail": "", "via": "", "line": 11107, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 1, "kind": "launder", "cls": "B", "detail": "", "via": "", "line": 11142, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 2, "kind": "launder", "cls": "B", "detail": "", "via": "", "line": 11177, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}], "compiles": 1, "seconds": 0.298, "objects": ["build/src/ov_SC06_032/ov_SC06_032_jr_80182890.o"], "before_text": "void func_8018EDB0(s32 param_1, u32 param_2, u16 *param_3, u32 param_4) {\n u8 dead[0x20]; /* 0x10 : reserved, never referenced (holds the frame at 0xC8) */\n SVECTOR_8018EDB0 scratch; /* 0x30 */\n B8_8018EDB0 out[6]; /* 0x38 */\n u32 pkt[10]; /* 0x68 : v0..v3 + color(0x88) + code(0x8C) */\n SVECTOR_8018EDB0 rtflag; /* 0x90 (8 bytes -> 0x94 gap) */\n s32 flag1; /* 0x98 */\n s32 flag2; /* 0x9C */\n s32 otz; /* 0xA0 */\n SVEC_8018EDB0 *src;\n s32 i, oz;\n long *p0, *p1, *p2, *p3, *pfl;\n u8 *mb;\n register long *pc __asm__(\"$16\"); // !FAKE: pin $16 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8004914C((void *)(((s32 *)param_1)[8] + 0x34));\n func_800491AC((void *)(((s32 *)param_1)[8] + 0x34));\n\n src = &D_801CC7FC[(param_2 & 1) * 3];\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[0];\n RotTransSV(&scratch, &out[i], &rtflag);\n }\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[1];\n RotTransSV(&scratch, &out[3 + i], &rtflag);\n }\n\n *(B4_8018EDB0 *)&pkt[8] = *(B4_8018EDB0 *)¶m_4;\n pkt[9] = 0x50000000;\n\n /* face 0: verts 0,1,3,4 */\n *(B8_8018EDB0 *)&pkt[0] = out[0];\n *(B8_8018EDB0 *)&pkt[2] = out[1];\n *(B8_8018EDB0 *)&pkt[4] = out[3];\n *(B8_8018EDB0 *)&pkt[6] = out[4];\n DRAW(); // !FAKE: launder via DRAW \u2014 REFUSED macro-carried launder: the lever is inside `#define DRAW` with real code around it (T5) (P36 rung B tus9)\n\n /* face 1: verts 1,2,4,5 */\n *(B8_8018EDB0 *)&pkt[0] = out[1];\n *(B8_8018EDB0 *)&pkt[2] = out[2];\n *(B8_8018EDB0 *)&pkt[4] = out[4];\n *(B8_8018EDB0 *)&pkt[6] = out[5];\n DRAW(); // !FAKE: launder via DRAW \u2014 REFUSED macro-carried launder: the lever is inside `#define DRAW` with real code around it (T5) (P36 rung B tus9)\n\n /* face 2: verts 2,0,5,3 */\n *(B8_8018EDB0 *)&pkt[0] = out[2];\n *(B8_8018EDB0 *)&pkt[2] = out[0];\n *(B8_8018EDB0 *)&pkt[4] = out[5];\n *(B8_8018EDB0 *)&pkt[6] = out[3];\n DRAW(); // !FAKE: launder via DRAW \u2014 REFUSED macro-carried launder: the lever is inside `#define DRAW` with real code around it (T5) (P36 rung B tus9)\n}\n", "after_text": "void func_8018EDB0(s32 param_1, u32 param_2, u16 *param_3, u32 param_4) {\n u8 dead[0x20]; /* 0x10 : reserved, never referenced (holds the frame at 0xC8) */\n SVECTOR_8018EDB0 scratch; /* 0x30 */\n B8_8018EDB0 out[6]; /* 0x38 */\n u32 pkt[10]; /* 0x68 : v0..v3 + color(0x88) + code(0x8C) */\n SVECTOR_8018EDB0 rtflag; /* 0x90 (8 bytes -> 0x94 gap) */\n s32 flag1; /* 0x98 */\n s32 flag2; /* 0x9C */\n s32 otz; /* 0xA0 */\n SVEC_8018EDB0 *src;\n s32 i, oz;\n u8 *mb;\n\n func_8004914C((void *)(((s32 *)param_1)[8] + 0x34));\n func_800491AC((void *)(((s32 *)param_1)[8] + 0x34));\n\n src = &D_801CC7FC[(param_2 & 1) * 3];\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[0];\n RotTransSV(&scratch, &out[i], &rtflag);\n }\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[1];\n RotTransSV(&scratch, &out[3 + i], &rtflag);\n }\n\n *(B4_8018EDB0 *)&pkt[8] = *(B4_8018EDB0 *)¶m_4;\n pkt[9] = 0x50000000;\n\n /* face 0: verts 0,1,3,4 */\n *(B8_8018EDB0 *)&pkt[0] = out[0];\n *(B8_8018EDB0 *)&pkt[2] = out[1];\n *(B8_8018EDB0 *)&pkt[4] = out[3];\n *(B8_8018EDB0 *)&pkt[6] = out[4];\n mb = (u8 *)&D_800AF630;\n func_8004914C(mb + 0x18);\n __asm__(\"\" : \"=r\"(mb) : \"0\"(mb)); // !FAKE: launder mb between the two matrix calls \u2014 cse unifies the second `mb + 0x18` through the class of its constant value `(const (plus D_800AF630 24))`, cse.c:6766-6850 + :7195-7225, and combine then folds the symbol into the lone survivor; an unknown value after the first call keeps two adds off one call-crossing base (P36 S105 f11 minimum-lever)\n func_800491AC(mb + 0x18);\n {\n long *p1 = (long *)&pkt[2];\n long *p2 = (long *)&pkt[4];\n long *p3 = (long *)&pkt[6];\n long *pfl = &flag1;\n long *p0 = (long *)&pkt[0];\n gte_ldv3(p0, p1, p2);\n gte_rtpt();\n gte_stflg(pfl);\n gte_stsxy3(p0, p1, p2);\n gte_ldv0(p3);\n gte_rtps();\n gte_stflg(&flag2);\n flag1 |= flag2;\n gte_stsxy(p3);\n }\n gte_avsz4();\n gte_stotz(&otz);\n oz = otz;\n *(s16 *)((u8 *)pkt + 4) = (s16)oz;\n if (oz > 0 && flag1 >= 0 &&\n !((u32)&D_800AE610 < (u32)(*(s32 *)((u8 *)&D_800A651C\n + (*(u16 *)&D_800B9A02) * 0x14) + oz * 4))) {\n func_80017254(&pkt[0]);\n }\n\n /* face 1: verts 1,2,4,5 */\n *(B8_8018EDB0 *)&pkt[0] = out[1];\n *(B8_8018EDB0 *)&pkt[2] = out[2];\n *(B8_8018EDB0 *)&pkt[4] = out[4];\n *(B8_8018EDB0 *)&pkt[6] = out[5];\n mb = (u8 *)&D_800AF630;\n func_8004914C(mb + 0x18);\n __asm__(\"\" : \"=r\"(mb) : \"0\"(mb)); // !FAKE: launder mb between the two matrix calls \u2014 cse unifies the second `mb + 0x18` through the class of its constant value `(const (plus D_800AF630 24))`, cse.c:6766-6850 + :7195-7225, and combine then folds the symbol into the lone survivor; an unknown value after the first call keeps two adds off one call-crossing base (P36 S105 f11 minimum-lever)\n func_800491AC(mb + 0x18);\n {\n long *p1 = (long *)&pkt[2];\n long *p2 = (long *)&pkt[4];\n long *p3 = (long *)&pkt[6];\n long *pfl = &flag1;\n long *p0 = (long *)&pkt[0];\n gte_ldv3(p0, p1, p2);\n gte_rtpt();\n gte_stflg(pfl);\n gte_stsxy3(p0, p1, p2);\n gte_ldv0(p3);\n gte_rtps();\n gte_stflg(&flag2);\n flag1 |= flag2;\n gte_stsxy(p3);\n }\n gte_avsz4();\n gte_stotz(&otz);\n oz = otz;\n *(s16 *)((u8 *)pkt + 4) = (s16)oz;\n if (oz > 0 && flag1 >= 0 &&\n !((u32)&D_800AE610 < (u32)(*(s32 *)((u8 *)&D_800A651C\n + (*(u16 *)&D_800B9A02) * 0x14) + oz * 4))) {\n func_80017254(&pkt[0]);\n }\n\n /* face 2: verts 2,0,5,3 */\n *(B8_8018EDB0 *)&pkt[0] = out[2];\n *(B8_8018EDB0 *)&pkt[2] = out[0];\n *(B8_8018EDB0 *)&pkt[4] = out[5];\n *(B8_8018EDB0 *)&pkt[6] = out[3];\n mb = (u8 *)&D_800AF630;\n func_8004914C(mb + 0x18);\n __asm__(\"\" : \"=r\"(mb) : \"0\"(mb)); // !FAKE: launder mb between the two matrix calls \u2014 cse unifies the second `mb + 0x18` through the class of its constant value `(const (plus D_800AF630 24))`, cse.c:6766-6850 + :7195-7225, and combine then folds the symbol into the lone survivor; an unknown value after the first call keeps two adds off one call-crossing base (P36 S105 f11 minimum-lever)\n func_800491AC(mb + 0x18);\n {\n long *p1 = (long *)&pkt[2];\n long *p2 = (long *)&pkt[4];\n long *p3 = (long *)&pkt[6];\n long *pfl = &flag1;\n long *p0 = (long *)&pkt[0];\n gte_ldv3(p0, p1, p2);\n gte_rtpt();\n gte_stflg(pfl);\n gte_stsxy3(p0, p1, p2);\n gte_ldv0(p3);\n gte_rtps();\n gte_stflg(&flag2);\n flag1 |= flag2;\n gte_stsxy(p3);\n }\n gte_avsz4();\n gte_stotz(&otz);\n oz = otz;\n *(s16 *)((u8 *)pkt + 4) = (s16)oz;\n if (oz > 0 && flag1 >= 0 &&\n !((u32)&D_800AE610 < (u32)(*(s32 *)((u8 *)&D_800A651C\n + (*(u16 *)&D_800B9A02) * 0x14) + oz * 4))) {\n func_80017254(&pkt[0]);\n }\n}\n"} {"ts": "2026-09-11 20:44:39", "label": "s105_f11_minlever", "rung": "E", "calib": {"head": "52a3953b2", "stamp": "e34b6679685f"}, "tu": "src/ov_SC06_033/ov_SC06_033_jr_80186574.c", "fn": "func_8018AD9C", "addr": 2149100956, "aliases": null, "header": false, "includers": 0, "nhash_before": "add165e4459c02cd544e35e2b7d643ae017d6e88", "nhash_after": "7ee40ef69d9b368fd29936e41ef2a3db4b55e57b", "source": ".run/P36/agents/ov_SC06_018__func_8018F060/scratch/copy_func_8018AD9C.c", "verdict": "LEVER-FREE", "sites": [{"ord": 0, "kind": "launder", "cls": "B", "detail": "", "via": "", "line": 6190, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 1, "kind": "launder", "cls": "B", "detail": "", "via": "", "line": 6225, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 2, "kind": "launder", "cls": "B", "detail": "", "via": "", "line": 6260, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}], "compiles": 1, "seconds": 0.142, "objects": ["build/src/ov_SC06_033/ov_SC06_033_jr_80186574.o"], "before_text": "void func_8018AD9C(s32 param_1, u32 param_2, u16 *param_3, u32 param_4) {\n extern void func_8004914C(void *a0);\n extern void func_800491AC(void *a0);\n extern void RotTransSV(void *a0, void *a1, void *a2);\n extern void func_80017254(void *a0);\n extern SVEC_8018AD9C D_801C8374[];\n extern short D_800B9A02;\n extern u8 D_800A651C[];\n extern u8 D_800AE610[];\n extern u8 D_800AF630[];\n u8 dead[0x20]; /* 0x10 : reserved, never referenced (holds the frame at 0xC8) */\n SVECTOR_8018AD9C scratch; /* 0x30 */\n B8_8018AD9C out[6]; /* 0x38 */\n u32 pkt[10]; /* 0x68 : v0..v3 + color(0x88) + code(0x8C) */\n SVECTOR_8018AD9C rtflag; /* 0x90 (8 bytes -> 0x94 gap) */\n s32 flag1; /* 0x98 */\n s32 flag2; /* 0x9C */\n s32 otz; /* 0xA0 */\n SVEC_8018AD9C *src;\n s32 i, oz;\n long *p0, *p1, *p2, *p3, *pfl;\n u8 *mb;\n register long *pc __asm__(\"$16\"); // !FAKE: pin $16 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8004914C((void *)(((s32 *)param_1)[8] + 0x34));\n func_800491AC((void *)(((s32 *)param_1)[8] + 0x34));\n\n src = &D_801C8374[(param_2 & 1) * 3];\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[0];\n RotTransSV(&scratch, &out[i], &rtflag);\n }\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[1];\n RotTransSV(&scratch, &out[3 + i], &rtflag);\n }\n\n *(B4_8018AD9C *)&pkt[8] = *(B4_8018AD9C *)¶m_4;\n pkt[9] = 0x50000000;\n\n /* face 0: verts 0,1,3,4 */\n *(B8_8018AD9C *)&pkt[0] = out[0];\n *(B8_8018AD9C *)&pkt[2] = out[1];\n *(B8_8018AD9C *)&pkt[4] = out[3];\n *(B8_8018AD9C *)&pkt[6] = out[4];\n DRAW(); // !FAKE: launder via DRAW \u2014 REFUSED macro-carried launder: the lever is inside `#define DRAW` with real code around it (T5) (P36 rung B tus9)\n\n /* face 1: verts 1,2,4,5 */\n *(B8_8018AD9C *)&pkt[0] = out[1];\n *(B8_8018AD9C *)&pkt[2] = out[2];\n *(B8_8018AD9C *)&pkt[4] = out[4];\n *(B8_8018AD9C *)&pkt[6] = out[5];\n DRAW(); // !FAKE: launder via DRAW \u2014 REFUSED macro-carried launder: the lever is inside `#define DRAW` with real code around it (T5) (P36 rung B tus9)\n\n /* face 2: verts 2,0,5,3 */\n *(B8_8018AD9C *)&pkt[0] = out[2];\n *(B8_8018AD9C *)&pkt[2] = out[0];\n *(B8_8018AD9C *)&pkt[4] = out[5];\n *(B8_8018AD9C *)&pkt[6] = out[3];\n DRAW(); // !FAKE: launder via DRAW \u2014 REFUSED macro-carried launder: the lever is inside `#define DRAW` with real code around it (T5) (P36 rung B tus9)\n}\n", "after_text": "void func_8018AD9C(s32 param_1, u32 param_2, u16 *param_3, u32 param_4) {\n extern void func_8004914C(void *a0);\n extern void func_800491AC(void *a0);\n extern void RotTransSV(void *a0, void *a1, void *a2);\n extern void func_80017254(void *a0);\n extern SVEC_8018AD9C D_801C8374[];\n extern short D_800B9A02;\n extern u8 D_800A651C[];\n extern u8 D_800AE610[];\n extern u8 D_800AF630[];\n u8 dead[0x20]; /* 0x10 : reserved, never referenced (holds the frame at 0xC8) */\n SVECTOR_8018AD9C scratch; /* 0x30 */\n B8_8018AD9C out[6]; /* 0x38 */\n u32 pkt[10]; /* 0x68 : v0..v3 + color(0x88) + code(0x8C) */\n SVECTOR_8018AD9C rtflag; /* 0x90 (8 bytes -> 0x94 gap) */\n s32 flag1; /* 0x98 */\n s32 flag2; /* 0x9C */\n s32 otz; /* 0xA0 */\n SVEC_8018AD9C *src;\n s32 i, oz;\n u8 *mb;\n\n func_8004914C((void *)(((s32 *)param_1)[8] + 0x34));\n func_800491AC((void *)(((s32 *)param_1)[8] + 0x34));\n\n src = &D_801C8374[(param_2 & 1) * 3];\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[0];\n RotTransSV(&scratch, &out[i], &rtflag);\n }\n for (i = 0; i < 3; i++) {\n scratch.vx = src[i].vx;\n scratch.vy = src[i].vy;\n scratch.vz = -param_3[1];\n RotTransSV(&scratch, &out[3 + i], &rtflag);\n }\n\n *(B4_8018AD9C *)&pkt[8] = *(B4_8018AD9C *)¶m_4;\n pkt[9] = 0x50000000;\n\n /* face 0: verts 0,1,3,4 */\n *(B8_8018AD9C *)&pkt[0] = out[0];\n *(B8_8018AD9C *)&pkt[2] = out[1];\n *(B8_8018AD9C *)&pkt[4] = out[3];\n *(B8_8018AD9C *)&pkt[6] = out[4];\n mb = (u8 *)&D_800AF630;\n func_8004914C(mb + 0x18);\n __asm__(\"\" : \"=r\"(mb) : \"0\"(mb)); // !FAKE: launder mb between the two matrix calls \u2014 cse unifies the second `mb + 0x18` through the class of its constant value `(const (plus D_800AF630 24))`, cse.c:6766-6850 + :7195-7225, and combine then folds the symbol into the lone survivor; an unknown value after the first call keeps two adds off one call-crossing base (P36 S105 f11 minimum-lever)\n func_800491AC(mb + 0x18);\n {\n long *p1 = (long *)&pkt[2];\n long *p2 = (long *)&pkt[4];\n long *p3 = (long *)&pkt[6];\n long *pfl = &flag1;\n long *p0 = (long *)&pkt[0];\n gte_ldv3(p0, p1, p2);\n gte_rtpt();\n gte_stflg(pfl);\n gte_stsxy3(p0, p1, p2);\n gte_ldv0(p3);\n gte_rtps();\n gte_stflg(&flag2);\n flag1 |= flag2;\n gte_stsxy(p3);\n }\n gte_avsz4();\n gte_stotz(&otz);\n oz = otz;\n *(s16 *)((u8 *)pkt + 4) = (s16)oz;\n if (oz > 0 && flag1 >= 0 &&\n !((u32)&D_800AE610 < (u32)(*(s32 *)((u8 *)&D_800A651C\n + (*(u16 *)&D_800B9A02) * 0x14) + oz * 4))) {\n func_80017254(&pkt[0]);\n }\n\n /* face 1: verts 1,2,4,5 */\n *(B8_8018AD9C *)&pkt[0] = out[1];\n *(B8_8018AD9C *)&pkt[2] = out[2];\n *(B8_8018AD9C *)&pkt[4] = out[4];\n *(B8_8018AD9C *)&pkt[6] = out[5];\n mb = (u8 *)&D_800AF630;\n func_8004914C(mb + 0x18);\n __asm__(\"\" : \"=r\"(mb) : \"0\"(mb)); // !FAKE: launder mb between the two matrix calls \u2014 cse unifies the second `mb + 0x18` through the class of its constant value `(const (plus D_800AF630 24))`, cse.c:6766-6850 + :7195-7225, and combine then folds the symbol into the lone survivor; an unknown value after the first call keeps two adds off one call-crossing base (P36 S105 f11 minimum-lever)\n func_800491AC(mb + 0x18);\n {\n long *p1 = (long *)&pkt[2];\n long *p2 = (long *)&pkt[4];\n long *p3 = (long *)&pkt[6];\n long *pfl = &flag1;\n long *p0 = (long *)&pkt[0];\n gte_ldv3(p0, p1, p2);\n gte_rtpt();\n gte_stflg(pfl);\n gte_stsxy3(p0, p1, p2);\n gte_ldv0(p3);\n gte_rtps();\n gte_stflg(&flag2);\n flag1 |= flag2;\n gte_stsxy(p3);\n }\n gte_avsz4();\n gte_stotz(&otz);\n oz = otz;\n *(s16 *)((u8 *)pkt + 4) = (s16)oz;\n if (oz > 0 && flag1 >= 0 &&\n !((u32)&D_800AE610 < (u32)(*(s32 *)((u8 *)&D_800A651C\n + (*(u16 *)&D_800B9A02) * 0x14) + oz * 4))) {\n func_80017254(&pkt[0]);\n }\n\n /* face 2: verts 2,0,5,3 */\n *(B8_8018AD9C *)&pkt[0] = out[2];\n *(B8_8018AD9C *)&pkt[2] = out[0];\n *(B8_8018AD9C *)&pkt[4] = out[5];\n *(B8_8018AD9C *)&pkt[6] = out[3];\n mb = (u8 *)&D_800AF630;\n func_8004914C(mb + 0x18);\n __asm__(\"\" : \"=r\"(mb) : \"0\"(mb)); // !FAKE: launder mb between the two matrix calls \u2014 cse unifies the second `mb + 0x18` through the class of its constant value `(const (plus D_800AF630 24))`, cse.c:6766-6850 + :7195-7225, and combine then folds the symbol into the lone survivor; an unknown value after the first call keeps two adds off one call-crossing base (P36 S105 f11 minimum-lever)\n func_800491AC(mb + 0x18);\n {\n long *p1 = (long *)&pkt[2];\n long *p2 = (long *)&pkt[4];\n long *p3 = (long *)&pkt[6];\n long *pfl = &flag1;\n long *p0 = (long *)&pkt[0];\n gte_ldv3(p0, p1, p2);\n gte_rtpt();\n gte_stflg(pfl);\n gte_stsxy3(p0, p1, p2);\n gte_ldv0(p3);\n gte_rtps();\n gte_stflg(&flag2);\n flag1 |= flag2;\n gte_stsxy(p3);\n }\n gte_avsz4();\n gte_stotz(&otz);\n oz = otz;\n *(s16 *)((u8 *)pkt + 4) = (s16)oz;\n if (oz > 0 && flag1 >= 0 &&\n !((u32)&D_800AE610 < (u32)(*(s32 *)((u8 *)&D_800A651C\n + (*(u16 *)&D_800B9A02) * 0x14) + oz * 4))) {\n func_80017254(&pkt[0]);\n }\n}\n"} +{"ts": "2026-10-01 12:34:51", "label": "P37-t3_S1", "rung": "S+A", "calib": {"head": "fe2e814776", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC02_005/ov_SC02_005_jr_80185E80.c", "fn": "func_8018A4C4", "addr": 2149098692, "aliases": [], "header": false, "nhash_before": "edd19d572e7357d4ca5c65d7f0cfef0cd21f7913", "nhash_after": null, "verdict": "LEVER-FREE", "sites": [{"ord": 0, "kind": "gte-lever", "cls": "B", "detail": "lw", "via": "", "line": 3184, "verdict": "REMOVED", "why": "", "oracle": "IDENTICAL"}], "compiles": 1, "seconds": 0.384} +{"ts": "2026-10-01 12:43:32", "label": "P37-t3_S1", "rung": "S+A", "calib": {"head": "fe2e814776", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC06_008/ov_SC06_008_jr_8017C294.c", "fn": "func_8017E830", "addr": 2149050416, "aliases": [], "header": false, "nhash_before": "bc475bb6761832dd6bea71aa953849cd90ad46b3", "nhash_after": null, "verdict": "LEVER-FREE", "sites": [{"ord": 0, "kind": "gte-lever", "cls": "B", "detail": "gte_rtv0tr_m", "via": "gte_rtv0tr_m", "line": 3694, "verdict": "REWRITTEN", "why": "gte_rtv0tr", "oracle": "IDENTICAL"}, {"ord": 1, "kind": "gte-lever", "cls": "B", "detail": "gte_rtv0tr_m", "via": "gte_rtv0tr_m", "line": 3698, "verdict": "REWRITTEN", "why": "gte_rtv0tr", "oracle": "IDENTICAL"}, {"ord": 2, "kind": "gte-lever", "cls": "B", "detail": "gte_rtv0tr_m", "via": "gte_rtv0tr_m", "line": 3702, "verdict": "REWRITTEN", "why": "gte_rtv0tr", "oracle": "IDENTICAL"}, {"ord": 3, "kind": "gte-lever", "cls": "B", "detail": "gte_rtv0tr_m", "via": "gte_rtv0tr_m", "line": 3711, "verdict": "REWRITTEN", "why": "gte_rtv0tr", "oracle": "IDENTICAL"}, {"ord": 4, "kind": "gte-lever", "cls": "B", "detail": "gte_rtv0tr_m", "via": "gte_rtv0tr_m", "line": 3719, "verdict": "REWRITTEN", "why": "gte_rtv0tr", "oracle": "IDENTICAL"}, {"ord": 5, "kind": "gte-lever", "cls": "B", "detail": "gte_rtv0tr_m", "via": "gte_rtv0tr_m", "line": 3727, "verdict": "REWRITTEN", "why": "gte_rtv0tr", "oracle": "IDENTICAL"}], "compiles": 1, "seconds": 0.552} +{"ts": "2026-10-01 12:49:37", "label": "P37-t3_S1", "rung": "S+A", "calib": {"head": "fe2e814776", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC05_008/ov_SC05_008_jr_8017AE2C.c", "fn": "func_80182560", "addr": 2149066080, "aliases": [], "header": false, "nhash_before": "e2b5e0c6b54dfc39354c41e500bbd02ce8c9ef33", "nhash_after": null, "verdict": "RESIDUE", "sites": [{"ord": 0, "kind": "barrier", "cls": "B", "detail": "memory", "via": "", "line": 6822, "verdict": "NEEDED", "why": "", "oracle": "DIFFERS"}, {"ord": 1, "kind": "cast", "cls": "C", "detail": "volatile u16 *", "via": "", "line": 6830, "verdict": "REMOVED", "why": "", "oracle": "IDENTICAL"}], "compiles": 3, "seconds": 0.971} +{"ts": "2026-10-01 12:50:49", "label": "P37-t3_S1", "rung": "S+A", "calib": {"head": "fe2e814776", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c", "fn": "func_80183C9C", "addr": 2149072028, "aliases": [], "header": false, "nhash_before": "4b0a71460277a21615d394a234c23aba0a4497cc", "nhash_after": null, "verdict": "LEVER-FREE", "sites": [{"ord": 0, "kind": "gte-lever", "cls": "B", "detail": "lw", "via": "", "line": 8160, "verdict": "REMOVED", "why": "", "oracle": "IDENTICAL"}, {"ord": 1, "kind": "gte-lever", "cls": "B", "detail": "lwc2", "via": "", "line": 8173, "verdict": "REMOVED", "why": "", "oracle": "IDENTICAL"}, {"ord": 2, "kind": "gte-lever", "cls": "B", "detail": "nop", "via": "", "line": 8175, "verdict": "REMOVED", "why": "", "oracle": "IDENTICAL"}], "compiles": 1, "seconds": 0.45} +{"ts": "2026-10-01 12:52:21", "label": "P37-t3_S1", "rung": "S+A", "calib": {"head": "fe2e814776", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c", "fn": "func_80182E38", "addr": 2149068344, "aliases": [], "header": false, "nhash_before": "553caff5373ee8264ec8d367827b3aa90a8e7ffc", "nhash_after": null, "verdict": "LEVER-FREE", "sites": [{"ord": 0, "kind": "gte-lever", "cls": "B", "detail": "lw", "via": "", "line": 7650, "verdict": "REMOVED", "why": "", "oracle": "IDENTICAL"}, {"ord": 1, "kind": "gte-lever", "cls": "B", "detail": "lwc2", "via": "", "line": 7656, "verdict": "REMOVED", "why": "", "oracle": "IDENTICAL"}, {"ord": 2, "kind": "gte-lever", "cls": "B", "detail": "nop", "via": "", "line": 7657, "verdict": "REMOVED", "why": "", "oracle": "IDENTICAL"}], "compiles": 1, "seconds": 0.416} +{"ts": "2026-10-01 13:13:32", "label": "P37-t3_S2", "rung": "S+A", "calib": {"head": "08b5b03dd0", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c", "fn": "func_8017FB04", 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"label": "c3b1", "rung": "gte", "calib": {"head": "8c3937da22", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC02_039/ov_SC02_039_jr_8013C98C.c", "fn": null, "addr": null, "aliases": null, "header": false, "sites": [], "compiles": 1, "seconds": 0.11227607727050781, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 2, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 1494, "action": "call", "name": "gte_mtc2_lwc2x2_1fc7"}, {"line": 1496, "action": "call", "name": "gte_move_swc2_e610"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:31:55", "label": "c3b1", "rung": "gte", "calib": {"head": "8c3937da22", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC02_039/ov_SC02_039_jr_8017BEBC.c", "fn": null, "addr": null, "aliases": null, "header": false, "sites": [], "compiles": 1, "seconds": 0.1339280605316162, "record": {"deleted": 1, "renamed_defs": 0, "use_renames": 0, "direct_calls": 1, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [{"name": "gte_stsxy3_f4", "l0": 2696, "action": "deleted", "canonical": "gte_stsxy3_f4"}], "direct": [{"line": 3024, "action": "call", "name": "gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} +{"ts": "2026-10-02 18:31:55", "label": "c3b1", "rung": "gte", "calib": {"head": "8c3937da22", "stamp": "588cbf38c6e4"}, "tu": "src/ov_SC02_041/ov_SC02_041_jr_8013C98C.c", "fn": null, "addr": null, "aliases": null, "header": false, "sites": [], "compiles": 1, "seconds": 0.1097564697265625, "record": {"deleted": 0, "renamed_defs": 0, "use_renames": 0, "direct_calls": 2, "direct_levers": 0, "direct_none": 0, "marked": 0, "defs": [], "direct": [{"line": 1494, "action": "call", "name": "gte_mtc2_lwc2x2_1fc7"}, {"line": 1496, "action": "call", "name": "gte_move_swc2_e610"}], "kept": 0, "variants_freed": 0, "variants_kept": 0}, "verdict": "CONSOLIDATED"} diff --git a/.run/P36/gte/canonical.json b/.run/P36/gte/canonical.json index b79e346fb3..6031b4c0bd 100644 --- a/.run/P36/gte/canonical.json +++ b/.run/P36/gte/canonical.json @@ -1,5 +1,5 @@ { - "generated": "2026-10-02 18:23", + "generated": "2026-10-02 18:31", "canonical": { "08008ce80c008de810008ee8|0|1": { "name": "gte_stsxy3_f3", diff --git a/.run/P36/gte/sig_cache.json b/.run/P36/gte/sig_cache.json index fdeba473db..e668107b9c 100644 --- a/.run/P36/gte/sig_cache.json +++ b/.run/P36/gte/sig_cache.json @@ -138,5 +138,17 @@ "mfc2 $12, $9\nmfc2 $13, $10\nmfc2 $14, $11\nsh $12, 0($4)\nsh $13, 2($4)\nsh $14, 4($4)": "00480c4800500d4800580e4800008ca402008da404008ea4", "swc2 $19, 0($4)": "000093e8", "mfc2 $12, $19\nnop\nsra $12, $12, 2\nsw $12, 0($4)\n": "00980c480000000083600c0000008cac", -"lwc2 $9, 0($4)\nlwc2 $10, 4($4)\nlwc2 $11, 8($4)\nnop\nnop\nsqr 1\n": "000089c804008ac808008bc800000000000000002804a84a" +"lwc2 $9, 0($4)\nlwc2 $10, 4($4)\nlwc2 $11, 8($4)\nnop\nnop\nsqr 1\n": "000089c804008ac808008bc800000000000000002804a84a", +"mtc2 $0, $8\n\nlwc2 $6, 0($4)\n\nlwc2 $28, 0($5)": "00408048000086c80000bcc8", +"move $12, $4\n\nswc2 $29, 0($12)": "2160800000009de9", +"nop\n\tnop\n\tdpcl": "00000000000000002900684a", +"lwc2 $9, 0($4)\n\tlwc2 $10, 4($4)\n\tlwc2 $11, 8($4)": "000089c804008ac808008bc8", +"nop\n\tnop\n\tsqr 0": "00000000000000002804a04a", +".set\tnoreorder\nlw $12, 0($4)\nlw $13, 4($4)\nctc2 $12, $0\nctc2 $13, $1\nlw $12, 8($4)\nlw $13, 12($4)\nlw $14, 16($4)\nctc2 $12, $2\nctc2 $13, $3\nctc2 $14, $4\nlwc2 $0, 0($5)\nlwc2 $1, 4($5)\nnop\nnop\nmvmva 1, 0, 0, 3, 0\nswc2 $25, 0($6)\nswc2 $26, 4($6)\nswc2 $27, 8($6)\n.set\treorder\n": "00008c8c04008d8c0000cc480008cd4808008c8c0c008d8c10008e8c0010cc480018cd480020ce480000a0c80400a1c800000000000000001260484a0000d9e80400dae80800dbe8", +"mtc2 $0, $8\n\tlwc2 $6, 0($4)\n\tlwc2 $28, 0($5)": "00408048000086c80000bcc8", +"move $12, $4\n\tswc2 $29, 0($12)": "2160800000009de9", +"lwc2 $0, 0($4)\n\tlwc2 $1, 4($4)": "000080c8040081c8", +"nop\n\tnop\n\trtps": "00000000000000000100184a", +"cfc2 $12, $31\n\tnop\n\tsw $12, 0($4)": "00f84c480000000000008cac", +"lw $2, 0($4);lw $3, 4($4);ctc2 $2, $0;ctc2 $3, $1;lw $2, 8($4);lw $3, 12($4);lw $24, 16($4);ctc2 $2, $2;ctc2 $3, $3;ctc2 $24, $4;lw $2, 20($4);lw $3, 24($4);ctc2 $2, $5;lw $24, 28($4);ctc2 $3, $6;ctc2 $24, $7": "0000828c0400838c0000c2480008c3480800828c0c00838c1000988c0010c2480018c3480020d8481400828c1800838c0028c2481c00988c0030c3480038d848" } \ No newline at end of file diff --git a/src/800.c b/src/800.c index 9850d357a2..47d3a0e2a6 100644 --- a/src/800.c +++ b/src/800.c @@ -42,71 +42,7 @@ void func_800123F0(s32 param_1, s32 param_2) *(s16 *)((s32)matrix + 0x0E) = 0; *(s16 *)((s32)matrix + 0x10) = 0x1000; - __asm__ __volatile__ ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 16;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 18;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 20;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2)" - : - : "r"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_8b56(s1); func_8001282C(s1); } @@ -142,71 +78,7 @@ void func_80012558(s32 param_1, s32 param_2) *(s16 *)((s32)matrix + 0x0E) = 0; *(s16 *)((s32)matrix + 0x10) = cos_val; - __asm__ __volatile__ ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 16;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 18;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 20;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2)" - : - : "r"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_8b56(s1); func_8001282C(s1); } @@ -242,71 +114,7 @@ void func_800126C4(s32 param_1, s32 param_2) *(s16 *)((s32)matrix + 0x0E) = sin_val; *(s16 *)((s32)matrix + 0x10) = cos_val; - __asm__ __volatile__ ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 16;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 18;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 20;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2)" - : - : "r"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_8b56(s1); func_8001282C(s1); } @@ -762,8 +570,8 @@ s32 func_80013478(void) { diff[1] = a0[3] - a1[1]; diff[2] = a0[5] - a1[2]; - __asm__ volatile("lwc2 $9, 0(%0)\n\tlwc2 $10, 4(%0)\n\tlwc2 $11, 8(%0)" : : "r"(diff)); - __asm__ volatile("nop\n\tnop\n\tsqr 0"); + gte_ldlvl(diff); + gte_sqr_a07d(); gte_stlvnl(result); return result[0] + result[1] + result[2]; @@ -800,70 +608,7 @@ void func_800134FC(s16 param_1, s32 param_2, s32 param_3) *(s16 *)((s32)m1 + 0x0A) = v1; *(s16 *)((s32)m1 + 0x0C) = 0; - __asm__ __volatile__ ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "lhu $12, 0(%1);" - "lhu $13, 6(%1);" - "lhu $14, 12(%1);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 50;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, $sp, 18;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 52;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, $sp, 20;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2)" - : - : "r"(m0), "r"(m1) - : "$12", "$13", "$14" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_3eb0(m0, m1); func_8001282C(m0); func_800484EC(m0, param_2, param_3); @@ -1242,28 +987,7 @@ void func_80014094(s32 *arg0, void *arg1) { void func_800140B8(s32 a0, s32 a1, s32 a2) { - __asm__ __volatile__( - ".set\tnoreorder\n" - "lw $12, 0($4)\n" - "lw $13, 4($4)\n" - "ctc2 $12, $0\n" - "ctc2 $13, $1\n" - "lw $12, 8($4)\n" - "lw $13, 12($4)\n" - "lw $14, 16($4)\n" - "ctc2 $12, $2\n" - "ctc2 $13, $3\n" - "ctc2 $14, $4\n" - "lwc2 $0, 0($5)\n" - "lwc2 $1, 4($5)\n" - "nop\n" - "nop\n" - "mvmva 1, 0, 0, 3, 0\n" - "swc2 $25, 0($6)\n" - "swc2 $26, 4($6)\n" - "swc2 $27, 8($6)\n" - ".set\treorder\n" - : : : "$12", "$13", "$14", "memory"); + gte_lwx2_ctc2x2_lwx3_ctc2x3_fc24(); *(s32 *)a2 <<= 16; *(s32 *)(a2 + 4) <<= 16; *(s32 *)(a2 + 8) <<= 16; @@ -4215,7 +3939,7 @@ void func_8001751C(s32 *arg0, s32 arg1) d1 = p + 20; d2 = p + 32; gte_stsxy3(d0, d1, d2); - __asm__ volatile ("swc2 $8, 0( %0 )" : : "r"(&sz) : "memory"); + gte_stdp(&sz); gte_stflg(&flag); gte_stszotz(&otz); } else { @@ -9510,68 +9234,7 @@ void func_8001D70C(s32 param_1) sc[7] = 0; sc[8] = 0x1000; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x30;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x32;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, $sp, 0x12;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x34;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, $sp, 0x14;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - : : "r"((s32)matrix) : "$12", "$13", "$14", "$2", "memory"); + gte_lwx2_ctc2x2_lwx3_ctc2x3_b751((s32)matrix); *(s32 *)((u8 *)matrix + 0x14) = *(s16 *)(param_1 + 8); *(s32 *)((u8 *)matrix + 0x18) = *(s16 *)(param_1 + 10); @@ -14105,7 +13768,7 @@ void func_80023BF0(s32 arg0) gte_ldv0(&v); gte_rtps(); gte_stsxy(&xy); - __asm__ volatile("swc2 $8, 0(%0)" : : "r"(&sxy2) : "memory"); + gte_stdp(&sxy2); gte_stflg(&mac0); gte_stszotz(&z); if (z <= 0) { diff --git a/src/md_MAIN_031/md_MAIN_031.c b/src/md_MAIN_031/md_MAIN_031.c index a865604052..4e3b749db6 100644 --- a/src/md_MAIN_031/md_MAIN_031.c +++ b/src/md_MAIN_031/md_MAIN_031.c @@ -344,31 +344,10 @@ void func_800CB5C8(s32 arg0, s32 arg1) { /* GTE VARIANT `gte_SetRotMatrix_m`: memory beyond Sony's `gte_SetRotMatrix` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_SetRotMatrix_m(p) __asm__ __volatile__( \ - "lw $12, 0(%0)\n" \ - "lw $13, 4(%0)\n" \ - "ctc2 $12, $0\n" \ - "ctc2 $13, $1\n" \ - "lw $12, 8(%0)\n" \ - "lw $13, 12(%0)\n" \ - "lw $14, 16(%0)\n" \ - "ctc2 $12, $2\n" \ - "ctc2 $13, $3\n" \ - "ctc2 $14, $4\n" \ - : : "r"(p) : "$12", "$13", "$14", "memory") /* GTE VARIANT `gte_ldv0_m`: memory beyond Sony's `gte_ldv0` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_ldv0_m(p) __asm__ __volatile__( \ - "lwc2 $0, 0(%0)\n" \ - "lwc2 $1, 4(%0)\n" \ - : : "r"(p) : "memory") /* GTE VARIANT `gte_rtv0_m`: memory beyond Sony's `gte_rtv0` — a scheduling steer, its uses are marked (P36 T5) */ -#define gte_rtv0_m() __asm__ __volatile__( \ - "nop\n" \ - "nop\n" \ - "mvmva 1, 0, 0, 3, 0\n" \ - : : : "memory") extern s32 func_80017DC4(void *a0, void *a1); diff --git a/src/ov_MAIN_012/ov_MAIN_012_jr_8013C98C.c b/src/ov_MAIN_012/ov_MAIN_012_jr_8013C98C.c index 2fd11e9805..36057d2ab6 100644 --- a/src/ov_MAIN_012/ov_MAIN_012_jr_8013C98C.c +++ b/src/ov_MAIN_012/ov_MAIN_012_jr_8013C98C.c @@ -1442,9 +1442,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC01_000/ov_SC01_000_jr_8013C98C.c b/src/ov_SC01_000/ov_SC01_000_jr_8013C98C.c index 377865da2f..ec261c4d11 100644 --- a/src/ov_SC01_000/ov_SC01_000_jr_8013C98C.c +++ b/src/ov_SC01_000/ov_SC01_000_jr_8013C98C.c @@ -1505,9 +1505,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC01_001/ov_SC01_001_jr_8013C98C.c b/src/ov_SC01_001/ov_SC01_001_jr_8013C98C.c index c19795afde..cd01b1c191 100644 --- a/src/ov_SC01_001/ov_SC01_001_jr_8013C98C.c +++ b/src/ov_SC01_001/ov_SC01_001_jr_8013C98C.c @@ -1492,9 +1492,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC01_004/ov_SC01_004_jr_8013C98C.c b/src/ov_SC01_004/ov_SC01_004_jr_8013C98C.c index 97f9e7d915..e0554e6fd7 100644 --- a/src/ov_SC01_004/ov_SC01_004_jr_8013C98C.c +++ b/src/ov_SC01_004/ov_SC01_004_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC01_005/ov_SC01_005_jr_8013C98C.c b/src/ov_SC01_005/ov_SC01_005_jr_8013C98C.c index 0e9a5b974d..4871646c03 100644 --- a/src/ov_SC01_005/ov_SC01_005_jr_8013C98C.c +++ b/src/ov_SC01_005/ov_SC01_005_jr_8013C98C.c @@ -1492,9 +1492,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC01_008/ov_SC01_008_jr_8013C98C.c b/src/ov_SC01_008/ov_SC01_008_jr_8013C98C.c index 35446c90c0..b9524b181f 100644 --- a/src/ov_SC01_008/ov_SC01_008_jr_8013C98C.c +++ b/src/ov_SC01_008/ov_SC01_008_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC01_009/ov_SC01_009_jr_8013C98C.c b/src/ov_SC01_009/ov_SC01_009_jr_8013C98C.c index b2374569b8..4f65454a22 100644 --- a/src/ov_SC01_009/ov_SC01_009_jr_8013C98C.c +++ b/src/ov_SC01_009/ov_SC01_009_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC01_074/ov_SC01_074_jr_8013C98C.c b/src/ov_SC01_074/ov_SC01_074_jr_8013C98C.c index a2d5813a0b..44e2894219 100644 --- a/src/ov_SC01_074/ov_SC01_074_jr_8013C98C.c +++ b/src/ov_SC01_074/ov_SC01_074_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC01_077/ov_SC01_077.c b/src/ov_SC01_077/ov_SC01_077.c index d9fcc45581..f02be48a20 100644 --- a/src/ov_SC01_077/ov_SC01_077.c +++ b/src/ov_SC01_077/ov_SC01_077.c @@ -715,9 +715,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC01_080/ov_SC01_080_jr_8013C98C.c b/src/ov_SC01_080/ov_SC01_080_jr_8013C98C.c index 437283b232..bc0d99217d 100644 --- a/src/ov_SC01_080/ov_SC01_080_jr_8013C98C.c +++ b/src/ov_SC01_080/ov_SC01_080_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC01_084/ov_SC01_084_jr_8013C98C.c b/src/ov_SC01_084/ov_SC01_084_jr_8013C98C.c index f715ba30e4..2ffab5438f 100644 --- a/src/ov_SC01_084/ov_SC01_084_jr_8013C98C.c +++ b/src/ov_SC01_084/ov_SC01_084_jr_8013C98C.c @@ -1496,9 +1496,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_000/ov_SC02_000_jr_8013C98C.c b/src/ov_SC02_000/ov_SC02_000_jr_8013C98C.c index fad4920a05..9ad217df2c 100644 --- a/src/ov_SC02_000/ov_SC02_000_jr_8013C98C.c +++ b/src/ov_SC02_000/ov_SC02_000_jr_8013C98C.c @@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_004/ov_SC02_004_jr_8013C98C.c b/src/ov_SC02_004/ov_SC02_004_jr_8013C98C.c index 6587cc52f6..6248222fdb 100644 --- a/src/ov_SC02_004/ov_SC02_004_jr_8013C98C.c +++ b/src/ov_SC02_004/ov_SC02_004_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_005/ov_SC02_005_jr_8013C98C.c b/src/ov_SC02_005/ov_SC02_005_jr_8013C98C.c index aedb68264e..3add4bef96 100644 --- a/src/ov_SC02_005/ov_SC02_005_jr_8013C98C.c +++ b/src/ov_SC02_005/ov_SC02_005_jr_8013C98C.c @@ -1496,9 +1496,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_011/ov_SC02_011_jr_8013C98C.c b/src/ov_SC02_011/ov_SC02_011_jr_8013C98C.c index e7f654329a..45e282dc96 100644 --- a/src/ov_SC02_011/ov_SC02_011_jr_8013C98C.c +++ b/src/ov_SC02_011/ov_SC02_011_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_015/ov_SC02_015_jr_8013C98C.c b/src/ov_SC02_015/ov_SC02_015_jr_8013C98C.c index bffb4caaed..5011572370 100644 --- a/src/ov_SC02_015/ov_SC02_015_jr_8013C98C.c +++ b/src/ov_SC02_015/ov_SC02_015_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_016/ov_SC02_016_jr_8013C98C.c b/src/ov_SC02_016/ov_SC02_016_jr_8013C98C.c index 11e14b394b..2eb2c972d4 100644 --- a/src/ov_SC02_016/ov_SC02_016_jr_8013C98C.c +++ b/src/ov_SC02_016/ov_SC02_016_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_017/ov_SC02_017_jr_8013C98C.c b/src/ov_SC02_017/ov_SC02_017_jr_8013C98C.c index 5dd25b1ae5..b4a4414cfb 100644 --- a/src/ov_SC02_017/ov_SC02_017_jr_8013C98C.c +++ b/src/ov_SC02_017/ov_SC02_017_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_021/ov_SC02_021_jr_8013C98C.c b/src/ov_SC02_021/ov_SC02_021_jr_8013C98C.c index 82617bcedf..01a585e21a 100644 --- a/src/ov_SC02_021/ov_SC02_021_jr_8013C98C.c +++ b/src/ov_SC02_021/ov_SC02_021_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_026/ov_SC02_026_jr_8013C98C.c b/src/ov_SC02_026/ov_SC02_026_jr_8013C98C.c index 161e817300..d67c94f9c2 100644 --- a/src/ov_SC02_026/ov_SC02_026_jr_8013C98C.c +++ b/src/ov_SC02_026/ov_SC02_026_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_026/ov_SC02_026_jr_8017C180.c b/src/ov_SC02_026/ov_SC02_026_jr_8017C180.c index 9f7dca2314..7aa8bb97e1 100644 --- a/src/ov_SC02_026/ov_SC02_026_jr_8017C180.c +++ b/src/ov_SC02_026/ov_SC02_026_jr_8017C180.c @@ -2683,13 +2683,6 @@ extern void func_8017C0E4(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -3083,19 +3076,8 @@ int func_8017D948(short *a0) data[0] = D_80126CAC - a0[0]; data[1] = 0; data[2] = D_80126CB0 - a0[2]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return (data[0] + data[1] + data[2]) - 0x10001U <= 0x8FFE; } @@ -3108,19 +3090,8 @@ int func_8017D9D8(short *a0) { data[0] = D_80126CAC - a0[3]; data[1] = 0; data[2] = D_80126CB0 - a0[7]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return (data[0] + data[1] + data[2]) > 0x8FFFF; } diff --git a/src/ov_SC02_027/ov_SC02_027_jr_8013C98C.c b/src/ov_SC02_027/ov_SC02_027_jr_8013C98C.c index 60e40f6442..4ebfb1ad6a 100644 --- a/src/ov_SC02_027/ov_SC02_027_jr_8013C98C.c +++ b/src/ov_SC02_027/ov_SC02_027_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_028/ov_SC02_028_jr_8013C98C.c b/src/ov_SC02_028/ov_SC02_028_jr_8013C98C.c index 912bd6f347..d11d92a506 100644 --- a/src/ov_SC02_028/ov_SC02_028_jr_8013C98C.c +++ b/src/ov_SC02_028/ov_SC02_028_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_031/ov_SC02_031_jr_8013C98C.c b/src/ov_SC02_031/ov_SC02_031_jr_8013C98C.c index 5deb52ca4a..2a173956ee 100644 --- a/src/ov_SC02_031/ov_SC02_031_jr_8013C98C.c +++ b/src/ov_SC02_031/ov_SC02_031_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_035/ov_SC02_035_jr_8013C98C.c b/src/ov_SC02_035/ov_SC02_035_jr_8013C98C.c index 0ce8e415ce..5aafe83042 100644 --- a/src/ov_SC02_035/ov_SC02_035_jr_8013C98C.c +++ b/src/ov_SC02_035/ov_SC02_035_jr_8013C98C.c @@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_037/ov_SC02_037_jr_8013C98C.c b/src/ov_SC02_037/ov_SC02_037_jr_8013C98C.c index 6f97d9085e..3c4612252c 100644 --- a/src/ov_SC02_037/ov_SC02_037_jr_8013C98C.c +++ b/src/ov_SC02_037/ov_SC02_037_jr_8013C98C.c @@ -1440,9 +1440,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_039/ov_SC02_039_jr_8013C98C.c b/src/ov_SC02_039/ov_SC02_039_jr_8013C98C.c index fd2f382081..43a0910854 100644 --- a/src/ov_SC02_039/ov_SC02_039_jr_8013C98C.c +++ b/src/ov_SC02_039/ov_SC02_039_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC02_039/ov_SC02_039_jr_8017BEBC.c b/src/ov_SC02_039/ov_SC02_039_jr_8017BEBC.c index 68ab78b680..9bd3fe4bb1 100644 --- a/src/ov_SC02_039/ov_SC02_039_jr_8017BEBC.c +++ b/src/ov_SC02_039/ov_SC02_039_jr_8017BEBC.c @@ -2693,13 +2693,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -3021,71 +3014,7 @@ void func_8017D7D0(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC02_041/ov_SC02_041_jr_8013C98C.c b/src/ov_SC02_041/ov_SC02_041_jr_8013C98C.c index af0db20cbb..75732f2da5 100644 --- a/src/ov_SC02_041/ov_SC02_041_jr_8013C98C.c +++ b/src/ov_SC02_041/ov_SC02_041_jr_8013C98C.c @@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1) r = pix & 0x1f; g = pix & 0x3e0; b = pix & 0x7c00; - __asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(>e[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) + gte_mtc2_lwc2x2_1fc7(fc, >e[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever) gte_dpcl(); - __asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(>e[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) + gte_move_swc2_e610(>e[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever) out = gte[2]; tr = out & 0x1f; tg = out & 0x3e0; diff --git a/src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c b/src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c index ec204800bf..7db62c1baa 100644 --- a/src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c +++ b/src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c @@ -5215,39 +5215,15 @@ void func_8017FB04(s32 s1) s2 = s1 + 0xFC; v0 = s3 + 0x18; - __asm__ volatile( - "lw %0, 0(%3);" - "lw %1, 4(%3);" - "ctc2 %0, $0;" - "ctc2 %1, $1;" - "lw %0, 8(%3);" - "lw %1, 12(%3);" - "lw %2, 16(%3);" - "ctc2 %0, $2;" - "ctc2 %1, $3;" - "ctc2 %2, $4;" - "lw %0, 20(%3);" - "lw %1, 24(%3);" - "ctc2 %0, $5;" - "lw %2, 28(%3);" - "ctc2 %1, $6;" - "ctc2 %2, $7" - : "=&r"(t4), "=&r"(t5), "=&r"(t6) - : "r"(v0)); + gte_lwx2_ctc2x2_lwx3_ctc2x3_42e3(t4, t5, t6, v0); - __asm__ volatile( - "lwc2 $0, 0(%0);" - "lwc2 $1, 4(%0);" - "nop;" - "nop;" - "rtps" : : "r"(s2) ); + gte_ldv0(s2); gte_rtps(); a0 = (s32)&stack[0]; gte_stsxy(a0); v0 = (s32)&stack[2]; - __asm__ volatile("cfc2 %0, $31; nop; sw %0, 0(%1)" - : "=&r"(t4) : "r"(v0) : "memory"); + gte_cfc2_sw_4531(t4, v0); v1 = 0x80000000; if ((s32)stack[2] < 0) { diff --git a/src/ov_SC04_006/ov_SC04_006_jr_8017BEBC.c b/src/ov_SC04_006/ov_SC04_006_jr_8017BEBC.c index 7780e592d0..b531d7ec23 100644 --- a/src/ov_SC04_006/ov_SC04_006_jr_8017BEBC.c +++ b/src/ov_SC04_006/ov_SC04_006_jr_8017BEBC.c @@ -2679,13 +2679,6 @@ extern void func_8017BEB4(void); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -3320,71 +3313,7 @@ void func_8017DBC8(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } @@ -4471,19 +4400,8 @@ int func_8017F43C(short *a0) { data[0] = a0[3] - a0[68]; data[1] = 0; data[2] = a0[7] - a0[70]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return (data[0] + data[2]) <= 0x18FFFF; } diff --git a/src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c b/src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c index 27fc389ccb..c53293d58d 100644 --- a/src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c +++ b/src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c @@ -4420,19 +4420,8 @@ int func_8017F150(short *a0) { data[0] = D_80126CAC - a0[0]; data[1] = 0; data[2] = D_80126CB0 - a0[2]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return (data[0] + data[1] + data[2]) - 0x90001U < 0x18FFF; } @@ -4447,19 +4436,8 @@ int func_8017F1E4(short *a0) { data[0] = D_80126CAC - a0[3]; data[1] = 0; data[2] = D_80126CB0 - a0[7]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return 0x143FFF < (data[0] + data[1] + data[2]); } @@ -5838,71 +5816,7 @@ void func_80180FFC(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC05_005/ov_SC05_005_jr_8017D898.c b/src/ov_SC05_005/ov_SC05_005_jr_8017D898.c index 8d40eaad44..544ddbeb3d 100644 --- a/src/ov_SC05_005/ov_SC05_005_jr_8017D898.c +++ b/src/ov_SC05_005/ov_SC05_005_jr_8017D898.c @@ -2698,13 +2698,6 @@ extern void func_8017D824(void *param_1); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -3238,71 +3231,7 @@ void func_8017F2E8(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } @@ -4850,19 +4779,7 @@ s32 func_80181828(void *arg0) { v.vz = (s16)D_80126B66 - raw[2]; /* gte SQR on the XZ difference vector (in place) */ - __asm__ volatile ( - "lwc2 $9, 0( %0 );" - "lwc2 $10, 4( %0 );" - "lwc2 $11, 8( %0 );" - "nop;" - "nop;" - "sqr 0;" - "swc2 $25, 0( %0 );" - "swc2 $26, 4( %0 );" - "swc2 $27, 8( %0 )" - : - : "r"(&v) - : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_swc2x3_c9fc(&v); if (r * r <= v.vx + v.vz) { return 0; diff --git a/src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c b/src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c index 3766277677..be60a1e165 100644 --- a/src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c +++ b/src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c @@ -7647,13 +7647,9 @@ void func_80182E38(int param_1) } *(short *)(sv + 4) = v0; func_8004978C((s16 *)(CAST_ALIAS(int, param_1, 0x20) + 0x10), mat); - __asm__ __volatile__( - "lw $12, 0(%0)\n" "lw $13, 4(%0)\n" - "ctc2 $12, $0\n" "ctc2 $13, $1\n" - "lw $12, 8(%0)\n" "lw $13, 12(%0)\n" "lw $14, 16(%0)\n" - "ctc2 $12, $2\n" "ctc2 $13, $3\n" "ctc2 $14, $4\n" : : "r"(mat) : "$12", "$13", "$14" ); - __asm__ __volatile__("lwc2 $0, 0(%0)\n" "lwc2 $1, 4(%0)\n" : : "r"(sv) ); - __asm__ __volatile__("nop\n" "nop\n" "mvmva 1, 0, 0, 3, 0\n" ); + gte_SetRotMatrix(mat); + gte_ldv0(sv); + gte_rtv0(); gte_stsv(sv); ((Unkstruct_800B5CB8 *)param_1)->unk6 = *(unsigned short *)(((Unkstruct_800B5CB8 *)param_1)->unk64 + 6) + *(unsigned short *)(sv + 0); ((Unkstruct_800B5CB8 *)param_1)->unkA = *(unsigned short *)(((Unkstruct_800B5CB8 *)param_1)->unk64 + 10) + *(unsigned short *)(sv + 2); @@ -8156,20 +8152,10 @@ void func_80183C9C(void *a0) func_8004978C((s16 *)(((Unkstruct_800B5CB8 *)self)->unk20 + 0x10), &mat); - __asm__ __volatile__( - "lw $12, 0(%0)\n" - "lw $13, 4(%0)\n" - "ctc2 $12, $0\n" - "ctc2 $13, $1\n" - "lw $12, 8(%0)\n" - "lw $13, 12(%0)\n" - "lw $14, 16(%0)\n" - "ctc2 $12, $2\n" - "ctc2 $13, $3\n" - "ctc2 $14, $4\n" : : "r"(&mat) : "$12", "$13", "$14" ); + gte_SetRotMatrix(&mat); - __asm__ __volatile__("lwc2 $0, 0(%0)\nlwc2 $1, 4(%0)" : : "r"(&D_8018C7BC[((Unkstruct_800B5CB8 *)self)->unk70 * 4]) ); - __asm__ __volatile__("nop\nnop\nmvmva 1, 0, 0, 3, 0" ); + gte_ldv0(&D_8018C7BC[((Unkstruct_800B5CB8 *)self)->unk70 * 4]); + gte_rtv0(); gte_stsv(res); ((Unkstruct_800B5CB8 *)self)->unk6 = *(u16 *)(((Unkstruct_800B5CB8 *)self)->unk64 + 0x6) + res[0]; @@ -9722,71 +9708,7 @@ void func_80185F48(s32 param_1, s32 *param_2) *(short *)((s32)matrix_stack + 0x0E) = 0; *(short *)((s32)matrix_stack + 0x10) = cos_val; - __asm__ volatile ( - "lw $12, 0(%0);" - "lw $13, 4(%0);" - "ctc2 $12, $0;" - "ctc2 $13, $1;" - "lw $12, 8(%0);" - "lw $13, 12(%0);" - "lw $14, 16(%0);" - "ctc2 $12, $2;" - "ctc2 $13, $3;" - "ctc2 $14, $4;" - "addiu $2, $sp, 0x10;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0);" - "addiu $2, $sp, 0x12;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu $2, %0, 0x2;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0($2);" - "sh $13, 6($2);" - "sh $14, 12($2);" - "addiu $2, $sp, 0x14;" - "lhu $12, 0($2);" - "lhu $13, 6($2);" - "lhu $14, 12($2);" - "mtc2 $12, $9;" - "mtc2 $13, $10;" - "mtc2 $14, $11;" - "nop;" - "nop;" - "mvmva 1, 0, 3, 3, 0;" - "addiu %0, %0, 4;" - "mfc2 $12, $9;" - "mfc2 $13, $10;" - "mfc2 $14, $11;" - "sh $12, 0(%0);" - "sh $13, 6(%0);" - "sh $14, 12(%0)" - : "=r"(s1) - : "0"(s1) - : "$12", "$13", "$14", "$2" - ); + gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1); } diff --git a/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c b/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c index 9f469193c7..365fca2d4d 100644 --- a/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c +++ b/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c @@ -2680,13 +2680,6 @@ extern void func_8017C090(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -2966,19 +2959,8 @@ int func_8017D7E0(short *a0) { data[0] = D_80126CAC - a0[0]; data[1] = 0; data[2] = D_80126CB0 - a0[2]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return (data[0] + data[1] + data[2]) - 0x90001U < 0x18FFF; } @@ -2991,19 +2973,8 @@ int func_8017D874(short *a0) { data[0] = D_80126CAC - a0[3]; data[1] = 0; data[2] = D_80126CB0 - a0[7]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return data[0] + data[1] + data[2] > 0xFFFFF; } diff --git a/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c b/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c index 5b5832672f..a6e59149ef 100644 --- a/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c +++ b/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c @@ -2680,13 +2680,6 @@ extern void func_8017C090(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -3083,14 +3076,7 @@ s32 func_8017DA50(s16 *arg) { s32 u = arg[2]; sp[2] = t - u; } - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(sp) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(sp); gte_stlvnl(sp); return !(0x14FFE < sp[0] + sp[1] + sp[2] + 0xFFF9BFFF); @@ -3116,14 +3102,7 @@ s32 func_8017DAE4(s16 *arg) { s32 u = arg[7]; sp[2] = t - u; } - __asm__ __volatile__( - "lwc2 $9, 0(%0)\n" - "lwc2 $10, 4(%0)\n" - "lwc2 $11, 8(%0)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : "r"(sp) : "$9", "$10", "$11", "memory"); + gte_lwc2x3_sqr_e416(sp); gte_stlvnl(sp); return sp[0] + sp[1] + sp[2] > 0xC3FFF; diff --git a/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c b/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c index ad855b0f92..05e607fdc2 100644 --- a/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c +++ b/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c @@ -2676,13 +2676,6 @@ extern void func_8017C090(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -2955,19 +2948,8 @@ int func_8017D77C(short *a0) { data[0] = D_80126CAC - a0[0]; data[1] = 0; data[2] = D_80126CB0 - a0[2]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return (data[0] + data[1] + data[2]) - 0x64001U <= 0x14FFE; } diff --git a/src/ov_SC06_033/ov_SC06_033_jr_8017C24C.c b/src/ov_SC06_033/ov_SC06_033_jr_8017C24C.c index 93d9d5948c..d496e99825 100644 --- a/src/ov_SC06_033/ov_SC06_033_jr_8017C24C.c +++ b/src/ov_SC06_033/ov_SC06_033_jr_8017C24C.c @@ -2685,13 +2685,6 @@ extern void func_8017C090(void *a0); -#define gte_stsxy3_f4(r0) __asm__ volatile ( \ - "swc2 $12, 8( %0 );" \ - "swc2 $13, 12( %0 );" \ - "swc2 $14, 16( %0 )" \ - : \ - : "r"( r0 ) \ - : "memory" ) @@ -3174,19 +3167,8 @@ int func_8017DC30(short *a0) { data[0] = D_80126CAC - a0[0]; data[1] = 0; data[2] = D_80126CB0 - a0[2]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return (data[0] + data[1] + data[2]) + 0xFFF9BFFFU <= 0x14FFE; } @@ -3199,19 +3181,8 @@ int func_8017DCC4(s16 *a0) { data[0] = D_80126CAC - a0[3]; data[1] = 0; data[2] = D_80126CB0 - a0[7]; - __asm__ __volatile__( - "lwc2 $9, 0($sp)\n" - "lwc2 $10, 4($sp)\n" - "lwc2 $11, 8($sp)\n" - "nop\n" - "nop\n" - "sqr 0\n" - : : : "$9", "$10", "$11", "memory"); - __asm__ __volatile__( - "swc2 $25, 0($sp)\n" - "swc2 $26, 4($sp)\n" - "swc2 $27, 8($sp)\n" - : : : "memory"); + gte_lwc2x3_sqr_6a00(); + gte_swc2x3_66ca(); return 0xC3FFF < data[0] + data[1] + data[2]; } diff --git a/tools/gte_consolidate.py b/tools/gte_consolidate.py index 113ae25b8f..e64f5c6b3c 100644 --- a/tools/gte_consolidate.py +++ b/tools/gte_consolidate.py @@ -318,7 +318,7 @@ def inventory(jobs=12, quiet=False): sg = signature(inner) except Exception as ex: # noqa: BLE001 sg = dict(bytes=f"ERROR: {ex}"[:100], ok=False, nout=0, nin=0, clob=[], tmpl="", ins=[], outs=[]) - direct.append(dict(tu=tu, line=s["line"], col=s["col"], fn=s.get("fn"), inner=inner, sig=sg, marked=s.get("marked", False), + direct.append(dict(tu=tu, line=s["line"], col=s["col"], fn=s.get("fn"), inner=inner, sig=sg, marked=s.get("marked", False), kind=s["kind"], kw=re.sub(r"\s+", " ", m[pos:o]).strip())) _save_cache() inv = dict(generated=time.strftime("%Y-%m-%d %H:%M"), definitions=defs, direct=direct, uses=dict(uses)) @@ -848,8 +848,9 @@ def direct_rewrite(s, canon): return "lever", f"{names[0]}+{variant_name(names[1], t2['clob'], vclob)}", extra or sorted(set(clob) - set(sg["clob"])) -def file_edits(tu, raw, p, canon, label): - """[(start, end, repl)] + the record (per definition / use / direct statement) for one file's consolidation.""" +def file_edits(tu, raw, p, canon, label, keep_levers=False): + """[(start, end, repl)] + the record (per definition / use / direct statement) for one file's consolidation. + keep_levers (T7.1.c3): a direct lever (census gte-lever, or a statement only a lever variant matches) keeps its text and marker (T8's).""" m = dl.same_len_mask(raw) ls = dl.line_starts(raw) edits, rec = [], dict(deleted=0, renamed_defs=0, use_renames=0, direct_calls=0, direct_levers=0, direct_none=0, marked=0, defs=[], direct=[]) @@ -924,6 +925,9 @@ def file_edits(tu, raw, p, canon, label): rec["direct"].append(dict(line=s["line"], action="refused", why="statement not found at the census position")) continue how, text, name = direct_rewrite(s, canon) + if keep_levers and (how == "lever" or s.get("kind") == lc.GTE_LEVER_KIND): + rec["direct"].append(dict(line=s["line"], action="lever-kept", how=how)) + continue eol = raw.find("\n", e) eol = len(raw) if eol < 0 else eol tail = raw[e:eol].strip(" \t\r;") @@ -1038,7 +1042,7 @@ def apply_batch(a): except (Refuse, dl.Refuse) as ex: d["trial"] = f"REFUSED {ex}" try: - edits, rec = file_edits(tu, raw, plan_tu, canon, a.label) + edits, rec = file_edits(tu, raw, plan_tu, canon, a.label, keep_levers=a.keep_levers) except Refuse as ex: row.update(verdict="REFUSED", why=str(ex)) log(f" {tu}: REFUSED {ex}") @@ -1497,6 +1501,11 @@ def selftest(): outl = dl.apply_edits(fxl, file_edits("fl.c", fxl, pl, canon2, "self")[0]) if not re.search(r"\n gte_ldv0_m\(v\); // !FAKE: gte via gte_ldv0_m — clobbers memory .*3\.39 T7\.1 self.*\n\}", outl) or "old" in outl: fail(f"direct lever respelled to its header variant, marked once:\n{outl}") + if dl.apply_edits(fxl, file_edits("fl.c", fxl, pl, canon2, "self", keep_levers=True)[0]) != fxl: + fail("--keep-levers: a direct lever must keep its text and marker") + pk = dict(defs=[], direct=[dict(pl["direct"][0], kind=lc.GTE_LEVER_KIND)], renames={}) + if dl.apply_edits(fxl, file_edits("fl.c", fxl, pk, canon2, "self", keep_levers=True)[0]) != fxl: + fail("--keep-levers: a census gte-lever statement must keep its text") print(f"gte_consolidate --selftest: {'OK' if ok else 'FAIL'} — signatures rtps={s1['bytes'][16:24]} ldv0={s4['bytes'][:16]}; table {len(canon2['canonical'])} canonical / {len(canon2['variants'])} variant; fixture edits {len(edits)}") return ok @@ -1514,6 +1523,7 @@ def main(): ap.add_argument("--label", default=None) ap.add_argument("--only", nargs="*", default=None) ap.add_argument("--rejudge", action="store_true") + ap.add_argument("--keep-levers", action="store_true", help="--apply: leave direct lever statements (census gte-lever) as they are (T8 owns them)") ap.add_argument("--dirty-ok", action="store_true", help="--remark on a tree the scrub just modified (one fleet run for both)") ap.add_argument("-j", "--jobs", type=int, default=12) a = ap.parse_args()