From 4e145caef48c20610dcd5104c03a16dc0601031c Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Thu, 10 Sep 2026 22:37:25 -0600 Subject: [PATCH] =?UTF-8?q?phase-36:=20S104=20s104=5Fd17=20=E2=80=94=20fun?= =?UTF-8?q?c=5F80181DAC=20banked=20at=200=20through=20the=20whole-object?= =?UTF-8?q?=20gate=20+=20propagated=20=E2=80=94=20$0=20pin=20+=20keepalive?= =?UTF-8?q?=20=E2=86=92=200:=20the=20goto=20chain=20as=20a=20switch,=20the?= =?UTF-8?q?=20do-while=20as=20a=20for=20with=20continue=20(a=20LOOP=5FVTOP?= =?UTF-8?q?=20note=20flips=20mostly=5Ftrue=5Fjump,=20reorg.c:1364-1372),?= =?UTF-8?q?=20the=20hoisted=20copy=20deleted=20(cse.c:846-862)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../agents/ov_SC04_004__func_80181DAC/body.c | 28 ++ .../ov_SC04_004__func_80181DAC/body_free.c | 49 +++ .../ov_SC04_004__func_80181DAC/body_tree.c | 51 +++ .../ov_SC04_004__func_80181DAC/history.txt | 14 + .../ov_SC04_004__func_80181DAC/mechanism.md | 110 ++++++ .../ov_SC04_004__func_80181DAC/neighbours.txt | 47 +++ .../ov_SC04_004__func_80181DAC/related.txt | 83 ++++ .../ov_SC04_004__func_80181DAC/residual.txt | 27 ++ .../ov_SC04_004__func_80181DAC/sites.txt | 2 + .../agents/ov_SC04_004__func_80181DAC/tu.txt | 2 + .run/P36/delever/calibration.json | 372 +++++++++--------- .run/P36/delever/ledger.jsonl | 3 + src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c | 55 +-- src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c | 55 +-- src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c | 55 +-- 15 files changed, 650 insertions(+), 303 deletions(-) create mode 100644 .run/P36/agents/ov_SC04_004__func_80181DAC/body.c create mode 100644 .run/P36/agents/ov_SC04_004__func_80181DAC/body_free.c create mode 100644 .run/P36/agents/ov_SC04_004__func_80181DAC/body_tree.c create mode 100644 .run/P36/agents/ov_SC04_004__func_80181DAC/history.txt create mode 100644 .run/P36/agents/ov_SC04_004__func_80181DAC/mechanism.md create mode 100644 .run/P36/agents/ov_SC04_004__func_80181DAC/neighbours.txt create mode 100644 .run/P36/agents/ov_SC04_004__func_80181DAC/related.txt create mode 100644 .run/P36/agents/ov_SC04_004__func_80181DAC/residual.txt create mode 100644 .run/P36/agents/ov_SC04_004__func_80181DAC/sites.txt create mode 100644 .run/P36/agents/ov_SC04_004__func_80181DAC/tu.txt diff --git a/.run/P36/agents/ov_SC04_004__func_80181DAC/body.c b/.run/P36/agents/ov_SC04_004__func_80181DAC/body.c new file mode 100644 index 000000000..a0e66b718 --- /dev/null +++ b/.run/P36/agents/ov_SC04_004__func_80181DAC/body.c @@ -0,0 +1,28 @@ +s32 func_80181DAC(s32 arg0) { + extern u8 D_801202A0[]; + u8 *pe; + u16 t; + s32 count; + + pe = D_801202A0; + for (count = 0; count < 0x60; count++, pe += 0x10C) { + if ((s32)pe == arg0) { + continue; + } + switch (*(u16 *)pe) { + case 0x1FC: + t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9; + if (func_80181E90((s16 *)arg0, (s16 *)(pe + 4), t) != 0) { + return (s32)pe; + } + break; + case 0x239: + t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(pe + 0x20) + 0x18)) >> 6; + if (func_80181E90((s16 *)arg0, (s16 *)(pe + 4), t) != 0) { + return (s32)pe; + } + break; + } + } + return 0; +} diff --git a/.run/P36/agents/ov_SC04_004__func_80181DAC/body_free.c b/.run/P36/agents/ov_SC04_004__func_80181DAC/body_free.c new file mode 100644 index 000000000..652231e78 --- /dev/null +++ b/.run/P36/agents/ov_SC04_004__func_80181DAC/body_free.c @@ -0,0 +1,49 @@ +s32 func_80181DAC(s32 arg0) { + extern u8 D_801202A0[]; + u8 *pe; + u8 *ps; + s16 *ca; + s16 *cb; + u16 state; + u16 t; + s32 count; + + pe = D_801202A0; + count = 0; + ps = pe + 4; + do { + if ((s32)pe == arg0) { + goto next; + } + state = *(u16 *)pe; + ca = (s16 *)((s32)arg0 + 0); + if (state == 0x1FC) { + goto b1fc; + } + cb = (s16 *)((s32)ps + 0); + if (state == 0x239) { + goto b239; + } + goto next; + + b1fc: + cb = (s16 *)((s32)ps + 0); + t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9; + goto call; + + b239: + t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(ps + 0x1C) + 0x18)) >> 6; + /* fall through */ + call: + if (func_80181E90(ca, cb, t) == 0) { + goto next; + } + return (s32)pe; + + next: + count++; + ps += 0x10C; + pe += 0x10C; + } while (count < 0x60); + return 0; +} diff --git a/.run/P36/agents/ov_SC04_004__func_80181DAC/body_tree.c b/.run/P36/agents/ov_SC04_004__func_80181DAC/body_tree.c new file mode 100644 index 000000000..98adfc2f9 --- /dev/null +++ b/.run/P36/agents/ov_SC04_004__func_80181DAC/body_tree.c @@ -0,0 +1,51 @@ +s32 func_80181DAC(s32 arg0) { + extern u8 D_801202A0[]; + register s32 zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus7) + u8 *pe; + u8 *ps; + s16 *ca; + s16 *cb; + u16 state; + u16 t; + s32 count; + + pe = D_801202A0; + count = 0; + ps = pe + 4; + do { + if ((s32)pe == arg0) { + goto next; + } + state = *(u16 *)pe; + ca = (s16 *)((s32)arg0 + zr); + if (state == 0x1FC) { + goto b1fc; + } + cb = (s16 *)((s32)ps + zr); + if (state == 0x239) { + goto b239; + } + goto next; + + b1fc: + cb = (s16 *)((s32)ps + zr); + t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9; + goto call; + + b239: + t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(ps + 0x1C) + 0x18)) >> 6; + /* fall through */ + call: + if (func_80181E90(ca, cb, t) == 0) { + goto next; + } + __asm__ __volatile__("" :: "r"(pe)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus7) + return (s32)pe; + + next: + count++; + ps += 0x10C; + pe += 0x10C; + } while (count < 0x60); + return 0; +} diff --git a/.run/P36/agents/ov_SC04_004__func_80181DAC/history.txt b/.run/P36/agents/ov_SC04_004__func_80181DAC/history.txt new file mode 100644 index 000000000..d0ff047de --- /dev/null +++ b/.run/P36/agents/ov_SC04_004__func_80181DAC/history.txt @@ -0,0 +1,14 @@ +g6: verdict NO-MATCH start 16 best 16 compiles 322 path +best-scoring single candidates of the last trace (move -> score [residual class]): + R12 width state u16->s32 @6988 -> 16 [COUNT] (from 16) + R8 temp tmp0 @7016 -> 16 [COUNT] (from 16) + R7 block @7016 -> 16 [COUNT] (from 16) + R10 param-copy arg0 @6991 -> 16 [COUNT] (from 16) + R8 base tmp0 @7016 -> 16 [COUNT] (from 16) + R9 swap-stmts @6999 -> 16 [COUNT] (from 16) + R7 block @7000 -> 16 [COUNT] (from 16) + R8 temp tmp0 @6999 -> 16 [COUNT] (from 16) + R7 do-while @7000 -> 16 [COUNT] (from 16) + R9 swap-stmts @7011 -> 16 [COUNT] (from 16) + R7 block @6992 -> 16 [COUNT] (from 16) + R8 temp tmp0 @7012 -> 16 [COUNT] (from 16) diff --git a/.run/P36/agents/ov_SC04_004__func_80181DAC/mechanism.md b/.run/P36/agents/ov_SC04_004__func_80181DAC/mechanism.md new file mode 100644 index 000000000..f6989038f --- /dev/null +++ b/.run/P36/agents/ov_SC04_004__func_80181DAC/mechanism.md @@ -0,0 +1,110 @@ +# func_80181DAC (ov_SC04_004_jr_8017AE2C.c) — d17, P36 T7 S104 + +**Result: score 0, plain C, zero levers.** It started at 16 (lever-free) with 2 levers in the tree: a `$0` pin and a keepalive. +The same text also closes the class's three other copies (table at the end). + +## (a) The residual (16, COUNT 55 vs 57) +The residual had two separate defects, and neither one is a register lever at heart: +1. **arg0/count swapped between s2 and s3, and the b1fc/b239 reads went through `a0`.** The target is `lw v0,32(s2)` and + mine was `lw v0,32(a0)`. cse rewrote the arms' `arg0 + 0x20` reads to use the hoisted copy `ca = arg0`, which is the + pseudo that lands in `a0`. That took refs off arg0, and arg0 then lost its callee-saved slot to count. +2. **Two missing instructions at the return.** The target has `beqz v0,` with `addiu s3,s3,1` in the + delay slot, then `j epilogue; move v0,s0`. Mine had `bnez v0,epilogue; move v0,s0`. reorg took the `move` from the + fall-through thread and inverted the branch around the jump. + +## (b) The passes and decisions (read in tools/reference/gcc-2.7.2) +- Defect 1: `cse.c:846-862` `make_regs_eqv`. The new register (`ca`) becomes the class head when it lives past the cse + block and its last use comes after the old register's (`arg0`'s last use is the b239 read; `ca`'s is the call, which + sits in a later block). The cse path follows the jumps into b1fc and b239 (`cse_end_of_basic_block`: the label has one + use and a barrier before it), so `canon_reg` rewrites those reads to `ca`. **Proved**: in the free body's `.rtl`, insn 36 + is `(set 75 72)`, and a1.c (no `ca`) fixes every register and scores 8. +- Defect 2: `reorg.c:1364-1372` `mostly_true_jump`. A branch whose target label is immediately followed by + `NOTE_INSN_LOOP_VTOP` is predicted taken (returns 1). `fill_eager_delay_slots` (`reorg.c:3688-3700`) then fills from the + **target** thread first and steals `count++`. The `j epilogue` keeps its backward-filled `move v0,s0` + (`fill_simple_delay_slots`), and relax finds no branch-around-a-jump to invert. `NOTE_INSN_LOOP_VTOP` is only emitted by + `duplicate_loop_exit_test` (`jump.c:2306`), which runs only on a rotated `for`/`while` loop, never on a `do-while`. + A do-while's `next:` label is followed by `NOTE_INSN_LOOP_CONT`, the EQ test predicts not-taken (`reorg.c:1405`), the + fall-through steal succeeds (`steal_delay_list_from_fallthrough`, `reorg.c:1699`), and the branch gets inverted. **Proved** from the + `.jump2` dumps: + - r12 (the `for` loop): `(code_label 145) (note NOTE_INSN_LOOP_VTOP)`. + - a3 (the do-while): `(code_label "next") (note NOTE_INSN_LOOP_CONT)`. + - r11 (the switch body with a do-while) keeps exactly this 6-point residual. + - The tree's keepalive `asm volatile` got the same result another way: an asm insn stops the fall-through search + (`stop_search_p`, `reorg.c:698`). +- Why a call per case costs 0 bytes: **post-reload cross-jump** (`toplev.c:3142` jump2, `find_cross_jump` `jump.c:2371`) + merges the two call tails from the `a2 = zext(t)` insn down (`.jump2` label 198). That produces the target's single + `jal` and b1fc's `j 7014`. Each arm's own `a0 = arg0` / `a1 = pe+4` copies stay at the arm heads (sched2), and reorg + moves them into the dispatch branches' delay slots. + +## (c) The moves that closed it (joint; each alone scores 6 or 8) +1. Delete the decompiler's hoisted argument copies `ca`/`cb` and the shared `call:` label. Write a `switch` on the + state with one call per case: `if (func_80181E90(arg0, pe + 4, t) != 0) return pe; break;`. This fixes defect 1. +2. Rewrite `do { … goto next; … next: count++; pe += 0x10C; } while (count < 0x60)` as + `for (count = 0; count < 0x60; count++, pe += 0x10C)` with `continue`. This fixes defect 2. +3. Delete the second walked pointer `ps = pe + 4` too, since loop.c's strength reduction rebuilds the `pe+4` giv in `s1` + (r12 = 0). `t` has to stay a `u16` temp: r9, with `t` inlined into the argument, scores 19 because the HImode + pseudo's `zero_extend` at the shared tail sets the cross-jump merge point. + +Also at 0: r3/r5-r8/r10 (with or without `ca`/`cb` once it is a switch), v4/v5 (the goto body inside a `for`), and s1.c +(struct form). + +## (d) Generator proposal +When a lever-free do-while's return path shows `bnez vX,; move v0,` where the target has +`beqz vX,; ` followed by `j ; move v0,`, and the tree needs a keepalive +asm before the `return`: rewrite `do { … goto next; … next: ; } while (c);` as `for (; c; ) { … continue; … }` +(VTOP prediction, `reorg.c:1364`). And when goto arms feed a shared `call:` label through copies hoisted before the +dispatch (`ca = arg0;` before the `==` tests, a `$0`-pinned `x + zr` in the tree), rewrite them as a `switch` with one +call per case and delete the copies: cross-jump re-merges the calls for free (`jump.c:2371`). + +## (e) What did not work (byte evidence) +- a1 (a switch-like goto chain with a single call and no `ca`): 8. Registers right, the a0/a1 delay-slot hoists and the + return missing. +- a2 (the argument computed straight into the call per case): 21. `t` lands in `a2`. +- a3 (the goto body with per-arm calls, in a do-while): 6. Only the return reorg is left. +- v1 (a positive test) and v2 (a `while` loop): 6. v3 (the `for` with `count = 0` in the init after `ps`): 4, prologue + order only. +- r1/r2/r4 (structured if/else instead of a switch): 13. The if/else keeps a single shared-call shape that cse and reorg + treat differently. +- r9 (`t` inlined as a `(u16)` argument): 19. + +## (f) Where the method fell short +- Step 1's "count first" was right (55 vs 57), but neither missing instruction was an allocation question. + `alloc_table.py` would have been a detour. The register swap was a consequence of cse's head choice, and the count gap + was a reorg prediction. The METHOD list has no "reorg thread-choice" entry. Add one: *a delay slot filled from the other + thread = `mostly_true_jump` (`reorg.c:1335`); a loop note (VTOP/LOOP_BEG) next to the target label flips it; a + do-while has none*. +- The decompiler's goto spelling (a shared `call:` label, hoisted copies, a `+ zr` pin) hid a plain `switch`. No generator + family reaches a switch from goto text (the same lesson as S104 d3/d9). The 16 from the free sweep was a structural + ceiling, not a search failure. + +## (g) The structs question +Structs were **not** the missing piece here. s1.c uses a body-local `Ent { u16 kind; u16 unk2; s16 pos[14]; Sub *sub +/*0x20*/; … }` (size 0x10C) and `Sub { u8 pad[0x18]; s16 v; }`, and scores **0**, byte-identical to the cast form. +Neither lever lived in an alias or scheduling decision, because the loop has no stores for `expr.c:4568`'s aggregate +channel to matter. Both lived in the control-flow shape (cse's copy head, reorg's loop-note prediction). A struct type for +`D_801202A0` (the 0x10C-byte entity table: `+0` kind, `+4` position, `+0x20` pointer to a sub-object with `s16` at +`+0x18`) is still the right long-term spelling and is byte-neutral. + +## Copies of this class (the same text; each `--try` = 0) +| function | TU | file | +|---|---|---| +| func_80181DAC | src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c | PACK/body.c (= scratch/copies/func_80181DAC_cast.c) | +| func_801872E0 | src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c | PACK/scratch/copies/func_801872E0.c (callee func_801873C4, prototyped) | +| func_80180D50 | src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c | PACK/scratch/copies/func_80180D50.c (keeps the tree's cast call `((s32 (*)(s16 *, s16 *, s32))func_80180E34)`) | +| func_80183820 | src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c | PACK/scratch/copies/func_80183820.c (callee func_80183904) | + +That is 4 bodies and 8 levers removed. + +## func_80181D1C (the neighbouring class, 4 copies): NOT closed by this mechanism +Its best lever-free text is PACK/scratch/d1c.c, at 15 (COUNT 34 vs 36). Two defects, both different from DAC's: +- **The early `return 0`** has the same reorg symptom (fall-through steal and inversion; the tree fixes it with + `asm volatile("")`), but there is no loop, so the VTOP prediction cannot apply. It would need `mostly_true_jump` > 0 + through rarity (`reorg.c:1375-1390`) or an own-fallthrough failure (a live label after the branch). No plain-C shape + was found. +- **The return value lives in the hard register v0 across the `x < t` test**, and the call result `r` is copied to `v1` + (`move v1,v0`). The tree pins `rr`→$3 and `z`→$2. Local-alloc gives the block-local `r` its `v0` suggestion before + global runs (`local-alloc.c:1797+`, qty_phys_sugg), and every `ret` variable shape tried (d1-d11) ends up with `ret` in + `v1` and a final `move v0,v1`. The target behaves as if `(set (reg:SI 2) 0)` were already live (a hard-register + return-value store hoisted before the test). jump.c's if-conversion (`jump.c:700-830`, allowed on MIPS hard registers) + is the only pass seen that does that, and its single-insn arm shape does not fit this body. +Candidates for the STRUCTS phase or a dedicated agent. diff --git a/.run/P36/agents/ov_SC04_004__func_80181DAC/neighbours.txt b/.run/P36/agents/ov_SC04_004__func_80181DAC/neighbours.txt new file mode 100644 index 000000000..f03dec717 --- /dev/null +++ b/.run/P36/agents/ov_SC04_004__func_80181DAC/neighbours.txt @@ -0,0 +1,47 @@ +--- every @class/@stuck/@crack note in this translation unit --- +// @class: plumbing +// @stuck: none — MATCH +// @class: regalloc-order — simplified sibling of matched func_8017B614. +// @stuck: none. Block-moves are align-1 struct-assigns (u8[8]) -> emit_block_move +// @class: struct +// @stuck: none — MATCH (74 ins) +// @class: regalloc-order + T1 memcpy-builtin→call re-crack +// @stuck: 0 (iso). Register lever = $16 pin + in-place re-tie on the memcpy-branch src (keeps +// @class: plumbing +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH (63 ins) +// @class: struct +// @stuck: none — MATCH (62 ins) +// @class: struct +// @stuck: none — MATCH (65 ins) +// @class: regalloc-order +// @stuck: pending self-check — register order param=$s2 counter=$s1 ptr=$s0 +// @class: plumbing +// @stuck: none — MATCH (expected); short-typed global increment + signed compare, store-2 on overflow +// @class: plumbing +// @stuck: none — MATCH expected (simple short-increment + guarded call) +// @class: regalloc-order +// @stuck: none — MATCH (branch-polarity invert: fn-ptr non-zero call is the fall-through arm) +// @class: plumbing +// @stuck: none — signed s32 counter at 0x1C, delay-slot store is the unconditional bump +// @class: schedule +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @class: struct +// @stuck: none — MATCH (94 ins). Keys: (1) cache out[0] in a local `o` before the switch so gcc +// @class: schedule +// @stuck: none — MATCH (71 ins). Tail schedule: read out.c into an explicit temp BEFORE the 0x5a/1 const stores so gcc hoists its lhu early (load-delay filled by li 0x5a) and stores out.c last from a held reg; without the temp gcc instead deferred out.b's store. in/out are two separate SV3{s16 a,b,c} stack slots (sp+0x10, sp+0x18) for ((void (*)(int, void *, void *))func_8012F214)(a0,&in,&out). 0x34 compare reads u16 (lhu, not lh). +// @class: other +// @stuck: none — MATCH (expected); 16-bit sh stores via short* casts, s0=param_1 call-crossing +// @class: plumbing +// @stuck: none — MATCH (18 ins): if((b&1) && p!=&sym) call(param,&sym); $a0 live, $a1=&sym fall out +// @class: schedule +// @stuck: none — MATCH (44 ins). Two §3-T4 branch-polarity inversions: outer if(param_2>=iVar2) makes the func_8018352C else-block fall-through; inner if(param_3>=iVar2) return 0 makes the func_8012A828 body fall-through. No pins needed — natural $s1/$s0/$s2 alloc matched. +// @class: plumbing +// @stuck: none — MATCH (straightforward; callee sigs canonical from overlay) +// @class: plumbing +// @stuck: none — MATCH expected (single call-crossing local pins to $s0 naturally; lhu via unsigned short) diff --git a/.run/P36/agents/ov_SC04_004__func_80181DAC/related.txt b/.run/P36/agents/ov_SC04_004__func_80181DAC/related.txt new file mode 100644 index 000000000..acc0661f3 --- /dev/null +++ b/.run/P36/agents/ov_SC04_004__func_80181DAC/related.txt @@ -0,0 +1,83 @@ +=== lever-free bodies in ov_SC04_004 sharing a callee or global with func_80181DAC (41 found; top 6 by shared symbols) — read them for the SHAPE === +--- func_8012A908 (src/shared/ov/func_8012A908.h:6) shares 1: D_801202A0 --- +void func_8012A908(void) { + u8 *p = D_801202A0; + s32 i; + for (i = 0; i < 0x60; i++) { + if (((s16)D_801270C0 == 1) || (*(u16 *)(p + 0x72) & 0x1000)) { + func_8012A988(p); + } + p += 0x10C; + } +} + +--- func_801787D4 (src/shared/ov/func_801787D4.h:5) shares 1: D_801202A0 --- +void func_801787D4(void) { + u8 *p = D_801202A0; + s32 i; + for (i = 0; i < 0x60; i++) { + if (*(u16 *)(p + 0) != 0 && p[0xC0] != 0) { + func_80178840(p); + } + p += 0x10C; + } +} + +--- func_8013E410 (src/shared/ov/func_8013E410.h:4) shares 1: D_801202A0 --- +s32 func_8013E410(void) { + s32 a0; + s32 v1; + v1 = (s32)D_801202A0; + for (a0 = 0; a0 < 0x60; a0++, v1 += 0x10C) { + if (*(u16 *)v1 == 0) { + return v1; + } + } + return 0; +} + +--- func_80149E94 (src/shared/ov/func_80149E94.h:6) shares 1: D_801202A0 --- +s32 func_80149E94(s32 arg0) { + u8 *p; + if ((func_8016F1AC() == 0) && (*(u8 *)(arg0 + 0x1C5) != 0)) { + *(u8 *)(arg0 + 0x1C5) = 0; + for (p = D_801202A0; p < D_801202A0 + 0x6480; p += 0x10C) { + if (func_80149F2C(arg0, (s32)p) != 0) { + return 1; + } + } + } + return 0; +} + +--- func_8014A238 (src/shared/ov/func_8014A238.h:6) shares 1: D_801202A0 --- +s32 func_8014A238(s32 arg0) { + u32 i; + Entry8014A238 *p; + for (i = 0; i < 0x60; i++) { + p = &((Entry8014A238 *)D_801202A0)[i]; + if ((p->f_0 != 0) && (p->f_AA != 0) && + (func_8014C278(arg0, (s32)p, 0x30) != 0) && + (func_8014C2B0((void *)arg0, (void *)p, 0x200) != 0)) { + return (s32)p; + } + } + return 0; +} + +--- func_8012E504 (src/shared/ov/func_8012E504.h:4) shares 1: D_801202A0 --- +s32 func_8012E504(s32 a0, s32 a1) { + s32 p; + s32 end; + p = (s32)D_801202A0; + end = (s32)D_801202A0 + 0x6480; + for (; p != end; p += 0x10C) { + if (p != a0) { + if (*(u16*)p == a1) { + return p; + } + } + } + return 0; +} + diff --git a/.run/P36/agents/ov_SC04_004__func_80181DAC/residual.txt b/.run/P36/agents/ov_SC04_004__func_80181DAC/residual.txt new file mode 100644 index 000000000..db8e92912 --- /dev/null +++ b/.run/P36/agents/ov_SC04_004__func_80181DAC/residual.txt @@ -0,0 +1,27 @@ +src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c:func_80181DAC: score 16 (COUNT; mine 55 ins, target 57) — not yet + register pairs (mine -> target, count): s2->s3 x6, s3->s2 x2, a0->s2 x2 + replace mine[1:3] target[1:3] + 1 sw s3,28(sp) | sw s2,24(sp) + 2 move s3,a0 | move s2,a0 + replace mine[6:8] target[6:8] + 6 sw s2,24(sp) | sw s3,28(sp) + 7 move s2,zero | move s3,zero + replace mine[11:12] target[11:12] + 11 beq s0,s3,7024 | beq s0,s2,702c + replace mine[16:17] target[16:17] + 16 move a0,s3 | move a0,s2 + replace mine[20:23] target[20:23] + 20 j 7028 | j 7030 + 21 addiu s2,s2,1 | addiu s3,s3,1 + 22 lw v0,32(a0) | lw v0,32(s2) + replace mine[30:31] target[30:31] + 30 lw v0,32(a0) | lw v0,32(s2) + replace mine[39:40] target[39:42] + 39 bnez v0,703c | beqz v0,7030 + 40 -- | addiu s3,s3,1 + 41 -- | j 7044 + replace mine[41:42] target[43:44] + 41 addiu s2,s2,1 | addiu s3,s3,1 + replace mine[43:45] target[45:47] + 43 slti v0,s2,96 | slti v0,s3,96 + 44 bnez v0,6fac | bnez v0,6fac diff --git a/.run/P36/agents/ov_SC04_004__func_80181DAC/sites.txt b/.run/P36/agents/ov_SC04_004__func_80181DAC/sites.txt new file mode 100644 index 000000000..ddb526b8e --- /dev/null +++ b/.run/P36/agents/ov_SC04_004__func_80181DAC/sites.txt @@ -0,0 +1,2 @@ +NEEDED pin $0 line 7085 +NEEDED keepalive line 7124 diff --git a/.run/P36/agents/ov_SC04_004__func_80181DAC/tu.txt b/.run/P36/agents/ov_SC04_004__func_80181DAC/tu.txt new file mode 100644 index 000000000..3eb23023f --- /dev/null +++ b/.run/P36/agents/ov_SC04_004__func_80181DAC/tu.txt @@ -0,0 +1,2 @@ +src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c +func_80181DAC diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index 0b5ca1665..c5a1ca937 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,7 +1,7 @@ { - "head": "91ae94a64", + "head": "c48582300", "stamp": "15956e4a96c4", - "generated": "2026-09-10 22:32", + "generated": "2026-09-10 22:36", "aliases": [ "main", "ov_SC03_014", @@ -21,207 +21,207 @@ "main": { "objects": 85, "identical": 85, - "seconds": 12.038000000000002, - "mean_s": 0.142 + "seconds": 11.349, + "mean_s": 0.134 }, "ov_SC03_014": { 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a/.run/P36/delever/ledger.jsonl +++ b/.run/P36/delever/ledger.jsonl @@ -29213,3 +29213,6 @@ {"ts": "2026-09-10 22:31:03", "label": "s104_d16", "rung": "E", "calib": {"head": "4c2e503ec", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_124/ov_SC03_124_jr_80181B44.c", "fn": "func_80182598", "addr": 2149066136, "aliases": null, "header": false, "includers": 0, "nhash_before": "c5e217212db4d19a96e948c172b5ddf4bf8fef9f", "nhash_after": "48eb838245b8dd738e3594d1acfb2918f8b526d6", "source": "propagate:src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c:func_8017F368", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.214, "objects": ["build/src/ov_SC03_124/ov_SC03_124_jr_80181B44.o"], "before_text": "void func_80182598(u16 *a0, s32 a1)\n{\n\n extern s32 D_800A651C[][5];\n extern u16 D_8019023C[];\n extern u16 D_801902BC[];\n extern u16 D_8019035C[][4];\n extern u16 D_8019035E[][4];\n extern u16 D_80190360[][4];\n extern u16 D_80190362[][4];\n register s32 zr __asm__(\"$0\"); // !FAKE: pin $0 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n u16 pad0[16]; /* dead: locals begin at sp+0x30, va must land at sp+0x50 */\n u16 va[16]; /* sp+0x50 \u2014 outer quad, 4 x SVECTOR */\n u16 vb[16]; /* sp+0x70 \u2014 inner quad, 4 x SVECTOR */\n s32 sxy[8]; /* sp+0x90 \u2014 [0..3] RotNclip4, [4..7] RotTransPers4 */\n s16 idx[4]; /* sp+0xB0 */\n s32 p; /* sp+0xB8 */\n s32 otz; /* sp+0xBC */\n s32 flag; /* sp+0xC0 */\n\n u16 attr;\n s32 type;\n s32 type2;\n u16 *p1;\n u16 *p2;\n register u16 *dst __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 i;\n u8 *pk;\n s32 j;\n\n func_8012E32C();\n\n attr = a0[3];\n type = attr & 0xFF;\n type2 = type + zr;\n if ((attr & 0xF00) == 0x200) {\n func_80182980(a0, a1);\n return;\n }\n\n p1 = (u16 *)((u8 *)D_8019023C + type * 0x20);\n i = 0;\n p2 = p1 + 2;\n dst = va;\n while (i < 4) {\n dst[0] = a0[0] + p1[0];\n dst[1] = a0[1] + p2[-1];\n dst[2] = a0[2] + p2[0];\n i++;\n p1 += 4;\n p2 += 4;\n dst += 4;\n }\n\n if (RotNclip4((s32)&va[0], (s32)&va[4], (s32)&va[8], (s32)&va[12],\n &sxy[0], &sxy[1], &sxy[2], &sxy[3], &p, &otz, &flag) <= 0) {\n return;\n }\n\n otz -= 0x10;\n if (otz < 0) {\n return;\n }\n if (otz >= 0x1000) {\n return;\n }\n\n p1 = (u16 *)((u8 *)D_801902BC + type2 * 0x20);\n i = 0;\n p2 = p1 + 2;\n dst = vb;\n while (i < 4) {\n dst[0] = a0[0] + p1[0];\n dst[1] = a0[1] + p2[-1];\n dst[2] = a0[2] + p2[0];\n i++;\n p1 += 4;\n p2 += 4;\n dst += 4;\n }\n\n RotTransPers4((s32)&vb[0], (s32)&vb[4], (s32)&vb[8], (s32)&vb[12],\n &sxy[4], &sxy[5], &sxy[6], &sxy[7], &p, &flag);\n\n pk = func_80010A08(0xA8);\n\n for (j = 0; j < 4; j++) {\n idx[0] = D_8019035C[j][0];\n idx[1] = D_8019035E[j][0];\n idx[2] = D_80190360[j][0];\n idx[3] = D_80190362[j][0];\n *(s32 *)(pk + 0x4) = a1 & -(idx[0] < 4);\n *(s32 *)(pk + 0xC) = a1 & -(idx[1] < 4);\n *(s32 *)(pk + 0x14) = a1 & -(idx[2] < 4);\n *(s32 *)(pk + 0x1C) = a1 & -(idx[3] < 4);\n pk[7] = 0x3A;\n *(u32 *)(pk + 0x0) = 0x08000000;\n *(s32 *)(pk + 0x8) = sxy[idx[0]];\n *(s32 *)(pk + 0x10) = sxy[idx[1]];\n *(s32 *)(pk + 0x18) = sxy[idx[2]];\n *(s32 *)(pk + 0x20) = sxy[idx[3]];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n pk += 0x24;\n }\n\n *(s32 *)(pk + 0x4) = a1;\n pk[7] = 0x2A;\n *(u32 *)(pk + 0x0) = 0x05000000;\n *(s32 *)(pk + 0x8) = sxy[0];\n *(s32 *)(pk + 0xC) = sxy[1];\n *(s32 *)(pk + 0x10) = sxy[2];\n *(s32 *)(pk + 0x14) = sxy[3];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n func_8012E28C(otz, 1);\n}\n", "after_text": "void func_80182598(u16 *a0, s32 a1)\n{\n\n extern s32 D_800A651C[][5];\n extern u16 D_8019023C[];\n extern u16 D_801902BC[];\n extern u16 D_8019035C[][4];\n extern u16 D_8019035E[][4];\n extern u16 D_80190360[][4];\n extern u16 D_80190362[][4];\n\n u16 pad0[16]; /* dead: locals begin at sp+0x30, va must land at sp+0x50 */\n SVECTOR va[4]; /* sp+0x50 \u2014 outer quad, 4 x SVECTOR */\n SVECTOR vb[4]; /* sp+0x70 \u2014 inner quad, 4 x SVECTOR */\n s32 sxy[8]; /* sp+0x90 \u2014 [0..3] RotNclip4, [4..7] RotTransPers4 */\n s16 idx[4]; /* sp+0xB0 */\n s32 p; /* sp+0xB8 */\n s32 otz; /* sp+0xBC */\n s32 flag; /* sp+0xC0 */\n\n u16 attr;\n s32 type;\n u8 type2;\n u16 *p1;\n u16 *p2;\n s32 i;\n u8 *pk;\n s32 j;\n\n func_8012E32C();\n\n attr = a0[3];\n type = attr & 0xFF;\n type2 = type;\n if ((attr & 0xF00) == 0x200) {\n func_80182980(a0, a1);\n return;\n }\n\n p1 = (u16 *)((u8 *)D_8019023C + type * 0x20);\n for (i = 0; i < 4; i++, p1 += 4) {\n va[i].vx = a0[0] + p1[0];\n va[i].vy = a0[1] + p1[1];\n va[i].vz = a0[2] + p1[2];\n }\n\n if (RotNclip4((s32)&va[0], (s32)&va[1], (s32)&va[2], (s32)&va[3],\n &sxy[0], &sxy[1], &sxy[2], &sxy[3], &p, &otz, &flag) <= 0) {\n return;\n }\n\n otz -= 0x10;\n if (otz < 0) {\n return;\n }\n if (otz >= 0x1000) {\n return;\n }\n\n p2 = (u16 *)((u8 *)D_801902BC + type2 * 0x20);\n for (i = 0; i < 4; i++, p2 += 4) {\n vb[i].vx = a0[0] + p2[0];\n vb[i].vy = a0[1] + p2[1];\n vb[i].vz = a0[2] + p2[2];\n }\n\n RotTransPers4((s32)&vb[0], (s32)&vb[1], (s32)&vb[2], (s32)&vb[3],\n &sxy[4], &sxy[5], &sxy[6], &sxy[7], &p, &flag);\n\n pk = func_80010A08(0xA8);\n\n for (j = 0; j < 4; j++) {\n idx[0] = D_8019035C[j][0];\n idx[1] = D_8019035E[j][0];\n idx[2] = D_80190360[j][0];\n idx[3] = D_80190362[j][0];\n *(s32 *)(pk + 0x4) = a1 & -(idx[0] < 4);\n *(s32 *)(pk + 0xC) = a1 & -(idx[1] < 4);\n *(s32 *)(pk + 0x14) = a1 & -(idx[2] < 4);\n *(s32 *)(pk + 0x1C) = a1 & -(idx[3] < 4);\n pk[7] = 0x3A;\n *(u32 *)(pk + 0x0) = 0x08000000;\n *(s32 *)(pk + 0x8) = sxy[idx[0]];\n *(s32 *)(pk + 0x10) = sxy[idx[1]];\n *(s32 *)(pk + 0x18) = sxy[idx[2]];\n *(s32 *)(pk + 0x20) = sxy[idx[3]];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n pk += 0x24;\n }\n\n *(s32 *)(pk + 0x4) = a1;\n pk[7] = 0x2A;\n *(u32 *)(pk + 0x0) = 0x05000000;\n *(s32 *)(pk + 0x8) = sxy[0];\n *(s32 *)(pk + 0xC) = sxy[1];\n *(s32 *)(pk + 0x10) = sxy[2];\n *(s32 *)(pk + 0x14) = sxy[3];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n func_8012E28C(otz, 1);\n}\n"} {"ts": "2026-09-10 22:31:03", "label": "s104_d16", "rung": "E", "calib": {"head": "4c2e503ec", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_015/ov_SC04_015_jr_801820DC.c", "fn": "func_80182F2C", "addr": 2149068588, "aliases": null, "header": false, "includers": 0, "nhash_before": "c5e217212db4d19a96e948c172b5ddf4bf8fef9f", "nhash_after": "48eb838245b8dd738e3594d1acfb2918f8b526d6", "source": "propagate:src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c:func_8017F368", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.162, "objects": ["build/src/ov_SC04_015/ov_SC04_015_jr_801820DC.o"], "before_text": "void func_80182F2C(u16 *a0, s32 a1)\n{\n\n extern s32 D_800A651C[][5];\n extern u16 D_801C4040[];\n extern u16 D_801C40C0[];\n extern u16 D_801C4160[][4];\n extern u16 D_801C4162[][4];\n extern u16 D_801C4164[][4];\n extern u16 D_801C4166[][4];\n register s32 zr __asm__(\"$0\"); // !FAKE: pin $0 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n u16 pad0[16]; /* dead: locals begin at sp+0x30, va must land at sp+0x50 */\n u16 va[16]; /* sp+0x50 \u2014 outer quad, 4 x SVECTOR */\n u16 vb[16]; /* sp+0x70 \u2014 inner quad, 4 x SVECTOR */\n s32 sxy[8]; /* sp+0x90 \u2014 [0..3] RotNclip4, [4..7] RotTransPers4 */\n s16 idx[4]; /* sp+0xB0 */\n s32 p; /* sp+0xB8 */\n s32 otz; /* sp+0xBC */\n s32 flag; /* sp+0xC0 */\n\n u16 attr;\n s32 type;\n s32 type2;\n u16 *p1;\n u16 *p2;\n register u16 *dst __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 i;\n u8 *pk;\n s32 j;\n\n func_8012E32C();\n\n attr = a0[3];\n type = attr & 0xFF;\n type2 = type + zr;\n if ((attr & 0xF00) == 0x200) {\n func_80183314(a0, a1);\n return;\n }\n\n p1 = (u16 *)((u8 *)D_801C4040 + type * 0x20);\n i = 0;\n p2 = p1 + 2;\n dst = va;\n while (i < 4) {\n dst[0] = a0[0] + p1[0];\n dst[1] = a0[1] + p2[-1];\n dst[2] = a0[2] + p2[0];\n i++;\n p1 += 4;\n p2 += 4;\n dst += 4;\n }\n\n if (RotNclip4((s32)&va[0], (s32)&va[4], (s32)&va[8], (s32)&va[12],\n &sxy[0], &sxy[1], &sxy[2], &sxy[3], &p, &otz, &flag) <= 0) {\n return;\n }\n\n otz -= 0x10;\n if (otz < 0) {\n return;\n }\n if (otz >= 0x1000) {\n return;\n }\n\n p1 = (u16 *)((u8 *)D_801C40C0 + type2 * 0x20);\n i = 0;\n p2 = p1 + 2;\n dst = vb;\n while (i < 4) {\n dst[0] = a0[0] + p1[0];\n dst[1] = a0[1] + p2[-1];\n dst[2] = a0[2] + p2[0];\n i++;\n p1 += 4;\n p2 += 4;\n dst += 4;\n }\n\n RotTransPers4((s32)&vb[0], (s32)&vb[4], (s32)&vb[8], (s32)&vb[12],\n &sxy[4], &sxy[5], &sxy[6], &sxy[7], &p, &flag);\n\n pk = func_80010A08(0xA8);\n\n for (j = 0; j < 4; j++) {\n idx[0] = D_801C4160[j][0];\n idx[1] = D_801C4162[j][0];\n idx[2] = D_801C4164[j][0];\n idx[3] = D_801C4166[j][0];\n *(s32 *)(pk + 0x4) = a1 & -(idx[0] < 4);\n *(s32 *)(pk + 0xC) = a1 & -(idx[1] < 4);\n *(s32 *)(pk + 0x14) = a1 & -(idx[2] < 4);\n *(s32 *)(pk + 0x1C) = a1 & -(idx[3] < 4);\n pk[7] = 0x3A;\n *(u32 *)(pk + 0x0) = 0x08000000;\n *(s32 *)(pk + 0x8) = sxy[idx[0]];\n *(s32 *)(pk + 0x10) = sxy[idx[1]];\n *(s32 *)(pk + 0x18) = sxy[idx[2]];\n *(s32 *)(pk + 0x20) = sxy[idx[3]];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n pk += 0x24;\n }\n\n *(s32 *)(pk + 0x4) = a1;\n pk[7] = 0x2A;\n *(u32 *)(pk + 0x0) = 0x05000000;\n *(s32 *)(pk + 0x8) = sxy[0];\n *(s32 *)(pk + 0xC) = sxy[1];\n *(s32 *)(pk + 0x10) = sxy[2];\n *(s32 *)(pk + 0x14) = sxy[3];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n func_8012E28C(otz, 1);\n}\n", "after_text": "void func_80182F2C(u16 *a0, s32 a1)\n{\n\n extern s32 D_800A651C[][5];\n extern u16 D_801C4040[];\n extern u16 D_801C40C0[];\n extern u16 D_801C4160[][4];\n extern u16 D_801C4162[][4];\n extern u16 D_801C4164[][4];\n extern u16 D_801C4166[][4];\n\n u16 pad0[16]; /* dead: locals begin at sp+0x30, va must land at sp+0x50 */\n SVECTOR va[4]; /* sp+0x50 \u2014 outer quad, 4 x SVECTOR */\n SVECTOR vb[4]; /* sp+0x70 \u2014 inner quad, 4 x SVECTOR */\n s32 sxy[8]; /* sp+0x90 \u2014 [0..3] RotNclip4, [4..7] RotTransPers4 */\n s16 idx[4]; /* sp+0xB0 */\n s32 p; /* sp+0xB8 */\n s32 otz; /* sp+0xBC */\n s32 flag; /* sp+0xC0 */\n\n u16 attr;\n s32 type;\n u8 type2;\n u16 *p1;\n u16 *p2;\n s32 i;\n u8 *pk;\n s32 j;\n\n func_8012E32C();\n\n attr = a0[3];\n type = attr & 0xFF;\n type2 = type;\n if ((attr & 0xF00) == 0x200) {\n func_80183314(a0, a1);\n return;\n }\n\n p1 = (u16 *)((u8 *)D_801C4040 + type * 0x20);\n for (i = 0; i < 4; i++, p1 += 4) {\n va[i].vx = a0[0] + p1[0];\n va[i].vy = a0[1] + p1[1];\n va[i].vz = a0[2] + p1[2];\n }\n\n if (RotNclip4((s32)&va[0], (s32)&va[1], (s32)&va[2], (s32)&va[3],\n &sxy[0], &sxy[1], &sxy[2], &sxy[3], &p, &otz, &flag) <= 0) {\n return;\n }\n\n otz -= 0x10;\n if (otz < 0) {\n return;\n }\n if (otz >= 0x1000) {\n return;\n }\n\n p2 = (u16 *)((u8 *)D_801C40C0 + type2 * 0x20);\n for (i = 0; i < 4; i++, p2 += 4) {\n vb[i].vx = a0[0] + p2[0];\n vb[i].vy = a0[1] + p2[1];\n vb[i].vz = a0[2] + p2[2];\n }\n\n RotTransPers4((s32)&vb[0], (s32)&vb[1], (s32)&vb[2], (s32)&vb[3],\n &sxy[4], &sxy[5], &sxy[6], &sxy[7], &p, &flag);\n\n pk = func_80010A08(0xA8);\n\n for (j = 0; j < 4; j++) {\n idx[0] = D_801C4160[j][0];\n idx[1] = D_801C4162[j][0];\n idx[2] = D_801C4164[j][0];\n idx[3] = D_801C4166[j][0];\n *(s32 *)(pk + 0x4) = a1 & -(idx[0] < 4);\n *(s32 *)(pk + 0xC) = a1 & -(idx[1] < 4);\n *(s32 *)(pk + 0x14) = a1 & -(idx[2] < 4);\n *(s32 *)(pk + 0x1C) = a1 & -(idx[3] < 4);\n pk[7] = 0x3A;\n *(u32 *)(pk + 0x0) = 0x08000000;\n *(s32 *)(pk + 0x8) = sxy[idx[0]];\n *(s32 *)(pk + 0x10) = sxy[idx[1]];\n *(s32 *)(pk + 0x18) = sxy[idx[2]];\n *(s32 *)(pk + 0x20) = sxy[idx[3]];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n pk += 0x24;\n }\n\n *(s32 *)(pk + 0x4) = a1;\n pk[7] = 0x2A;\n *(u32 *)(pk + 0x0) = 0x05000000;\n *(s32 *)(pk + 0x8) = sxy[0];\n *(s32 *)(pk + 0xC) = sxy[1];\n *(s32 *)(pk + 0x10) = sxy[2];\n *(s32 *)(pk + 0x14) = sxy[3];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n func_8012E28C(otz, 1);\n}\n"} {"ts": "2026-09-10 22:32:03", "label": "s104_d16", "rung": "E", "calib": {"head": "a225fe560", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_018/ov_SC04_018_jr_80188E1C.c", "fn": "func_8018A2E0", "addr": 2149098208, "aliases": null, "header": false, "includers": 0, "nhash_before": "3bbc9facb6a72e405c2feaf895d27dbe806530ac", "nhash_after": "cdcb33e92cb8621441906931a4a91012dfc89b11", "source": ".run/P36/agents/ov_SC03_001__func_8017F368/scratch/copy_func_8018A2E0.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 2, "seconds": 0.429, "objects": ["build/src/ov_SC04_018/ov_SC04_018_jr_80188E1C.o", "build/src/ov_SC04_019/ov_SC04_019_jr_80188E1C.o"], "before_text": "void func_8018A2E0(u16 *a0, s32 a1)\n{\n register s32 zr __asm__(\"$0\"); // !FAKE: pin $0 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n u16 pad0[16]; /* dead: locals begin at sp+0x30, va must land at sp+0x50 */\n u16 va[16]; /* sp+0x50 \u2014 outer quad, 4 x SVECTOR */\n u16 vb[16]; /* sp+0x70 \u2014 inner quad, 4 x SVECTOR */\n s32 sxy[8]; /* sp+0x90 \u2014 [0..3] RotNclip4, [4..7] RotTransPers4 */\n s16 idx[4]; /* sp+0xB0 */\n s32 p; /* sp+0xB8 */\n s32 otz; /* sp+0xBC */\n s32 flag; /* sp+0xC0 */\n\n u16 attr;\n s32 type;\n s32 type2;\n u16 *p1;\n u16 *p2;\n register u16 *dst __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 i;\n u8 *pk;\n s32 j;\n\n func_8012E32C();\n\n attr = a0[3];\n type = attr & 0xFF;\n type2 = type + zr;\n if ((attr & 0xF00) == 0x200) {\n func_8018A6C8(a0, a1);\n return;\n }\n\n p1 = (u16 *)((u8 *)D_801E00B0 + type * 0x20);\n i = 0;\n p2 = p1 + 2;\n dst = va;\n while (i < 4) {\n dst[0] = a0[0] + p1[0];\n dst[1] = a0[1] + p2[-1];\n dst[2] = a0[2] + p2[0];\n i++;\n p1 += 4;\n p2 += 4;\n dst += 4;\n }\n\n if (RotNclip4((s32)&va[0], (s32)&va[4], (s32)&va[8], (s32)&va[12],\n &sxy[0], &sxy[1], &sxy[2], &sxy[3], &p, &otz, &flag) <= 0) {\n return;\n }\n\n otz -= 0x10;\n if (otz < 0) {\n return;\n }\n if (otz >= 0x1000) {\n return;\n }\n\n p1 = (u16 *)((u8 *)D_801E0130 + type2 * 0x20);\n i = 0;\n p2 = p1 + 2;\n dst = vb;\n while (i < 4) {\n dst[0] = a0[0] + p1[0];\n dst[1] = a0[1] + p2[-1];\n dst[2] = a0[2] + p2[0];\n i++;\n p1 += 4;\n p2 += 4;\n dst += 4;\n }\n\n RotTransPers4((s32)&vb[0], (s32)&vb[4], (s32)&vb[8], (s32)&vb[12],\n &sxy[4], &sxy[5], &sxy[6], &sxy[7], &p, &flag);\n\n pk = func_80010A08(0xA8);\n\n for (j = 0; j < 4; j++) {\n idx[0] = D_801E01D0[j][0];\n idx[1] = D_801E01D2[j][0];\n idx[2] = D_801E01D4[j][0];\n idx[3] = D_801E01D6[j][0];\n *(s32 *)(pk + 0x4) = a1 & -(idx[0] < 4);\n *(s32 *)(pk + 0xC) = a1 & -(idx[1] < 4);\n *(s32 *)(pk + 0x14) = a1 & -(idx[2] < 4);\n *(s32 *)(pk + 0x1C) = a1 & -(idx[3] < 4);\n pk[7] = 0x3A;\n *(u32 *)(pk + 0x0) = 0x08000000;\n *(s32 *)(pk + 0x8) = sxy[idx[0]];\n *(s32 *)(pk + 0x10) = sxy[idx[1]];\n *(s32 *)(pk + 0x18) = sxy[idx[2]];\n *(s32 *)(pk + 0x20) = sxy[idx[3]];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n pk += 0x24;\n }\n\n *(s32 *)(pk + 0x4) = a1;\n pk[7] = 0x2A;\n *(u32 *)(pk + 0x0) = 0x05000000;\n *(s32 *)(pk + 0x8) = sxy[0];\n *(s32 *)(pk + 0xC) = sxy[1];\n *(s32 *)(pk + 0x10) = sxy[2];\n *(s32 *)(pk + 0x14) = sxy[3];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n func_8012E28C(otz, 1);\n}\n", "after_text": "void func_8018A2E0(u16 *a0, s32 a1)\n{\n\n u16 pad0[16]; /* dead: locals begin at sp+0x30, va must land at sp+0x50 */\n SVECTOR va[4]; /* sp+0x50 \u2014 outer quad, 4 x SVECTOR */\n SVECTOR vb[4]; /* sp+0x70 \u2014 inner quad, 4 x SVECTOR */\n s32 sxy[8]; /* sp+0x90 \u2014 [0..3] RotNclip4, [4..7] RotTransPers4 */\n s16 idx[4]; /* sp+0xB0 */\n s32 p; /* sp+0xB8 */\n s32 otz; /* sp+0xBC */\n s32 flag; /* sp+0xC0 */\n\n u16 attr;\n s32 type;\n u8 type2;\n u16 *p1;\n u16 *p2;\n s32 i;\n u8 *pk;\n s32 j;\n\n func_8012E32C();\n\n attr = a0[3];\n type = attr & 0xFF;\n type2 = type;\n if ((attr & 0xF00) == 0x200) {\n func_8018A6C8(a0, a1);\n return;\n }\n\n p1 = (u16 *)((u8 *)D_801E00B0 + type * 0x20);\n for (i = 0; i < 4; i++, p1 += 4) {\n va[i].vx = a0[0] + p1[0];\n va[i].vy = a0[1] + p1[1];\n va[i].vz = a0[2] + p1[2];\n }\n\n if (RotNclip4((s32)&va[0], (s32)&va[1], (s32)&va[2], (s32)&va[3],\n &sxy[0], &sxy[1], &sxy[2], &sxy[3], &p, &otz, &flag) <= 0) {\n return;\n }\n\n otz -= 0x10;\n if (otz < 0) {\n return;\n }\n if (otz >= 0x1000) {\n return;\n }\n\n p2 = (u16 *)((u8 *)D_801E0130 + type2 * 0x20);\n for (i = 0; i < 4; i++, p2 += 4) {\n vb[i].vx = a0[0] + p2[0];\n vb[i].vy = a0[1] + p2[1];\n vb[i].vz = a0[2] + p2[2];\n }\n\n RotTransPers4((s32)&vb[0], (s32)&vb[1], (s32)&vb[2], (s32)&vb[3],\n &sxy[4], &sxy[5], &sxy[6], &sxy[7], &p, &flag);\n\n pk = func_80010A08(0xA8);\n\n for (j = 0; j < 4; j++) {\n idx[0] = D_801E01D0[j][0];\n idx[1] = D_801E01D2[j][0];\n idx[2] = D_801E01D4[j][0];\n idx[3] = D_801E01D6[j][0];\n *(s32 *)(pk + 0x4) = a1 & -(idx[0] < 4);\n *(s32 *)(pk + 0xC) = a1 & -(idx[1] < 4);\n *(s32 *)(pk + 0x14) = a1 & -(idx[2] < 4);\n *(s32 *)(pk + 0x1C) = a1 & -(idx[3] < 4);\n pk[7] = 0x3A;\n *(u32 *)(pk + 0x0) = 0x08000000;\n *(s32 *)(pk + 0x8) = sxy[idx[0]];\n *(s32 *)(pk + 0x10) = sxy[idx[1]];\n *(s32 *)(pk + 0x18) = sxy[idx[2]];\n *(s32 *)(pk + 0x20) = sxy[idx[3]];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n pk += 0x24;\n }\n\n *(s32 *)(pk + 0x4) = a1;\n pk[7] = 0x2A;\n *(u32 *)(pk + 0x0) = 0x05000000;\n *(s32 *)(pk + 0x8) = sxy[0];\n *(s32 *)(pk + 0xC) = sxy[1];\n *(s32 *)(pk + 0x10) = sxy[2];\n *(s32 *)(pk + 0x14) = sxy[3];\n AddPrim(D_800A651C[(u16)D_800B9A02][0] + (otz * 4), pk);\n func_8012E28C(otz, 1);\n}\n"} +{"ts": "2026-09-10 22:37:05", "label": "s104_d17", "rung": "E", "calib": {"head": "c48582300", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c", "fn": "func_80181DAC", "addr": 2149064108, "aliases": null, "header": false, "includers": 0, "nhash_before": "0fc96ee1701a3a68937d5589ded519b19e134182", "nhash_after": "bc931d465f3a7f55790e8bc6e16b6615e7c04a7b", "source": ".run/P36/agents/ov_SC04_004__func_80181DAC/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.28, "objects": ["build/src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.o"], "before_text": "s32 func_80181DAC(s32 arg0) {\n extern u8 D_801202A0[];\n register s32 zr __asm__(\"$0\"); // !FAKE: pin $0 \u2014 NEEDED DIFFERS (P36 rung B tus7)\n u8 *pe;\n u8 *ps;\n s16 *ca;\n s16 *cb;\n u16 state;\n u16 t;\n s32 count;\n\n pe = D_801202A0;\n count = 0;\n ps = pe + 4;\n do {\n if ((s32)pe == arg0) {\n goto next;\n }\n state = *(u16 *)pe;\n ca = (s16 *)((s32)arg0 + zr);\n if (state == 0x1FC) {\n goto b1fc;\n }\n cb = (s16 *)((s32)ps + zr);\n if (state == 0x239) {\n goto b239;\n }\n goto next;\n\n b1fc:\n cb = (s16 *)((s32)ps + zr);\n t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9;\n goto call;\n\n b239:\n t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(ps + 0x1C) + 0x18)) >> 6;\n /* fall through */\n call:\n if (func_80181E90(ca, cb, t) == 0) {\n goto next;\n }\n __asm__ __volatile__(\"\" :: \"r\"(pe)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus7)\n return (s32)pe;\n\n next:\n count++;\n ps += 0x10C;\n pe += 0x10C;\n } while (count < 0x60);\n return 0;\n}\n", "after_text": "s32 func_80181DAC(s32 arg0) {\n extern u8 D_801202A0[];\n u8 *pe;\n u16 t;\n s32 count;\n\n pe = D_801202A0;\n for (count = 0; count < 0x60; count++, pe += 0x10C) {\n if ((s32)pe == arg0) {\n continue;\n }\n switch (*(u16 *)pe) {\n case 0x1FC:\n t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9;\n if (func_80181E90((s16 *)arg0, (s16 *)(pe + 4), t) != 0) {\n return (s32)pe;\n }\n break;\n case 0x239:\n t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(pe + 0x20) + 0x18)) >> 6;\n if (func_80181E90((s16 *)arg0, (s16 *)(pe + 4), t) != 0) {\n return (s32)pe;\n }\n break;\n }\n }\n return 0;\n}\n"} +{"ts": "2026-09-10 22:37:22", "label": "s104_d17", "rung": "E", "calib": {"head": "c48582300", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c", "fn": "func_80183820", "addr": 2149070880, "aliases": null, "header": false, "includers": 0, "nhash_before": "0fc96ee1701a3a68937d5589ded519b19e134182", "nhash_after": "bc931d465f3a7f55790e8bc6e16b6615e7c04a7b", "source": "propagate:src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c:func_80181DAC", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.471, "objects": ["build/src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.o"], "before_text": "s32 func_80183820(s32 arg0) {\n extern u8 D_801202A0[];\n register s32 zr __asm__(\"$0\"); // !FAKE: pin $0 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n u8 *pe;\n u8 *ps;\n s16 *ca;\n s16 *cb;\n u16 state;\n u16 t;\n s32 count;\n\n pe = D_801202A0;\n count = 0;\n ps = pe + 4;\n do {\n if ((s32)pe == arg0) {\n goto next;\n }\n state = *(u16 *)pe;\n ca = (s16 *)((s32)arg0 + zr);\n if (state == 0x1FC) {\n goto b1fc;\n }\n cb = (s16 *)((s32)ps + zr);\n if (state == 0x239) {\n goto b239;\n }\n goto next;\n\n b1fc:\n cb = (s16 *)((s32)ps + zr);\n t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9;\n goto call;\n\n b239:\n t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(ps + 0x1C) + 0x18)) >> 6;\n /* fall through */\n call:\n if (func_80183904(ca, cb, t) == 0) {\n goto next;\n }\n __asm__ __volatile__(\"\" :: \"r\"(pe)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus8)\n return (s32)pe;\n\n next:\n count++;\n ps += 0x10C;\n pe += 0x10C;\n } while (count < 0x60);\n return 0;\n}\n", "after_text": "s32 func_80183820(s32 arg0) {\n extern u8 D_801202A0[];\n u8 *pe;\n u16 t;\n s32 count;\n\n pe = D_801202A0;\n for (count = 0; count < 0x60; count++, pe += 0x10C) {\n if ((s32)pe == arg0) {\n continue;\n }\n switch (*(u16 *)pe) {\n case 0x1FC:\n t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9;\n if (func_80183904((s16 *)arg0, (s16 *)(pe + 4), t) != 0) {\n return (s32)pe;\n }\n break;\n case 0x239:\n t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(pe + 0x20) + 0x18)) >> 6;\n if (func_80183904((s16 *)arg0, (s16 *)(pe + 4), t) != 0) {\n return (s32)pe;\n }\n break;\n }\n }\n return 0;\n}\n"} +{"ts": "2026-09-10 22:37:24", "label": "s104_d17", "rung": "E", "calib": {"head": "c48582300", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c", "fn": "func_801872E0", "addr": 2149085920, "aliases": null, "header": false, "includers": 0, "nhash_before": "0fc96ee1701a3a68937d5589ded519b19e134182", "nhash_after": "bc931d465f3a7f55790e8bc6e16b6615e7c04a7b", "source": "propagate:src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c:func_80181DAC", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.473, "objects": ["build/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.o"], "before_text": "s32 func_801872E0(s32 arg0) {\n extern u8 D_801202A0[];\n register s32 zr __asm__(\"$0\"); // !FAKE: pin $0 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n u8 *pe;\n u8 *ps;\n s16 *ca;\n s16 *cb;\n u16 state;\n u16 t;\n s32 count;\n\n pe = D_801202A0;\n count = 0;\n ps = pe + 4;\n do {\n if ((s32)pe == arg0) {\n goto next;\n }\n state = *(u16 *)pe;\n ca = (s16 *)((s32)arg0 + zr);\n if (state == 0x1FC) {\n goto b1fc;\n }\n cb = (s16 *)((s32)ps + zr);\n if (state == 0x239) {\n goto b239;\n }\n goto next;\n\n b1fc:\n cb = (s16 *)((s32)ps + zr);\n t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9;\n goto call;\n\n b239:\n t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(ps + 0x1C) + 0x18)) >> 6;\n /* fall through */\n call:\n if (func_801873C4(ca, cb, t) == 0) {\n goto next;\n }\n __asm__ __volatile__(\"\" :: \"r\"(pe)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus8)\n return (s32)pe;\n\n next:\n count++;\n ps += 0x10C;\n pe += 0x10C;\n } while (count < 0x60);\n return 0;\n}\n", "after_text": "s32 func_801872E0(s32 arg0) {\n extern u8 D_801202A0[];\n u8 *pe;\n u16 t;\n s32 count;\n\n pe = D_801202A0;\n for (count = 0; count < 0x60; count++, pe += 0x10C) {\n if ((s32)pe == arg0) {\n continue;\n }\n switch (*(u16 *)pe) {\n case 0x1FC:\n t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9;\n if (func_801873C4((s16 *)arg0, (s16 *)(pe + 4), t) != 0) {\n return (s32)pe;\n }\n break;\n case 0x239:\n t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(pe + 0x20) + 0x18)) >> 6;\n if (func_801873C4((s16 *)arg0, (s16 *)(pe + 4), t) != 0) {\n return (s32)pe;\n }\n break;\n }\n }\n return 0;\n}\n"} diff --git a/src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c b/src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c index 823f3f580..83b401e94 100644 --- a/src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c +++ b/src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c @@ -7772,53 +7772,30 @@ extern s32 func_80183904(s16 *a0, s16 *a1, s32 a2); s32 func_80183820(s32 arg0) { extern u8 D_801202A0[]; - register s32 zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus8) u8 *pe; - u8 *ps; - s16 *ca; - s16 *cb; - u16 state; u16 t; s32 count; pe = D_801202A0; - count = 0; - ps = pe + 4; - do { + for (count = 0; count < 0x60; count++, pe += 0x10C) { if ((s32)pe == arg0) { - goto next; + continue; } - state = *(u16 *)pe; - ca = (s16 *)((s32)arg0 + zr); - if (state == 0x1FC) { - goto b1fc; + switch (*(u16 *)pe) { + case 0x1FC: + t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9; + if (func_80183904((s16 *)arg0, (s16 *)(pe + 4), t) != 0) { + return (s32)pe; + } + break; + case 0x239: + t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(pe + 0x20) + 0x18)) >> 6; + if (func_80183904((s16 *)arg0, (s16 *)(pe + 4), t) != 0) { + return (s32)pe; + } + break; } - cb = (s16 *)((s32)ps + zr); - if (state == 0x239) { - goto b239; - } - goto next; - - b1fc: - cb = (s16 *)((s32)ps + zr); - t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9; - goto call; - - b239: - t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(ps + 0x1C) + 0x18)) >> 6; - /* fall through */ - call: - if (func_80183904(ca, cb, t) == 0) { - goto next; - } - __asm__ __volatile__("" :: "r"(pe)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus8) - return (s32)pe; - - next: - count++; - ps += 0x10C; - pe += 0x10C; - } while (count < 0x60); + } return 0; } diff --git a/src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c b/src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c index ea597d305..b16b50b06 100644 --- a/src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c +++ b/src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c @@ -6968,53 +6968,30 @@ extern s32 func_80181E90(); s32 func_80181DAC(s32 arg0) { extern u8 D_801202A0[]; - register s32 zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus7) u8 *pe; - u8 *ps; - s16 *ca; - s16 *cb; - u16 state; u16 t; s32 count; pe = D_801202A0; - count = 0; - ps = pe + 4; - do { + for (count = 0; count < 0x60; count++, pe += 0x10C) { if ((s32)pe == arg0) { - goto next; + continue; } - state = *(u16 *)pe; - ca = (s16 *)((s32)arg0 + zr); - if (state == 0x1FC) { - goto b1fc; + switch (*(u16 *)pe) { + case 0x1FC: + t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9; + if (func_80181E90((s16 *)arg0, (s16 *)(pe + 4), t) != 0) { + return (s32)pe; + } + break; + case 0x239: + t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(pe + 0x20) + 0x18)) >> 6; + if (func_80181E90((s16 *)arg0, (s16 *)(pe + 4), t) != 0) { + return (s32)pe; + } + break; } - cb = (s16 *)((s32)ps + zr); - if (state == 0x239) { - goto b239; - } - goto next; - - b1fc: - cb = (s16 *)((s32)ps + zr); - t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9; - goto call; - - b239: - t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(ps + 0x1C) + 0x18)) >> 6; - /* fall through */ - call: - if (func_80181E90(ca, cb, t) == 0) { - goto next; - } - __asm__ __volatile__("" :: "r"(pe)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus7) - return (s32)pe; - - next: - count++; - ps += 0x10C; - pe += 0x10C; - } while (count < 0x60); + } return 0; } diff --git a/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c b/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c index 11baf73aa..483841418 100644 --- a/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c +++ b/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c @@ -10161,53 +10161,30 @@ extern s32 func_801873C4(s16 *a0, s16 *a1, s32 a2); s32 func_801872E0(s32 arg0) { extern u8 D_801202A0[]; - register s32 zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus8) u8 *pe; - u8 *ps; - s16 *ca; - s16 *cb; - u16 state; u16 t; s32 count; pe = D_801202A0; - count = 0; - ps = pe + 4; - do { + for (count = 0; count < 0x60; count++, pe += 0x10C) { if ((s32)pe == arg0) { - goto next; + continue; } - state = *(u16 *)pe; - ca = (s16 *)((s32)arg0 + zr); - if (state == 0x1FC) { - goto b1fc; + switch (*(u16 *)pe) { + case 0x1FC: + t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9; + if (func_801873C4((s16 *)arg0, (s16 *)(pe + 4), t) != 0) { + return (s32)pe; + } + break; + case 0x239: + t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(pe + 0x20) + 0x18)) >> 6; + if (func_801873C4((s16 *)arg0, (s16 *)(pe + 4), t) != 0) { + return (s32)pe; + } + break; } - cb = (s16 *)((s32)ps + zr); - if (state == 0x239) { - goto b239; - } - goto next; - - b1fc: - cb = (s16 *)((s32)ps + zr); - t = (*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) * 9u) >> 9; - goto call; - - b239: - t = (u32)(*(s16 *)(*(s32 *)(arg0 + 0x20) + 0x18) + *(s16 *)(*(s32 *)(ps + 0x1C) + 0x18)) >> 6; - /* fall through */ - call: - if (func_801873C4(ca, cb, t) == 0) { - goto next; - } - __asm__ __volatile__("" :: "r"(pe)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus8) - return (s32)pe; - - next: - count++; - ps += 0x10C; - pe += 0x10C; - } while (count < 0x60); + } return 0; }