diff --git a/phase-ends/CURRENT_PHASE.md b/phase-ends/CURRENT_PHASE.md
index 56764f42c1..76238344c1 100644
--- a/phase-ends/CURRENT_PHASE.md
+++ b/phase-ends/CURRENT_PHASE.md
@@ -42,7 +42,7 @@ Two further roadmap premises are stale (verified): the **parallel gate farm alre
   - Bounded ~8 members, byte-gated, R22-clean. **Either outcome is the deliverable.** Correct `calibration.md` + `decision-log.md` (R31) in-session (R30).
 - [x] **T2 — Purge the poisoned grinder blacklist** · xHigh · ✅ purged (8 of 22 had MATCHED anyway)
   - 22 permanent never-retry entries built from a known-broken gate (`tooling-audit.md:927-931`: 16/22 never compiled, 5 absent); `worklist.md:50,56` marks two of them **"none — MATCH"**. Purge; fix `harvest_verify`'s `--src`/`--asm-subdir` split coupling that poisoned it; re-derive only from the fixed gate.
-- [ ] **T3 — The stratified templatability re-probe: THE swing number** · Max · 🚩 **milestone report to Drew** · blocked by T0,T1
+- [~] **T3 — The stratified templatability re-probe: THE swing number** · Max · 🚩 **stratum A done — 0 DIFF; the pool is h_exact + UNWIRED.** Strata B/C (legacy) carried → T3b
   - Strata: **PURE non-jr** (96 fam / 7,148 members) · **IMM** (35 fam, `imm_map_tier1`) · **MIXED** (30 fam). ~8–12 members/class, byte-gated, R22-clean.
   - **Classify every failure** (`harvest_verify.classify_fail` → DIFF/PLUMBING/CC1-FAIL/SKIP) — the distinction Phase 26 never recorded.
   - **Do not score with `masked_diff`** — `mask_for` drops HI16/LO16 (`:92-124`), blind to this delta class (would score all 112 `0x8017BEBC` members a perfect 0). The gate decides.
@@ -119,5 +119,33 @@ Whole-binary byte-gate = sole arbiter (G3/P9) · R22 clean-fleet per banked batc
   - **The proof the verdict was manufactured, not observed:** of the 22 entries — recorded as "permuter won, gate rejected ⇒ plumbing-bound, never re-permute" — **8 have since MATCHED anyway** (`func_80131D68/80149374/8014FE60/80150528/8016BBE0/80171C64/80174684/8017F290`); the other **14 are still stubs** and would have been skipped **forever** on a verdict from a gate that no longer exists. (The audit predicted 5 such; it is 8.)
   - **Done:** blacklist → `[]` (poisoned copy kept at `.run/auto/grinder_blacklist.json.poisoned-pre-T2`); `grinder.py` carries the **rule** (R35): *a blacklist entry is a verdict from a specific gate and EXPIRES when that gate changes — purge and re-derive; never inherit.* No `harvest_verify` change was needed or made.
 
+- **2026-07-15 — T3 stratum A 🚩 — ZERO DIFF. The SC07 pool is the EASY (h_exact) class, and it is simply UNWIRED.**
+  - **The probe (cleanest available):** the 4 SC07-only families of highest byte-weight are **the giants** — `0x80144B9C` (770, the whale), `0x80141CA4` (476), `0x80132784` (400, "irreducible for 22 phases"), `0x80133CD4` (399, the §45 Fable5 crack). Exemplars already byte-proven, members PURE, non-jr → **every confound removed; a failure here is pure mechanism.** `family_sweep --hseq --band substantial --chunk 1`.
+  - **Result: 4 banked / 8 failed / 4 skipped of 16 — and the classification is the finding:**
+
+    | verdict | fns | n |
+    |---|---|---|
+    | **BANKED** | `func_80133CD4` — a 399-ins Fable5 giant → **4/4 overlays, free** | 4 |
+    | **PLUMBING** `parse error before ')'` | `func_80144B9C`, `func_80132784` | 8 |
+    | skipped `pinned-exemplar` (the §42e guard — P27's T5 dissolved the wall behind it; `--allow-pins` bypasses) | `func_80141CA4` | 4 |
+    | **DIFF (real codegen)** | — | **0** |
+
+    **Not one failure is a byte mismatch.** Of the members that reached the gate as valid C: **4/4 = 100%**. The 8 never compiled. *This is the DIFF-vs-CC1-FAIL distinction Phase 26 never recorded — and precisely why its 0% could not be trusted.*
+  - **🔑 ROOT CAUSE (byte-verified, and far bigger than the parse error): the 4 new overlays were onboarded but NEVER WIRED INTO THE SHARED-BODY ECOSYSTEM.**
+
+    | | established (`ov_SC01_001`) | the 4 new SC07 |
+    |---|---|---|
+    | includes | `common.h` + **`../shared/engine_core.h`** | `common.h` **only** |
+    | body | `DEFINE_func_*()` instantiations | **~2,400 raw `INCLUDE_ASM` stubs** |
+    | matched | ~2,150 | ~80 |
+    | refs in `config/dedup.us.yaml` | member of 1,689 groups | **0** |
+
+    The parse error is a *symptom*: the drafts reference types (`P10/P14/P18/P1C/HDR/ENT`) that live in `src/shared/func_80144B9C.h` — a header the SC07 TU doesn't include. **1,689 registry groups say "134 binaries", never 138.**
+  - **📐 SCALE (measured against the registry): 6,513 live stubs across the 4 new overlays are byte-identical to an ALREADY-REGISTERED h_exact group** (1,625 / 1,628 / 1,627 / 1,633). That is the **h_exact** class — which `calibration.md` itself rates **≈×N, near-100%** — not the h_seq class, and **not** a `member_adapt` problem.
+  - **✅ MECHANISM PROVEN BY HAND (probe-before-investing):** added `#include "../shared/engine_core.h"` + swapped ONE stub → `DEFINE_func_80128158()` in `ov_SC07_006.c` → `make build BINARY=ov_SC07_006` → **`7ca772be…` BYTE-IDENTICAL**. Probe reverted; let the tool do it uniformly.
+  - **The gap in the tooling:** `dedup_propagate --auto-from` only plans **11** fns here — it authors macros from ov_SC01_077's *inline defs*; the ~1,600 shared bodies are **already** `DEFINE_func_*` macros in `engine_core.h`, and `--addr` errors *"no source overlay has it matched"* because no overlay holds an inline def. **There is no mode for "extend an existing macro-backed group to a newly-onboarded binary."** → T4.
+  - **R22: `make clean` + extract-all + `check-all` → 140/140**, 0 FAIL (stratum A's 4 banks).
+  - **Carried → T3b:** strata **B** (legacy PURE non-jr, 95 fam / 7,993 members) and **C** (legacy IMM, 36 fam / 6,644) — the *legacy* h_seq rate, still genuinely unmeasured. The SC07 pool answered a different (and cheaper) question than the one T3 set out to ask.
+
   - **T3 strata (honest, from the fixed map):** SC07-only **1,255 fam / 6,268 mem / 230,612 ins** · legacy PURE non-jr **95 / 7,993 / 478,379** · legacy IMM **36 / 6,644 / 212,707** · legacy MIXED **30 / 968 / 10,462** · legacy PURE w/ jr **2 / 16 / 5,088** (T1's jtbl territory — note B2's family is far smaller here than the roadmap's "×112 ≈ 106k ins"; T1 re-derives it). **Total addressable = 937,248 ins = 21.7% of all remaining weight = 7.16pp of fleet instr if it all banked.** This is the prize the roadmap declared dead. It stays a prediction until T3's gate.
 </content>
diff --git a/src/ov_SC07_006/ov_SC07_006.c b/src/ov_SC07_006/ov_SC07_006.c
index f8e0302479..3388e9d17f 100644
--- a/src/ov_SC07_006/ov_SC07_006.c
+++ b/src/ov_SC07_006/ov_SC07_006.c
@@ -631,7 +631,175 @@ INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006", func_80133784);
 
 INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006", func_80133AB0);
 
-INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006", func_80133CD4);
+
+s32 func_80133CD4(arg0, cmd, base, arr)
+    s16 arg0;
+    s16 *cmd;
+    s16 *base;
+    s32 *arr;
+{
+    typedef struct { s16 e[4]; } ElemK;
+
+    extern u16 *D_8018A9A0;
+    extern u16 *D_8018A99C;
+    extern s16 *D_8018A9A8;
+    extern s16 *D_8018A9A4;
+    extern s32 *D_8018A9B0;
+    extern s32 *D_8018A9B4;
+    extern u16 D_801F4DD8;
+    extern u8  D_801152A8[];
+    extern s16 D_801152AA;
+    extern s16 D_801152AC;
+    extern u16 D_801152AE;
+    extern u8  D_801152B0;
+    extern s32 func_80134310();
+    extern s32 func_8013435C();
+
+    s16 *s3 = ((ElemK *)base)[cmd[1]].e;
+    s32 s6 = arr[cmd[2]];
+    s32 s0var, s1var;
+    s32 s2a;
+    s16 y;
+
+    if (func_80134310(s3, D_8018A9A0, s6) >= 0)
+        return 0;
+
+    s1var = func_80134310(s3, D_8018A99C, s6);
+    if (s1var < 0)
+        return 0;
+
+    s0var = func_80134310(s3, D_8018A9A8, 0);
+    {
+        u16 *pac = D_8018A99C;
+        s16 *pb8 = D_8018A9A8;
+        s16 *pb4 = D_8018A9A4;
+        s32 neg = -s1var;
+        pb4[0] = pac[0] + neg * pb8[0] / s0var;
+        pb4[1] = pac[1] + neg * pb8[1] / s0var;
+        pb4[2] = pac[2] + neg * pb8[2] / s0var;
+        if (func_8013435C(((ElemK *)base)[cmd[3]].e, pb4, arr[cmd[4]], s3))
+            return 0;
+    }
+    if (func_8013435C(((ElemK *)base)[cmd[5]].e, D_8018A9A4, arr[cmd[6]], s3))
+        return 0;
+    if (func_8013435C(((ElemK *)base)[cmd[7]].e, D_8018A9A4, arr[cmd[8]], s3))
+        return 0;
+    if (arg0 < 0) {
+        if (func_8013435C(((ElemK *)base)[cmd[9]].e, D_8018A9A4, arr[cmd[10]], s3))
+            return 0;
+    }
+    if (arg0 & 0x10) {
+        if (*(u16 *)cmd & 0x100)
+            return 0;
+    }
+    if (*(u16 *)cmd & 0x200) {
+        D_801F4DD8 = *(u16 *)cmd;
+        return 0;
+    }
+
+    {
+        s32 ret = func_80134310(s3, D_8018A9A0, s6);
+        s32 *pc0;
+        s32 *pc4;
+        u16 *pb0;
+        s32 t, o2;
+        s32 q3v;
+
+        {
+            s32 *pw = D_8018A9B0;
+            ((struct { s32 w; } *)pw)->w = s3[0];
+            pw[1] = s3[1];
+            pw[2] = s3[2];
+        }
+        s1var = -ret;
+
+        __asm__ __volatile__(
+            "lwc2 $9, 0(%0)\n"
+            "lwc2 $10, 4(%0)\n"
+            "lwc2 $11, 8(%0)\n"
+            "nop\n"
+            "nop\n"
+            "sqr 0\n"
+            : : "r"(D_8018A9B0) : "$9", "$10", "$11", "memory");
+        __asm__ __volatile__(
+            "swc2 $25, 0(%0)\n"
+            "swc2 $26, 4(%0)\n"
+            "swc2 $27, 8(%0)\n"
+            : : "r"(D_8018A9B4) : "memory");
+
+        pc0 = D_8018A9B0;
+        pc4 = D_8018A9B4;
+        s0var = pc4[0] + pc4[1] + pc4[2];
+        pb0 = D_8018A9A0;
+        pb0[0] += s1var * pc0[0] / s0var;
+        pb0[1] += s1var * pc0[1] / s0var;
+        q3v = s1var * pc0[2] / s0var;
+
+        {
+            s32 h;
+            h = ((s16 *)pb0)[0];
+            s1var = h << 16;
+            __asm__("lh %0, 2(%2)" : "=r"(h) : "0"(h), "r"(pb0) : "memory");
+            s0var = h << 16;
+        }
+        pb0[2] += q3v;
+        s2a = (s16)pb0[2] << 16;
+
+        t = pc0[0] << 4;
+        pc0[0] = t;
+        if (t < 0) s1var |= 0xFFFF;
+        t = pc0[1] << 4;
+        pc0[1] = t;
+        if (t < 0) s0var |= 0xFFFF;
+        o2 = pc0[2];
+        t = o2 << 4;
+        pc0[2] = t;
+        if (t < 0) s2a |= 0xFFFF;
+        s2a += o2 << 5;
+        s1var += pc0[0] << 1;
+        s0var += pc0[1] << 1;
+
+        do {
+            s32 *pl = D_8018A9B0;
+            u16 *pb;
+            s1var += pl[0];
+            s0var += pl[1];
+            s2a += pl[2];
+            pb = D_8018A9A0;
+            pb[0] = s1var >> 16;
+            pb[1] = s0var >> 16;
+            pb[2] = s2a >> 16;
+            ret = func_80134310(s3, pb, s6);
+        } while (ret < ((s3[1] < -0xE00) ? 0x1800 : 0x2F00));
+    }
+
+    y = s3[1];
+    if (y >= -0xBCB) {
+        D_8018A99C[3] = y;
+        {
+            typedef struct { s8 c[8]; } Blk8;
+            *(Blk8 *)&D_801152B0 = *(Blk8 *)s3;
+        }
+        if (*(u8 *)cmd != 0)
+            goto ret1;
+        return -1;
+    }
+    {
+        typedef struct { u16 h; } H16;
+        u16 *s3u = (u16 *)s3;
+        u16 *bp = D_8018A9A0;
+        u16 w;
+        ((H16 *)D_801152A8)->h = s3u[0];
+        w = s3u[1];
+        bp[3] = w;
+        ((H16 *)&D_801152AA)->h = w;
+        ((H16 *)&D_801152AC)->h = s3u[2];
+        ((H16 *)&D_801152AE)->h = s3u[3];
+    }
+ret1:
+    return 1;
+}
+
 
 INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006", func_80134310);
 
diff --git a/src/ov_SC07_007/ov_SC07_007.c b/src/ov_SC07_007/ov_SC07_007.c
index 7c1db1eaf8..ed7732c2d3 100644
--- a/src/ov_SC07_007/ov_SC07_007.c
+++ b/src/ov_SC07_007/ov_SC07_007.c
@@ -631,7 +631,175 @@ INCLUDE_ASM("asm/ov_SC07_007/nonmatchings/ov_SC07_007", func_80133784);
 
 INCLUDE_ASM("asm/ov_SC07_007/nonmatchings/ov_SC07_007", func_80133AB0);
 
-INCLUDE_ASM("asm/ov_SC07_007/nonmatchings/ov_SC07_007", func_80133CD4);
+
+s32 func_80133CD4(arg0, cmd, base, arr)
+    s16 arg0;
+    s16 *cmd;
+    s16 *base;
+    s32 *arr;
+{
+    typedef struct { s16 e[4]; } ElemK;
+
+    extern u16 *D_801834C4;
+    extern u16 *D_801834C0;
+    extern s16 *D_801834CC;
+    extern s16 *D_801834C8;
+    extern s32 *D_801834D4;
+    extern s32 *D_801834D8;
+    extern u16 D_801C6540;
+    extern u8  D_801152A8[];
+    extern s16 D_801152AA;
+    extern s16 D_801152AC;
+    extern u16 D_801152AE;
+    extern u8  D_801152B0;
+    extern s32 func_80134310();
+    extern s32 func_8013435C();
+
+    s16 *s3 = ((ElemK *)base)[cmd[1]].e;
+    s32 s6 = arr[cmd[2]];
+    s32 s0var, s1var;
+    s32 s2a;
+    s16 y;
+
+    if (func_80134310(s3, D_801834C4, s6) >= 0)
+        return 0;
+
+    s1var = func_80134310(s3, D_801834C0, s6);
+    if (s1var < 0)
+        return 0;
+
+    s0var = func_80134310(s3, D_801834CC, 0);
+    {
+        u16 *pac = D_801834C0;
+        s16 *pb8 = D_801834CC;
+        s16 *pb4 = D_801834C8;
+        s32 neg = -s1var;
+        pb4[0] = pac[0] + neg * pb8[0] / s0var;
+        pb4[1] = pac[1] + neg * pb8[1] / s0var;
+        pb4[2] = pac[2] + neg * pb8[2] / s0var;
+        if (func_8013435C(((ElemK *)base)[cmd[3]].e, pb4, arr[cmd[4]], s3))
+            return 0;
+    }
+    if (func_8013435C(((ElemK *)base)[cmd[5]].e, D_801834C8, arr[cmd[6]], s3))
+        return 0;
+    if (func_8013435C(((ElemK *)base)[cmd[7]].e, D_801834C8, arr[cmd[8]], s3))
+        return 0;
+    if (arg0 < 0) {
+        if (func_8013435C(((ElemK *)base)[cmd[9]].e, D_801834C8, arr[cmd[10]], s3))
+            return 0;
+    }
+    if (arg0 & 0x10) {
+        if (*(u16 *)cmd & 0x100)
+            return 0;
+    }
+    if (*(u16 *)cmd & 0x200) {
+        D_801C6540 = *(u16 *)cmd;
+        return 0;
+    }
+
+    {
+        s32 ret = func_80134310(s3, D_801834C4, s6);
+        s32 *pc0;
+        s32 *pc4;
+        u16 *pb0;
+        s32 t, o2;
+        s32 q3v;
+
+        {
+            s32 *pw = D_801834D4;
+            ((struct { s32 w; } *)pw)->w = s3[0];
+            pw[1] = s3[1];
+            pw[2] = s3[2];
+        }
+        s1var = -ret;
+
+        __asm__ __volatile__(
+            "lwc2 $9, 0(%0)\n"
+            "lwc2 $10, 4(%0)\n"
+            "lwc2 $11, 8(%0)\n"
+            "nop\n"
+            "nop\n"
+            "sqr 0\n"
+            : : "r"(D_801834D4) : "$9", "$10", "$11", "memory");
+        __asm__ __volatile__(
+            "swc2 $25, 0(%0)\n"
+            "swc2 $26, 4(%0)\n"
+            "swc2 $27, 8(%0)\n"
+            : : "r"(D_801834D8) : "memory");
+
+        pc0 = D_801834D4;
+        pc4 = D_801834D8;
+        s0var = pc4[0] + pc4[1] + pc4[2];
+        pb0 = D_801834C4;
+        pb0[0] += s1var * pc0[0] / s0var;
+        pb0[1] += s1var * pc0[1] / s0var;
+        q3v = s1var * pc0[2] / s0var;
+
+        {
+            s32 h;
+            h = ((s16 *)pb0)[0];
+            s1var = h << 16;
+            __asm__("lh %0, 2(%2)" : "=r"(h) : "0"(h), "r"(pb0) : "memory");
+            s0var = h << 16;
+        }
+        pb0[2] += q3v;
+        s2a = (s16)pb0[2] << 16;
+
+        t = pc0[0] << 4;
+        pc0[0] = t;
+        if (t < 0) s1var |= 0xFFFF;
+        t = pc0[1] << 4;
+        pc0[1] = t;
+        if (t < 0) s0var |= 0xFFFF;
+        o2 = pc0[2];
+        t = o2 << 4;
+        pc0[2] = t;
+        if (t < 0) s2a |= 0xFFFF;
+        s2a += o2 << 5;
+        s1var += pc0[0] << 1;
+        s0var += pc0[1] << 1;
+
+        do {
+            s32 *pl = D_801834D4;
+            u16 *pb;
+            s1var += pl[0];
+            s0var += pl[1];
+            s2a += pl[2];
+            pb = D_801834C4;
+            pb[0] = s1var >> 16;
+            pb[1] = s0var >> 16;
+            pb[2] = s2a >> 16;
+            ret = func_80134310(s3, pb, s6);
+        } while (ret < ((s3[1] < -0xE00) ? 0x1800 : 0x2F00));
+    }
+
+    y = s3[1];
+    if (y >= -0xBCB) {
+        D_801834C0[3] = y;
+        {
+            typedef struct { s8 c[8]; } Blk8;
+            *(Blk8 *)&D_801152B0 = *(Blk8 *)s3;
+        }
+        if (*(u8 *)cmd != 0)
+            goto ret1;
+        return -1;
+    }
+    {
+        typedef struct { u16 h; } H16;
+        u16 *s3u = (u16 *)s3;
+        u16 *bp = D_801834C4;
+        u16 w;
+        ((H16 *)D_801152A8)->h = s3u[0];
+        w = s3u[1];
+        bp[3] = w;
+        ((H16 *)&D_801152AA)->h = w;
+        ((H16 *)&D_801152AC)->h = s3u[2];
+        ((H16 *)&D_801152AE)->h = s3u[3];
+    }
+ret1:
+    return 1;
+}
+
 
 INCLUDE_ASM("asm/ov_SC07_007/nonmatchings/ov_SC07_007", func_80134310);
 
diff --git a/src/ov_SC07_010/ov_SC07_010.c b/src/ov_SC07_010/ov_SC07_010.c
index ae9d8bcb46..6c718db769 100644
--- a/src/ov_SC07_010/ov_SC07_010.c
+++ b/src/ov_SC07_010/ov_SC07_010.c
@@ -631,7 +631,175 @@ INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_80133784);
 
 INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_80133AB0);
 
-INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_80133CD4);
+
+s32 func_80133CD4(arg0, cmd, base, arr)
+    s16 arg0;
+    s16 *cmd;
+    s16 *base;
+    s32 *arr;
+{
+    typedef struct { s16 e[4]; } ElemK;
+
+    extern u16 *D_80182554;
+    extern u16 *D_80182550;
+    extern s16 *D_8018255C;
+    extern s16 *D_80182558;
+    extern s32 *D_80182564;
+    extern s32 *D_80182568;
+    extern u16 D_801A6A38;
+    extern u8  D_801152A8[];
+    extern s16 D_801152AA;
+    extern s16 D_801152AC;
+    extern u16 D_801152AE;
+    extern u8  D_801152B0;
+    extern s32 func_80134310();
+    extern s32 func_8013435C();
+
+    s16 *s3 = ((ElemK *)base)[cmd[1]].e;
+    s32 s6 = arr[cmd[2]];
+    s32 s0var, s1var;
+    s32 s2a;
+    s16 y;
+
+    if (func_80134310(s3, D_80182554, s6) >= 0)
+        return 0;
+
+    s1var = func_80134310(s3, D_80182550, s6);
+    if (s1var < 0)
+        return 0;
+
+    s0var = func_80134310(s3, D_8018255C, 0);
+    {
+        u16 *pac = D_80182550;
+        s16 *pb8 = D_8018255C;
+        s16 *pb4 = D_80182558;
+        s32 neg = -s1var;
+        pb4[0] = pac[0] + neg * pb8[0] / s0var;
+        pb4[1] = pac[1] + neg * pb8[1] / s0var;
+        pb4[2] = pac[2] + neg * pb8[2] / s0var;
+        if (func_8013435C(((ElemK *)base)[cmd[3]].e, pb4, arr[cmd[4]], s3))
+            return 0;
+    }
+    if (func_8013435C(((ElemK *)base)[cmd[5]].e, D_80182558, arr[cmd[6]], s3))
+        return 0;
+    if (func_8013435C(((ElemK *)base)[cmd[7]].e, D_80182558, arr[cmd[8]], s3))
+        return 0;
+    if (arg0 < 0) {
+        if (func_8013435C(((ElemK *)base)[cmd[9]].e, D_80182558, arr[cmd[10]], s3))
+            return 0;
+    }
+    if (arg0 & 0x10) {
+        if (*(u16 *)cmd & 0x100)
+            return 0;
+    }
+    if (*(u16 *)cmd & 0x200) {
+        D_801A6A38 = *(u16 *)cmd;
+        return 0;
+    }
+
+    {
+        s32 ret = func_80134310(s3, D_80182554, s6);
+        s32 *pc0;
+        s32 *pc4;
+        u16 *pb0;
+        s32 t, o2;
+        s32 q3v;
+
+        {
+            s32 *pw = D_80182564;
+            ((struct { s32 w; } *)pw)->w = s3[0];
+            pw[1] = s3[1];
+            pw[2] = s3[2];
+        }
+        s1var = -ret;
+
+        __asm__ __volatile__(
+            "lwc2 $9, 0(%0)\n"
+            "lwc2 $10, 4(%0)\n"
+            "lwc2 $11, 8(%0)\n"
+            "nop\n"
+            "nop\n"
+            "sqr 0\n"
+            : : "r"(D_80182564) : "$9", "$10", "$11", "memory");
+        __asm__ __volatile__(
+            "swc2 $25, 0(%0)\n"
+            "swc2 $26, 4(%0)\n"
+            "swc2 $27, 8(%0)\n"
+            : : "r"(D_80182568) : "memory");
+
+        pc0 = D_80182564;
+        pc4 = D_80182568;
+        s0var = pc4[0] + pc4[1] + pc4[2];
+        pb0 = D_80182554;
+        pb0[0] += s1var * pc0[0] / s0var;
+        pb0[1] += s1var * pc0[1] / s0var;
+        q3v = s1var * pc0[2] / s0var;
+
+        {
+            s32 h;
+            h = ((s16 *)pb0)[0];
+            s1var = h << 16;
+            __asm__("lh %0, 2(%2)" : "=r"(h) : "0"(h), "r"(pb0) : "memory");
+            s0var = h << 16;
+        }
+        pb0[2] += q3v;
+        s2a = (s16)pb0[2] << 16;
+
+        t = pc0[0] << 4;
+        pc0[0] = t;
+        if (t < 0) s1var |= 0xFFFF;
+        t = pc0[1] << 4;
+        pc0[1] = t;
+        if (t < 0) s0var |= 0xFFFF;
+        o2 = pc0[2];
+        t = o2 << 4;
+        pc0[2] = t;
+        if (t < 0) s2a |= 0xFFFF;
+        s2a += o2 << 5;
+        s1var += pc0[0] << 1;
+        s0var += pc0[1] << 1;
+
+        do {
+            s32 *pl = D_80182564;
+            u16 *pb;
+            s1var += pl[0];
+            s0var += pl[1];
+            s2a += pl[2];
+            pb = D_80182554;
+            pb[0] = s1var >> 16;
+            pb[1] = s0var >> 16;
+            pb[2] = s2a >> 16;
+            ret = func_80134310(s3, pb, s6);
+        } while (ret < ((s3[1] < -0xE00) ? 0x1800 : 0x2F00));
+    }
+
+    y = s3[1];
+    if (y >= -0xBCB) {
+        D_80182550[3] = y;
+        {
+            typedef struct { s8 c[8]; } Blk8;
+            *(Blk8 *)&D_801152B0 = *(Blk8 *)s3;
+        }
+        if (*(u8 *)cmd != 0)
+            goto ret1;
+        return -1;
+    }
+    {
+        typedef struct { u16 h; } H16;
+        u16 *s3u = (u16 *)s3;
+        u16 *bp = D_80182554;
+        u16 w;
+        ((H16 *)D_801152A8)->h = s3u[0];
+        w = s3u[1];
+        bp[3] = w;
+        ((H16 *)&D_801152AA)->h = w;
+        ((H16 *)&D_801152AC)->h = s3u[2];
+        ((H16 *)&D_801152AE)->h = s3u[3];
+    }
+ret1:
+    return 1;
+}
+
 
 INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_80134310);
 
diff --git a/src/ov_SC07_011/ov_SC07_011.c b/src/ov_SC07_011/ov_SC07_011.c
index b42662cf4c..451a6769ee 100644
--- a/src/ov_SC07_011/ov_SC07_011.c
+++ b/src/ov_SC07_011/ov_SC07_011.c
@@ -631,7 +631,175 @@ INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011", func_80133784);
 
 INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011", func_80133AB0);
 
-INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011", func_80133CD4);
+
+s32 func_80133CD4(arg0, cmd, base, arr)
+    s16 arg0;
+    s16 *cmd;
+    s16 *base;
+    s32 *arr;
+{
+    typedef struct { s16 e[4]; } ElemK;
+
+    extern u16 *D_8017EC14;
+    extern u16 *D_8017EC10;
+    extern s16 *D_8017EC1C;
+    extern s16 *D_8017EC18;
+    extern s32 *D_8017EC24;
+    extern s32 *D_8017EC28;
+    extern u16 D_8018F0D0;
+    extern u8  D_801152A8[];
+    extern s16 D_801152AA;
+    extern s16 D_801152AC;
+    extern u16 D_801152AE;
+    extern u8  D_801152B0;
+    extern s32 func_80134310();
+    extern s32 func_8013435C();
+
+    s16 *s3 = ((ElemK *)base)[cmd[1]].e;
+    s32 s6 = arr[cmd[2]];
+    s32 s0var, s1var;
+    s32 s2a;
+    s16 y;
+
+    if (func_80134310(s3, D_8017EC14, s6) >= 0)
+        return 0;
+
+    s1var = func_80134310(s3, D_8017EC10, s6);
+    if (s1var < 0)
+        return 0;
+
+    s0var = func_80134310(s3, D_8017EC1C, 0);
+    {
+        u16 *pac = D_8017EC10;
+        s16 *pb8 = D_8017EC1C;
+        s16 *pb4 = D_8017EC18;
+        s32 neg = -s1var;
+        pb4[0] = pac[0] + neg * pb8[0] / s0var;
+        pb4[1] = pac[1] + neg * pb8[1] / s0var;
+        pb4[2] = pac[2] + neg * pb8[2] / s0var;
+        if (func_8013435C(((ElemK *)base)[cmd[3]].e, pb4, arr[cmd[4]], s3))
+            return 0;
+    }
+    if (func_8013435C(((ElemK *)base)[cmd[5]].e, D_8017EC18, arr[cmd[6]], s3))
+        return 0;
+    if (func_8013435C(((ElemK *)base)[cmd[7]].e, D_8017EC18, arr[cmd[8]], s3))
+        return 0;
+    if (arg0 < 0) {
+        if (func_8013435C(((ElemK *)base)[cmd[9]].e, D_8017EC18, arr[cmd[10]], s3))
+            return 0;
+    }
+    if (arg0 & 0x10) {
+        if (*(u16 *)cmd & 0x100)
+            return 0;
+    }
+    if (*(u16 *)cmd & 0x200) {
+        D_8018F0D0 = *(u16 *)cmd;
+        return 0;
+    }
+
+    {
+        s32 ret = func_80134310(s3, D_8017EC14, s6);
+        s32 *pc0;
+        s32 *pc4;
+        u16 *pb0;
+        s32 t, o2;
+        s32 q3v;
+
+        {
+            s32 *pw = D_8017EC24;
+            ((struct { s32 w; } *)pw)->w = s3[0];
+            pw[1] = s3[1];
+            pw[2] = s3[2];
+        }
+        s1var = -ret;
+
+        __asm__ __volatile__(
+            "lwc2 $9, 0(%0)\n"
+            "lwc2 $10, 4(%0)\n"
+            "lwc2 $11, 8(%0)\n"
+            "nop\n"
+            "nop\n"
+            "sqr 0\n"
+            : : "r"(D_8017EC24) : "$9", "$10", "$11", "memory");
+        __asm__ __volatile__(
+            "swc2 $25, 0(%0)\n"
+            "swc2 $26, 4(%0)\n"
+            "swc2 $27, 8(%0)\n"
+            : : "r"(D_8017EC28) : "memory");
+
+        pc0 = D_8017EC24;
+        pc4 = D_8017EC28;
+        s0var = pc4[0] + pc4[1] + pc4[2];
+        pb0 = D_8017EC14;
+        pb0[0] += s1var * pc0[0] / s0var;
+        pb0[1] += s1var * pc0[1] / s0var;
+        q3v = s1var * pc0[2] / s0var;
+
+        {
+            s32 h;
+            h = ((s16 *)pb0)[0];
+            s1var = h << 16;
+            __asm__("lh %0, 2(%2)" : "=r"(h) : "0"(h), "r"(pb0) : "memory");
+            s0var = h << 16;
+        }
+        pb0[2] += q3v;
+        s2a = (s16)pb0[2] << 16;
+
+        t = pc0[0] << 4;
+        pc0[0] = t;
+        if (t < 0) s1var |= 0xFFFF;
+        t = pc0[1] << 4;
+        pc0[1] = t;
+        if (t < 0) s0var |= 0xFFFF;
+        o2 = pc0[2];
+        t = o2 << 4;
+        pc0[2] = t;
+        if (t < 0) s2a |= 0xFFFF;
+        s2a += o2 << 5;
+        s1var += pc0[0] << 1;
+        s0var += pc0[1] << 1;
+
+        do {
+            s32 *pl = D_8017EC24;
+            u16 *pb;
+            s1var += pl[0];
+            s0var += pl[1];
+            s2a += pl[2];
+            pb = D_8017EC14;
+            pb[0] = s1var >> 16;
+            pb[1] = s0var >> 16;
+            pb[2] = s2a >> 16;
+            ret = func_80134310(s3, pb, s6);
+        } while (ret < ((s3[1] < -0xE00) ? 0x1800 : 0x2F00));
+    }
+
+    y = s3[1];
+    if (y >= -0xBCB) {
+        D_8017EC10[3] = y;
+        {
+            typedef struct { s8 c[8]; } Blk8;
+            *(Blk8 *)&D_801152B0 = *(Blk8 *)s3;
+        }
+        if (*(u8 *)cmd != 0)
+            goto ret1;
+        return -1;
+    }
+    {
+        typedef struct { u16 h; } H16;
+        u16 *s3u = (u16 *)s3;
+        u16 *bp = D_8017EC14;
+        u16 w;
+        ((H16 *)D_801152A8)->h = s3u[0];
+        w = s3u[1];
+        bp[3] = w;
+        ((H16 *)&D_801152AA)->h = w;
+        ((H16 *)&D_801152AC)->h = s3u[2];
+        ((H16 *)&D_801152AE)->h = s3u[3];
+    }
+ret1:
+    return 1;
+}
+
 
 INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011", func_80134310);