From 54311fa3594efa9441c4937dff95b43e911e33b7 Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Thu, 10 Sep 2026 18:11:17 -0600 Subject: [PATCH] =?UTF-8?q?phase-36:=20T7=20agents=20c38=20+=20c40=20?= =?UTF-8?q?=E2=80=94=20func=5F80180EDC,=20func=5F8018431C,=20func=5F80185D?= =?UTF-8?q?D8,=20func=5F80184854=20closed=20(30=20bodies)=20(R22=20218/218?= =?UTF-8?q?)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../agents/ov_SC03_111__func_80182F8C/body.c | 64 ++++ .../ov_SC03_111__func_80182F8C/mechanism.md | 86 +++++ .run/P36/census/lever_census.json | 76 ++-- .run/P36/census/lever_census.txt | 28 +- .run/P36/delever/calibration.json | 352 +++++++++--------- .run/P36/delever/ledger.jsonl | 30 ++ docs/lever-progress.tsv | 1 + docs/levers.md | 7 +- phase-ends/CURRENT_PHASE.md | 10 + src/ov_SC02_028/ov_SC02_028_jr_8017D898.c | 7 +- src/ov_SC03_001/ov_SC03_001_jr_801870B0.c | 17 +- src/ov_SC03_001/ov_SC03_001_jr_80188830.c | 28 +- src/ov_SC03_002/ov_SC03_002_jr_80181D78.c | 17 +- src/ov_SC03_002/ov_SC03_002_jr_8018431C.c | 28 +- src/ov_SC03_089/ov_SC03_089_jr_80185E50.c | 7 +- src/ov_SC03_090/ov_SC03_090_jr_80188274.c | 7 +- src/ov_SC03_091/ov_SC03_091_jr_8018911C.c | 7 +- src/ov_SC03_092/ov_SC03_092_jr_80181694.c | 7 +- src/ov_SC03_097/ov_SC03_097_jr_8017D898.c | 7 +- src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c | 7 +- src/ov_SC03_104/ov_SC03_104_jr_80182038.c | 7 +- src/ov_SC03_124/ov_SC03_124_jr_80181B44.c | 17 +- src/ov_SC03_124/ov_SC03_124_jr_80185498.c | 28 +- src/ov_SC03_125/ov_SC03_125_jr_8017D604.c | 17 +- src/ov_SC03_125/ov_SC03_125_jr_80182BA0.c | 28 +- src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c | 17 +- src/ov_SC04_015/ov_SC04_015_jr_801820DC.c | 28 +- src/ov_SC04_020/ov_SC04_020_jr_8017D604.c | 17 +- src/ov_SC04_020/ov_SC04_020_jr_8018254C.c | 28 +- src/ov_SC05_017/ov_SC05_017_jr_80182A74.c | 17 +- src/ov_SC05_017/ov_SC05_017_jr_80185A70.c | 28 +- src/ov_SC05_018/ov_SC05_018_jr_8017D604.c | 17 +- src/ov_SC05_018/ov_SC05_018_jr_80185754.c | 28 +- src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c | 31 +- src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c | 31 +- src/ov_SC06_022/ov_SC06_022_jr_80182D08.c | 31 +- src/ov_SC06_024/ov_SC06_024_jr_801851E0.c | 31 +- src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c | 31 +- src/ov_SC06_033/ov_SC06_033_jr_801836FC.c | 31 +- 39 files changed, 591 insertions(+), 665 deletions(-) create mode 100644 .run/P36/agents/ov_SC03_111__func_80182F8C/body.c create mode 100644 .run/P36/agents/ov_SC03_111__func_80182F8C/mechanism.md diff --git a/.run/P36/agents/ov_SC03_111__func_80182F8C/body.c b/.run/P36/agents/ov_SC03_111__func_80182F8C/body.c new file mode 100644 index 0000000000..e5da561e7c --- /dev/null +++ b/.run/P36/agents/ov_SC03_111__func_80182F8C/body.c @@ -0,0 +1,64 @@ +void func_80182F8C(s32 a0) +{ + u16 out[4]; /* sp+0x10 */ + s16 sv[4]; /* sp+0x18 */ + s16 pos[4]; /* sp+0x20 */ + s32 flag; /* sp+0x28 */ + s16 *p; + + if (*(s16 *)(*(s32 *)(a0 + 0x64) + 0x36) != *(s16 *)(a0 + 0xFE)) { + ((void (*)(void))func_8012C218)(); + return; + } + + if (*(s16 *)(a0 + 0x70) == 0x11) { + s32 ang; + s32 t; + ang = (*(u16 *)(a0 + 0xFC) + 0x40) & 0xFFF; + p = *(s16 **)(a0 + 0xCC); + *(s16 *)(a0 + 0xFC) = ang; + t = (func_8004787C(ang) >> 6) + 0xBF; + p[2] = t; + p[1] = t; + p[0] = t; + } + + if (*(u32 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 4) & 0x80000000) { + *(u32 *)(*(s32 *)(a0 + 0x20) + 4) |= 0x80000000; + } else { + *(u32 *)(*(s32 *)(a0 + 0x20) + 4) &= ~0x80000000; + } + + *(u16 *)(*(s32 *)(a0 + 0x20) + 0x18) = + *(u16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x18); + + *(u16 *)(*(s32 *)(a0 + 0x20) + 0x14) = + *(u16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x14); + + { + s32 ang; + s32 ang2; + + ang = (*(u16 *)(a0 + 0x102) + *(u16 *)(a0 + 0x106)) & 0xFFF; + *(s16 *)(a0 + 0x102) = ang; + *(s16 *)(*(s32 *)(a0 + 0x20) + 0x10) = func_80047948(ang) >> 3; + + ang2 = (*(u16 *)(a0 + 0x104) + *(u16 *)(a0 + 0x100)) & 0xFFF; + *(s16 *)(a0 + 0x104) = ang2; + *(s16 *)(*(s32 *)(a0 + 0x20) + 0x12) = func_80047948(ang2) >> 3; + + func_80049CAC(*(s32 *)(a0 + 0x20) + 0x10, *(s32 *)(a0 + 0x20) + 0x34); + gte_SetRotMatrix((s32 *)(*(s32 *)(a0 + 0x20) + 0x34)); + gte_SetTransMatrix((s32 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x34)); + + p = *(s16 **)(a0 + 0xD0); + sv[0] = 0; + sv[1] = 0; + sv[2] = (p[2] * *(s16 *)(*(s32 *)(a0 + 0x20) + 0x18)) >> 12; + RotTransSV(sv, out, &flag); + + *(s16 *)(a0 + 6) = out[0]; + *(s16 *)(a0 + 0xA) = out[1]; + *(s16 *)(a0 + 0xE) = out[2]; + } +} diff --git a/.run/P36/agents/ov_SC03_111__func_80182F8C/mechanism.md b/.run/P36/agents/ov_SC03_111__func_80182F8C/mechanism.md new file mode 100644 index 0000000000..814261f1de --- /dev/null +++ b/.run/P36/agents/ov_SC03_111__func_80182F8C/mechanism.md @@ -0,0 +1,86 @@ +# func_80182F8C (ov_SC03_111, 7 copies): closed lever-free — the sign-bit copy written as a bit test (agent c43, S103) + +**Result: score 0 with `--body` only.** No pin, no asm, no volatile, and no pad: the `{ s32 pad[2]; }` "LEVER 1 frame +pad" at the end is REMOVED (the real construct supplies those 8 bytes, see (b3)). Body: `PACK/body.c` +(= `scratch/s7.c`). The only change is the flag copy: + +```c + if (*(u32 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 4) & 0x80000000) { + *(u32 *)(*(s32 *)(a0 + 0x20) + 4) |= 0x80000000; + } else { + *(u32 *)(*(s32 *)(a0 + 0x20) + 4) &= ~0x80000000; + } +``` +(it copies the parent's bit 31 into our own flag word), plus deleting the trailing `{ s32 pad[2]; }`. + +**Transfer: all 14 copies of the family score 0 with the same edit** (`scratch/xfer.py`, which applies it and runs +`--try` on each). That's both classes in 7 overlays (SC03_107/111/112/113/117/118, SC05_004): this function +(145 ins) and its sibling func_80182490 / func_80186B78 / func_8017F9BC / ... (386 ins), which has the same pin + +barrier + pad trio. + +## (a) The residual +Same count (145/145). The lever-free `if (x < 0)` fills the `bgez` delay slot with the ELSE arm's `lui v1,0x7fff` +and leaves a `nop` in that arm's load-delay slot. The target fills it with `lui a0,0x8000`, and the then-arm uses +`v1` for the pointer and `v0` for the value, where mine has them the other way round. So it's one delay-slot choice +plus the register swap that goes with it. The pin fixed the swap (score 3 alone) and the barrier fixed the slot +(score 4 alone). + +## (b) The passes (proved on dumps, `scratch/dumps_s5/`, `scratch/dumps_free/`) +1. **cse1 shares the constant across the branch.** `x & 0x80000000` can't take an immediate on MIPS, so the + expander loads the constant into a pseudo (`.cse` insn 84: `(set (reg 97) (const_int 0x80000000))`), and then + insn 85 `and`s it with the flag word. The then-arm is the jump's fall-through, so it's in the same extended basic + block, and cse replaces the arm's own `0x80000000` with `reg 97` (`.cse` insn 98: `(ior (reg 100) (reg 97))`). +2. **combine turns the bit test into a sign test** (`and` + `eq 0` becomes `(ge (reg 95) 0)`, the same `bgez` the + target has). The constant load stays alive because the then-arm still reads reg 97. So the constant is set + BEFORE the branch (`.lreg` insn 85). +3. **reorg's backward fill takes it.** `fill_simple_delay_slots` runs before `fill_eager_delay_slots` + (reorg.c:4331 area), and it moves `li $4,0x80000000` from before the branch into the `bgez` slot. The eager fill, + which in the lever-free build stole the else arm's `lui` (`mostly_true_jump` says GE-against-0 is taken, + reorg.c:1335-1420, so the target thread is tried first), never runs, because the slot is already full. With + `$4` busy across the branch, the then-arm's local allocation lands the pointer in `$3`, as in the target. +4. **The 8-byte "frame pad" is this construct's fingerprint.** When combine deletes the `and`, the REG_DEAD note + for its result (reg 96) has no insn left to go on, so `distribute_notes` emits a `(use (reg 96))` at the block's + code label (combine.c:10830-10840; `.combine`: `(insn 283 (use (reg:SI 96)))` after `code_label 504`). Reg 96 is + never set, so global allocation gives it no hard register (`.greg`: "5 regs to allocate: 72 74 96 97 150", and + 96 is the only pseudo with no disposition; the lever-free build has none). Reload then gives it a stack slot, and + the frame grows by 8 after rounding (with the pad kept: 80 vs 72; with it removed: 72 = target). This is the + METHOD c35 frame-only mechanism, and it's why a previous agent needed an invented dead `pad[2]` local: the pad + was standing in for the phantom slot of the real `&` test. The same holds for the 386-ins sibling, whose pad + comment said "INNER-BLOCK + LAST is load-bearing". + +What's proved on bytes: the score-0 compiles (this function and all 14 copies), the frame arithmetic (s1 = with pad += 80, s5/s7 = without = 72), and pin-alone = 3 / barrier-alone = 4. What's proved on dumps: points 1, 2, the USE +insn and the missing disposition. What I read but did not trace in a dump (there's no dbr dump): that +`fill_simple` is the pass that fills the slot. It's consistent with the `.s`, where the slot holds the pre-branch +insn. + +## (c) The move +Rewrite `if (x < 0) set bit31; else clear bit31;` as `if (x & 0x80000000) x' |= 0x80000000; else x' &= ~0x80000000;` +(u32 view), and delete the trailing `{ s32 pad[2]; }`. It's one edit: the pad has to go BECAUSE the test now +supplies the phantom slot. + +## (d) GENERATOR PROPOSAL +When a `< 0` / `>= 0` test on a word guards `|= 0x80000000` (or any constant that can't be an immediate), and the +target fills the branch delay slot with that constant's `lui` while the lever-free build fills it from the other arm +(or the tree carries a pin + barrier there and/or a dead trailing `pad[]` local), rewrite the test as +`x & CONST` with the same constant and drop any frame pad. cse shares the constant with the arm, combine turns the +`&` back into a sign test, and the USE of the dead `&` result gives back the pad's stack slot. +Family sizing grep: `grep -rn -B1 "0x80000000; }" src | grep "FAKE: pin"` = 14 hits, and all 14 scored 0. Another +possible family for the same idea (not tested): `uVar1 = val | 0x80000000;` under lever-carrying `< 0` tests in +ov_SC06_008/010/032. + +## (e) Tried and did not work (bytes) +- `pin.c` (pin only) = 3 [ORDER], `bar.c` (barrier only) = 4 [REG]. Lever-free = 18. +- `t1`-`t5`: every spelling of the then/else arms (`|=` vs `= x |`, s32 vs u32, a local `q`) with the `< 0` test + kept = 18. With the `< 0` test the constant is only ever loaded inside the arm, so arm spellings can't help. +- `s1`-`s4` (the `&` test with the pad kept) = 8, frame only (80 vs 72). That's what revealed the pad as a stand-in. +- Removing the unused `s16 pos[4]` as well = 9. `pos` is a real frame member (the sibling uses it), so it stays. + +## (f) Where the method fell short +- METHOD's list has no row for "the delay slot is filled from the wrong arm". The fix wasn't about the arms at all: + the test has to create a value that's live BEFORE the branch, so the backward fill wins. residual_moves.md needs + a row for it: *delay slot holds the other arm's constant → make the test compute that constant (bit test instead + of sign test)*. +- The tree's "frame pad" levers are worth auditing as a class. A dead `pad[N]` local that some earlier agent + "byte-verified" may be standing in for a combine-emitted USE slot (c35 again) from a test spelled the wrong way. + When one of those pads comes out, look at the tests near it. diff --git a/.run/P36/census/lever_census.json b/.run/P36/census/lever_census.json index 06b5b0e975..130f03bc02 100644 --- a/.run/P36/census/lever_census.json +++ b/.run/P36/census/lever_census.json @@ -54,7 +54,7 @@ }, "kinds": { "asm-body/direct": 13, - "barrier/direct": 1948, + "barrier/direct": 1934, "barrier/via-macro": 2, "gte-lever/direct": 362, "gte-lever/via-macro": 100, @@ -72,26 +72,26 @@ "binaries": 218, "classes": { "A": { - "bodies": 2350, - "distinct_bodies": 871, + "bodies": 2334, + "distinct_bodies": 869, "file_scope": 0, - "in_bodies": 6926, + "in_bodies": 6910, "kinds": { - "pin": 6926 + "pin": 6910 }, - "marked": 6926, - "sites": 6926, - "tus": 1418, + "marked": 6910, + "sites": 6910, + "tus": 1416, "unmarked": 0 }, "B": { - "bodies": 5038, - "distinct_bodies": 859, + "bodies": 5024, + "distinct_bodies": 857, "file_scope": 13, - "in_bodies": 14637, + "in_bodies": 14623, "kinds": { "asm-body": 13, - "barrier": 1950, + "barrier": 1936, "gte": 6858, "gte-lever": 462, "gte-unsigned": 3, @@ -100,9 +100,9 @@ "launder": 1801, "verbatim-body": 2682 }, - "marked": 5373, - "sites": 14650, - "tus": 1607, + "marked": 5359, + "sites": 14636, + "tus": 1599, "unmarked": 9277 }, "C": { @@ -206,10 +206,10 @@ ], "coverage": { "asm": { - "comment_dead": 6792, - "live": 22578, + "comment_dead": 6786, + "live": 22548, "macro_block": 194, - "raw": 29564 + "raw": 29528 }, "attribute": { "comment_dead": 0, @@ -225,9 +225,9 @@ }, "register": { "comment_dead": 8565, - "live": 6976, + "live": 6960, "macro_block": 18, - "raw": 15559 + "raw": 15543 }, "volatile": { "comment_dead": 2476, @@ -237,7 +237,7 @@ } }, "coverage_ok": true, - "elapsed_s": 31.1, + "elapsed_s": 29.7, "generated": "2026-09-10", "gte_levers": { "direct": 362, @@ -248,15 +248,15 @@ "via_macro": 100, "what": "GTE ops whose clobbers exceed the canonical macro's (a scheduling steer): class-B levers INSIDE the headline number since T5 (2026-09-09), marked, 0 at the close" }, - "head": "7d5964b27", + "head": "321b540e7", "headers": 3181, "levers_AB": { - "asm": 5107, - "bodies": 3090, - "distinct_bodies": 1164, - "marked": 12033, - "pins": 6926, - "sites": 12033, + "asm": 5093, + "bodies": 3060, + "distinct_bodies": 1160, + "marked": 12003, + "pins": 6910, + "sites": 12003, "unmarked": 0, "what": "register pins + asm statements excluding GTE ops: the classes the phase drives to 0" }, @@ -410,8 +410,8 @@ "$23": 10, "$25": 1, "$29": 13, - "$3": 706, - "$4": 1053, + "$3": 698, + "$4": 1045, "$5": 969, "$6": 212, "$7": 175, @@ -423,30 +423,30 @@ "v0": 2, "v1": 3 }, - "sites": 6926, + "sites": 6910, "sp": 13, "spelling": { - "__asm__": 6869, + "__asm__": 6853, "asm": 57 }, "volatile_qualified": 3, "zero": 106 }, - "src_stamp": "747a986f93943d72", + "src_stamp": "7552158a131a0fab", "tus": 4121, "unclassified": 0, "union_AD": { - "bodies": 6616, + "bodies": 6586, "by_kind": { "main": 165, "md": 133, - "ov": 6127, + "ov": 6097, "resident": 10, "shared": 181 }, - "copies_in_multi": 5381, - "distinct_bodies": 1454, - "multi_copy_classes": 219 + "copies_in_multi": 5351, + "distinct_bodies": 1450, + "multi_copy_classes": 215 }, "verbatim_excluded": { "functions": 13, diff --git a/.run/P36/census/lever_census.txt b/.run/P36/census/lever_census.txt index 6f93c28413..d0fe344f21 100644 --- a/.run/P36/census/lever_census.txt +++ b/.run/P36/census/lever_census.txt @@ -1,31 +1,31 @@ lever_census: 218 binaries · 4,121 TUs + 3,181 headers · coverage OK · unclassified 0 · verbatim excluded 13 fn / 14 sites (manifest 13) - coverage asm raw 29564 = live 22578 + macro-block 194 + comment/dead 6792 - coverage register raw 15559 = live 6976 + macro-block 18 + comment/dead 8565 + coverage asm raw 29528 = live 22548 + macro-block 194 + comment/dead 6786 + coverage register raw 15543 = live 6960 + macro-block 18 + comment/dead 8565 coverage volatile raw 4448 = live 1890 + macro-block 82 + comment/dead 2476 coverage builtin raw 599 = live 445 + macro-block 0 + comment/dead 154 coverage attribute raw 76 = live 76 + macro-block 0 + comment/dead 0 class sites in-bodies file-scope bodies distinct TUs marked unmarked kinds - A pins 6926 6926 0 2350 871 1418 6926 0 {'pin': 6926} - B asm 14650 14637 13 5038 859 1607 5373 9277 {'launder': 1801, 'barrier': 1950, 'keepalive': 645, 'instruction': 236, 'gte-lever': 462, 'gte': 6858, 'verbatim-body': 2682, 'gte-unsigned': 3, 'asm-body': 13} - C volatile 1590 1438 152 496 95 610 14 1576 {'cast': 1378, 'decl-body': 58, 'decl-file': 152, 'param': 2} + A pins 6910 6910 0 2334 869 1416 6910 0 {'pin': 6910} + B asm 14636 14623 13 5024 857 1599 5359 9277 {'launder': 1801, 'barrier': 1936, 'keepalive': 645, 'gte': 6858, 'gte-lever': 462, 'instruction': 236, 'asm-body': 13, 'gte-unsigned': 3, 'verbatim-body': 2682} + C volatile 1590 1438 152 496 95 610 14 1576 {'decl-body': 58, 'cast': 1378, 'decl-file': 152, 'param': 2} D register 50 50 0 47 47 6 0 50 {'register': 50} E asm-label 7688 1265 6423 997 120 2084 0 7688 {'asm-label': 7688} F builtin 445 445 0 428 28 302 0 445 {'builtin': 445} G attribute 76 1 75 1 1 40 0 76 {'attribute': 76} - UNION A–D: 6,616 bodies · 1,454 distinct (addresses normalized) · 219 multi-copy classes holding 5,381 bodies · by kind {'ov': 6127, 'shared': 181, 'main': 165, 'md': 133, 'resident': 10} - THE PHASE'S NUMBER (pins + asm statements, GTE excluded): 12,033 sites in 3,090 bodies (1,164 distinct) · marked !FAKE 12,033 · UNMARKED 0 + UNION A–D: 6,586 bodies · 1,450 distinct (addresses normalized) · 215 multi-copy classes holding 5,351 bodies · by kind {'ov': 6097, 'md': 133, 'shared': 181, 'main': 165, 'resident': 10} + THE PHASE'S NUMBER (pins + asm statements, GTE excluded): 12,003 sites in 3,060 bodies (1,160 distinct) · marked !FAKE 12,003 · UNMARKED 0 orphan !FAKE markers (no pin/asm site on the line nor below): 0 GTE levers (clobbers beyond the canonical macro's): 462 sites (100 via a variant macro, 362 direct) · marked 462 · UNMARKED 0 · unsigned GTE statements 3 - per-TU asm macro definitions outside the GTE header: 314 {'launder': 154, 'gte': 150, 'instruction': 9, 'barrier': 1} (GTE variants 64) - pins: 6,926 · $0 106 · $sp 13 · with initializer 538 · volatile-qualified 3 · bare-name 15 · spellings {'__asm__': 6869, 'asm': 57} + per-TU asm macro definitions outside the GTE header: 314 {'gte': 150, 'instruction': 9, 'launder': 154, 'barrier': 1} (GTE variants 64) + pins: 6,910 · $0 106 · $sp 13 · with initializer 538 · volatile-qualified 3 · bare-name 15 · spellings {'__asm__': 6853, 'asm': 57} whole-body asm routines in C shells, manifest PERMANENT (hand asm, NOT levers): 22 routines · 2,682 sites (2,660 private copies + 22 shared headers); asm-bodies NOT permanent (levers): 13 site(s) ['func_8001E378:DECOMPILE-NOW', 'func_80020F34:DECOMPILE-NOW', 'func_800249F0:DECOMPILE-NOW', 'func_80025CBC:DECOMPILE-NOW', 'func_80026514:UNCERTAIN', 'func_800268D0:UNCERTAIN', 'func_80027058:DECOMPILE-NOW', 'func_80027200:DECOMPILE-NOW', 'func_800CBA44:DECOMPILE-NOW', 'func_8017D810:DECOMPILE-NOW', 'func_8017E26C:UNCERTAIN', 'func_80184440:DECOMPILE-NOW', 'func_801A3BCC:DECOMPILE-NOW'] - asm kinds: {'asm-body/direct': 13, 'barrier/direct': 1948, 'barrier/via-macro': 2, 'gte/direct': 200, 'gte/via-macro': 6658, 'gte-lever/direct': 362, 'gte-lever/via-macro': 100, 'gte-unsigned/direct': 3, 'instruction/direct': 214, 'instruction/via-macro': 22, 'keepalive/direct': 645, 'launder/direct': 1735, 'launder/via-macro': 66, 'verbatim-body/direct': 2682} - instruction mnemonics: {'la': 142, 'addu': 23, 'RTP_SND': 22, 'addiu': 22, '.section': 7, 'move': 4, 'lui': 4, 'lh': 3, 'and': 2, 'mult': 1, 'mfhi': 1, 'sll': 1, 'li': 1, 'lw': 1, 'nop': 1, 'srl': 1} - gte mnemonics: {'gte_ldv0': 757, 'gte_stlvnl': 593, 'gte_stsxy': 447, 'gte_rtps': 437, 'gte_stflg': 415, 'gte_rtpt': 352, 'gte_SetRotMatrix': 246, 'gte_stsxy3': 236, 'gte_rtv0tr': 228, 'gte_SetTransMatrix': 226, 'gte_ldv3c': 184, 'gte_ldv3': 177, 'gte_ldrgb': 164, 'gte_stsv': 161, 'lwc2': 159, 'gte_stsz4': 149, 'gte_stsz3': 147, 'gte_stszotz': 134, 'gte_ldIR0z': 134, 'gte_ldIRGB': 134, 'gte_dpcl': 134, 'gte_stORGB': 134, 'gte_stsxy3_f3': 111, 'gte_nclip': 108, 'gte_stopz': 108, 'gte_stsxy3c': 108, 'gte_stclmv': 108, 'gte_stsxy3_ft3': 79, 'gte_rtir': 75, 'gte_ldclmv': 72} - asm-bearing macro definitions: 314 (20 names, 3 with >1 text) kinds {'launder': 154, 'gte': 150, 'instruction': 9, 'barrier': 1} + asm kinds: {'asm-body/direct': 13, 'barrier/direct': 1934, 'barrier/via-macro': 2, 'gte/direct': 200, 'gte/via-macro': 6658, 'gte-lever/direct': 362, 'gte-lever/via-macro': 100, 'gte-unsigned/direct': 3, 'instruction/direct': 214, 'instruction/via-macro': 22, 'keepalive/direct': 645, 'launder/direct': 1735, 'launder/via-macro': 66, 'verbatim-body/direct': 2682} + instruction mnemonics: {'la': 142, 'addu': 23, 'RTP_SND': 22, 'addiu': 22, '.section': 7, 'lui': 4, 'move': 4, 'lh': 3, 'and': 2, 'mult': 1, 'mfhi': 1, 'sll': 1, 'li': 1, 'lw': 1, 'nop': 1, 'srl': 1} + gte mnemonics: {'gte_ldv0': 757, 'gte_stlvnl': 593, 'gte_stsxy': 447, 'gte_rtps': 437, 'gte_stflg': 415, 'gte_rtpt': 352, 'gte_SetRotMatrix': 246, 'gte_stsxy3': 236, 'gte_rtv0tr': 228, 'gte_SetTransMatrix': 226, 'gte_ldv3c': 184, 'gte_ldv3': 177, 'gte_ldrgb': 164, 'gte_stsv': 161, 'lwc2': 159, 'gte_stsz4': 149, 'gte_stsz3': 147, 'gte_stszotz': 134, 'gte_ldIR0z': 134, 'gte_ldIRGB': 134, 'gte_dpcl': 134, 'gte_stORGB': 134, 'gte_stsxy3_f3': 111, 'gte_stclmv': 108, 'gte_nclip': 108, 'gte_stopz': 108, 'gte_stsxy3c': 108, 'gte_stsxy3_ft3': 79, 'gte_rtir': 75, 'gte_ldclmv': 72} + asm-bearing macro definitions: 314 (20 names, 3 with >1 text) kinds {'gte': 150, 'instruction': 9, 'launder': 154, 'barrier': 1} controls (R39): src/800.c func_800226C0 pins got 14 expected 45 N-A src/shared/ov/func_80178004.h pins got 8 expected 26 N-A ov_SC03_006 func_80184034 bare-name pins got 0 expected 3 N-A engine_prelude.h asm sites (a macro definition only) got 0 expected 0 OK - elapsed 31.1 s + elapsed 29.7 s diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index 5711e21a05..374c4a1c98 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,7 +1,7 @@ { - "head": "7d5964b27", + "head": "321b540e7", "stamp": "15956e4a96c4", - "generated": "2026-09-10 18:02", + "generated": "2026-09-10 18:08", "aliases": [ "main", "ov_SC03_014", @@ -21,206 +21,206 @@ "main": { "objects": 85, "identical": 85, - "seconds": 8.427999999999999, - "mean_s": 0.099 + "seconds": 8.127000000000002, + "mean_s": 0.096 }, "ov_SC03_014": { "objects": 32, "identical": 32, - "seconds": 5.498000000000001, - "mean_s": 0.172 + "seconds": 5.461000000000001, + "mean_s": 0.171 }, "ov_SC03_015": { "objects": 32, "identical": 32, - "seconds": 5.393, - "mean_s": 0.169 + "seconds": 5.338000000000001, + "mean_s": 0.167 }, "ov_SC04_011": { "objects": 28, "identical": 28, - "seconds": 4.7090000000000005, - "mean_s": 0.168 + "seconds": 4.664000000000001, + "mean_s": 0.167 } }, "per_object_seconds": { - "build/src/800.o": 0.879, - "build/src/800_b.o": 0.093, - "build/src/800_b_2.o": 0.358, - "build/src/800_b_o0a.o": 0.078, - "build/src/800_c.o": 0.245, - "build/src/800b2.o": 0.098, - "build/src/apicard1.o": 0.082, - "build/src/apicard2.o": 0.078, - "build/src/apicard3.o": 0.12, - "build/src/apicard4.o": 0.094, - "build/src/apicard5.o": 0.08, - "build/src/apicard6.o": 0.083, - "build/src/apicard7.o": 0.11, - "build/src/boot.o": 0.108, - "build/src/gap.o": 0.083, - "build/src/libapi1.o": 0.076, - "build/src/libapi2.o": 0.075, - "build/src/libc2_1.o": 0.075, - "build/src/libc2_2.o": 0.077, - "build/src/libcd1.o": 0.093, - "build/src/libcd2.o": 0.081, - "build/src/libetc.o": 0.082, - "build/src/libgpu.o": 0.084, - "build/src/libgpu2.o": 0.092, - "build/src/libgs1.o": 0.08, - "build/src/libgs2.o": 0.079, - "build/src/libgs3.o": 0.071, - "build/src/libgs4.o": 0.08, - "build/src/libgs5.o": 0.08, - "build/src/libgs6.o": 0.096, - "build/src/libgs7.o": 0.072, - "build/src/libgs8.o": 0.082, - "build/src/libgte1.o": 0.076, - "build/src/libgte10.o": 0.075, - "build/src/libgte11.o": 0.08, - "build/src/libgte12.o": 0.078, + "build/src/800.o": 0.863, + "build/src/800_b.o": 0.119, + "build/src/800_b_2.o": 0.357, + "build/src/800_b_o0a.o": 0.083, + "build/src/800_c.o": 0.227, + "build/src/800b2.o": 0.085, + "build/src/apicard1.o": 0.076, + "build/src/apicard2.o": 0.082, + "build/src/apicard3.o": 0.078, + "build/src/apicard4.o": 0.079, + "build/src/apicard5.o": 0.117, + "build/src/apicard6.o": 0.094, + "build/src/apicard7.o": 0.108, + "build/src/boot.o": 0.115, + "build/src/gap.o": 0.088, + "build/src/libapi1.o": 0.085, + "build/src/libapi2.o": 0.069, + "build/src/libc2_1.o": 0.079, + "build/src/libc2_2.o": 0.074, + "build/src/libcd1.o": 0.082, + "build/src/libcd2.o": 0.069, + "build/src/libetc.o": 0.071, + "build/src/libgpu.o": 0.091, + "build/src/libgpu2.o": 0.088, + "build/src/libgs1.o": 0.078, + "build/src/libgs2.o": 0.073, + "build/src/libgs3.o": 0.069, + "build/src/libgs4.o": 0.079, + "build/src/libgs5.o": 0.079, + "build/src/libgs6.o": 0.097, + "build/src/libgs7.o": 0.074, + "build/src/libgs8.o": 0.085, + "build/src/libgte1.o": 0.079, + "build/src/libgte10.o": 0.078, + "build/src/libgte11.o": 0.078, + "build/src/libgte12.o": 0.076, "build/src/libgte13.o": 0.078, - "build/src/libgte14.o": 0.085, - "build/src/libgte15.o": 0.098, - "build/src/libgte16.o": 0.085, + "build/src/libgte14.o": 0.073, + "build/src/libgte15.o": 0.076, + "build/src/libgte16.o": 0.078, "build/src/libgte17.o": 0.079, - "build/src/libgte18.o": 0.077, - "build/src/libgte19.o": 0.086, - "build/src/libgte2.o": 0.091, - "build/src/libgte20.o": 0.082, - "build/src/libgte21.o": 0.086, - "build/src/libgte22.o": 0.083, - "build/src/libgte23.o": 0.082, - "build/src/libgte24.o": 0.079, - "build/src/libgte25.o": 0.075, + "build/src/libgte18.o": 0.083, + "build/src/libgte19.o": 0.078, + "build/src/libgte2.o": 0.077, + "build/src/libgte20.o": 0.075, + "build/src/libgte21.o": 0.074, + "build/src/libgte22.o": 0.076, + "build/src/libgte23.o": 0.071, + "build/src/libgte24.o": 0.081, + "build/src/libgte25.o": 0.078, "build/src/libgte26.o": 0.083, - "build/src/libgte27.o": 0.084, - "build/src/libgte28.o": 0.074, - "build/src/libgte29.o": 0.076, - "build/src/libgte3.o": 0.086, + "build/src/libgte27.o": 0.075, + "build/src/libgte28.o": 0.079, + "build/src/libgte29.o": 0.078, + "build/src/libgte3.o": 0.077, "build/src/libgte30.o": 0.081, - "build/src/libgte4.o": 0.084, - "build/src/libgte5.o": 0.083, - "build/src/libgte6.o": 0.08, - "build/src/libgte7.o": 0.083, - "build/src/libgte8.o": 0.078, - "build/src/libgte9.o": 0.079, - "build/src/libmcrd1.o": 0.101, - "build/src/libmcrd2.o": 0.091, - "build/src/libpad1.o": 0.095, + "build/src/libgte4.o": 0.078, + "build/src/libgte5.o": 0.074, + "build/src/libgte6.o": 0.089, + "build/src/libgte7.o": 0.086, + "build/src/libgte8.o": 0.079, + "build/src/libgte9.o": 0.084, + "build/src/libmcrd1.o": 0.091, + "build/src/libmcrd2.o": 0.087, + "build/src/libpad1.o": 0.078, "build/src/libpad2.o": 0.092, - "build/src/sgap.o": 0.091, - "build/src/sgap_2.o": 0.082, - "build/src/sgap_3.o": 0.092, - "build/src/sgap_4.o": 0.1, - "build/src/sgap_5.o": 0.074, - "build/src/sgap_6.o": 0.086, - "build/src/sgap_8.o": 0.089, - "build/src/snd1.o": 0.092, - "build/src/snd10.o": 0.078, - "build/src/snd11.o": 0.084, - "build/src/snd12.o": 0.085, - "build/src/snd2.o": 0.081, - "build/src/snd3.o": 0.085, - "build/src/snd4.o": 0.094, - "build/src/snd5.o": 0.081, - "build/src/snd6.o": 0.089, - "build/src/snd7.o": 0.088, - "build/src/snd8.o": 0.08, - "build/src/snd9.o": 0.088, - "build/src/ov_SC03_014/ov_SC03_014.o": 0.14, - "build/src/ov_SC03_014/ov_SC03_014_after.o": 0.584, - "build/src/ov_SC03_014/ov_SC03_014_jr_8012ACE0.o": 0.456, - "build/src/ov_SC03_014/ov_SC03_014_jr_80135888.o": 0.078, - "build/src/ov_SC03_014/ov_SC03_014_jr_80135A4C.o": 0.079, - "build/src/ov_SC03_014/ov_SC03_014_jr_80135D20.o": 0.147, - "build/src/ov_SC03_014/ov_SC03_014_jr_801380E0.o": 0.184, - "build/src/ov_SC03_014/ov_SC03_014_jr_8013C98C.o": 0.133, - "build/src/ov_SC03_014/ov_SC03_014_jr_8013F350.o": 0.091, - "build/src/ov_SC03_014/ov_SC03_014_jr_8013FFD8.o": 0.081, - "build/src/ov_SC03_014/ov_SC03_014_jr_80140608.o": 0.219, - "build/src/ov_SC03_014/ov_SC03_014_jr_8015444C.o": 0.086, - "build/src/ov_SC03_014/ov_SC03_014_jr_80154C24.o": 0.21, - "build/src/ov_SC03_014/ov_SC03_014_jr_801588CC.o": 0.105, - "build/src/ov_SC03_014/ov_SC03_014_jr_80159C84.o": 0.081, - "build/src/ov_SC03_014/ov_SC03_014_jr_8015A3C8.o": 0.079, - "build/src/ov_SC03_014/ov_SC03_014_jr_8015AE2C.o": 0.116, - "build/src/ov_SC03_014/ov_SC03_014_jr_8015C32C.o": 0.555, - "build/src/ov_SC03_014/ov_SC03_014_jr_8016AB6C.o": 0.311, - "build/src/ov_SC03_014/ov_SC03_014_jr_80171B4C.o": 0.124, - "build/src/ov_SC03_014/ov_SC03_014_jr_801734BC.o": 0.234, - "build/src/ov_SC03_014/ov_SC03_014_jr_801789AC.o": 0.076, - "build/src/ov_SC03_014/ov_SC03_014_jr_80178D40.o": 0.118, - "build/src/ov_SC03_014/ov_SC03_014_jr_8017A4AC.o": 0.084, - "build/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.o": 0.198, - "build/src/ov_SC03_014/ov_SC03_014_jr_8017EB7C.o": 0.235, - "build/src/ov_SC03_014/ov_SC03_014_jr_80184440.o": 0.059, - "build/src/ov_SC03_014/ov_SC03_014_jr_801848E4.o": 0.331, - "build/src/ov_SC03_014/ov_SC03_014_o0b.o": 0.077, - "build/src/ov_SC03_014/ov_SC03_014_o0c.o": 0.074, - "build/src/ov_SC03_014/ov_SC03_014_o0d.o": 0.07, - "build/src/ov_SC03_014/ov_SC03_014_o0e.o": 0.083, - "build/src/ov_SC03_015/ov_SC03_015.o": 0.146, - "build/src/ov_SC03_015/ov_SC03_015_after.o": 0.572, - "build/src/ov_SC03_015/ov_SC03_015_jr_8012ACE0.o": 0.448, - "build/src/ov_SC03_015/ov_SC03_015_jr_80135888.o": 0.067, - "build/src/ov_SC03_015/ov_SC03_015_jr_80135A4C.o": 0.067, - "build/src/ov_SC03_015/ov_SC03_015_jr_80135D20.o": 0.137, - "build/src/ov_SC03_015/ov_SC03_015_jr_801380E0.o": 0.178, - "build/src/ov_SC03_015/ov_SC03_015_jr_8013C98C.o": 0.131, - "build/src/ov_SC03_015/ov_SC03_015_jr_8013F350.o": 0.09, - "build/src/ov_SC03_015/ov_SC03_015_jr_8013FFD8.o": 0.078, - "build/src/ov_SC03_015/ov_SC03_015_jr_80140608.o": 0.209, - "build/src/ov_SC03_015/ov_SC03_015_jr_8015444C.o": 0.078, - "build/src/ov_SC03_015/ov_SC03_015_jr_80154C24.o": 0.2, + "build/src/sgap.o": 0.075, + "build/src/sgap_2.o": 0.076, + "build/src/sgap_3.o": 0.085, + "build/src/sgap_4.o": 0.086, + "build/src/sgap_5.o": 0.079, + "build/src/sgap_6.o": 0.077, + "build/src/sgap_8.o": 0.08, + "build/src/snd1.o": 0.085, + "build/src/snd10.o": 0.076, + "build/src/snd11.o": 0.075, + "build/src/snd12.o": 0.072, + "build/src/snd2.o": 0.083, + "build/src/snd3.o": 0.079, + "build/src/snd4.o": 0.076, + "build/src/snd5.o": 0.08, + "build/src/snd6.o": 0.087, + "build/src/snd7.o": 0.084, + "build/src/snd8.o": 0.074, + "build/src/snd9.o": 0.086, + "build/src/ov_SC03_014/ov_SC03_014.o": 0.154, + "build/src/ov_SC03_014/ov_SC03_014_after.o": 0.592, + "build/src/ov_SC03_014/ov_SC03_014_jr_8012ACE0.o": 0.454, + "build/src/ov_SC03_014/ov_SC03_014_jr_80135888.o": 0.076, + "build/src/ov_SC03_014/ov_SC03_014_jr_80135A4C.o": 0.076, + "build/src/ov_SC03_014/ov_SC03_014_jr_80135D20.o": 0.146, + "build/src/ov_SC03_014/ov_SC03_014_jr_801380E0.o": 0.189, + "build/src/ov_SC03_014/ov_SC03_014_jr_8013C98C.o": 0.139, + "build/src/ov_SC03_014/ov_SC03_014_jr_8013F350.o": 0.095, + "build/src/ov_SC03_014/ov_SC03_014_jr_8013FFD8.o": 0.086, + "build/src/ov_SC03_014/ov_SC03_014_jr_80140608.o": 0.225, + "build/src/ov_SC03_014/ov_SC03_014_jr_8015444C.o": 0.091, + "build/src/ov_SC03_014/ov_SC03_014_jr_80154C24.o": 0.203, + "build/src/ov_SC03_014/ov_SC03_014_jr_801588CC.o": 0.114, + "build/src/ov_SC03_014/ov_SC03_014_jr_80159C84.o": 0.08, + "build/src/ov_SC03_014/ov_SC03_014_jr_8015A3C8.o": 0.086, + "build/src/ov_SC03_014/ov_SC03_014_jr_8015AE2C.o": 0.113, + "build/src/ov_SC03_014/ov_SC03_014_jr_8015C32C.o": 0.549, + "build/src/ov_SC03_014/ov_SC03_014_jr_8016AB6C.o": 0.308, + "build/src/ov_SC03_014/ov_SC03_014_jr_80171B4C.o": 0.116, + "build/src/ov_SC03_014/ov_SC03_014_jr_801734BC.o": 0.229, + "build/src/ov_SC03_014/ov_SC03_014_jr_801789AC.o": 0.07, + "build/src/ov_SC03_014/ov_SC03_014_jr_80178D40.o": 0.126, + "build/src/ov_SC03_014/ov_SC03_014_jr_8017A4AC.o": 0.083, + "build/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.o": 0.196, + "build/src/ov_SC03_014/ov_SC03_014_jr_8017EB7C.o": 0.221, + "build/src/ov_SC03_014/ov_SC03_014_jr_80184440.o": 0.057, + "build/src/ov_SC03_014/ov_SC03_014_jr_801848E4.o": 0.306, + "build/src/ov_SC03_014/ov_SC03_014_o0b.o": 0.065, + "build/src/ov_SC03_014/ov_SC03_014_o0c.o": 0.069, + "build/src/ov_SC03_014/ov_SC03_014_o0d.o": 0.065, + "build/src/ov_SC03_014/ov_SC03_014_o0e.o": 0.082, + "build/src/ov_SC03_015/ov_SC03_015.o": 0.153, + "build/src/ov_SC03_015/ov_SC03_015_after.o": 0.6, + "build/src/ov_SC03_015/ov_SC03_015_jr_8012ACE0.o": 0.432, + "build/src/ov_SC03_015/ov_SC03_015_jr_80135888.o": 0.063, + "build/src/ov_SC03_015/ov_SC03_015_jr_80135A4C.o": 0.056, + "build/src/ov_SC03_015/ov_SC03_015_jr_80135D20.o": 0.135, + "build/src/ov_SC03_015/ov_SC03_015_jr_801380E0.o": 0.177, + "build/src/ov_SC03_015/ov_SC03_015_jr_8013C98C.o": 0.122, + "build/src/ov_SC03_015/ov_SC03_015_jr_8013F350.o": 0.089, + "build/src/ov_SC03_015/ov_SC03_015_jr_8013FFD8.o": 0.072, + "build/src/ov_SC03_015/ov_SC03_015_jr_80140608.o": 0.204, + "build/src/ov_SC03_015/ov_SC03_015_jr_8015444C.o": 0.087, + "build/src/ov_SC03_015/ov_SC03_015_jr_80154C24.o": 0.193, "build/src/ov_SC03_015/ov_SC03_015_jr_801588CC.o": 0.102, - "build/src/ov_SC03_015/ov_SC03_015_jr_80159C84.o": 0.079, - "build/src/ov_SC03_015/ov_SC03_015_jr_8015A3C8.o": 0.078, - "build/src/ov_SC03_015/ov_SC03_015_jr_8015AE2C.o": 0.112, - "build/src/ov_SC03_015/ov_SC03_015_jr_8015C32C.o": 0.525, - "build/src/ov_SC03_015/ov_SC03_015_jr_8016AB6C.o": 0.314, - "build/src/ov_SC03_015/ov_SC03_015_jr_80171B4C.o": 0.127, - "build/src/ov_SC03_015/ov_SC03_015_jr_801734BC.o": 0.237, - "build/src/ov_SC03_015/ov_SC03_015_jr_801789AC.o": 0.07, + "build/src/ov_SC03_015/ov_SC03_015_jr_80159C84.o": 0.076, + "build/src/ov_SC03_015/ov_SC03_015_jr_8015A3C8.o": 0.077, + "build/src/ov_SC03_015/ov_SC03_015_jr_8015AE2C.o": 0.109, + "build/src/ov_SC03_015/ov_SC03_015_jr_8015C32C.o": 0.528, + "build/src/ov_SC03_015/ov_SC03_015_jr_8016AB6C.o": 0.319, + "build/src/ov_SC03_015/ov_SC03_015_jr_80171B4C.o": 0.121, + "build/src/ov_SC03_015/ov_SC03_015_jr_801734BC.o": 0.23, + "build/src/ov_SC03_015/ov_SC03_015_jr_801789AC.o": 0.069, "build/src/ov_SC03_015/ov_SC03_015_jr_80178D40.o": 0.123, - "build/src/ov_SC03_015/ov_SC03_015_jr_8017A4AC.o": 0.073, - "build/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.o": 0.212, - "build/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.o": 0.236, + "build/src/ov_SC03_015/ov_SC03_015_jr_8017A4AC.o": 0.075, + "build/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.o": 0.197, + "build/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.o": 0.242, "build/src/ov_SC03_015/ov_SC03_015_jr_80184440.o": 0.065, - "build/src/ov_SC03_015/ov_SC03_015_jr_801848E4.o": 0.334, - "build/src/ov_SC03_015/ov_SC03_015_o0b.o": 0.079, - "build/src/ov_SC03_015/ov_SC03_015_o0c.o": 0.073, - "build/src/ov_SC03_015/ov_SC03_015_o0d.o": 0.069, - "build/src/ov_SC03_015/ov_SC03_015_o0e.o": 0.084, - "build/src/ov_SC04_011/ov_SC04_011.o": 0.149, - "build/src/ov_SC04_011/ov_SC04_011_after.o": 0.484, - "build/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.o": 0.395, - "build/src/ov_SC04_011/ov_SC04_011_jr_80135888.o": 0.068, + "build/src/ov_SC03_015/ov_SC03_015_jr_801848E4.o": 0.322, + "build/src/ov_SC03_015/ov_SC03_015_o0b.o": 0.078, + "build/src/ov_SC03_015/ov_SC03_015_o0c.o": 0.067, + "build/src/ov_SC03_015/ov_SC03_015_o0d.o": 0.068, + "build/src/ov_SC03_015/ov_SC03_015_o0e.o": 0.087, + "build/src/ov_SC04_011/ov_SC04_011.o": 0.144, + "build/src/ov_SC04_011/ov_SC04_011_after.o": 0.487, + "build/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.o": 0.396, + "build/src/ov_SC04_011/ov_SC04_011_jr_80135888.o": 0.065, "build/src/ov_SC04_011/ov_SC04_011_jr_80135A4C.o": 0.064, - "build/src/ov_SC04_011/ov_SC04_011_jr_80135D20.o": 0.136, - "build/src/ov_SC04_011/ov_SC04_011_jr_801380E0.o": 0.179, + "build/src/ov_SC04_011/ov_SC04_011_jr_80135D20.o": 0.132, + "build/src/ov_SC04_011/ov_SC04_011_jr_801380E0.o": 0.173, "build/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.o": 0.127, - "build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o": 0.094, - "build/src/ov_SC04_011/ov_SC04_011_jr_8013FFD8.o": 0.079, - "build/src/ov_SC04_011/ov_SC04_011_jr_80140608.o": 0.211, - "build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o": 0.093, - "build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.195, - "build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.119, - "build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o": 0.082, - "build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.091, - "build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.111, - "build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.409, - "build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.258, - "build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.127, - "build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.209, + "build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o": 0.086, + "build/src/ov_SC04_011/ov_SC04_011_jr_8013FFD8.o": 0.082, + "build/src/ov_SC04_011/ov_SC04_011_jr_80140608.o": 0.21, + "build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o": 0.088, + "build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.203, + "build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.111, + "build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o": 0.075, + "build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.077, + "build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.112, + "build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.418, + "build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.261, + "build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.122, + "build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.203, "build/src/ov_SC04_011/ov_SC04_011_jr_801789AC.o": 0.07, - "build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.111, - "build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.074, - "build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.117, - "build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.52, - "build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.068, - "build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.069 + "build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.106, + "build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.08, + "build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.122, + "build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.525, + "build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.06, + "build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.065 }, "ok": true, "seconds": 2.7 diff --git a/.run/P36/delever/ledger.jsonl b/.run/P36/delever/ledger.jsonl index 35322064d8..f62fa80fdf 100644 --- a/.run/P36/delever/ledger.jsonl +++ b/.run/P36/delever/ledger.jsonl @@ -27928,3 +27928,33 @@ {"ts": "2026-09-10 18:03:49", "label": "c41p", "rung": "E", "calib": {"head": "7d5964b27", "stamp": "15956e4a96c4"}, "tu": "src/ov_MAIN_012/ov_MAIN_012_jr_801458E0.c", "fn": "func_80145A2C", "addr": 2148817452, "aliases": null, "header": false, "includers": 0, "nhash_before": "9d523cda5f82b483301da1ea21bff80d3f5cd31f", "nhash_after": "1a43a7c13ea3d0bebf9b30d28fd18bfcbea2a418", "source": "propagate:src/ov_SC07_006/ov_SC07_006_jr_801457A4.c:func_80145934", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.393, "objects": ["build/src/ov_MAIN_012/ov_MAIN_012_jr_801458E0.o"], "before_text": "void func_80145A2C(void) {\n\n extern u8 D_80180948;\n extern u8 D_80180828;\n extern u8 D_80180804;\n extern u8 D_801807E0;\n extern u8 D_80180924;\n extern u8 D_80180900;\n extern u8 D_801808DC;\n extern u8 D_801807BC;\n s32 v;\n void *p;\n\n v = func_80029504();\n if (v >= 0x6A4) {\n p = &D_80180948;\n /* \u00a75a cross-jump barrier \u2014 LOAD-BEARING: keeps this D_80180948 load from being\n * tail-merged with the v>=0x384 D_80180948 load below (emits zero machine code). */\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus4)\n } else if (v >= 0x5DC) {\n p = &D_80180828;\n } else if (v >= 0x578) {\n p = &D_80180804;\n } else if (v >= 0x514) {\n p = &D_801807E0;\n } else if (v >= 0x384) {\n p = &D_80180948;\n } else if (v >= 0x258) {\n p = &D_80180924;\n } else if (v >= 0xC8) {\n p = &D_80180900;\n } else if (v >= 0xA) {\n p = &D_801808DC;\n } else {\n p = &D_801807BC;\n }\n ((void (*)(void *))func_800D185C)(p);\n func_80145B24();\n}\n", "after_text": "void func_80145A2C(void) {\n\n extern u8 D_80180948;\n extern u8 D_80180828;\n extern u8 D_80180804;\n extern u8 D_801807E0;\n extern u8 D_80180924;\n extern u8 D_80180900;\n extern u8 D_801808DC;\n extern u8 D_801807BC;\n /* \u00a75a cross-jump alias (replaces the memory barrier that used to sit in the >=0x6A4 arm).\n * Both the >=0x6A4 and the >=0x384 arm take the address of D_80180948, so their blocks are the\n * identical pair `la a0,D_80180948 / j ` and jump2's cross-jumper merges them (jump.c:1969).\n * find_cross_jump compares the two SYMBOL_REFs with rtx_renumbered_equal_p, which tests the name\n * STRING POINTERS (jump.c:2440 `case SYMBOL_REF: return XSTR (x, 0) == XSTR (y, 0);`), so a second\n * declaration of the same symbol under its own asm label gives the first arm a distinct string and\n * the two blocks stay separate. Same bytes, same R_MIPS_HI16/LO16 D_80180948 relocations. */\n extern u8 aD8018C944 __asm__(\"D_80180948\");\n s32 v;\n void *p;\n\n v = func_80029504();\n if (v >= 0x6A4) {\n p = &aD8018C944;\n } else if (v >= 0x5DC) {\n p = &D_80180828;\n } else if (v >= 0x578) {\n p = &D_80180804;\n } else if (v >= 0x514) {\n p = &D_801807E0;\n } else if (v >= 0x384) {\n p = &D_80180948;\n } else if (v >= 0x258) {\n p = &D_80180924;\n } else if (v >= 0xC8) {\n p = &D_80180900;\n } else if (v >= 0xA) {\n p = &D_801808DC;\n } else {\n p = &D_801807BC;\n }\n ((void (*)(void *))func_800D185C)(p);\n func_80145B24();\n}\n"} {"ts": "2026-09-10 18:03:50", "label": "c41p", "rung": "E", "calib": {"head": "7d5964b27", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_037/ov_SC02_037_jr_801458E0.c", "fn": "func_80145A2C", "addr": 2148817452, "aliases": null, "header": false, "includers": 0, "nhash_before": "9d523cda5f82b483301da1ea21bff80d3f5cd31f", "nhash_after": "1a43a7c13ea3d0bebf9b30d28fd18bfcbea2a418", "source": "propagate:src/ov_SC07_006/ov_SC07_006_jr_801457A4.c:func_80145934", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.393, "objects": ["build/src/ov_SC02_037/ov_SC02_037_jr_801458E0.o"], "before_text": "void func_80145A2C(void) {\n\n extern u8 D_801861D4;\n extern u8 D_801860B4;\n extern u8 D_80186090;\n extern u8 D_8018606C;\n extern u8 D_801861B0;\n extern u8 D_8018618C;\n extern u8 D_80186168;\n extern u8 D_80186048;\n s32 v;\n void *p;\n\n v = func_80029504();\n if (v >= 0x6A4) {\n p = &D_801861D4;\n /* \u00a75a cross-jump barrier \u2014 LOAD-BEARING: keeps this D_801861D4 load from being\n * tail-merged with the v>=0x384 D_801861D4 load below (emits zero machine code). */\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus4)\n } else if (v >= 0x5DC) {\n p = &D_801860B4;\n } else if (v >= 0x578) {\n p = &D_80186090;\n } else if (v >= 0x514) {\n p = &D_8018606C;\n } else if (v >= 0x384) {\n p = &D_801861D4;\n } else if (v >= 0x258) {\n p = &D_801861B0;\n } else if (v >= 0xC8) {\n p = &D_8018618C;\n } else if (v >= 0xA) {\n p = &D_80186168;\n } else {\n p = &D_80186048;\n }\n ((void (*)(void *))func_800D185C)(p);\n func_80145B24();\n}\n", "after_text": "void func_80145A2C(void) {\n\n extern u8 D_801861D4;\n extern u8 D_801860B4;\n extern u8 D_80186090;\n extern u8 D_8018606C;\n extern u8 D_801861B0;\n extern u8 D_8018618C;\n extern u8 D_80186168;\n extern u8 D_80186048;\n /* \u00a75a cross-jump alias (replaces the memory barrier that used to sit in the >=0x6A4 arm).\n * Both the >=0x6A4 and the >=0x384 arm take the address of D_801861D4, so their blocks are the\n * identical pair `la a0,D_801861D4 / j ` and jump2's cross-jumper merges them (jump.c:1969).\n * find_cross_jump compares the two SYMBOL_REFs with rtx_renumbered_equal_p, which tests the name\n * STRING POINTERS (jump.c:2440 `case SYMBOL_REF: return XSTR (x, 0) == XSTR (y, 0);`), so a second\n * declaration of the same symbol under its own asm label gives the first arm a distinct string and\n * the two blocks stay separate. Same bytes, same R_MIPS_HI16/LO16 D_801861D4 relocations. */\n extern u8 aD8018C944 __asm__(\"D_801861D4\");\n s32 v;\n void *p;\n\n v = func_80029504();\n if (v >= 0x6A4) {\n p = &aD8018C944;\n } else if (v >= 0x5DC) {\n p = &D_801860B4;\n } else if (v >= 0x578) {\n p = &D_80186090;\n } else if (v >= 0x514) {\n p = &D_8018606C;\n } else if (v >= 0x384) {\n p = &D_801861D4;\n } else if (v >= 0x258) {\n p = &D_801861B0;\n } else if (v >= 0xC8) {\n p = &D_8018618C;\n } else if (v >= 0xA) {\n p = &D_80186168;\n } else {\n p = &D_80186048;\n }\n ((void (*)(void *))func_800D185C)(p);\n func_80145B24();\n}\n"} {"ts": "2026-09-10 18:03:50", "label": "c41p", "rung": "E", "calib": {"head": "7d5964b27", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_107/ov_SC03_107_jr_801458E0.c", "fn": "func_80145A2C", "addr": 2148817452, "aliases": null, "header": false, "includers": 0, "nhash_before": "9d523cda5f82b483301da1ea21bff80d3f5cd31f", "nhash_after": "1a43a7c13ea3d0bebf9b30d28fd18bfcbea2a418", "source": "propagate:src/ov_SC07_006/ov_SC07_006_jr_801457A4.c:func_80145934", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.39, "objects": ["build/src/ov_SC03_107/ov_SC03_107_jr_801458E0.o"], "before_text": "void func_80145A2C(void) {\n\n extern u8 D_80184A70;\n extern u8 D_80184950;\n extern u8 D_8018492C;\n extern u8 D_80184908;\n extern u8 D_80184A4C;\n extern u8 D_80184A28;\n extern u8 D_80184A04;\n extern u8 D_801848E4;\n s32 v;\n void *p;\n\n v = func_80029504();\n if (v >= 0x6A4) {\n p = &D_80184A70;\n /* \u00a75a cross-jump barrier \u2014 LOAD-BEARING: keeps this D_80184A70 load from being\n * tail-merged with the v>=0x384 D_80184A70 load below (emits zero machine code). */\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus4)\n } else if (v >= 0x5DC) {\n p = &D_80184950;\n } else if (v >= 0x578) {\n p = &D_8018492C;\n } else if (v >= 0x514) {\n p = &D_80184908;\n } else if (v >= 0x384) {\n p = &D_80184A70;\n } else if (v >= 0x258) {\n p = &D_80184A4C;\n } else if (v >= 0xC8) {\n p = &D_80184A28;\n } else if (v >= 0xA) {\n p = &D_80184A04;\n } else {\n p = &D_801848E4;\n }\n ((void (*)(void *))func_800D185C)(p);\n func_80145B24();\n}\n", "after_text": "void func_80145A2C(void) {\n\n extern u8 D_80184A70;\n extern u8 D_80184950;\n extern u8 D_8018492C;\n extern u8 D_80184908;\n extern u8 D_80184A4C;\n extern u8 D_80184A28;\n extern u8 D_80184A04;\n extern u8 D_801848E4;\n /* \u00a75a cross-jump alias (replaces the memory barrier that used to sit in the >=0x6A4 arm).\n * Both the >=0x6A4 and the >=0x384 arm take the address of D_80184A70, so their blocks are the\n * identical pair `la a0,D_80184A70 / j ` and jump2's cross-jumper merges them (jump.c:1969).\n * find_cross_jump compares the two SYMBOL_REFs with rtx_renumbered_equal_p, which tests the name\n * STRING POINTERS (jump.c:2440 `case SYMBOL_REF: return XSTR (x, 0) == XSTR (y, 0);`), so a second\n * declaration of the same symbol under its own asm label gives the first arm a distinct string and\n * the two blocks stay separate. Same bytes, same R_MIPS_HI16/LO16 D_80184A70 relocations. */\n extern u8 aD8018C944 __asm__(\"D_80184A70\");\n s32 v;\n void *p;\n\n v = func_80029504();\n if (v >= 0x6A4) {\n p = &aD8018C944;\n } else if (v >= 0x5DC) {\n p = &D_80184950;\n } else if (v >= 0x578) {\n p = &D_8018492C;\n } else if (v >= 0x514) {\n p = &D_80184908;\n } else if (v >= 0x384) {\n p = &D_80184A70;\n } else if (v >= 0x258) {\n p = &D_80184A4C;\n } else if (v >= 0xC8) {\n p = &D_80184A28;\n } else if (v >= 0xA) {\n p = &D_80184A04;\n } else {\n p = &D_801848E4;\n }\n ((void (*)(void *))func_800D185C)(p);\n func_80145B24();\n}\n"} +{"ts": "2026-09-10 18:08:15", "label": "c38", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c", "fn": "func_80180EDC", "addr": 2149060316, "aliases": null, "header": false, "includers": 0, "nhash_before": "e8b18c0dbf1bc7eaf159f128b24c18c22f1807e8", "nhash_after": "cd53a23c023330ac560806eb55f46b30add0cec5", "source": "T7 agent c38", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.215, "objects": ["build/src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.o"], "before_text": "void func_80180EDC(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n s32 v0;\n register s32 v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus7)\n\n v0 = D_80078EB1;\n if (!(v0 < a1)) {\n if (v0 < a2) {\n v0 = 1;\n v1 = *(s32 *)((s32)a0 + 0xCC);\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n *(s32 *)(v1 + 0xB0) = v0;\n}\n", "after_text": "void func_80180EDC(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n\n if (D_80078EB1 >= a1 && D_80078EB1 < a2) {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1;\n } else {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2;\n }\n}\n"} +{"ts": "2026-09-10 18:08:17", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC05_018/ov_SC05_018_jr_8017D604.c", "fn": "func_80184554", "addr": 2149074260, "aliases": null, "header": false, "includers": 0, "nhash_before": "e8b18c0dbf1bc7eaf159f128b24c18c22f1807e8", "nhash_after": "cd53a23c023330ac560806eb55f46b30add0cec5", "source": "propagate:src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c:func_80180EDC", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.228, "objects": ["build/src/ov_SC05_018/ov_SC05_018_jr_8017D604.o"], "before_text": "void func_80184554(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n s32 v0;\n register s32 v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n\n v0 = D_80078EB1;\n if (!(v0 < a1)) {\n if (v0 < a2) {\n v0 = 1;\n v1 = *(s32 *)((s32)a0 + 0xCC);\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n *(s32 *)(v1 + 0xB0) = v0;\n}\n", "after_text": "void func_80184554(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n\n if (D_80078EB1 >= a1 && D_80078EB1 < a2) {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1;\n } else {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2;\n }\n}\n"} +{"ts": "2026-09-10 18:08:17", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_125/ov_SC03_125_jr_8017D604.c", "fn": "func_801819A0", "addr": 2149063072, "aliases": null, "header": false, "includers": 0, "nhash_before": "e8b18c0dbf1bc7eaf159f128b24c18c22f1807e8", "nhash_after": "cd53a23c023330ac560806eb55f46b30add0cec5", "source": "propagate:src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c:func_80180EDC", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.168, "objects": ["build/src/ov_SC03_125/ov_SC03_125_jr_8017D604.o"], "before_text": "void func_801819A0(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n s32 v0;\n register s32 v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n\n v0 = D_80078EB1;\n if (!(v0 < a1)) {\n if (v0 < a2) {\n v0 = 1;\n v1 = *(s32 *)((s32)a0 + 0xCC);\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n *(s32 *)(v1 + 0xB0) = v0;\n}\n", "after_text": "void func_801819A0(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n\n if (D_80078EB1 >= a1 && D_80078EB1 < a2) {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1;\n } else {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2;\n }\n}\n"} +{"ts": "2026-09-10 18:08:18", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_020/ov_SC04_020_jr_8017D604.c", "fn": "func_8018134C", "addr": 2149061452, "aliases": null, "header": false, "includers": 0, "nhash_before": "e8b18c0dbf1bc7eaf159f128b24c18c22f1807e8", "nhash_after": "cd53a23c023330ac560806eb55f46b30add0cec5", "source": "propagate:src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c:func_80180EDC", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.165, "objects": ["build/src/ov_SC04_020/ov_SC04_020_jr_8017D604.o"], "before_text": "void func_8018134C(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n s32 v0;\n register s32 v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n\n v0 = D_80078EB1;\n if (!(v0 < a1)) {\n if (v0 < a2) {\n v0 = 1;\n v1 = *(s32 *)((s32)a0 + 0xCC);\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n *(s32 *)(v1 + 0xB0) = v0;\n}\n", "after_text": "void func_8018134C(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n\n if (D_80078EB1 >= a1 && D_80078EB1 < a2) {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1;\n } else {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2;\n }\n}\n"} +{"ts": "2026-09-10 18:08:18", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_124/ov_SC03_124_jr_80181B44.c", "fn": "func_80184298", "addr": 2149073560, "aliases": null, "header": false, "includers": 0, "nhash_before": "e8b18c0dbf1bc7eaf159f128b24c18c22f1807e8", "nhash_after": "cd53a23c023330ac560806eb55f46b30add0cec5", "source": "propagate:src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c:func_80180EDC", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.13, "objects": ["build/src/ov_SC03_124/ov_SC03_124_jr_80181B44.o"], "before_text": "void func_80184298(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n s32 v0;\n register s32 v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n v0 = D_80078EB1;\n if (!(v0 < a1)) {\n if (v0 < a2) {\n v0 = 1;\n v1 = *(s32 *)((s32)a0 + 0xCC);\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n *(s32 *)(v1 + 0xB0) = v0;\n}\n", "after_text": "void func_80184298(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n\n if (D_80078EB1 >= a1 && D_80078EB1 < a2) {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1;\n } else {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2;\n }\n}\n"} +{"ts": "2026-09-10 18:08:18", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_002/ov_SC03_002_jr_80181D78.c", "fn": "func_8018311C", "addr": 2149069084, "aliases": null, "header": false, "includers": 0, "nhash_before": "e8b18c0dbf1bc7eaf159f128b24c18c22f1807e8", "nhash_after": "cd53a23c023330ac560806eb55f46b30add0cec5", "source": "propagate:src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c:func_80180EDC", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.096, "objects": ["build/src/ov_SC03_002/ov_SC03_002_jr_80181D78.o"], "before_text": "void func_8018311C(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n s32 v0;\n register s32 v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n v0 = D_80078EB1;\n if (!(v0 < a1)) {\n if (v0 < a2) {\n v0 = 1;\n v1 = *(s32 *)((s32)a0 + 0xCC);\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n *(s32 *)(v1 + 0xB0) = v0;\n}\n", "after_text": "void func_8018311C(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n\n if (D_80078EB1 >= a1 && D_80078EB1 < a2) {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1;\n } else {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2;\n }\n}\n"} +{"ts": "2026-09-10 18:08:19", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC05_017/ov_SC05_017_jr_80182A74.c", "fn": "func_80184870", "addr": 2149075056, "aliases": null, "header": false, "includers": 0, "nhash_before": "e8b18c0dbf1bc7eaf159f128b24c18c22f1807e8", "nhash_after": "cd53a23c023330ac560806eb55f46b30add0cec5", "source": "propagate:src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c:func_80180EDC", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.12, "objects": ["build/src/ov_SC05_017/ov_SC05_017_jr_80182A74.o"], "before_text": "void func_80184870(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n s32 v0;\n register s32 v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n v0 = D_80078EB1;\n if (!(v0 < a1)) {\n if (v0 < a2) {\n v0 = 1;\n v1 = *(s32 *)((s32)a0 + 0xCC);\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n *(s32 *)(v1 + 0xB0) = v0;\n}\n", "after_text": "void func_80184870(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n\n if (D_80078EB1 >= a1 && D_80078EB1 < a2) {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1;\n } else {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2;\n }\n}\n"} +{"ts": "2026-09-10 18:08:19", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_001/ov_SC03_001_jr_801870B0.c", "fn": "func_80187630", "addr": 2149086768, "aliases": null, "header": false, "includers": 0, "nhash_before": "e8b18c0dbf1bc7eaf159f128b24c18c22f1807e8", "nhash_after": "cd53a23c023330ac560806eb55f46b30add0cec5", "source": "propagate:src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c:func_80180EDC", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.082, "objects": ["build/src/ov_SC03_001/ov_SC03_001_jr_801870B0.o"], "before_text": "void func_80187630(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n s32 v0;\n register s32 v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n v0 = D_80078EB1;\n if (!(v0 < a1)) {\n if (v0 < a2) {\n v0 = 1;\n v1 = *(s32 *)((s32)a0 + 0xCC);\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n } else {\n v1 = *(s32 *)((s32)a0 + 0xCC);\n v0 = 2;\n }\n *(s32 *)(v1 + 0xB0) = v0;\n}\n", "after_text": "void func_80187630(void *a0, s32 a1, s32 a2)\n{\n\n extern u8 D_80078EB1;\n\n if (D_80078EB1 >= a1 && D_80078EB1 < a2) {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1;\n } else {\n *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2;\n }\n}\n"} +{"ts": "2026-09-10 18:08:21", "label": "c38", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_104/ov_SC03_104_jr_80182038.c", "fn": "func_8018431C", "addr": 2149073692, "aliases": null, "header": false, "includers": 0, "nhash_before": "b9da8061c7b02142ca66e8e7251a35cd83e5918e", "nhash_after": "09936842f3317d8910cf2204e2c1316ba9e76a82", "source": "T7 agent c38", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.143, "objects": ["build/src/ov_SC03_104/ov_SC03_104_jr_80182038.o"], "before_text": "void func_8018431C(void *a0)\n{\n extern s32 D_8019CAF4[];\n extern u8 D_8019CAE4[];\n extern u8 D_8019CA7C[];\n extern u8 D_8019CA7E[];\n extern u8 D_801C00F0[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_8019CAE4 + idx * 8;\n func_8001CB6C((u8 *)s1, D_8019CAF4[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n register u8 *dptr __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8001CF00(s1);\n dptr = D_801C00F0;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u32 *)(s1 + 0x20) = (s32)dptr;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(dptr, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_8019CA7C + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_8019CA7C + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_8019CA7E + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n", "after_text": "void func_8018431C(void *a0)\n{\n extern s32 D_8019CAF4[];\n extern u8 D_8019CAE4[];\n extern u8 D_8019CA7C[];\n extern u8 D_8019CA7E[];\n extern u8 D_801C00F0[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_8019CAE4 + idx * 8;\n func_8001CB6C((u8 *)s1, D_8019CAF4[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n func_8001CF00(s1);\n *(u32 *)(s1 + 0x20) = (s32)D_801C00F0;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(D_801C00F0, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_8019CA7C + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_8019CA7C + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_8019CA7E + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n"} +{"ts": "2026-09-10 18:08:23", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_028/ov_SC02_028_jr_8017D898.c", "fn": "func_801829BC", "addr": 2149067196, "aliases": null, "header": false, "includers": 0, "nhash_before": "b9da8061c7b02142ca66e8e7251a35cd83e5918e", "nhash_after": "09936842f3317d8910cf2204e2c1316ba9e76a82", "source": "propagate:src/ov_SC03_104/ov_SC03_104_jr_80182038.c:func_8018431C", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.201, "objects": ["build/src/ov_SC02_028/ov_SC02_028_jr_8017D898.o"], "before_text": "void func_801829BC(void *a0)\n{\n extern s32 D_801A4F84[];\n extern u8 D_801A4F74[];\n extern u8 D_801A4F0C[];\n extern u8 D_801A4F0E[];\n extern u8 D_801D3140[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_801A4F74 + idx * 8;\n func_8001CB6C((u8 *)s1, D_801A4F84[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n register u8 *dptr __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8001CF00(s1);\n dptr = D_801D3140;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u32 *)(s1 + 0x20) = (s32)dptr;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(dptr, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_801A4F0C + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_801A4F0C + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_801A4F0E + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n", "after_text": "void func_801829BC(void *a0)\n{\n extern s32 D_801A4F84[];\n extern u8 D_801A4F74[];\n extern u8 D_801A4F0C[];\n extern u8 D_801A4F0E[];\n extern u8 D_801D3140[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_801A4F74 + idx * 8;\n func_8001CB6C((u8 *)s1, D_801A4F84[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n func_8001CF00(s1);\n *(u32 *)(s1 + 0x20) = (s32)D_801D3140;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(D_801D3140, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_801A4F0C + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_801A4F0C + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_801A4F0E + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n"} +{"ts": "2026-09-10 18:08:23", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_097/ov_SC03_097_jr_8017D898.c", "fn": "func_80180980", "addr": 2149058944, "aliases": null, "header": false, "includers": 0, "nhash_before": "b9da8061c7b02142ca66e8e7251a35cd83e5918e", "nhash_after": "09936842f3317d8910cf2204e2c1316ba9e76a82", "source": "propagate:src/ov_SC03_104/ov_SC03_104_jr_80182038.c:func_8018431C", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.158, "objects": ["build/src/ov_SC03_097/ov_SC03_097_jr_8017D898.o"], "before_text": "void func_80180980(void *a0)\n{\n extern s32 D_8019AFC8[];\n extern u8 D_8019AFB8[];\n extern u8 D_8019AF50[];\n extern u8 D_8019AF52[];\n extern u8 D_801AAB20[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_8019AFB8 + idx * 8;\n func_8001CB6C((u8 *)s1, D_8019AFC8[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n register u8 *dptr __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8001CF00(s1);\n dptr = D_801AAB20;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u32 *)(s1 + 0x20) = (s32)dptr;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(dptr, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_8019AF50 + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_8019AF50 + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_8019AF52 + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n", "after_text": "void func_80180980(void *a0)\n{\n extern s32 D_8019AFC8[];\n extern u8 D_8019AFB8[];\n extern u8 D_8019AF50[];\n extern u8 D_8019AF52[];\n extern u8 D_801AAB20[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_8019AFB8 + idx * 8;\n func_8001CB6C((u8 *)s1, D_8019AFC8[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n func_8001CF00(s1);\n *(u32 *)(s1 + 0x20) = (s32)D_801AAB20;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(D_801AAB20, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_8019AF50 + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_8019AF50 + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_8019AF52 + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n"} +{"ts": "2026-09-10 18:08:24", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c", "fn": "func_80180EE0", "addr": 2149060320, "aliases": null, "header": false, "includers": 0, "nhash_before": "b9da8061c7b02142ca66e8e7251a35cd83e5918e", "nhash_after": "09936842f3317d8910cf2204e2c1316ba9e76a82", "source": "propagate:src/ov_SC03_104/ov_SC03_104_jr_80182038.c:func_8018431C", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.197, "objects": ["build/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.o"], "before_text": "void func_80180EE0(void *a0)\n{\n extern s32 D_8019AABC[];\n extern u8 D_8019AAAC[];\n extern u8 D_8019AA44[];\n extern u8 D_8019AA46[];\n extern u8 D_8019DD38[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_8019AAAC + idx * 8;\n func_8001CB6C((u8 *)s1, D_8019AABC[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n register u8 *dptr __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8001CF00(s1);\n dptr = D_8019DD38;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u32 *)(s1 + 0x20) = (s32)dptr;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(dptr, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_8019AA44 + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_8019AA44 + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_8019AA46 + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n", "after_text": "void func_80180EE0(void *a0)\n{\n extern s32 D_8019AABC[];\n extern u8 D_8019AAAC[];\n extern u8 D_8019AA44[];\n extern u8 D_8019AA46[];\n extern u8 D_8019DD38[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_8019AAAC + idx * 8;\n func_8001CB6C((u8 *)s1, D_8019AABC[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n func_8001CF00(s1);\n *(u32 *)(s1 + 0x20) = (s32)D_8019DD38;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(D_8019DD38, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_8019AA44 + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_8019AA44 + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_8019AA46 + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n"} +{"ts": "2026-09-10 18:08:24", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_090/ov_SC03_090_jr_80188274.c", "fn": "func_8018A5F4", "addr": 2149098996, "aliases": null, "header": false, "includers": 0, "nhash_before": "b9da8061c7b02142ca66e8e7251a35cd83e5918e", "nhash_after": "09936842f3317d8910cf2204e2c1316ba9e76a82", "source": "propagate:src/ov_SC03_104/ov_SC03_104_jr_80182038.c:func_8018431C", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.122, "objects": ["build/src/ov_SC03_090/ov_SC03_090_jr_80188274.o"], "before_text": "void func_8018A5F4(void *a0)\n{\n extern s32 D_801C9078[];\n extern u8 D_801C9068[];\n extern u8 D_801C9000[];\n extern u8 D_801C9002[];\n extern u8 D_801CBBE0[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_801C9068 + idx * 8;\n func_8001CB6C((u8 *)s1, D_801C9078[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n register u8 *dptr __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8001CF00(s1);\n dptr = D_801CBBE0;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u32 *)(s1 + 0x20) = (s32)dptr;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(dptr, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_801C9000 + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_801C9000 + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_801C9002 + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n", "after_text": "void func_8018A5F4(void *a0)\n{\n extern s32 D_801C9078[];\n extern u8 D_801C9068[];\n extern u8 D_801C9000[];\n extern u8 D_801C9002[];\n extern u8 D_801CBBE0[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_801C9068 + idx * 8;\n func_8001CB6C((u8 *)s1, D_801C9078[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n func_8001CF00(s1);\n *(u32 *)(s1 + 0x20) = (s32)D_801CBBE0;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(D_801CBBE0, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_801C9000 + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_801C9000 + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_801C9002 + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n"} +{"ts": "2026-09-10 18:08:24", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_089/ov_SC03_089_jr_80185E50.c", "fn": "func_801881D0", "addr": 2149089744, "aliases": null, "header": false, "includers": 0, "nhash_before": "b9da8061c7b02142ca66e8e7251a35cd83e5918e", "nhash_after": "09936842f3317d8910cf2204e2c1316ba9e76a82", "source": "propagate:src/ov_SC03_104/ov_SC03_104_jr_80182038.c:func_8018431C", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.121, "objects": ["build/src/ov_SC03_089/ov_SC03_089_jr_80185E50.o"], "before_text": "void func_801881D0(void *a0)\n{\n extern s32 D_801C3C0C[];\n extern u8 D_801C3BFC[];\n extern u8 D_801C3B94[];\n extern u8 D_801C3B96[];\n extern u8 D_801C6770[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_801C3BFC + idx * 8;\n func_8001CB6C((u8 *)s1, D_801C3C0C[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n register u8 *dptr __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8001CF00(s1);\n dptr = D_801C6770;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u32 *)(s1 + 0x20) = (s32)dptr;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(dptr, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_801C3B94 + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_801C3B94 + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_801C3B96 + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n", "after_text": "void func_801881D0(void *a0)\n{\n extern s32 D_801C3C0C[];\n extern u8 D_801C3BFC[];\n extern u8 D_801C3B94[];\n extern u8 D_801C3B96[];\n extern u8 D_801C6770[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_801C3BFC + idx * 8;\n func_8001CB6C((u8 *)s1, D_801C3C0C[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n func_8001CF00(s1);\n *(u32 *)(s1 + 0x20) = (s32)D_801C6770;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(D_801C6770, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_801C3B94 + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_801C3B94 + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_801C3B96 + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n"} +{"ts": "2026-09-10 18:08:25", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_091/ov_SC03_091_jr_8018911C.c", "fn": "func_8018B49C", "addr": 2149102748, "aliases": null, "header": false, "includers": 0, "nhash_before": "b9da8061c7b02142ca66e8e7251a35cd83e5918e", "nhash_after": "09936842f3317d8910cf2204e2c1316ba9e76a82", "source": "propagate:src/ov_SC03_104/ov_SC03_104_jr_80182038.c:func_8018431C", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.124, "objects": ["build/src/ov_SC03_091/ov_SC03_091_jr_8018911C.o"], "before_text": "void func_8018B49C(void *a0)\n{\n extern s32 D_801CC0A4[];\n extern u8 D_801CC094[];\n extern u8 D_801CC02C[];\n extern u8 D_801CC02E[];\n extern u8 D_801D2530[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_801CC094 + idx * 8;\n func_8001CB6C((u8 *)s1, D_801CC0A4[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n register u8 *dptr __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8001CF00(s1);\n dptr = D_801D2530;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u32 *)(s1 + 0x20) = (s32)dptr;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(dptr, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_801CC02C + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_801CC02C + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_801CC02E + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n", "after_text": "void func_8018B49C(void *a0)\n{\n extern s32 D_801CC0A4[];\n extern u8 D_801CC094[];\n extern u8 D_801CC02C[];\n extern u8 D_801CC02E[];\n extern u8 D_801D2530[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_801CC094 + idx * 8;\n func_8001CB6C((u8 *)s1, D_801CC0A4[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n func_8001CF00(s1);\n *(u32 *)(s1 + 0x20) = (s32)D_801D2530;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(D_801D2530, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_801CC02C + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_801CC02C + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_801CC02E + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n"} +{"ts": "2026-09-10 18:08:25", "label": "c38p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_092/ov_SC03_092_jr_80181694.c", "fn": "func_80183D58", "addr": 2149072216, "aliases": null, "header": false, "includers": 0, "nhash_before": "b9da8061c7b02142ca66e8e7251a35cd83e5918e", "nhash_after": "09936842f3317d8910cf2204e2c1316ba9e76a82", "source": "propagate:src/ov_SC03_104/ov_SC03_104_jr_80182038.c:func_8018431C", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.124, "objects": ["build/src/ov_SC03_092/ov_SC03_092_jr_80181694.o"], "before_text": "void func_80183D58(void *a0)\n{\n extern s32 D_801B03E4[];\n extern u8 D_801B03D4[];\n extern u8 D_801B036C[];\n extern u8 D_801B036E[];\n extern u8 D_801B2ED8[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_801B03D4 + idx * 8;\n func_8001CB6C((u8 *)s1, D_801B03E4[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n register u8 *dptr __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n func_8001CF00(s1);\n dptr = D_801B2ED8;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u32 *)(s1 + 0x20) = (s32)dptr;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(dptr, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_801B036C + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_801B036C + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_801B036E + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n", "after_text": "void func_80183D58(void *a0)\n{\n extern s32 D_801B03E4[];\n extern u8 D_801B03D4[];\n extern u8 D_801B036C[];\n extern u8 D_801B036E[];\n extern u8 D_801B2ED8[];\n\n s32 s2;\n s32 s1;\n u16 v0;\n s16 v1;\n s16 s0raw;\n\n s2 = (s32)a0;\n s1 = func_8012C194();\n if (s1 == 0) {\n func_8012CAE4((void *)s2);\n return;\n }\n\n v0 = *(u16 *)(s2 + 0x72);\n *(s32 *)(s2 + 0x20) = s1;\n v0 |= 0x1000;\n *(u16 *)(s2 + 0x72) = v0;\n v1 = *(s16 *)(s2 + 0x70);\n s0raw = v1;\n\n if ((v1 & 0x8000) != 0) {\n s32 idx;\n u8 *p;\n u16 b;\n\n idx = s0raw & 1;\n p = D_801B03D4 + idx * 8;\n func_8001CB6C((u8 *)s1, D_801B03E4[idx], *(s16 *)(p + 0), *(s16 *)(p + 2));\n b = *(u16 *)(p + 4);\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x2000;\n *(u16 *)(s1 + 0x18) = 0x2000;\n *(u8 *)(s1 + 0x27) = b;\n } else {\n func_8001CF00(s1);\n *(u32 *)(s1 + 0x20) = (s32)D_801B2ED8;\n *(u16 *)(s1 + 0x28) = 0x300;\n *(u16 *)(s1 + 0x2A) = 0x110;\n *(u8 *)(s1 + 0x27) = 0x78;\n *(u16 *)(s1 + 0x10) = 0x400;\n *(u16 *)(s1 + 0x1A) = 0x800;\n *(u16 *)(s1 + 0x18) = 0x800;\n\n if ((*(u16 *)(s2 + 0x70) & 3) == 0) {\n func_800233CC(D_801B2ED8, 0x80);\n }\n\n {\n u16 flags = *(u16 *)(s2 + 0x70);\n if ((flags & 1) != 0) {\n *(u16 *)(D_801B036C + (flags & 3) * 12) = 0x10;\n *(u16 *)(s1 + 0x14) = 0x400;\n goto shared_tail;\n }\n *(u16 *)(D_801B036C + (flags & 3) * 12) = 0x20;\n }\n\n *(u32 *)(s1 + 4) |= 0x40000000;\n\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n func_8002D4C8(0x701, 0);\n }\n if ((*(u16 *)(s2 + 0x70) & 0x2000) != 0) {\n s32 ret = func_800291B4(*(s16 *)(s2 + 0xFC));\n if ((ret & 0xFF) == 0) {\n *(u16 *)(s2 + 0x70) |= 0x4000;\n } else {\n *(u16 *)(s2 + 0x70) &= 0xDFFF;\n }\n }\n func_8012C658(0x1E1, (s16)(*(u16 *)(s2 + 0x70) | 1), s2);\n\n shared_tail:\n *(u16 *)(D_801B036E + ((*(u16 *)(s2 + 0x70)) & 3) * 12) = 0x20;\n if ((*(u16 *)(s2 + 0x70) & 0x4000) != 0) {\n *(u16 *)(s1 + 0x1A) = 0;\n *(u16 *)(s1 + 0x18) = 0;\n }\n }\n\n func_8012AD50((void *)s2);\n}\n"} +{"ts": "2026-09-10 18:08:28", "label": "c40", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c", "fn": "func_80185DD8", "addr": 2149080536, "aliases": null, "header": false, "includers": 0, "nhash_before": "52fc915d416a3c7c1fa8e425a623dffcc8cc6bee", "nhash_after": "58644c54c924f284e18e1306e3dfebebc2fbf3cf", "source": "T7 agent c40", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.298, "objects": ["build/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.o"], "before_text": "void func_80185DD8(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x, z;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_8018765C(a0) == 0) {\n func_801877E4(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n if (x < 0x105) {\n z = vecB[1];\n if (z >= 0) {\n if (z < 0xC9) {\n /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles\n * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z,\n * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare\n * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the\n * else arm). A zero-emission `__asm__ __volatile__(\"\":::\"memory\")` right\n * before this `return` is a scheduling/combine barrier that blocks whatever\n * RTL-level pass performs that merge, without adding a single byte itself --\n * the compiled result is byte-exact target. Byte-proven via 9 probe variants\n * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled\n * return) that ALL either fully merged or left a redundant extra sign-retest;\n * only this barrier reproduces the target exactly. See match_one MATCH 96/96.\n */\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return;\n }\n } else {\n if (-z < 0xC9) {\n return;\n }\n }\n }\n func_8012C098((void *)a0);\n}\n", "after_text": "void func_80185DD8(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_8018765C(a0) == 0) {\n func_801877E4(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch,\n * so the two `slti 201` tails are not one value-converged abs (the x test above is). */\n if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) {\n func_8012C098((void *)a0);\n }\n}\n"} +{"ts": "2026-09-10 18:08:29", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c", "fn": "func_80180B7C", "addr": 2149059452, "aliases": null, "header": false, "includers": 0, "nhash_before": "52fc915d416a3c7c1fa8e425a623dffcc8cc6bee", "nhash_after": "58644c54c924f284e18e1306e3dfebebc2fbf3cf", "source": "propagate:src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c:func_80185DD8", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.165, "objects": ["build/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.o"], "before_text": "void func_80180B7C(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x, z;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_80182400(a0) == 0) {\n func_80182588(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n if (x < 0x105) {\n z = vecB[1];\n if (z >= 0) {\n if (z < 0xC9) {\n /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles\n * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z,\n * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare\n * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the\n * else arm). A zero-emission `__asm__ __volatile__(\"\":::\"memory\")` right\n * before this `return` is a scheduling/combine barrier that blocks whatever\n * RTL-level pass performs that merge, without adding a single byte itself --\n * the compiled result is byte-exact target. Byte-proven via 9 probe variants\n * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled\n * return) that ALL either fully merged or left a redundant extra sign-retest;\n * only this barrier reproduces the target exactly. See match_one MATCH 96/96.\n */\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return;\n }\n } else {\n if (-z < 0xC9) {\n return;\n }\n }\n }\n func_8012C098((void *)a0);\n}\n", "after_text": "void func_80180B7C(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_80182400(a0) == 0) {\n func_80182588(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch,\n * so the two `slti 201` tails are not one value-converged abs (the x test above is). */\n if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) {\n func_8012C098((void *)a0);\n }\n}\n"} +{"ts": "2026-09-10 18:08:30", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c", "fn": "func_8017FF48", "addr": 2149056328, "aliases": null, "header": false, "includers": 0, "nhash_before": "52fc915d416a3c7c1fa8e425a623dffcc8cc6bee", "nhash_after": "58644c54c924f284e18e1306e3dfebebc2fbf3cf", "source": "propagate:src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c:func_80185DD8", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.142, "objects": ["build/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.o"], "before_text": "void func_8017FF48(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x, z;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_801817CC(a0) == 0) {\n func_80181954(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n if (x < 0x105) {\n z = vecB[1];\n if (z >= 0) {\n if (z < 0xC9) {\n /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles\n * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z,\n * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare\n * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the\n * else arm). A zero-emission `__asm__ __volatile__(\"\":::\"memory\")` right\n * before this `return` is a scheduling/combine barrier that blocks whatever\n * RTL-level pass performs that merge, without adding a single byte itself --\n * the compiled result is byte-exact target. Byte-proven via 9 probe variants\n * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled\n * return) that ALL either fully merged or left a redundant extra sign-retest;\n * only this barrier reproduces the target exactly. See match_one MATCH 96/96.\n */\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return;\n }\n } else {\n if (-z < 0xC9) {\n return;\n }\n }\n }\n func_8012C098((void *)a0);\n}\n", "after_text": "void func_8017FF48(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_801817CC(a0) == 0) {\n func_80181954(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch,\n * so the two `slti 201` tails are not one value-converged abs (the x test above is). */\n if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) {\n func_8012C098((void *)a0);\n }\n}\n"} +{"ts": "2026-09-10 18:08:30", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_022/ov_SC06_022_jr_80182D08.c", "fn": "func_80183E6C", "addr": 2149072492, "aliases": null, "header": false, "includers": 0, "nhash_before": "52fc915d416a3c7c1fa8e425a623dffcc8cc6bee", "nhash_after": "58644c54c924f284e18e1306e3dfebebc2fbf3cf", "source": "propagate:src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c:func_80185DD8", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.079, "objects": ["build/src/ov_SC06_022/ov_SC06_022_jr_80182D08.o"], "before_text": "void func_80183E6C(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x, z;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_801856F0(a0) == 0) {\n func_80185878(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n if (x < 0x105) {\n z = vecB[1];\n if (z >= 0) {\n if (z < 0xC9) {\n /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles\n * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z,\n * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare\n * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the\n * else arm). A zero-emission `__asm__ __volatile__(\"\":::\"memory\")` right\n * before this `return` is a scheduling/combine barrier that blocks whatever\n * RTL-level pass performs that merge, without adding a single byte itself --\n * the compiled result is byte-exact target. Byte-proven via 9 probe variants\n * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled\n * return) that ALL either fully merged or left a redundant extra sign-retest;\n * only this barrier reproduces the target exactly. See match_one MATCH 96/96.\n */\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return;\n }\n } else {\n if (-z < 0xC9) {\n return;\n }\n }\n }\n func_8012C098((void *)a0);\n}\n", "after_text": "void func_80183E6C(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_801856F0(a0) == 0) {\n func_80185878(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch,\n * so the two `slti 201` tails are not one value-converged abs (the x test above is). */\n if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) {\n func_8012C098((void *)a0);\n }\n}\n"} +{"ts": "2026-09-10 18:08:30", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_024/ov_SC06_024_jr_801851E0.c", "fn": "func_80186344", "addr": 2149081924, "aliases": null, "header": false, "includers": 0, "nhash_before": "52fc915d416a3c7c1fa8e425a623dffcc8cc6bee", "nhash_after": "58644c54c924f284e18e1306e3dfebebc2fbf3cf", "source": "propagate:src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c:func_80185DD8", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.077, "objects": ["build/src/ov_SC06_024/ov_SC06_024_jr_801851E0.o"], "before_text": "void func_80186344(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x, z;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_80187BC8(a0) == 0) {\n func_80187D50(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n if (x < 0x105) {\n z = vecB[1];\n if (z >= 0) {\n if (z < 0xC9) {\n /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles\n * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z,\n * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare\n * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the\n * else arm). A zero-emission `__asm__ __volatile__(\"\":::\"memory\")` right\n * before this `return` is a scheduling/combine barrier that blocks whatever\n * RTL-level pass performs that merge, without adding a single byte itself --\n * the compiled result is byte-exact target. Byte-proven via 9 probe variants\n * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled\n * return) that ALL either fully merged or left a redundant extra sign-retest;\n * only this barrier reproduces the target exactly. See match_one MATCH 96/96.\n */\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return;\n }\n } else {\n if (-z < 0xC9) {\n return;\n }\n }\n }\n func_8012C098((void *)a0);\n}\n", "after_text": "void func_80186344(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_80187BC8(a0) == 0) {\n func_80187D50(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch,\n * so the two `slti 201` tails are not one value-converged abs (the x test above is). */\n if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) {\n func_8012C098((void *)a0);\n }\n}\n"} +{"ts": "2026-09-10 18:08:30", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_033/ov_SC06_033_jr_801836FC.c", "fn": "func_80184860", "addr": 2149075040, "aliases": null, "header": false, "includers": 0, "nhash_before": "52fc915d416a3c7c1fa8e425a623dffcc8cc6bee", "nhash_after": "58644c54c924f284e18e1306e3dfebebc2fbf3cf", "source": "propagate:src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c:func_80185DD8", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.085, "objects": ["build/src/ov_SC06_033/ov_SC06_033_jr_801836FC.o"], "before_text": "void func_80184860(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x, z;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_801860E4(a0) == 0) {\n func_8018626C(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n if (x < 0x105) {\n z = vecB[1];\n if (z >= 0) {\n if (z < 0xC9) {\n /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles\n * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z,\n * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare\n * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the\n * else arm). A zero-emission `__asm__ __volatile__(\"\":::\"memory\")` right\n * before this `return` is a scheduling/combine barrier that blocks whatever\n * RTL-level pass performs that merge, without adding a single byte itself --\n * the compiled result is byte-exact target. Byte-proven via 9 probe variants\n * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled\n * return) that ALL either fully merged or left a redundant extra sign-retest;\n * only this barrier reproduces the target exactly. See match_one MATCH 96/96.\n */\n __asm__ __volatile__(\"\" ::: \"memory\"); // !FAKE: barrier memory \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return;\n }\n } else {\n if (-z < 0xC9) {\n return;\n }\n }\n }\n func_8012C098((void *)a0);\n}\n", "after_text": "void func_80184860(s32 a0) {\n s32 r;\n s16 vecA[4];\n s16 vecB[4];\n s32 x;\n\n if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) {\n s32 ret = ((s32 (*)(s32))func_8012BE54)(a0);\n if (ret <= 0x63FFF) {\n if (func_8012BEE8(a0) != 0) {\n s32 t;\n s32 rr;\n\n t = func_8012B8A4((s16 *)a0);\n *(u32 *)(a0 + 0xE8) = (t + 0x800) & 0xFFF;\n rr = rand();\n *(s32 *)(a0 + 0x1C) = rr % 0x40 + 0x40;\n }\n }\n }\n\n r = func_8012B608((s32) * (s16 *)(*(s32 *)(a0 + 0x20) + 0x12), *(s32 *)(a0 + 0xE8), 8);\n *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) + r;\n\n *(u32 *)(a0 + 0xE0) &= 0xFFFFFFBF;\n func_8012B178(a0, 0xFFF8D000);\n\n if (func_801860E4(a0) == 0) {\n func_8018626C(a0);\n }\n\n vecA[0] = *(s16 *)(a0 + 0x6);\n vecA[1] = *(s16 *)(a0 + 0xA);\n vecA[2] = *(s16 *)(a0 + 0xE);\n ((s32 (*)(void *, void *))func_8012EFB8)(vecA, vecB);\n\n x = vecB[0];\n if (x < 0) {\n x = -x;\n }\n /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch,\n * so the two `slti 201` tails are not one value-converged abs (the x test above is). */\n if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) {\n func_8012C098((void *)a0);\n }\n}\n"} +{"ts": "2026-09-10 18:08:32", "label": "c40", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_002/ov_SC03_002_jr_8018431C.c", "fn": "func_80184854", "addr": 2149075028, "aliases": null, "header": false, "includers": 0, "nhash_before": "ab02047dfdd6f5e359fa63b1ece91fdec0971e1f", "nhash_after": "9b515b1117939aa896767ac9b4b1c5ac07a2f77a", "source": "T7 agent c40", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.074, "objects": ["build/src/ov_SC03_002/ov_SC03_002_jr_8018431C.o"], "before_text": "s32 func_80184854(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n if (p != end) {\n do {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80184960((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n __asm__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return 1;\n }\n }\n }\n p += 0x10C;\n } while (p != end);\n }\n return 0;\n}\n", "after_text": "s32 func_80184854(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n for (; p != end; p += 0x10C) {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80184960((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n return 1;\n }\n }\n }\n }\n return 0;\n}\n"} +{"ts": "2026-09-10 18:08:34", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_125/ov_SC03_125_jr_80182BA0.c", "fn": "func_801830D8", "addr": 2149069016, "aliases": null, "header": false, "includers": 0, "nhash_before": "ab02047dfdd6f5e359fa63b1ece91fdec0971e1f", "nhash_after": "9b515b1117939aa896767ac9b4b1c5ac07a2f77a", "source": "propagate:src/ov_SC03_002/ov_SC03_002_jr_8018431C.c:func_80184854", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.072, "objects": ["build/src/ov_SC03_125/ov_SC03_125_jr_80182BA0.o"], "before_text": "s32 func_801830D8(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n if (p != end) {\n do {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_801831E4((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n __asm__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return 1;\n }\n }\n }\n p += 0x10C;\n } while (p != end);\n }\n return 0;\n}\n", "after_text": "s32 func_801830D8(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n for (; p != end; p += 0x10C) {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_801831E4((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n return 1;\n }\n }\n }\n }\n return 0;\n}\n"} +{"ts": "2026-09-10 18:08:34", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_001/ov_SC03_001_jr_80188830.c", "fn": "func_80188D68", "addr": 2149092712, "aliases": null, "header": false, "includers": 0, "nhash_before": "ab02047dfdd6f5e359fa63b1ece91fdec0971e1f", "nhash_after": "9b515b1117939aa896767ac9b4b1c5ac07a2f77a", "source": "propagate:src/ov_SC03_002/ov_SC03_002_jr_8018431C.c:func_80184854", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.054, "objects": ["build/src/ov_SC03_001/ov_SC03_001_jr_80188830.o"], "before_text": "s32 func_80188D68(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n if (p != end) {\n do {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80188E74((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n __asm__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return 1;\n }\n }\n }\n p += 0x10C;\n } while (p != end);\n }\n return 0;\n}\n", "after_text": "s32 func_80188D68(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n for (; p != end; p += 0x10C) {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80188E74((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n return 1;\n }\n }\n }\n }\n return 0;\n}\n"} +{"ts": "2026-09-10 18:08:34", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_124/ov_SC03_124_jr_80185498.c", "fn": "func_801859D0", "addr": 2149079504, "aliases": null, "header": false, "includers": 0, "nhash_before": "ab02047dfdd6f5e359fa63b1ece91fdec0971e1f", "nhash_after": "9b515b1117939aa896767ac9b4b1c5ac07a2f77a", "source": "propagate:src/ov_SC03_002/ov_SC03_002_jr_8018431C.c:func_80184854", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.058, "objects": ["build/src/ov_SC03_124/ov_SC03_124_jr_80185498.o"], "before_text": "s32 func_801859D0(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n if (p != end) {\n do {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80185ADC((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n __asm__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return 1;\n }\n }\n }\n p += 0x10C;\n } while (p != end);\n }\n return 0;\n}\n", "after_text": "s32 func_801859D0(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n for (; p != end; p += 0x10C) {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80185ADC((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n return 1;\n }\n }\n }\n }\n return 0;\n}\n"} +{"ts": "2026-09-10 18:08:35", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC05_017/ov_SC05_017_jr_80185A70.c", "fn": "func_80185FA8", "addr": 2149081000, "aliases": null, "header": false, "includers": 0, "nhash_before": "ab02047dfdd6f5e359fa63b1ece91fdec0971e1f", "nhash_after": "9b515b1117939aa896767ac9b4b1c5ac07a2f77a", "source": "propagate:src/ov_SC03_002/ov_SC03_002_jr_8018431C.c:func_80184854", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.055, "objects": ["build/src/ov_SC05_017/ov_SC05_017_jr_80185A70.o"], "before_text": "s32 func_80185FA8(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n if (p != end) {\n do {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_801860B4((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n __asm__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return 1;\n }\n }\n }\n p += 0x10C;\n } while (p != end);\n }\n return 0;\n}\n", "after_text": "s32 func_80185FA8(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n for (; p != end; p += 0x10C) {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_801860B4((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n return 1;\n }\n }\n }\n }\n return 0;\n}\n"} +{"ts": "2026-09-10 18:08:35", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC05_018/ov_SC05_018_jr_80185754.c", "fn": "func_80185C8C", "addr": 2149080204, "aliases": null, "header": false, "includers": 0, "nhash_before": "ab02047dfdd6f5e359fa63b1ece91fdec0971e1f", "nhash_after": "9b515b1117939aa896767ac9b4b1c5ac07a2f77a", "source": "propagate:src/ov_SC03_002/ov_SC03_002_jr_8018431C.c:func_80184854", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.075, "objects": ["build/src/ov_SC05_018/ov_SC05_018_jr_80185754.o"], "before_text": "s32 func_80185C8C(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n if (p != end) {\n do {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80185D98((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n __asm__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return 1;\n }\n }\n }\n p += 0x10C;\n } while (p != end);\n }\n return 0;\n}\n", "after_text": "s32 func_80185C8C(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n for (; p != end; p += 0x10C) {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80185D98((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n return 1;\n }\n }\n }\n }\n return 0;\n}\n"} +{"ts": "2026-09-10 18:08:35", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_015/ov_SC04_015_jr_801820DC.c", "fn": "func_80182614", "addr": 2149066260, "aliases": null, "header": false, "includers": 0, "nhash_before": "ab02047dfdd6f5e359fa63b1ece91fdec0971e1f", "nhash_after": "9b515b1117939aa896767ac9b4b1c5ac07a2f77a", "source": "propagate:src/ov_SC03_002/ov_SC03_002_jr_8018431C.c:func_80184854", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.097, "objects": ["build/src/ov_SC04_015/ov_SC04_015_jr_801820DC.o"], "before_text": "s32 func_80182614(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n if (p != end) {\n do {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80182720((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n __asm__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return 1;\n }\n }\n }\n p += 0x10C;\n } while (p != end);\n }\n return 0;\n}\n", "after_text": "s32 func_80182614(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n for (; p != end; p += 0x10C) {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80182720((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n return 1;\n }\n }\n }\n }\n return 0;\n}\n"} +{"ts": "2026-09-10 18:08:35", "label": "c40p", "rung": "E", "calib": {"head": "321b540e7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_020/ov_SC04_020_jr_8018254C.c", "fn": "func_80182A84", "addr": 2149067396, "aliases": null, "header": false, "includers": 0, "nhash_before": "ab02047dfdd6f5e359fa63b1ece91fdec0971e1f", "nhash_after": "9b515b1117939aa896767ac9b4b1c5ac07a2f77a", "source": "propagate:src/ov_SC03_002/ov_SC03_002_jr_8018431C.c:func_80184854", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.066, "objects": ["build/src/ov_SC04_020/ov_SC04_020_jr_8018254C.o"], "before_text": "s32 func_80182A84(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n if (p != end) {\n do {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80182B90((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n __asm__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n return 1;\n }\n }\n }\n p += 0x10C;\n } while (p != end);\n }\n return 0;\n}\n", "after_text": "s32 func_80182A84(void *a0) {\n\n extern u8 D_801202A0[];\n u8 *p;\n u8 *end;\n s32 t;\n u16 tag;\n s16 out[3];\n s16 in[3];\n\n p = D_801202A0;\n end = p + 0x6480;\n for (; p != end; p += 0x10C) {\n tag = *(u16 *)p;\n if (tag != 0 && tag != 0x61 && func_80182B90((s32)p) != 0) {\n t = *(s32 *)(p + 0x20);\n if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) {\n in[0] = *(u16 *)(p + 0x6);\n in[1] = *(u16 *)(p + 0xA);\n in[2] = *(u16 *)(p + 0xE);\n func_8012F2E8((s32)a0, (s32)in, (s32)out);\n if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) {\n return 1;\n }\n }\n }\n }\n return 0;\n}\n"} diff --git a/docs/lever-progress.tsv b/docs/lever-progress.tsv index ceb87f9336..d04e090800 100644 --- a/docs/lever-progress.tsv +++ b/docs/lever-progress.tsv @@ -46,3 +46,4 @@ date milestone head sites_AB pins asm bodies_AB distinct_AB marked unmarked gte_ 2026-09-10 S103: c33 func_80169058 + func_80168D94 (12 bodies) a2a1fc186 12531 7236 5295 3303 1211 12531 0 462 314 1590 50 7680 445 76 2026-09-10 S103: c36 + c35 (four ov_SC07_006/ov_SC06_010 classes, 39 bodies); R19 reads cast arity dd5e44c24 12481 7186 5295 3260 1207 12481 0 462 314 1590 50 7680 445 76 2026-09-10 S103: extern-variant re-propagation (97), R19 cast regen (8 classes), c39 + c41 + c34 + c32 closes 7d5964b27 12033 6926 5107 3090 1164 12033 0 462 314 1590 50 7688 445 76 +2026-09-10 S103: c38 + c40 (four tier classes, 30 bodies) 321b540e7 12003 6910 5093 3060 1160 12003 0 462 314 1590 50 7688 445 76 diff --git a/docs/levers.md b/docs/levers.md index fbc727c63b..c22110a33a 100644 --- a/docs/levers.md +++ b/docs/levers.md @@ -92,6 +92,7 @@ counted, not marked). E, F and G belong to the canonical type layer and are the | 2026-09-10 | S103: c33 func_80169058 + func_80168D94 (12 bodies) | 7236 | 5295 | **12531** | 3303 | 1211 | 462 | 314 | 1590 | 50 | 7680 | 445 | 76 | `a2a1fc186` | | 2026-09-10 | S103: c36 + c35 (four ov_SC07_006/ov_SC06_010 classes, 39 bodies); R19 reads cast arity | 7186 | 5295 | **12481** | 3260 | 1207 | 462 | 314 | 1590 | 50 | 7680 | 445 | 76 | `dd5e44c24` | | 2026-09-10 | S103: extern-variant re-propagation (97), R19 cast regen (8 classes), c39 + c41 + c34 + c32 closes | 6926 | 5107 | **12033** | 3090 | 1164 | 462 | 314 | 1590 | 50 | 7688 | 445 | 76 | `7d5964b27` | +| 2026-09-10 | S103: c38 + c40 (four tier classes, 30 bodies) | 6910 | 5093 | **12003** | 3060 | 1160 | 462 | 314 | 1590 | 50 | 7688 | 445 | 76 | `321b540e7` | ### The campaign — every batch, from the ledger (derived on every render) @@ -259,7 +260,11 @@ counted, not marked). E, F and G belong to the canonical type layer and are the | `s103_r19castp` | 2026-09-10 | E | 0 | 0 | 0 | 8 | 4 | | `c41` | 2026-09-10 | E | 0 | 0 | 0 | 2 | 1 | | `c41p` | 2026-09-10 | E | 0 | 0 | 0 | 27 | 17 | -| **total** | | | **17,119** | **20,778** | **283** | **22,387** | **9,646** | +| `c38` | 2026-09-10 | E | 0 | 0 | 0 | 2 | 2 | +| `c38p` | 2026-09-10 | E | 0 | 0 | 0 | 14 | 14 | +| `c40` | 2026-09-10 | E | 0 | 0 | 0 | 2 | 2 | +| `c40p` | 2026-09-10 | E | 0 | 0 | 0 | 12 | 12 | +| **total** | | | **17,119** | **20,778** | **283** | **22,417** | **9,676** | *Generated by `tools/lever_progress.py --render` from `.run/P36/census/lever_census.json` and `.run/P36/delever/ledger.jsonl`; the series lives in `docs/lever-progress.tsv` (R75: published numbers are generated, never typed).* diff --git a/phase-ends/CURRENT_PHASE.md b/phase-ends/CURRENT_PHASE.md index eb4d34122d..63dc691d0d 100644 --- a/phase-ends/CURRENT_PHASE.md +++ b/phase-ends/CURRENT_PHASE.md @@ -1684,6 +1684,16 @@ accumulate here as the phase produces them.** dead initialiser but through ONE variable holding two unrelated 8s (flagged by the agent itself as steering); the pre-loop order unclosable without raising `j`'s weight (sched1 rewrites `reg_live_length`, `sched.c:4947`; k 5270 vs j 4400, `global.c:587-609`). +- **S103 — c38: `func_80180EDC` (ov_SC04_015, 3 → 0; 7/7) and `func_8018431C` (ov_SC03_104, 4 → 0; 7/7); c40: + `func_80185DD8` (ov_SC06_018, 7 → 0; 5/5) and `func_80184854` (ov_SC03_002, 11 → 0; 7/7) CLOSED.** c38: a local that + carried a pointer to a join took a dying argument register's preference (`expand_preferences`, `global.c:781-821`) — + the store written in each arm (cross-jump re-merges it); a single-set `la` launched low by sched1 + (`birthing_insn_p`, `sched.c:2469/2489`) — its store moved to the head of the run (sched2 re-sorts the independent + stores, `sched.c:2616/2657-2670`). c40: a `?:` inside the branch condition (`do_jump`'s COND_EXPR, `expr.c:9124`) + gives each arm its own compare so jump's inversion (`jump.c:1737-1782`) and the cross-jump (`:2371`) find nothing to + merge; and a hand-rotated `if … do … while` written as a real `for` loop, whose `NOTE_INSN_LOOP_VTOP` + (`jump.c:2306`) makes reorg's `mostly_true_jump` predict taken (`reorg.c:1364-1372`) and fill the slot from the target. + Tools: `cc1_dumps_tu.sh` gains `-dd` (`.dbr`); METHOD notes `--keep`'s path is the LAST output line. - **S103 — packs for the next tier: `delever_pack --build --min-copies 5` → `64 packs under .run/P36/agents; ORDER.tsv written`** (the head-only ORDER kept as `ORDER_head.tsv`). The head (≥100 copies) is down to classes with honest readings; the tier below has several classes at a mechanical best of 1-2 — agents now take TWO small classes each. diff --git a/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c b/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c index f7b0d9c48b..b8598a22e3 100644 --- a/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c +++ b/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c @@ -5936,20 +5936,17 @@ void func_801829BC(void *a0) *(u16 *)(s1 + 0x18) = 0x2000; *(u8 *)(s1 + 0x27) = b; } else { - register u8 *dptr __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) - func_8001CF00(s1); - dptr = D_801D3140; + *(u32 *)(s1 + 0x20) = (s32)D_801D3140; *(u16 *)(s1 + 0x28) = 0x300; *(u16 *)(s1 + 0x2A) = 0x110; *(u8 *)(s1 + 0x27) = 0x78; - *(u32 *)(s1 + 0x20) = (s32)dptr; *(u16 *)(s1 + 0x10) = 0x400; *(u16 *)(s1 + 0x1A) = 0x800; *(u16 *)(s1 + 0x18) = 0x800; if ((*(u16 *)(s2 + 0x70) & 3) == 0) { - func_800233CC(dptr, 0x80); + func_800233CC(D_801D3140, 0x80); } { diff --git a/src/ov_SC03_001/ov_SC03_001_jr_801870B0.c b/src/ov_SC03_001/ov_SC03_001_jr_801870B0.c index 6dca1d3694..86ba5a18d3 100644 --- a/src/ov_SC03_001/ov_SC03_001_jr_801870B0.c +++ b/src/ov_SC03_001/ov_SC03_001_jr_801870B0.c @@ -3432,23 +3432,12 @@ void func_80187630(void *a0, s32 a1, s32 a2) { extern u8 D_80078EB1; - s32 v0; - register s32 v1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus9) - v0 = D_80078EB1; - if (!(v0 < a1)) { - if (v0 < a2) { - v0 = 1; - v1 = *(s32 *)((s32)a0 + 0xCC); - } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; - } + if (D_80078EB1 >= a1 && D_80078EB1 < a2) { + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1; } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2; } - *(s32 *)(v1 + 0xB0) = v0; } diff --git a/src/ov_SC03_001/ov_SC03_001_jr_80188830.c b/src/ov_SC03_001/ov_SC03_001_jr_80188830.c index 4904783ffc..17afef7ad1 100644 --- a/src/ov_SC03_001/ov_SC03_001_jr_80188830.c +++ b/src/ov_SC03_001/ov_SC03_001_jr_80188830.c @@ -3479,24 +3479,20 @@ s32 func_80188D68(void *a0) { p = D_801202A0; end = p + 0x6480; - if (p != end) { - do { - tag = *(u16 *)p; - if (tag != 0 && tag != 0x61 && func_80188E74((s32)p) != 0) { - t = *(s32 *)(p + 0x20); - if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { - in[0] = *(u16 *)(p + 0x6); - in[1] = *(u16 *)(p + 0xA); - in[2] = *(u16 *)(p + 0xE); - func_8012F2E8((s32)a0, (s32)in, (s32)out); - if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { - __asm__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) - return 1; - } + for (; p != end; p += 0x10C) { + tag = *(u16 *)p; + if (tag != 0 && tag != 0x61 && func_80188E74((s32)p) != 0) { + t = *(s32 *)(p + 0x20); + if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { + in[0] = *(u16 *)(p + 0x6); + in[1] = *(u16 *)(p + 0xA); + in[2] = *(u16 *)(p + 0xE); + func_8012F2E8((s32)a0, (s32)in, (s32)out); + if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { + return 1; } } - p += 0x10C; - } while (p != end); + } } return 0; } diff --git a/src/ov_SC03_002/ov_SC03_002_jr_80181D78.c b/src/ov_SC03_002/ov_SC03_002_jr_80181D78.c index 15d8a89734..752e5544ee 100644 --- a/src/ov_SC03_002/ov_SC03_002_jr_80181D78.c +++ b/src/ov_SC03_002/ov_SC03_002_jr_80181D78.c @@ -3814,23 +3814,12 @@ void func_8018311C(void *a0, s32 a1, s32 a2) { extern u8 D_80078EB1; - s32 v0; - register s32 v1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus9) - v0 = D_80078EB1; - if (!(v0 < a1)) { - if (v0 < a2) { - v0 = 1; - v1 = *(s32 *)((s32)a0 + 0xCC); - } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; - } + if (D_80078EB1 >= a1 && D_80078EB1 < a2) { + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1; } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2; } - *(s32 *)(v1 + 0xB0) = v0; } diff --git a/src/ov_SC03_002/ov_SC03_002_jr_8018431C.c b/src/ov_SC03_002/ov_SC03_002_jr_8018431C.c index 011861c41d..8b0d338749 100644 --- a/src/ov_SC03_002/ov_SC03_002_jr_8018431C.c +++ b/src/ov_SC03_002/ov_SC03_002_jr_8018431C.c @@ -3237,24 +3237,20 @@ s32 func_80184854(void *a0) { p = D_801202A0; end = p + 0x6480; - if (p != end) { - do { - tag = *(u16 *)p; - if (tag != 0 && tag != 0x61 && func_80184960((s32)p) != 0) { - t = *(s32 *)(p + 0x20); - if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { - in[0] = *(u16 *)(p + 0x6); - in[1] = *(u16 *)(p + 0xA); - in[2] = *(u16 *)(p + 0xE); - func_8012F2E8((s32)a0, (s32)in, (s32)out); - if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { - __asm__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) - return 1; - } + for (; p != end; p += 0x10C) { + tag = *(u16 *)p; + if (tag != 0 && tag != 0x61 && func_80184960((s32)p) != 0) { + t = *(s32 *)(p + 0x20); + if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { + in[0] = *(u16 *)(p + 0x6); + in[1] = *(u16 *)(p + 0xA); + in[2] = *(u16 *)(p + 0xE); + func_8012F2E8((s32)a0, (s32)in, (s32)out); + if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { + return 1; } } - p += 0x10C; - } while (p != end); + } } return 0; } diff --git a/src/ov_SC03_089/ov_SC03_089_jr_80185E50.c b/src/ov_SC03_089/ov_SC03_089_jr_80185E50.c index 2d23cb3a1f..a5afc0c110 100644 --- a/src/ov_SC03_089/ov_SC03_089_jr_80185E50.c +++ b/src/ov_SC03_089/ov_SC03_089_jr_80185E50.c @@ -4650,20 +4650,17 @@ void func_801881D0(void *a0) *(u16 *)(s1 + 0x18) = 0x2000; *(u8 *)(s1 + 0x27) = b; } else { - register u8 *dptr __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) - func_8001CF00(s1); - dptr = D_801C6770; + *(u32 *)(s1 + 0x20) = (s32)D_801C6770; *(u16 *)(s1 + 0x28) = 0x300; *(u16 *)(s1 + 0x2A) = 0x110; *(u8 *)(s1 + 0x27) = 0x78; - *(u32 *)(s1 + 0x20) = (s32)dptr; *(u16 *)(s1 + 0x10) = 0x400; *(u16 *)(s1 + 0x1A) = 0x800; *(u16 *)(s1 + 0x18) = 0x800; if ((*(u16 *)(s2 + 0x70) & 3) == 0) { - func_800233CC(dptr, 0x80); + func_800233CC(D_801C6770, 0x80); } { diff --git a/src/ov_SC03_090/ov_SC03_090_jr_80188274.c b/src/ov_SC03_090/ov_SC03_090_jr_80188274.c index 77507fb212..95a8963e5f 100644 --- a/src/ov_SC03_090/ov_SC03_090_jr_80188274.c +++ b/src/ov_SC03_090/ov_SC03_090_jr_80188274.c @@ -4679,20 +4679,17 @@ void func_8018A5F4(void *a0) *(u16 *)(s1 + 0x18) = 0x2000; *(u8 *)(s1 + 0x27) = b; } else { - register u8 *dptr __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) - func_8001CF00(s1); - dptr = D_801CBBE0; + *(u32 *)(s1 + 0x20) = (s32)D_801CBBE0; *(u16 *)(s1 + 0x28) = 0x300; *(u16 *)(s1 + 0x2A) = 0x110; *(u8 *)(s1 + 0x27) = 0x78; - *(u32 *)(s1 + 0x20) = (s32)dptr; *(u16 *)(s1 + 0x10) = 0x400; *(u16 *)(s1 + 0x1A) = 0x800; *(u16 *)(s1 + 0x18) = 0x800; if ((*(u16 *)(s2 + 0x70) & 3) == 0) { - func_800233CC(dptr, 0x80); + func_800233CC(D_801CBBE0, 0x80); } { diff --git a/src/ov_SC03_091/ov_SC03_091_jr_8018911C.c b/src/ov_SC03_091/ov_SC03_091_jr_8018911C.c index 4aa5521437..2cbcf042e2 100644 --- a/src/ov_SC03_091/ov_SC03_091_jr_8018911C.c +++ b/src/ov_SC03_091/ov_SC03_091_jr_8018911C.c @@ -4643,20 +4643,17 @@ void func_8018B49C(void *a0) *(u16 *)(s1 + 0x18) = 0x2000; *(u8 *)(s1 + 0x27) = b; } else { - register u8 *dptr __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) - func_8001CF00(s1); - dptr = D_801D2530; + *(u32 *)(s1 + 0x20) = (s32)D_801D2530; *(u16 *)(s1 + 0x28) = 0x300; *(u16 *)(s1 + 0x2A) = 0x110; *(u8 *)(s1 + 0x27) = 0x78; - *(u32 *)(s1 + 0x20) = (s32)dptr; *(u16 *)(s1 + 0x10) = 0x400; *(u16 *)(s1 + 0x1A) = 0x800; *(u16 *)(s1 + 0x18) = 0x800; if ((*(u16 *)(s2 + 0x70) & 3) == 0) { - func_800233CC(dptr, 0x80); + func_800233CC(D_801D2530, 0x80); } { diff --git a/src/ov_SC03_092/ov_SC03_092_jr_80181694.c b/src/ov_SC03_092/ov_SC03_092_jr_80181694.c index c916060207..d7da30f95a 100644 --- a/src/ov_SC03_092/ov_SC03_092_jr_80181694.c +++ b/src/ov_SC03_092/ov_SC03_092_jr_80181694.c @@ -4390,20 +4390,17 @@ void func_80183D58(void *a0) *(u16 *)(s1 + 0x18) = 0x2000; *(u8 *)(s1 + 0x27) = b; } else { - register u8 *dptr __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) - func_8001CF00(s1); - dptr = D_801B2ED8; + *(u32 *)(s1 + 0x20) = (s32)D_801B2ED8; *(u16 *)(s1 + 0x28) = 0x300; *(u16 *)(s1 + 0x2A) = 0x110; *(u8 *)(s1 + 0x27) = 0x78; - *(u32 *)(s1 + 0x20) = (s32)dptr; *(u16 *)(s1 + 0x10) = 0x400; *(u16 *)(s1 + 0x1A) = 0x800; *(u16 *)(s1 + 0x18) = 0x800; if ((*(u16 *)(s2 + 0x70) & 3) == 0) { - func_800233CC(dptr, 0x80); + func_800233CC(D_801B2ED8, 0x80); } { diff --git a/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c b/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c index bbba5438fb..749d905250 100644 --- a/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c +++ b/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c @@ -4417,20 +4417,17 @@ void func_80180980(void *a0) *(u16 *)(s1 + 0x18) = 0x2000; *(u8 *)(s1 + 0x27) = b; } else { - register u8 *dptr __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) - func_8001CF00(s1); - dptr = D_801AAB20; + *(u32 *)(s1 + 0x20) = (s32)D_801AAB20; *(u16 *)(s1 + 0x28) = 0x300; *(u16 *)(s1 + 0x2A) = 0x110; *(u8 *)(s1 + 0x27) = 0x78; - *(u32 *)(s1 + 0x20) = (s32)dptr; *(u16 *)(s1 + 0x10) = 0x400; *(u16 *)(s1 + 0x1A) = 0x800; *(u16 *)(s1 + 0x18) = 0x800; if ((*(u16 *)(s2 + 0x70) & 3) == 0) { - func_800233CC(dptr, 0x80); + func_800233CC(D_801AAB20, 0x80); } { diff --git a/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c b/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c index 2f90076a22..c0409cdd47 100644 --- a/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c +++ b/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c @@ -4980,20 +4980,17 @@ void func_80180EE0(void *a0) *(u16 *)(s1 + 0x18) = 0x2000; *(u8 *)(s1 + 0x27) = b; } else { - register u8 *dptr __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) - func_8001CF00(s1); - dptr = D_8019DD38; + *(u32 *)(s1 + 0x20) = (s32)D_8019DD38; *(u16 *)(s1 + 0x28) = 0x300; *(u16 *)(s1 + 0x2A) = 0x110; *(u8 *)(s1 + 0x27) = 0x78; - *(u32 *)(s1 + 0x20) = (s32)dptr; *(u16 *)(s1 + 0x10) = 0x400; *(u16 *)(s1 + 0x1A) = 0x800; *(u16 *)(s1 + 0x18) = 0x800; if ((*(u16 *)(s2 + 0x70) & 3) == 0) { - func_800233CC(dptr, 0x80); + func_800233CC(D_8019DD38, 0x80); } { diff --git a/src/ov_SC03_104/ov_SC03_104_jr_80182038.c b/src/ov_SC03_104/ov_SC03_104_jr_80182038.c index 6ccf216175..a4b07c69ee 100644 --- a/src/ov_SC03_104/ov_SC03_104_jr_80182038.c +++ b/src/ov_SC03_104/ov_SC03_104_jr_80182038.c @@ -4483,20 +4483,17 @@ void func_8018431C(void *a0) *(u16 *)(s1 + 0x18) = 0x2000; *(u8 *)(s1 + 0x27) = b; } else { - register u8 *dptr __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) - func_8001CF00(s1); - dptr = D_801C00F0; + *(u32 *)(s1 + 0x20) = (s32)D_801C00F0; *(u16 *)(s1 + 0x28) = 0x300; *(u16 *)(s1 + 0x2A) = 0x110; *(u8 *)(s1 + 0x27) = 0x78; - *(u32 *)(s1 + 0x20) = (s32)dptr; *(u16 *)(s1 + 0x10) = 0x400; *(u16 *)(s1 + 0x1A) = 0x800; *(u16 *)(s1 + 0x18) = 0x800; if ((*(u16 *)(s2 + 0x70) & 3) == 0) { - func_800233CC(dptr, 0x80); + func_800233CC(D_801C00F0, 0x80); } { diff --git a/src/ov_SC03_124/ov_SC03_124_jr_80181B44.c b/src/ov_SC03_124/ov_SC03_124_jr_80181B44.c index 44a2608878..e0a0b433b9 100644 --- a/src/ov_SC03_124/ov_SC03_124_jr_80181B44.c +++ b/src/ov_SC03_124/ov_SC03_124_jr_80181B44.c @@ -4840,23 +4840,12 @@ void func_80184298(void *a0, s32 a1, s32 a2) { extern u8 D_80078EB1; - s32 v0; - register s32 v1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus9) - v0 = D_80078EB1; - if (!(v0 < a1)) { - if (v0 < a2) { - v0 = 1; - v1 = *(s32 *)((s32)a0 + 0xCC); - } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; - } + if (D_80078EB1 >= a1 && D_80078EB1 < a2) { + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1; } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2; } - *(s32 *)(v1 + 0xB0) = v0; } diff --git a/src/ov_SC03_124/ov_SC03_124_jr_80185498.c b/src/ov_SC03_124/ov_SC03_124_jr_80185498.c index f67f6ca828..6ed6dae27d 100644 --- a/src/ov_SC03_124/ov_SC03_124_jr_80185498.c +++ b/src/ov_SC03_124/ov_SC03_124_jr_80185498.c @@ -3337,24 +3337,20 @@ s32 func_801859D0(void *a0) { p = D_801202A0; end = p + 0x6480; - if (p != end) { - do { - tag = *(u16 *)p; - if (tag != 0 && tag != 0x61 && func_80185ADC((s32)p) != 0) { - t = *(s32 *)(p + 0x20); - if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { - in[0] = *(u16 *)(p + 0x6); - in[1] = *(u16 *)(p + 0xA); - in[2] = *(u16 *)(p + 0xE); - func_8012F2E8((s32)a0, (s32)in, (s32)out); - if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { - __asm__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) - return 1; - } + for (; p != end; p += 0x10C) { + tag = *(u16 *)p; + if (tag != 0 && tag != 0x61 && func_80185ADC((s32)p) != 0) { + t = *(s32 *)(p + 0x20); + if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { + in[0] = *(u16 *)(p + 0x6); + in[1] = *(u16 *)(p + 0xA); + in[2] = *(u16 *)(p + 0xE); + func_8012F2E8((s32)a0, (s32)in, (s32)out); + if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { + return 1; } } - p += 0x10C; - } while (p != end); + } } return 0; } diff --git a/src/ov_SC03_125/ov_SC03_125_jr_8017D604.c b/src/ov_SC03_125/ov_SC03_125_jr_8017D604.c index 87961bab43..f30259787e 100644 --- a/src/ov_SC03_125/ov_SC03_125_jr_8017D604.c +++ b/src/ov_SC03_125/ov_SC03_125_jr_8017D604.c @@ -5444,23 +5444,12 @@ void func_801819A0(void *a0, s32 a1, s32 a2) { extern u8 D_80078EB1; - s32 v0; - register s32 v1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus8) - v0 = D_80078EB1; - if (!(v0 < a1)) { - if (v0 < a2) { - v0 = 1; - v1 = *(s32 *)((s32)a0 + 0xCC); - } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; - } + if (D_80078EB1 >= a1 && D_80078EB1 < a2) { + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1; } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2; } - *(s32 *)(v1 + 0xB0) = v0; } diff --git a/src/ov_SC03_125/ov_SC03_125_jr_80182BA0.c b/src/ov_SC03_125/ov_SC03_125_jr_80182BA0.c index 009f992810..4a9d3a46c7 100644 --- a/src/ov_SC03_125/ov_SC03_125_jr_80182BA0.c +++ b/src/ov_SC03_125/ov_SC03_125_jr_80182BA0.c @@ -3208,24 +3208,20 @@ s32 func_801830D8(void *a0) { p = D_801202A0; end = p + 0x6480; - if (p != end) { - do { - tag = *(u16 *)p; - if (tag != 0 && tag != 0x61 && func_801831E4((s32)p) != 0) { - t = *(s32 *)(p + 0x20); - if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { - in[0] = *(u16 *)(p + 0x6); - in[1] = *(u16 *)(p + 0xA); - in[2] = *(u16 *)(p + 0xE); - func_8012F2E8((s32)a0, (s32)in, (s32)out); - if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { - __asm__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) - return 1; - } + for (; p != end; p += 0x10C) { + tag = *(u16 *)p; + if (tag != 0 && tag != 0x61 && func_801831E4((s32)p) != 0) { + t = *(s32 *)(p + 0x20); + if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { + in[0] = *(u16 *)(p + 0x6); + in[1] = *(u16 *)(p + 0xA); + in[2] = *(u16 *)(p + 0xE); + func_8012F2E8((s32)a0, (s32)in, (s32)out); + if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { + return 1; } } - p += 0x10C; - } while (p != end); + } } return 0; } diff --git a/src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c b/src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c index 85c3a0d7de..c78baf0ccf 100644 --- a/src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c +++ b/src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c @@ -6838,23 +6838,12 @@ void func_80180EDC(void *a0, s32 a1, s32 a2) { extern u8 D_80078EB1; - s32 v0; - register s32 v1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus7) - v0 = D_80078EB1; - if (!(v0 < a1)) { - if (v0 < a2) { - v0 = 1; - v1 = *(s32 *)((s32)a0 + 0xCC); - } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; - } + if (D_80078EB1 >= a1 && D_80078EB1 < a2) { + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1; } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2; } - *(s32 *)(v1 + 0xB0) = v0; } diff --git a/src/ov_SC04_015/ov_SC04_015_jr_801820DC.c b/src/ov_SC04_015/ov_SC04_015_jr_801820DC.c index 22451cc72b..322cac7689 100644 --- a/src/ov_SC04_015/ov_SC04_015_jr_801820DC.c +++ b/src/ov_SC04_015/ov_SC04_015_jr_801820DC.c @@ -3224,24 +3224,20 @@ s32 func_80182614(void *a0) { p = D_801202A0; end = p + 0x6480; - if (p != end) { - do { - tag = *(u16 *)p; - if (tag != 0 && tag != 0x61 && func_80182720((s32)p) != 0) { - t = *(s32 *)(p + 0x20); - if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { - in[0] = *(u16 *)(p + 0x6); - in[1] = *(u16 *)(p + 0xA); - in[2] = *(u16 *)(p + 0xE); - func_8012F2E8((s32)a0, (s32)in, (s32)out); - if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { - __asm__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) - return 1; - } + for (; p != end; p += 0x10C) { + tag = *(u16 *)p; + if (tag != 0 && tag != 0x61 && func_80182720((s32)p) != 0) { + t = *(s32 *)(p + 0x20); + if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { + in[0] = *(u16 *)(p + 0x6); + in[1] = *(u16 *)(p + 0xA); + in[2] = *(u16 *)(p + 0xE); + func_8012F2E8((s32)a0, (s32)in, (s32)out); + if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { + return 1; } } - p += 0x10C; - } while (p != end); + } } return 0; } diff --git a/src/ov_SC04_020/ov_SC04_020_jr_8017D604.c b/src/ov_SC04_020/ov_SC04_020_jr_8017D604.c index 90a2065c7c..abf4b26ba5 100644 --- a/src/ov_SC04_020/ov_SC04_020_jr_8017D604.c +++ b/src/ov_SC04_020/ov_SC04_020_jr_8017D604.c @@ -5136,23 +5136,12 @@ void func_8018134C(void *a0, s32 a1, s32 a2) { extern u8 D_80078EB1; - s32 v0; - register s32 v1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus8) - v0 = D_80078EB1; - if (!(v0 < a1)) { - if (v0 < a2) { - v0 = 1; - v1 = *(s32 *)((s32)a0 + 0xCC); - } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; - } + if (D_80078EB1 >= a1 && D_80078EB1 < a2) { + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1; } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2; } - *(s32 *)(v1 + 0xB0) = v0; } diff --git a/src/ov_SC04_020/ov_SC04_020_jr_8018254C.c b/src/ov_SC04_020/ov_SC04_020_jr_8018254C.c index 52454276d9..4cf1e92f1f 100644 --- a/src/ov_SC04_020/ov_SC04_020_jr_8018254C.c +++ b/src/ov_SC04_020/ov_SC04_020_jr_8018254C.c @@ -3194,24 +3194,20 @@ s32 func_80182A84(void *a0) { p = D_801202A0; end = p + 0x6480; - if (p != end) { - do { - tag = *(u16 *)p; - if (tag != 0 && tag != 0x61 && func_80182B90((s32)p) != 0) { - t = *(s32 *)(p + 0x20); - if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { - in[0] = *(u16 *)(p + 0x6); - in[1] = *(u16 *)(p + 0xA); - in[2] = *(u16 *)(p + 0xE); - func_8012F2E8((s32)a0, (s32)in, (s32)out); - if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { - __asm__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) - return 1; - } + for (; p != end; p += 0x10C) { + tag = *(u16 *)p; + if (tag != 0 && tag != 0x61 && func_80182B90((s32)p) != 0) { + t = *(s32 *)(p + 0x20); + if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { + in[0] = *(u16 *)(p + 0x6); + in[1] = *(u16 *)(p + 0xA); + in[2] = *(u16 *)(p + 0xE); + func_8012F2E8((s32)a0, (s32)in, (s32)out); + if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { + return 1; } } - p += 0x10C; - } while (p != end); + } } return 0; } diff --git a/src/ov_SC05_017/ov_SC05_017_jr_80182A74.c b/src/ov_SC05_017/ov_SC05_017_jr_80182A74.c index f483a2d1f2..1ffbd2c976 100644 --- a/src/ov_SC05_017/ov_SC05_017_jr_80182A74.c +++ b/src/ov_SC05_017/ov_SC05_017_jr_80182A74.c @@ -4457,23 +4457,12 @@ void func_80184870(void *a0, s32 a1, s32 a2) { extern u8 D_80078EB1; - s32 v0; - register s32 v1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus9) - v0 = D_80078EB1; - if (!(v0 < a1)) { - if (v0 < a2) { - v0 = 1; - v1 = *(s32 *)((s32)a0 + 0xCC); - } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; - } + if (D_80078EB1 >= a1 && D_80078EB1 < a2) { + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1; } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2; } - *(s32 *)(v1 + 0xB0) = v0; } diff --git a/src/ov_SC05_017/ov_SC05_017_jr_80185A70.c b/src/ov_SC05_017/ov_SC05_017_jr_80185A70.c index 1ca3569911..05f3ba9e77 100644 --- a/src/ov_SC05_017/ov_SC05_017_jr_80185A70.c +++ b/src/ov_SC05_017/ov_SC05_017_jr_80185A70.c @@ -3335,24 +3335,20 @@ s32 func_80185FA8(void *a0) { p = D_801202A0; end = p + 0x6480; - if (p != end) { - do { - tag = *(u16 *)p; - if (tag != 0 && tag != 0x61 && func_801860B4((s32)p) != 0) { - t = *(s32 *)(p + 0x20); - if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { - in[0] = *(u16 *)(p + 0x6); - in[1] = *(u16 *)(p + 0xA); - in[2] = *(u16 *)(p + 0xE); - func_8012F2E8((s32)a0, (s32)in, (s32)out); - if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { - __asm__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) - return 1; - } + for (; p != end; p += 0x10C) { + tag = *(u16 *)p; + if (tag != 0 && tag != 0x61 && func_801860B4((s32)p) != 0) { + t = *(s32 *)(p + 0x20); + if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { + in[0] = *(u16 *)(p + 0x6); + in[1] = *(u16 *)(p + 0xA); + in[2] = *(u16 *)(p + 0xE); + func_8012F2E8((s32)a0, (s32)in, (s32)out); + if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { + return 1; } } - p += 0x10C; - } while (p != end); + } } return 0; } diff --git a/src/ov_SC05_018/ov_SC05_018_jr_8017D604.c b/src/ov_SC05_018/ov_SC05_018_jr_8017D604.c index e601750efb..e3459767c9 100644 --- a/src/ov_SC05_018/ov_SC05_018_jr_8017D604.c +++ b/src/ov_SC05_018/ov_SC05_018_jr_8017D604.c @@ -7366,23 +7366,12 @@ void func_80184554(void *a0, s32 a1, s32 a2) { extern u8 D_80078EB1; - s32 v0; - register s32 v1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus8) - v0 = D_80078EB1; - if (!(v0 < a1)) { - if (v0 < a2) { - v0 = 1; - v1 = *(s32 *)((s32)a0 + 0xCC); - } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; - } + if (D_80078EB1 >= a1 && D_80078EB1 < a2) { + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 1; } else { - v1 = *(s32 *)((s32)a0 + 0xCC); - v0 = 2; + *(s32 *)(*(s32 *)((s32)a0 + 0xCC) + 0xB0) = 2; } - *(s32 *)(v1 + 0xB0) = v0; } diff --git a/src/ov_SC05_018/ov_SC05_018_jr_80185754.c b/src/ov_SC05_018/ov_SC05_018_jr_80185754.c index 0e539c3cd0..246707e2c2 100644 --- a/src/ov_SC05_018/ov_SC05_018_jr_80185754.c +++ b/src/ov_SC05_018/ov_SC05_018_jr_80185754.c @@ -3241,24 +3241,20 @@ s32 func_80185C8C(void *a0) { p = D_801202A0; end = p + 0x6480; - if (p != end) { - do { - tag = *(u16 *)p; - if (tag != 0 && tag != 0x61 && func_80185D98((s32)p) != 0) { - t = *(s32 *)(p + 0x20); - if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { - in[0] = *(u16 *)(p + 0x6); - in[1] = *(u16 *)(p + 0xA); - in[2] = *(u16 *)(p + 0xE); - func_8012F2E8((s32)a0, (s32)in, (s32)out); - if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { - __asm__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) - return 1; - } + for (; p != end; p += 0x10C) { + tag = *(u16 *)p; + if (tag != 0 && tag != 0x61 && func_80185D98((s32)p) != 0) { + t = *(s32 *)(p + 0x20); + if (t != 0 && *(s32 *)(t + 0x24) != 0 && *(s32 *)(t + 0x4) >= 0) { + in[0] = *(u16 *)(p + 0x6); + in[1] = *(u16 *)(p + 0xA); + in[2] = *(u16 *)(p + 0xE); + func_8012F2E8((s32)a0, (s32)in, (s32)out); + if (func_8012CB64((s32)out, -0xA0, 0x80, -0xC0, 0x80) != 0) { + return 1; } } - p += 0x10C; - } while (p != end); + } } return 0; } diff --git a/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c b/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c index 858137c814..36ce1482d2 100644 --- a/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c +++ b/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c @@ -8695,7 +8695,7 @@ void func_80185DD8(s32 a0) { s32 r; s16 vecA[4]; s16 vecB[4]; - s32 x, z; + s32 x; if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) { s32 ret = ((s32 (*)(s32))func_8012BE54)(a0); @@ -8731,32 +8731,11 @@ void func_80185DD8(s32 a0) { if (x < 0) { x = -x; } - if (x < 0x105) { - z = vecB[1]; - if (z >= 0) { - if (z < 0xC9) { - /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles - * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z, - * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare - * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the - * else arm). A zero-emission `__asm__ __volatile__("":::"memory")` right - * before this `return` is a scheduling/combine barrier that blocks whatever - * RTL-level pass performs that merge, without adding a single byte itself -- - * the compiled result is byte-exact target. Byte-proven via 9 probe variants - * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled - * return) that ALL either fully merged or left a redundant extra sign-retest; - * only this barrier reproduces the target exactly. See match_one MATCH 96/96. - */ - __asm__ __volatile__("" ::: "memory"); // !FAKE: barrier memory — NEEDED DIFFERS (P36 rung B tus9) - return; - } - } else { - if (-z < 0xC9) { - return; - } - } + /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch, + * so the two `slti 201` tails are not one value-converged abs (the x test above is). */ + if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) { + func_8012C098((void *)a0); } - func_8012C098((void *)a0); } diff --git a/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c b/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c index 31e78e0db6..2235f46586 100644 --- a/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c +++ b/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c @@ -4713,7 +4713,7 @@ void func_8017FF48(s32 a0) { s32 r; s16 vecA[4]; s16 vecB[4]; - s32 x, z; + s32 x; if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) { s32 ret = ((s32 (*)(s32))func_8012BE54)(a0); @@ -4749,32 +4749,11 @@ void func_8017FF48(s32 a0) { if (x < 0) { x = -x; } - if (x < 0x105) { - z = vecB[1]; - if (z >= 0) { - if (z < 0xC9) { - /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles - * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z, - * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare - * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the - * else arm). A zero-emission `__asm__ __volatile__("":::"memory")` right - * before this `return` is a scheduling/combine barrier that blocks whatever - * RTL-level pass performs that merge, without adding a single byte itself -- - * the compiled result is byte-exact target. Byte-proven via 9 probe variants - * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled - * return) that ALL either fully merged or left a redundant extra sign-retest; - * only this barrier reproduces the target exactly. See match_one MATCH 96/96. - */ - __asm__ __volatile__("" ::: "memory"); // !FAKE: barrier memory — NEEDED DIFFERS (P36 rung B tus9) - return; - } - } else { - if (-z < 0xC9) { - return; - } - } + /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch, + * so the two `slti 201` tails are not one value-converged abs (the x test above is). */ + if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) { + func_8012C098((void *)a0); } - func_8012C098((void *)a0); } diff --git a/src/ov_SC06_022/ov_SC06_022_jr_80182D08.c b/src/ov_SC06_022/ov_SC06_022_jr_80182D08.c index c8ea7dacb8..4733f08502 100644 --- a/src/ov_SC06_022/ov_SC06_022_jr_80182D08.c +++ b/src/ov_SC06_022/ov_SC06_022_jr_80182D08.c @@ -3507,7 +3507,7 @@ void func_80183E6C(s32 a0) { s32 r; s16 vecA[4]; s16 vecB[4]; - s32 x, z; + s32 x; if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) { s32 ret = ((s32 (*)(s32))func_8012BE54)(a0); @@ -3543,32 +3543,11 @@ void func_80183E6C(s32 a0) { if (x < 0) { x = -x; } - if (x < 0x105) { - z = vecB[1]; - if (z >= 0) { - if (z < 0xC9) { - /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles - * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z, - * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare - * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the - * else arm). A zero-emission `__asm__ __volatile__("":::"memory")` right - * before this `return` is a scheduling/combine barrier that blocks whatever - * RTL-level pass performs that merge, without adding a single byte itself -- - * the compiled result is byte-exact target. Byte-proven via 9 probe variants - * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled - * return) that ALL either fully merged or left a redundant extra sign-retest; - * only this barrier reproduces the target exactly. See match_one MATCH 96/96. - */ - __asm__ __volatile__("" ::: "memory"); // !FAKE: barrier memory — NEEDED DIFFERS (P36 rung B tus9) - return; - } - } else { - if (-z < 0xC9) { - return; - } - } + /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch, + * so the two `slti 201` tails are not one value-converged abs (the x test above is). */ + if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) { + func_8012C098((void *)a0); } - func_8012C098((void *)a0); } diff --git a/src/ov_SC06_024/ov_SC06_024_jr_801851E0.c b/src/ov_SC06_024/ov_SC06_024_jr_801851E0.c index f3f40727d6..70707b4462 100644 --- a/src/ov_SC06_024/ov_SC06_024_jr_801851E0.c +++ b/src/ov_SC06_024/ov_SC06_024_jr_801851E0.c @@ -3552,7 +3552,7 @@ void func_80186344(s32 a0) { s32 r; s16 vecA[4]; s16 vecB[4]; - s32 x, z; + s32 x; if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) { s32 ret = ((s32 (*)(s32))func_8012BE54)(a0); @@ -3588,32 +3588,11 @@ void func_80186344(s32 a0) { if (x < 0) { x = -x; } - if (x < 0x105) { - z = vecB[1]; - if (z >= 0) { - if (z < 0xC9) { - /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles - * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z, - * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare - * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the - * else arm). A zero-emission `__asm__ __volatile__("":::"memory")` right - * before this `return` is a scheduling/combine barrier that blocks whatever - * RTL-level pass performs that merge, without adding a single byte itself -- - * the compiled result is byte-exact target. Byte-proven via 9 probe variants - * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled - * return) that ALL either fully merged or left a redundant extra sign-retest; - * only this barrier reproduces the target exactly. See match_one MATCH 96/96. - */ - __asm__ __volatile__("" ::: "memory"); // !FAKE: barrier memory — NEEDED DIFFERS (P36 rung B tus9) - return; - } - } else { - if (-z < 0xC9) { - return; - } - } + /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch, + * so the two `slti 201` tails are not one value-converged abs (the x test above is). */ + if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) { + func_8012C098((void *)a0); } - func_8012C098((void *)a0); } diff --git a/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c b/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c index ba261fce65..3fb7fb7f5e 100644 --- a/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c +++ b/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c @@ -5347,7 +5347,7 @@ void func_80180B7C(s32 a0) { s32 r; s16 vecA[4]; s16 vecB[4]; - s32 x, z; + s32 x; if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) { s32 ret = ((s32 (*)(s32))func_8012BE54)(a0); @@ -5383,32 +5383,11 @@ void func_80180B7C(s32 a0) { if (x < 0) { x = -x; } - if (x < 0x105) { - z = vecB[1]; - if (z >= 0) { - if (z < 0xC9) { - /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles - * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z, - * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare - * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the - * else arm). A zero-emission `__asm__ __volatile__("":::"memory")` right - * before this `return` is a scheduling/combine barrier that blocks whatever - * RTL-level pass performs that merge, without adding a single byte itself -- - * the compiled result is byte-exact target. Byte-proven via 9 probe variants - * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled - * return) that ALL either fully merged or left a redundant extra sign-retest; - * only this barrier reproduces the target exactly. See match_one MATCH 96/96. - */ - __asm__ __volatile__("" ::: "memory"); // !FAKE: barrier memory — NEEDED DIFFERS (P36 rung B tus9) - return; - } - } else { - if (-z < 0xC9) { - return; - } - } + /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch, + * so the two `slti 201` tails are not one value-converged abs (the x test above is). */ + if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) { + func_8012C098((void *)a0); } - func_8012C098((void *)a0); } diff --git a/src/ov_SC06_033/ov_SC06_033_jr_801836FC.c b/src/ov_SC06_033/ov_SC06_033_jr_801836FC.c index 0ad507e32e..08a20dfb5e 100644 --- a/src/ov_SC06_033/ov_SC06_033_jr_801836FC.c +++ b/src/ov_SC06_033/ov_SC06_033_jr_801836FC.c @@ -3569,7 +3569,7 @@ void func_80184860(s32 a0) { s32 r; s16 vecA[4]; s16 vecB[4]; - s32 x, z; + s32 x; if ((*(u32 *)(a0 + 0xE0) & 0x40) == 0) { s32 ret = ((s32 (*)(s32))func_8012BE54)(a0); @@ -3605,32 +3605,11 @@ void func_80184860(s32 a0) { if (x < 0) { x = -x; } - if (x < 0x105) { - z = vecB[1]; - if (z >= 0) { - if (z < 0xC9) { - /* NEW LEVER (not yet in cookbook): a bare if/else-with-return here compiles - * to a value-converge merge (ONE shared `slti`+`bne` fed by both signs of z, - * ~91 ins) instead of the target's genuine PER-BRANCH duplicate compare - * (96 ins: `bltz`+`slti`+`beqz`+`j` in this arm, `negu`+`slti`+`bnez` in the - * else arm). A zero-emission `__asm__ __volatile__("":::"memory")` right - * before this `return` is a scheduling/combine barrier that blocks whatever - * RTL-level pass performs that merge, without adding a single byte itself -- - * the compiled result is byte-exact target. Byte-proven via 9 probe variants - * (assignment-abs, ternary-condition, if/else, 2-independent-ifs, goto-labeled - * return) that ALL either fully merged or left a redundant extra sign-retest; - * only this barrier reproduces the target exactly. See match_one MATCH 96/96. - */ - __asm__ __volatile__("" ::: "memory"); // !FAKE: barrier memory — NEEDED DIFFERS (P36 rung B tus9) - return; - } - } else { - if (-z < 0xC9) { - return; - } - } + /* |z| tested per sign inside the jump context: each arm of the ?: is its own compare-and-branch, + * so the two `slti 201` tails are not one value-converged abs (the x test above is). */ + if (x >= 0x105 || (vecB[1] >= 0 ? vecB[1] >= 0xC9 : -vecB[1] >= 0xC9)) { + func_8012C098((void *)a0); } - func_8012C098((void *)a0); }