From 580d7bfd86e25b67ae8eca483ea4eb2745dd6a5e Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 11 Sep 2026 02:05:21 -0600 Subject: [PATCH] =?UTF-8?q?phase-36:=20S104=20s104=5Fe13=20=E2=80=94=20fun?= =?UTF-8?q?c=5F80185574=20banked=20at=200=20through=20the=20whole-object?= =?UTF-8?q?=20gate=20+=20propagated=20=E2=80=94=203=20pins=20=E2=86=92=200?= =?UTF-8?q?:=20the=20parameter=20copy=20deleted,=20one=20value=20per=20var?= =?UTF-8?q?iable=20(sched.c:2469-2547=20=E2=86=92=20the=20three-quantity?= =?UTF-8?q?=20order,=20local-alloc.c:1486-1500)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../agents/ov_SC02_017__func_801842E0/body.c | 50 +++ .../ov_SC02_017__func_801842E0/mechanism.md | 57 +++ .../agents/ov_SC02_017__func_80185574/body.c | 12 + .../ov_SC02_017__func_80185574/mechanism.md | 60 +++ .run/P36/delever/calibration.json | 346 +++++++++--------- .run/P36/delever/ledger.jsonl | 1 + src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c | 35 +- 7 files changed, 361 insertions(+), 200 deletions(-) create mode 100644 .run/P36/agents/ov_SC02_017__func_801842E0/body.c create mode 100644 .run/P36/agents/ov_SC02_017__func_801842E0/mechanism.md create mode 100644 .run/P36/agents/ov_SC02_017__func_80185574/body.c create mode 100644 .run/P36/agents/ov_SC02_017__func_80185574/mechanism.md diff --git a/.run/P36/agents/ov_SC02_017__func_801842E0/body.c b/.run/P36/agents/ov_SC02_017__func_801842E0/body.c new file mode 100644 index 000000000..3bf4c00e4 --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_801842E0/body.c @@ -0,0 +1,50 @@ +void func_801842E0(void) { + s32 t; + s32 y; + + t = D_800B99DA; + if (t != D_8018EF88) { + y = (s16)D_80126B62; + D_8018EF88 = t; + + if (y >= -0x7FF) { + t = D_8018EF84; + } else if (y < -0xC00) { + t = D_8018EF84; + } else { + SV3_8012CC88 sp10; + SV3_8012CC88 sp18; + + sp10.vx = D_80126B5E; + sp10.vy = 0; + sp10.vz = D_80126B66; + sp18.vx = 0x11; + sp18.vz = -0x3AA; + sp18.vy = 0; + + t = func_800132BC((s32)&sp10, (s32)&sp18); + } + + if (t >= D_8018EF84) { + func_8002D4C8(4, 0x5E5); + } else { + t = D_8018EF84 - t - 0x10000; + if (t < 0) { + t = -t; + } + t = t * 127 / D_8018EF84; + + if (t <= 0) { + t = 0; + } else if (t >= 0x80) { + t = 0x7F; + } + + if (D_801270C8 != 0) { + t /= 2; + } + + func_8002D4C8(0x5E5, (u16)(t | 0x1000)); + } + } +} diff --git a/.run/P36/agents/ov_SC02_017__func_801842E0/mechanism.md b/.run/P36/agents/ov_SC02_017__func_801842E0/mechanism.md new file mode 100644 index 000000000..41fcf3866 --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_801842E0/mechanism.md @@ -0,0 +1,57 @@ +# func_801842E0 — e13 (P36 T7 S104) — score 34 (sweep best 20) -> 0, ZERO levers (was: NEEDED pins `$3`, `$5` + a NEEDED `launder`) + +(a) Residual: 86/86 insns, two defects. (1) A register permutation over the whole function: the main value `t` +(the `D_800B99DA` stamp, then the call result / `D_8018EF84`, then the volume) sits in `a1` instead of `v1` (x25) and the +second variable (`(s16)D_80126B62`, then `D_8018EF84`) in `v1` instead of `a0` (x13). (2) ORDER at the tail: the target +emits `li a0,1509; ori a1,v1,0x1000; andi a1,a1,0xffff; jal`, the lever-free text puts `li a0,1509` after the `ori`. + +(b) Pass/decision (dump-verified: `scratch/dumps_b0` (body_free, 34), `dumps_f1` (b0 + move 1, 2), `dumps_f3` (b0 + both, 0); +`tools/alloc_table.py`): + 1. global.c preferences. `t = a0 - t; t -= 0x10000;` sets `t` from `(minus a0 t)` — `set_preference` + (global.c:1535; for a non-copy the source is `XEXP (src, 0)` = `a0`, a global pseudo, so no hard-register + preference) — then from `t + K` (itself). The only hard preference `t` (r72) gets is `a1`, from `a1p = t | 0x1000` + (a1p is local-allocated into `a1`): b0 table "r72 prefers a1" -> `find_reg` gives `a1`. Written as ONE expression + `t = a0 - t - 0x10000;`, expand makes the inner difference a fresh block-local temp (f1 r89, local-alloc puts it in + `v1`) and `t = r89 + K` adds the preference `v1`: f1 "r72 prefers v1,a1". `find_reg`'s preference scan runs from hard + reg 0 upward (global.c:1039-1068), so `v1` (3) wins over `a1` (5). With `t` in `v1` for its whole life, the other + global (r73, `a0`) now conflicts with `v1` (f1 "r73 conflicts v0,v1") and takes `a0` — both halves of the permutation + close with this one move (34 -> 2). Same channel as e7's func_801831FC (a second preference from a fresh temp). + 2. sched1's birthing boost. `a1p = t | 0x1000; a1p = (u16)a1p;` sets `a1p` twice (`reg_n_sets == 2`), so the `ori` + is not a birthing insn (`birthing_insn_p`, sched.c:2469-2490) and gets no `adjust_priority` boost + (sched.c:2507-2547): f1 `.sched` block 17 `ready list at T-3: 187 (1) 182 (1), now 187 182` — the `li a0,1509` + (187) takes the later slot. With one set (`a1p = t | 0x1000; func_8002D4C8(0x5E5, (u16)a1p);`, or the value + inline) the `ori` is birthing: f3 `T-3: 183 (1) 179 (7f000001), now 179 183` — the `ori` goes last, `li a0` first + = the target. The tree's launder on `a0 = 0x5E5` faked the same reordering. + +(c) Moves — the minimum proof (b0 + two edits = `scratch/f3.c`, 0): + - `t = a0 - t; t -= 0x10000;` -> `t = a0 - t - 0x10000;` (alone: 34 -> 2); + - the call's `u16` narrowing at the call, not as a second assignment (`a1p = (u16)a1p;` deleted; f4 with only the + `a0 = 0x5E5` temp removed stays 2, f3 = 0). + body.c (`scratch/n3.c`, 0) is the readable text built around those two facts: `D_8018EF84` read at each use, the + `(s16)D_80126B62` in its own `s32 y`, `if (t < 0) t = -t; t = t * 127 / D_8018EF84;` for the hand-expanded + abs/shift-subtract, `t /= 2` for the hand-rolled `(u32)t >> 31` rounding shift, and + `func_8002D4C8(0x5E5, (u16)(t | 0x1000));` (the spelling func_801831FC uses for the same call). The nested + `if (y >= -0x7FF) … else if (y < -0xC00) …` with the duplicated `t = D_8018EF84;` is kept: `||` lets gcc fold the + two tests into one unsigned range check (n1/A7: 6/10, `addiu 3072; andi 0xffff; sltiu 1025`). + Ablations from body.c (`scratch/abl/`, all proven on bytes): the split subtraction 33; the hand abs 12; + `t = t * 127; t = t / D;` 3; the call temps (`a0 = 0x5E5; a1p = …; a1p = (u16)a1p;`) 2; the hand `/2` 1; `||` range 10; + `s16 y = D_80126B62` 10 (`lhu; sll; sra` — S104 d13's re-extension; `(s16)` into an `s32` gives `lh`). Neutral (0): + a `lim = D_8018EF84` local, or reusing `y` for it. + +(d) GENERATOR PROPOSAL: when a variable is updated by two consecutive statements (`t = a - t; t -= K;`, `t = f(t); t op= K;`) +and the residual is a whole-function register swap of that variable, fold them into one expression (`t = a - t - K;`) +— the inner temp's local-alloc register becomes `t`'s first global preference (global.c:1535, :1039-1068); and when a +call argument is narrowed by a second assignment (`x = e; x = (u16)x; f(…, x)`) with an ORDER residual on the +neighbouring argument's `li`, move the cast into the call (one set -> sched1-birthing, sched.c:2469-2490). + +(e) Did not work: n1 (`||` range test) 6; n2/n4 (`s16 y`) 10; every ablation above. The sweep's best (R12 width + R6 +inline, 20) touched neither the two-statement update nor the second set of `a1p`. + +(f) Method: the allocation table's "prefers" column (b0 `a1` only, f1 `v1,a1`) and the `.sched` ready-list lines gave +both mechanisms in two dumps, but the close came first from writing the natural C (n1 = 6 on the first try) and then +ablating it — a residual of 34 with a clean permutation looked like a priority problem and was a preference problem. +The METHOD rows for "a hand-rolled shift as a real division" (e7 func_801831FC) and "narrow at the call" were the +right ones; neither is needed for the bytes here (f3 keeps the hand shapes), they are readability. + +(g) Structs: no. Both decisions are about scalar locals (a global allocno's copy preference; sched1's set count). The +body touches only globals and two `SV3_8012CC88` stack vectors, which are already struct-typed. diff --git a/.run/P36/agents/ov_SC02_017__func_80185574/body.c b/.run/P36/agents/ov_SC02_017__func_80185574/body.c new file mode 100644 index 000000000..b0a29ea58 --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_80185574/body.c @@ -0,0 +1,12 @@ +void func_80185574(s32 arg0) { + *(s16 *)(arg0 + 0x5C) = 0; + *(s16 *)(arg0 + 0x98) = 0; + *(s32 *)(arg0 + 0x1C) = 0; + if (*(s16 *)(arg0 + 0xAA) == 0) { + *(s16 *)(arg0 + 0x100) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18); + *(s32 *)(arg0 + 0xDC) &= ~0x80; + } else { + *(s16 *)(arg0 + 0x104) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18); + *(s32 *)(arg0 + 0xDC) |= 0x80; + } +} diff --git a/.run/P36/agents/ov_SC02_017__func_80185574/mechanism.md b/.run/P36/agents/ov_SC02_017__func_80185574/mechanism.md new file mode 100644 index 000000000..caac1fd9e --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_80185574/mechanism.md @@ -0,0 +1,60 @@ +# func_80185574 — e13 (P36 T7 S104) — score 16 (sweep best 4) -> 0, ZERO levers (was: NEEDED pins `$0`, `$2`, `$3`) + +(a) Residual: two defects, 22/22 insns. (1) The else arm reads the object through `a0` (the incoming parameter) while +the target reads it through `a1` in both arms (`move a1,a0` in the prologue, `a0` reused for the `-129` mask). +(2) A v0/v1 permutation in each arm: target then-arm `lw v1,0x20 / lw v0,0xDC / lhu v1 / and v0,v0,a0`, else-arm +`lw v0,0x20 / lw v1,0xDC / lhu v0 / ori v1`; lever-free text the opposite in both. + +(b) Pass/decision (dump-verified: `scratch/dumps_b1` (param copy deleted, decompiler temps) vs `scratch/dumps_c3` (body.c)): + 1. `self = arg0 + 0;` makes two pseudos (param r72-equivalent + the copy); cse's canonical-register choice + (`make_regs_eqv`, cse.c:826-862) leaves the else arm reading the parameter pseudo, which global puts in `a0`. + One pseudo (use the parameter directly, METHOD d24) lives across the then arm where local-alloc has put the + mask in `a0`, so it conflicts with `a0` and lands in `a1` in both arms (b1: the `a0` reads are gone, 16 -> REG-only). + c4/c5 (body.c + `s32 arg0 = a + 0;` / `= a;`): 4 — the copy is part of the joint close. + 2. The decompiler REUSES one variable for the pointer and the halfword read through it (`p = *(s32 *)(self+0x20); + p = *(u16 *)(p + 0x18);`) and `g` for the flag word and its `|= 0x80` result — each has `reg_n_sets == 2`, so + sched1's `birthing_insn_p` (sched.c:2469-2490) is false for those loads and `adjust_priority` (sched.c:2507-2547) + gives them no boost. b1 `.sched` block 1: `ready list at T-5: 40 (2) 30 (7f000001), now 30 40` — the mask `li` + (insn 30) is launched late, the pointer load (33) first. With one pseudo per value every load is birthing + (c3 `.sched`: `T-5: 36 (7f000001) 29 (7f000001) … 29 has a greater potential hazard`) and the mask `li` ends up + FIRST in the block. + That changes the quantity NUMBERING (birth order) of the block's three local-alloc quantities, and a block with + exactly three quantities is ordered by the hand-written sort at local-alloc.c:1486-1500, which compares quantity + NUMBERS 0/1/2, not positions in `qty_order`: b1 {q0 pointer/value (4 refs), q1 flag+and, q2 mask} ends [q0,q1,q2] + -> pointer `v0`, flag `v1`, mask `a0` (`.lreg`: "Register 77 in 2 / 78 in 3 / 73 in 4"); c3 {q0 mask, q1 pointer + tied to the u16 value, q2 flag tied to the and result} ends [q2,q1,q0] -> flag `v0`, pointer `v1`, mask `a0` + (`.lreg`: "78 in 2 / 76 in 3 / 80 in 4") = the target. Same for the else arm (c3: pointer/value r81/r82 in 2, + flag r83/r84 in 3). + 3. The halfword copy must be written BEFORE the read-modify-write of `+0xDC`: the target does the `lhu` before the + `sw 220`, and a scalar store through the object vs a load through `*(obj+0x20)` may alias (`true_dependence`, + sched.c:817-841), so a source order with the RMW first keeps the load after the store (enum `AB__*` 6, `*__AB` 7 COUNT). + +(c) Moves (joint): + - delete `self = arg0 + 0;` and use the parameter directly (d24); + - one value per name: the pointer, its halfword, the flag word each its own value — body.c inlines them all + (`*(s16 *)(arg0 + 0x100) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18); *(s32 *)(arg0 + 0xDC) &= ~0x80;`), the spelling + the neighbour func_80185494 uses for the same `+0x20 -> +0x18` halfword; the `mask`/`flag` locals are gone and the + test reads `*(s16 *)(arg0 + 0xAA)` inline (c3 = 0); + - the halfword store first, the `+0xDC` RMW second, in both arms. + Enumeration (`scratch/gen.py` -> `scratch/enum/`, 143 bodies, `scratch/enum_scores.txt`): every arm spelling that + reads the halfword into its own value before the RMW scores 0 in combination (42 of 143: `BA`, `vu16A`, `vs32A`, + `tmpPVF` (decompiler temps with the pointer and value split), `fB`, `pfB`, `mBA`); every spelling that keeps the RMW + first or reuses `p` does not. Kept a `s32 flag` local: c1 = 0; declared `s16 flag = …` (c2): 1. + +(d) GENERATOR PROPOSAL: when a local is assigned twice in a straight-line block (`p = *(T *)(x + K); p = *(U *)(p + J);` +or `g = load; g |= C; store g`) and the residual is a register permutation in that block, give each assignment its own +value (inline or a fresh name) — both sets become sched1-birthing (sched.c:2469-2490), which reorders the block and +therefore local-alloc's quantity NUMBERS, which is all a three-quantity block's order depends on (local-alloc.c:1486-1500). + +(e) Did not work: b1 (param copy deleted only) 16; c4/c5 (body.c with the param copy kept) 4 REG; every `AB`/`pA`/ +`fpA`/`tmpPF`/`tmpPF2`/`mAB` arm (store order or reused pointer) 6/7/13. The sweep's R7/R8/R5/R9/R10/R18 reached 4. + +(f) Method: METHOD c1/c8/d15 ("a local REUSED … split it") was the row; the new fact is that here the split acts through +sched1's birthing boost and the three-quantity sort's use of quantity numbers, not through death counts — the +allocation table (global) is blind to it; the `.sched` ready-list lines and `.lreg` "Register N in R" lines settled it. +An enumeration over arm spellings (143 bodies, ~1 min) found it before any reading. + +(g) Structs: no. The decisions are sched1's birthing test (a register's set count) and local-alloc's quantity numbering; +the object (`s16 +0x5C/+0x98/+0xAA/+0x100/+0x104`, `s32 +0x1C/+0xDC`, `+0x20` pointer to a record with `u16 +0x18`) +as a struct would change spelling only. (The `+0x18` load vs the `+0xDC` store ordering is already what the source +order gives; an in-struct marking would only matter if the store came first.) diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index 07f70477e..45235198f 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,7 +1,7 @@ { - "head": "7e7d9c523", + "head": "c37ef9c15", "stamp": "15956e4a96c4", - "generated": "2026-09-11 02:04", + "generated": "2026-09-11 02:05", "aliases": [ "main", "ov_SC03_014", @@ -21,205 +21,205 @@ "main": { "objects": 85, "identical": 85, - "seconds": 6.5459999999999985, - "mean_s": 0.077 + "seconds": 6.725000000000002, + "mean_s": 0.079 }, "ov_SC03_014": { "objects": 32, "identical": 32, - "seconds": 4.541, - "mean_s": 0.142 + "seconds": 4.6339999999999995, + "mean_s": 0.145 }, "ov_SC03_015": { "objects": 32, "identical": 32, - "seconds": 4.361000000000001, - "mean_s": 0.136 + "seconds": 4.427999999999998, + "mean_s": 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b/.run/P36/delever/ledger.jsonl index 9e37ad31e..02f2e3ea9 100644 --- a/.run/P36/delever/ledger.jsonl +++ b/.run/P36/delever/ledger.jsonl @@ -29416,3 +29416,4 @@ {"ts": "2026-09-11 02:04:09", "label": "s104_e10", "rung": "E", "calib": {"head": "1f997967f", "stamp": "15956e4a96c4"}, "tu": "src/800.c", "fn": "func_80020598", "addr": 2147616152, "aliases": null, "header": false, "includers": 0, "nhash_before": "52fdb84e9f58799573ee1b242e36b9f49fcc05c7", "nhash_after": "07b889daa90864206a8c317aba41cf1dfbb3afe6", "source": ".run/P36/agents/main__func_80020598/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.43, "objects": ["build/src/800.o"], "before_text": "void func_80020598(s32 *a0, OBJ598 *a1, MTX_80020248 *a2, MTX_80020248 *a3)\n{\n MTX_80020248 lm;\n s16 local[3];\n MTX_80020248 *rm;\n s32 i;\n u32 w;\n s16 v;\n MH h2;\n MH h3;\n register MTX_80020248 *m3 __asm__(\"$8\"); // !FAKE: pin $8 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 pad[4];\n\n h2.p = a2;\n h3.p = a3;\n i = 0;\n rm = D_80074818;\n while (*a0 != 0) {\n switch (i) {\n case 0:\n local[0] = a1[3].h;\n w = *(u32 *)&a1[3];\n local[1] = a1[3].b1 | ((w & 0xF) << 8);\n local[2] = ((w >> 16) & 0xFF) | ((w & 0xF0) << 4);\n func_80020DA4((s32)local, (s32)&lm);\n func_80012558((s32)&lm, 0x800);\n lm.t[0] = (s8)a1->b0;\n lm.t[1] = (s8)a1->b1;\n lm.t[2] = (s8)a1->b2;\n break;\n case 1:\n local[0] = a1[3].h;\n w = *(u32 *)&a1[3];\n local[1] = a1[3].b1 | ((w & 0xF) << 8);\n local[2] = ((w >> 16) & 0xFF) | ((w & 0xF0) << 4);\n func_80020DA4((s32)local, (s32)&lm);\n lm.t[0] = a1->t[0];\n lm.t[1] = a1->t[1];\n lm.t[2] = a1->t[2];\n a1++;\n break;\n default:\n local[0] = a1->h;\n w = *(u32 *)a1;\n local[1] = ((w >> 8) & 0xFF) | ((w & 0xF) << 8);\n local[2] = ((w >> 16) & 0xFF) | ((w & 0xF0) << 4);\n func_80020DA4((s32)local, (s32)&lm);\n lm.t[0] = a1->t[0];\n lm.t[1] = a1->t[1];\n lm.t[2] = a1->t[2];\n a1++;\n if (i == 0x19) {\n v = D_80126C4E;\n local[2] = v;\n local[1] = v;\n local[0] = v;\n func_80020F34((s32)&lm, (s32)local);\n } else if (i == 0x16) {\n v = D_80126D10;\n local[2] = v;\n local[1] = v;\n local[0] = v;\n func_80020F34((s32)&lm, (s32)local);\n } else if (i == 8) {\n v = D_80126D12;\n local[2] = v;\n local[1] = v;\n local[0] = v;\n func_80020F34((s32)&lm, (s32)local);\n }\n break;\n }\n m3 = h2.p;\n gte_SetRotMatrix(m3);\n gte_ldclmv(&lm.m[0][0]);\n gte_rtir();\n gte_stclmv(&rm->m[0][0]);\n gte_ldclmv(&lm.m[0][1]);\n gte_rtir();\n gte_stclmv(&rm->m[0][1]);\n gte_ldclmv(&lm.m[0][2]);\n gte_rtir();\n gte_stclmv(&rm->m[0][2]);\n m3 = h3.p;\n gte_SetRotMatrix(m3);\n gte_ldclmv(&lm.m[0][0]);\n gte_rtir();\n gte_stclmv(&rm[0x40].m[0][0]);\n gte_ldclmv(&lm.m[0][1]);\n gte_rtir();\n gte_stclmv(&rm[0x40].m[0][1]);\n gte_ldclmv(&lm.m[0][2]);\n gte_rtir();\n gte_stclmv(&rm[0x40].m[0][2]);\n gte_SetTransMatrix(m3);\n gte_ldlv0(&lm.t[0]);\n gte_rtv0tr();\n gte_stlvnl(&rm[0x40].t[0]);\n rm++;\n a0++;\n i++;\n }\n}\n", "after_text": "void func_80020598(s32 *a0, OBJ598 *a1, MTX_80020248 *a2, MTX_80020248 *a3)\n{\n MTX_80020248 lm;\n s16 local[3];\n MTX_80020248 *rm;\n s32 i;\n u32 w;\n s16 v;\n\n i = 0;\n rm = D_80074818;\n while (*a0 != 0) {\n switch (i) {\n case 0:\n local[0] = a1[3].h;\n w = *(u32 *)&a1[3];\n local[1] = ((w >> 8) & 0xFF) | ((w & 0xF) << 8);\n local[2] = ((w >> 16) & 0xFF) | ((w & 0xF0) << 4);\n func_80020DA4((s32)local, (s32)&lm);\n func_80012558((s32)&lm, 0x800);\n lm.t[0] = (s8)a1->b0;\n lm.t[1] = (s8)a1->b1;\n lm.t[2] = (s8)a1->b2;\n break;\n case 1:\n local[0] = a1[3].h;\n w = *(u32 *)&a1[3];\n local[1] = ((w >> 8) & 0xFF) | ((w & 0xF) << 8);\n local[2] = ((w >> 16) & 0xFF) | ((w & 0xF0) << 4);\n func_80020DA4((s32)local, (s32)&lm);\n lm.t[0] = a1->t[0];\n lm.t[1] = a1->t[1];\n lm.t[2] = a1->t[2];\n a1++;\n break;\n default:\n local[0] = a1->h;\n w = *(u32 *)a1;\n local[1] = ((w >> 8) & 0xFF) | ((w & 0xF) << 8);\n local[2] = ((w >> 16) & 0xFF) | ((w & 0xF0) << 4);\n func_80020DA4((s32)local, (s32)&lm);\n lm.t[0] = a1->t[0];\n lm.t[1] = a1->t[1];\n lm.t[2] = a1->t[2];\n a1++;\n if (i == 0x19) {\n v = D_80126C4E;\n local[2] = v;\n local[1] = v;\n local[0] = v;\n func_80020F34((s32)&lm, (s32)local);\n } else if (i == 0x16) {\n v = D_80126D10;\n local[2] = v;\n local[1] = v;\n local[0] = v;\n func_80020F34((s32)&lm, (s32)local);\n } else if (i == 8) {\n v = D_80126D12;\n local[2] = v;\n local[1] = v;\n local[0] = v;\n func_80020F34((s32)&lm, (s32)local);\n }\n break;\n }\n gte_SetRotMatrix(a2);\n gte_ldclmv(&lm.m[0][0]);\n gte_rtir();\n gte_stclmv(&rm->m[0][0]);\n gte_ldclmv(&lm.m[0][1]);\n gte_rtir();\n gte_stclmv(&rm->m[0][1]);\n gte_ldclmv(&lm.m[0][2]);\n gte_rtir();\n gte_stclmv(&rm->m[0][2]);\n gte_SetRotMatrix(a3);\n gte_ldclmv(&lm.m[0][0]);\n gte_rtir();\n gte_stclmv(&rm[0x40].m[0][0]);\n gte_ldclmv(&lm.m[0][1]);\n gte_rtir();\n gte_stclmv(&rm[0x40].m[0][1]);\n gte_ldclmv(&lm.m[0][2]);\n gte_rtir();\n gte_stclmv(&rm[0x40].m[0][2]);\n gte_SetTransMatrix(a3);\n gte_ldlv0(&lm.t[0]);\n gte_rtv0tr();\n gte_stlvnl(&rm[0x40].t[0]);\n rm++;\n a0++;\n i++;\n }\n}\n"} {"ts": "2026-09-11 02:04:29", "label": "s104_e10", "rung": "E", "calib": {"head": "7f80f6682", "stamp": "15956e4a96c4"}, "tu": "src/800.c", "fn": "func_80015208", "addr": 2147570184, "aliases": null, "header": false, "includers": 0, "nhash_before": "d31038adf45d68a464526e443932c5472dfd3482", "nhash_after": "1efc316b0e1c3b700cd36ee602ff07595a52f3b6", "source": ".run/P36/agents/main__func_80015208/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.434, "objects": ["build/src/800.o"], "before_text": "void func_80015208(void) {\n u8 flag0;\n s32 v;\n u8 *base;\n\n flag0 = D_800B9A64;\n base = D_800AF630;\n\n if (flag0) {\n return;\n }\n if (D_800B9A10 != 1) {\n return;\n }\n if (D_800B9A17 != D_800B9A10) {\n return;\n }\n if (D_800B9A15 == D_800B9A17) {\n return;\n }\n if (D_800B9A16 != 0) {\n D_800B9A15 = 1;\n return;\n }\n if (D_800B9A13 != 0) {\n return;\n }\n\n {\n s32 mask = 0x800;\n\n if ((*(u16 *)&D_80078DD2 & 0x800) == mask) {\n v = 1;\n __asm__ __volatile__(\"\" : \"=r\"(v) : \"0\"(v)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus9)\n } else {\n v = 0;\n }\n if (!v) {\n if (D_800A5E78 != 0) {\n return;\n }\n }\n v = 1;\n base[0xA3E5] = v;\n func_801281D8();\n }\n}\n", "after_text": "void func_80015208(void) {\n s32 v;\n u8 *base;\n\n base = D_800AF630;\n\n if (D_800B9A64) {\n return;\n }\n if (D_800B9A10 != 1) {\n return;\n }\n if (D_800B9A17 != D_800B9A10) {\n return;\n }\n if (D_800B9A15 == D_800B9A17) {\n return;\n }\n if (D_800B9A16 != 0) {\n D_800B9A15 = 1;\n return;\n }\n {\n s32 mask = 0x800;\n\n if (D_800B9A13 != 0) {\n return;\n }\n v = *(u16 *)&D_80078DD2 & mask;\n if (v == mask) {\n v = 1;\n } else {\n v = 0;\n }\n if (!v && D_800A5E78 != 0) {\n return;\n }\n base[0xA3E5] = 1;\n func_801281D8();\n }\n}\n"} {"ts": "2026-09-11 02:04:50", "label": "s104_e10", "rung": "E", "calib": {"head": "7e7d9c523", "stamp": "15956e4a96c4"}, "tu": "src/800.c", "fn": "func_80021174", "addr": 2147619188, "aliases": null, "header": false, "includers": 0, "nhash_before": "ff01f6d8bf282c431329206e903f5ab8fb9a952c", "nhash_after": "27b3d5dffa268ac2b379b13c87142ab329756edf", "source": ".run/P36/agents/main__func_80021174/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.438, "objects": ["build/src/800.o"], "before_text": "s32 func_80021174(s32 a0, s32 a1)\n{\n s32 sp[4];\n s32 lim;\ns32 *p_a3;\nregister s32 ret __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n if (a0 == 0x7FFF7FFF)\n {\n return 1;\n }\n p_a3 = D_800AE688;\n__asm__ volatile ( \"lw $12, 0( %0 );\" \"lw $13, 4( %0 );\" \"ctc2 $12, $0;\" \"ctc2 $13, $1;\" \"lw $12, 8( %0 );\" \"lw $13, 12( %0 );\" \"lw $14, 16( %0 );\" \"ctc2 $12, $2;\" \"ctc2 $13, $3;\" \"ctc2 $14, $4;\" \"lw $12, 20( %0 );\" \"lw $13, 24( %0 );\" \"ctc2 $12, $5;\" \"lw $14, 28( %0 );\" \"ctc2 $13, $6;\" \"ctc2 $14, $7\" : : \"r\"( p_a3 ) : \"$12\", \"$13\", \"$14\", \"memory\" ); // !FAKE: gte direct \u2014 clobbers ['memory'] (gte_SetRotTransMatrix_m) beyond Sony's (P36 T5 gte1)\n__asm__ volatile ( \"lhu $13, 4( %0 );\" \"lhu $12, 0( %0 );\" \"sll $13, $13, 16;\" \"or $12, $12, $13;\" \"mtc2 $12, $0;\" \"lwc2 $1, 8( %0 )\" : : \"r\"( (SV_80021174 *)a1 ) : \"$12\", \"$13\", \"memory\" ); // !FAKE: gte direct \u2014 clobbers ['memory'] (gte_ldlv0_m) beyond Sony's (P36 T5 gte1)\n__asm__ volatile ( \"nop;\" \"nop;\" \"rtps\" : : : \"memory\" ); // !FAKE: gte direct \u2014 clobbers ['memory'] (gte_rtps_m) beyond Sony's (P36 T5 gte1)\ngte_stsxy(sp);\ngte_stflg(&sp[1]);\ngte_stszotz(&sp[2]);\n if (sp[1] < 0)\n {\n return 0;\n }\n ret = 0;\n lim = (s16) a0;\n ;\n if ((*((s16 *) sp)) <= (-lim))\n {\n return ret;\n }\n if (lim < (*((s16 *) sp)))\n {\n return ret;\n }\n a0 = a0 >> 16;\n a1 = *((s16 *) (((char *) sp) + 2));\n if (a1 <= (-a0))\n {\n return ret;\n }\n ret = !(a0 < a1);\n return ret;\n}\n", "after_text": "s32 func_80021174(s32 a0, s32 a1)\n{\n struct {\n s16 sx, sy;\n s32 flag;\n s32 otz;\n } r;\n s32 lim;\n\n if (a0 == 0x7FFF7FFF) {\n return 1;\n }\n gte_SetRotTransMatrix(D_800AE688);\n gte_ldlv0((SV_80021174 *)a1);\n gte_rtps();\n gte_stsxy(&r.sx);\n gte_stflg(&r.flag);\n gte_stszotz(&r.otz);\n if (r.flag < 0) {\n return 0;\n }\n lim = (s16)a0;\n if (-lim < r.sx && r.sx <= lim && -(a0 >> 16) < r.sy && r.sy <= (a0 >> 16)) {\n return 1;\n }\n return 0;\n}\n"} +{"ts": "2026-09-11 02:05:20", "label": "s104_e13", "rung": "E", "calib": {"head": "c37ef9c15", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c", "fn": "func_80185574", "addr": 2149078388, "aliases": null, "header": false, "includers": 0, "nhash_before": "9d423d4275920c5121fd435c05fc402c1fba561c", "nhash_after": "0bee5bbfb3d4a6371c187915f491596b1b83bab8", "source": ".run/P36/agents/ov_SC02_017__func_80185574/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.202, "objects": ["build/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.o"], "before_text": "void func_80185574(s32 arg0) {\n s32 self;\n register s32 zr __asm__(\"$0\"); // !FAKE: pin $0 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n s32 mask;\n s32 flag;\n\n self = arg0 + zr;\n flag = *(s16 *)(self + 0xAA);\n *(s16 *)(self + 0x5C) = 0;\n *(s16 *)(self + 0x98) = 0;\n *(s32 *)(self + 0x1C) = 0;\n if (flag == 0) {\n s32 p;\n register s32 f __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n mask = ~0x80;\n p = *(s32 *)(self + 0x20);\n f = *(s32 *)(self + 0xDC);\n p = *(u16 *)(p + 0x18);\n *(s32 *)(self + 0xDC) = f & mask;\n *(s16 *)(self + 0x100) = p;\n } else {\n s32 q;\n register s32 g __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n q = *(s32 *)(self + 0x20);\n g = *(s32 *)(self + 0xDC);\n q = *(u16 *)(q + 0x18);\n g |= 0x80;\n *(s32 *)(self + 0xDC) = g;\n *(s16 *)(self + 0x104) = q;\n }\n}\n", "after_text": "void func_80185574(s32 arg0) {\n *(s16 *)(arg0 + 0x5C) = 0;\n *(s16 *)(arg0 + 0x98) = 0;\n *(s32 *)(arg0 + 0x1C) = 0;\n if (*(s16 *)(arg0 + 0xAA) == 0) {\n *(s16 *)(arg0 + 0x100) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18);\n *(s32 *)(arg0 + 0xDC) &= ~0x80;\n } else {\n *(s16 *)(arg0 + 0x104) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18);\n *(s32 *)(arg0 + 0xDC) |= 0x80;\n }\n}\n"} diff --git a/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c b/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c index 7019af8a3..61ce62e46 100644 --- a/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c +++ b/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c @@ -7572,34 +7572,15 @@ void func_80185494(s32 a0) { void func_80185574(s32 arg0) { - s32 self; - register s32 zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus8) - s32 mask; - s32 flag; - - self = arg0 + zr; - flag = *(s16 *)(self + 0xAA); - *(s16 *)(self + 0x5C) = 0; - *(s16 *)(self + 0x98) = 0; - *(s32 *)(self + 0x1C) = 0; - if (flag == 0) { - s32 p; - register s32 f __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus8) - mask = ~0x80; - p = *(s32 *)(self + 0x20); - f = *(s32 *)(self + 0xDC); - p = *(u16 *)(p + 0x18); - *(s32 *)(self + 0xDC) = f & mask; - *(s16 *)(self + 0x100) = p; + *(s16 *)(arg0 + 0x5C) = 0; + *(s16 *)(arg0 + 0x98) = 0; + *(s32 *)(arg0 + 0x1C) = 0; + if (*(s16 *)(arg0 + 0xAA) == 0) { + *(s16 *)(arg0 + 0x100) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18); + *(s32 *)(arg0 + 0xDC) &= ~0x80; } else { - s32 q; - register s32 g __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus8) - q = *(s32 *)(self + 0x20); - g = *(s32 *)(self + 0xDC); - q = *(u16 *)(q + 0x18); - g |= 0x80; - *(s32 *)(self + 0xDC) = g; - *(s16 *)(self + 0x104) = q; + *(s16 *)(arg0 + 0x104) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18); + *(s32 *)(arg0 + 0xDC) |= 0x80; } }