diff --git a/.run/s43/r22c_check.log b/.run/s43/r22c_check.log new file mode 100644 index 000000000..febd17602 --- /dev/null +++ b/.run/s43/r22c_check.log @@ -0,0 +1,141 @@ +[ OK ] resident +[ OK ] ov_SC01_000 +[ OK ] ov_SC05_000 +[ OK ] ov_SC04_000 +[ OK ] ov_SC01_006 +[ OK ] ov_SC01_005 +[ OK ] ov_SC01_001 +[ OK ] ov_SC03_006 +[ OK ] ov_SC03_002 +[ OK ] ov_SC04_018 +[ OK ] ov_SC04_019 +[ OK ] ov_SC06_000 +[ OK ] ov_SC03_001 +[ OK ] ov_SC02_000 +[ OK ] ov_SC01_077 +[ OK ] ov_SC02_003 +[ OK ] ov_SC07_000 +[ OK ] ov_SC01_004 +[ OK ] ov_SC01_074 +[ OK ] ov_SC01_008 +[ OK ] ov_SC01_080 +[ OK ] ov_SC02_004 +[ OK ] ov_SC01_084 +[ OK ] ov_SC02_015 +[ OK ] ov_SC01_009 +[ OK ] ov_SC02_005 +[ OK ] ov_SC02_011 +[ OK ] ov_SC02_016 +[ OK ] ov_SC02_021 +[ OK ] ov_SC02_017 +[ OK ] ov_SC02_026 +[ OK ] main +[ OK ] ov_SC02_031 +[ OK ] ov_SC03_010 +[ OK ] ov_SC02_039 +[ OK ] ov_SC03_007 +[ OK ] ov_SC03_003 +[ OK ] ov_SC02_041 +[ OK ] ov_SC02_035 +[ OK ] ov_SC02_027 +[ OK ] ov_SC03_012 +[ OK ] ov_SC02_028 +[ OK ] ov_SC03_011 +[ OK ] ov_SC03_013 +[ OK ] ov_SC03_023 +[ OK ] ov_SC03_014 +[ OK ] ov_SC03_015 +[ OK ] ov_SC03_024 +[ OK ] ov_SC03_030 +[ OK ] ov_SC03_031 +[ OK ] ov_SC03_029 +[ OK ] ov_SC03_028 +[ OK ] ov_SC03_092 +[ OK ] ov_SC03_095 +[ OK ] ov_SC03_096 +[ OK ] ov_SC03_089 +[ OK ] ov_SC03_093 +[ OK ] ov_SC03_094 +[ OK ] ov_SC03_090 +[ OK ] ov_SC03_091 +[ OK ] ov_SC03_097 +[ OK ] ov_SC03_099 +[ OK ] ov_SC03_098 +[ OK ] ov_SC03_100 +[ OK ] ov_SC03_101 +[ OK ] ov_SC03_103 +[ OK ] ov_SC03_108 +[ OK ] ov_SC03_109 +[ OK ] ov_SC03_105 +[ OK ] ov_SC03_102 +[ OK ] ov_SC03_110 +[ OK ] ov_SC03_113 +[ OK ] ov_SC03_104 +[ OK ] ov_SC03_111 +[ OK ] ov_SC03_115 +[ OK ] ov_SC03_114 +[ OK ] ov_SC03_112 +[ OK ] ov_SC03_116 +[ OK ] ov_SC03_117 +[ OK ] ov_SC03_121 +[ OK ] ov_SC03_126 +[ OK ] ov_SC03_118 +[ OK ] ov_SC03_119 +[ OK ] ov_SC04_008 +[ OK ] ov_SC03_125 +[ OK ] ov_SC04_003 +[ OK ] ov_SC04_006 +[ OK ] ov_SC03_124 +[ OK ] ov_SC04_002 +[ OK ] ov_SC04_004 +[ OK ] ov_SC04_009 +[ OK ] ov_SC04_007 +[ OK ] ov_SC04_005 +[ OK ] ov_SC04_010 +[ OK ] ov_SC04_011 +[ OK ] ov_SC04_012 +[ OK ] ov_SC04_016 +[ OK ] ov_SC04_015 +[ OK ] ov_SC04_021 +[ OK ] ov_SC04_020 +[ OK ] ov_SC05_005 +[ OK ] ov_SC05_003 +[ OK ] ov_SC05_002 +[ OK ] ov_SC05_009 +[ OK ] ov_SC05_001 +[ OK ] ov_SC05_006 +[ OK ] ov_SC05_004 +[ OK ] ov_SC05_008 +[ OK ] ov_SC05_007 +[ OK ] ov_SC05_010 +[ OK ] ov_SC05_011 +[ OK ] ov_SC05_019 +[ OK ] ov_SC05_017 +[ OK ] ov_SC05_018 +[ OK ] ov_SC06_006 +[ OK ] ov_SC06_010 +[ OK ] ov_SC06_013 +[ OK ] ov_SC06_015 +[ OK ] ov_SC06_011 +[ OK ] ov_SC06_014 +[ OK ] ov_SC06_008 +[ OK ] ov_SC06_016 +[ OK ] ov_SC06_020 +[ OK ] ov_SC06_022 +[ OK ] ov_SC06_018 +[ OK ] ov_SC06_025 +[ OK ] ov_SC06_024 +[ OK ] ov_SC06_027 +[ OK ] ov_SC07_009 +[ OK ] ov_SC07_008 +[ OK ] ov_SC06_030 +[ OK ] ov_SC07_002 +[ OK ] ov_SC07_001 +[ OK ] ov_SC07_007 +[ OK ] ov_SC06_029 +[ OK ] ov_SC07_010 +[ OK ] ov_SC07_011 +[ OK ] ov_SC06_032 +[ OK ] ov_SC06_033 +[ OK ] ov_SC07_006 +check-all: 140 passed, 0 failed of 140 diff --git a/.run/s43/r22c_extract.log b/.run/s43/r22c_extract.log new file mode 100644 index 000000000..8775612c7 --- /dev/null +++ b/.run/s43/r22c_extract.log @@ -0,0 +1,154 @@ +splat 0.41.0 (powered by spimdisasm 1.41.0) + 0%| | 0/1050 [00:00 31/36, and every blocker was a DECLARATION (2026-08-03/04) Lane 2 of the S10 checkpoint ("26,006 ins, ~0 agent tokens, PARTLY BLOCKED"), taken first on the standing doctrine that the cheap deterministic lever is probed before the expensive agent one. diff --git a/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c b/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c index 8a3d813e6..8dd09df38 100644 --- a/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c +++ b/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c @@ -4785,7 +4785,206 @@ INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_801813C INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_801814AC); -INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_801814F8); + + +#define gte_ldv0(r0) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 )" \ + : \ + : "r"( r0 ) ) +#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 );" \ + "lwc2 $2, 0( %1 );" \ + "lwc2 $3, 4( %1 );" \ + "lwc2 $4, 0( %2 );" \ + "lwc2 $5, 4( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) ) +#define gte_rtps() __asm__ volatile ("nop;nop;rtps") +#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt") +#define gte_stsxy(r0) __asm__ volatile ( \ + "swc2 $14, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) +#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \ + "swc2 $12, 0( %0 );" \ + "swc2 $13, 0( %1 );" \ + "swc2 $14, 0( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ + : "memory" ) +#define gte_stszotz(r0) __asm__ volatile ( \ + "mfc2 $12, $19;" \ + "nop;" \ + "sra $12, $12, 2;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_stflg(r0) __asm__ volatile ( \ + "cfc2 $12, $31;" \ + "nop;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_ldv0(r0) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 )" \ + : \ + : "r"( r0 ) ) +#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 );" \ + "lwc2 $2, 0( %1 );" \ + "lwc2 $3, 4( %1 );" \ + "lwc2 $4, 0( %2 );" \ + "lwc2 $5, 4( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) ) +#define gte_rtps() __asm__ volatile ("nop;nop;rtps") +#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt") +#define gte_stsxy(r0) __asm__ volatile ( \ + "swc2 $14, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) +#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \ + "swc2 $12, 0( %0 );" \ + "swc2 $13, 0( %1 );" \ + "swc2 $14, 0( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ + : "memory" ) +#define gte_stszotz(r0) __asm__ volatile ( \ + "mfc2 $12, $19;" \ + "nop;" \ + "sra $12, $12, 2;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_stflg(r0) __asm__ volatile ( \ + "cfc2 $12, $31;" \ + "nop;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) + +void func_801814F8(void *a0, void *a1) +{ + + extern void func_8001E094(void); + extern void func_8001E378(void *a0); + extern void func_80181914(void *a0, void *a1, u32 *a2, u32 *a3); + extern u8 D_800A6610[]; + extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0); + * unsigned access forced at the use — §8d sub-class (b) */ + + Vec8_80182FD4 base; + Vec8_80182FD4 v[3]; + u32 buf[19]; + long flag; + long otz; + long flag2; + + Src_80182FD4 *s; + u32 *ot; + s32 z; + s32 i; + u16 w; + + ot = (u32 *)&D_800A6610[(*(u16 *)&D_800B9A02) << 14]; + s = *(Src_80182FD4 **)((s32)a0 + 0x20); + if (s == 0) { + return; + } + + if (*(s32 *)((s32)a0 + 0x34) != 0) { + func_8001E094(); + } else { + func_8001E378(a0); + } + + base.vx = *(u16 *)((s32)a0 + 0x2E); + base.vy = *(u16 *)((s32)a0 + 0x30); + base.vz = *(u16 *)((s32)a0 + 0x32); + + gte_ldv0(&base); + gte_rtps(); + gte_stsxy(&buf[0]); + gte_stflg(&flag); + gte_stszotz(&otz); + + if (flag & ~0x1000) { + return; + } + + w = *(u16 *)((s32)a0 + 0x2C); + z = otz + 1; + if ((w & 0xC000) != 0) { + if ((w & 0xC000) == 0xC000) { + z -= (w & 0xFFF); + if (z < 0) { + z = 0; + } + } else { + z += (w & 0xFFF); + } + } + if (z >= 0x1000) { + return; + } + + if (*(s16 *)((s32)a0 + 0x1E) & 0x8000) { + for (i = 0; i < 12; i += 6) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + v[1].vx = base.vx + s->pt[i + 2].vx; + v[1].vy = base.vy + s->pt[i + 2].vy; + v[1].vz = base.vz; + v[2].vx = base.vx + s->pt[i + 4].vx; + v[2].vy = base.vy + s->pt[i + 4].vy; + v[2].vz = base.vz; + gte_ldv3(&v[0], &v[1], &v[2]); + gte_rtpt(); + gte_stsxy3(&buf[i + 1], &buf[i + 3], &buf[i + 5]); + } + for (i = 1; i < 12; i += 2) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + gte_ldv0(&v[0]); + gte_rtps(); + gte_stsxy(&buf[i + 1]); + gte_stflg(&flag2); + gte_stszotz(&otz); + buf[13 + (i >> 1)] = otz + 1; + } + func_80181914(a0, a1, &buf[0], ot); + } else { + for (i = 0; i < 12; i += 3) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + v[1].vx = base.vx + s->pt[i + 1].vx; + v[1].vy = base.vy + s->pt[i + 1].vy; + v[1].vz = base.vz; + v[2].vx = base.vx + s->pt[i + 2].vx; + v[2].vy = base.vy + s->pt[i + 2].vy; + v[2].vz = base.vz; + gte_ldv3(&v[0], &v[1], &v[2]); + gte_rtpt(); + gte_stsxy3(&buf[i + 1], &buf[i + 2], &buf[i + 3]); + } + func_80181914(a0, a1, &buf[0], ot + z); + } +} + #define ADDPRIM_801833F0(o, p) \ (((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \ diff --git a/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c b/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c index b597a1503..546e639b8 100644 --- a/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c +++ b/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c @@ -4897,7 +4897,206 @@ INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_8018480 INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_801848E8); -INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_80184934); + + +#define gte_ldv0(r0) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 )" \ + : \ + : "r"( r0 ) ) +#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 );" \ + "lwc2 $2, 0( %1 );" \ + "lwc2 $3, 4( %1 );" \ + "lwc2 $4, 0( %2 );" \ + "lwc2 $5, 4( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) ) +#define gte_rtps() __asm__ volatile ("nop;nop;rtps") +#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt") +#define gte_stsxy(r0) __asm__ volatile ( \ + "swc2 $14, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) +#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \ + "swc2 $12, 0( %0 );" \ + "swc2 $13, 0( %1 );" \ + "swc2 $14, 0( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ + : "memory" ) +#define gte_stszotz(r0) __asm__ volatile ( \ + "mfc2 $12, $19;" \ + "nop;" \ + "sra $12, $12, 2;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_stflg(r0) __asm__ volatile ( \ + "cfc2 $12, $31;" \ + "nop;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_ldv0(r0) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 )" \ + : \ + : "r"( r0 ) ) +#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 );" \ + "lwc2 $2, 0( %1 );" \ + "lwc2 $3, 4( %1 );" \ + "lwc2 $4, 0( %2 );" \ + "lwc2 $5, 4( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) ) +#define gte_rtps() __asm__ volatile ("nop;nop;rtps") +#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt") +#define gte_stsxy(r0) __asm__ volatile ( \ + "swc2 $14, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) +#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \ + "swc2 $12, 0( %0 );" \ + "swc2 $13, 0( %1 );" \ + "swc2 $14, 0( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ + : "memory" ) +#define gte_stszotz(r0) __asm__ volatile ( \ + "mfc2 $12, $19;" \ + "nop;" \ + "sra $12, $12, 2;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_stflg(r0) __asm__ volatile ( \ + "cfc2 $12, $31;" \ + "nop;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) + +void func_80184934(void *a0, void *a1) +{ + + extern void func_8001E094(void); + extern void func_8001E378(void *a0); + extern void func_80184D50(void *a0, void *a1, u32 *a2, u32 *a3); + extern u8 D_800A6610[]; + extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0); + * unsigned access forced at the use — §8d sub-class (b) */ + + Vec8_80182FD4 base; + Vec8_80182FD4 v[3]; + u32 buf[19]; + long flag; + long otz; + long flag2; + + Src_80182FD4 *s; + u32 *ot; + s32 z; + s32 i; + u16 w; + + ot = (u32 *)&D_800A6610[(*(u16 *)&D_800B9A02) << 14]; + s = *(Src_80182FD4 **)((s32)a0 + 0x20); + if (s == 0) { + return; + } + + if (*(s32 *)((s32)a0 + 0x34) != 0) { + func_8001E094(); + } else { + func_8001E378(a0); + } + + base.vx = *(u16 *)((s32)a0 + 0x2E); + base.vy = *(u16 *)((s32)a0 + 0x30); + base.vz = *(u16 *)((s32)a0 + 0x32); + + gte_ldv0(&base); + gte_rtps(); + gte_stsxy(&buf[0]); + gte_stflg(&flag); + gte_stszotz(&otz); + + if (flag & ~0x1000) { + return; + } + + w = *(u16 *)((s32)a0 + 0x2C); + z = otz + 1; + if ((w & 0xC000) != 0) { + if ((w & 0xC000) == 0xC000) { + z -= (w & 0xFFF); + if (z < 0) { + z = 0; + } + } else { + z += (w & 0xFFF); + } + } + if (z >= 0x1000) { + return; + } + + if (*(s16 *)((s32)a0 + 0x1E) & 0x8000) { + for (i = 0; i < 12; i += 6) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + v[1].vx = base.vx + s->pt[i + 2].vx; + v[1].vy = base.vy + s->pt[i + 2].vy; + v[1].vz = base.vz; + v[2].vx = base.vx + s->pt[i + 4].vx; + v[2].vy = base.vy + s->pt[i + 4].vy; + v[2].vz = base.vz; + gte_ldv3(&v[0], &v[1], &v[2]); + gte_rtpt(); + gte_stsxy3(&buf[i + 1], &buf[i + 3], &buf[i + 5]); + } + for (i = 1; i < 12; i += 2) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + gte_ldv0(&v[0]); + gte_rtps(); + gte_stsxy(&buf[i + 1]); + gte_stflg(&flag2); + gte_stszotz(&otz); + buf[13 + (i >> 1)] = otz + 1; + } + func_80184D50(a0, a1, &buf[0], ot); + } else { + for (i = 0; i < 12; i += 3) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + v[1].vx = base.vx + s->pt[i + 1].vx; + v[1].vy = base.vy + s->pt[i + 1].vy; + v[1].vz = base.vz; + v[2].vx = base.vx + s->pt[i + 2].vx; + v[2].vy = base.vy + s->pt[i + 2].vy; + v[2].vz = base.vz; + gte_ldv3(&v[0], &v[1], &v[2]); + gte_rtpt(); + gte_stsxy3(&buf[i + 1], &buf[i + 2], &buf[i + 3]); + } + func_80184D50(a0, a1, &buf[0], ot + z); + } +} + #define ADDPRIM_801833F0(o, p) \ (((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \ diff --git a/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c b/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c index a1fb2e17f..54753e6a2 100644 --- a/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c +++ b/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c @@ -3855,7 +3855,206 @@ INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8017BEBC", func_8017E39 INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8017BEBC", func_8017E498); -INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8017BEBC", func_8017E4F4); + + +#define gte_ldv0(r0) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 )" \ + : \ + : "r"( r0 ) ) +#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 );" \ + "lwc2 $2, 0( %1 );" \ + "lwc2 $3, 4( %1 );" \ + "lwc2 $4, 0( %2 );" \ + "lwc2 $5, 4( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) ) +#define gte_rtps() __asm__ volatile ("nop;nop;rtps") +#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt") +#define gte_stsxy(r0) __asm__ volatile ( \ + "swc2 $14, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) +#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \ + "swc2 $12, 0( %0 );" \ + "swc2 $13, 0( %1 );" \ + "swc2 $14, 0( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ + : "memory" ) +#define gte_stszotz(r0) __asm__ volatile ( \ + "mfc2 $12, $19;" \ + "nop;" \ + "sra $12, $12, 2;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_stflg(r0) __asm__ volatile ( \ + "cfc2 $12, $31;" \ + "nop;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_ldv0(r0) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 )" \ + : \ + : "r"( r0 ) ) +#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 );" \ + "lwc2 $2, 0( %1 );" \ + "lwc2 $3, 4( %1 );" \ + "lwc2 $4, 0( %2 );" \ + "lwc2 $5, 4( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) ) +#define gte_rtps() __asm__ volatile ("nop;nop;rtps") +#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt") +#define gte_stsxy(r0) __asm__ volatile ( \ + "swc2 $14, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) +#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \ + "swc2 $12, 0( %0 );" \ + "swc2 $13, 0( %1 );" \ + "swc2 $14, 0( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ + : "memory" ) +#define gte_stszotz(r0) __asm__ volatile ( \ + "mfc2 $12, $19;" \ + "nop;" \ + "sra $12, $12, 2;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_stflg(r0) __asm__ volatile ( \ + "cfc2 $12, $31;" \ + "nop;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) + +void func_8017E4F4(void *a0, void *a1) +{ + + extern void func_8001E094(void); + extern void func_8001E378(void *a0); + extern void func_8017E910(void *a0, void *a1, u32 *a2, u32 *a3); + extern u8 D_800A6610[]; + extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0); + * unsigned access forced at the use — §8d sub-class (b) */ + + Vec8_80182FD4 base; + Vec8_80182FD4 v[3]; + u32 buf[19]; + long flag; + long otz; + long flag2; + + Src_80182FD4 *s; + u32 *ot; + s32 z; + s32 i; + u16 w; + + ot = (u32 *)&D_800A6610[(*(u16 *)&D_800B9A02) << 14]; + s = *(Src_80182FD4 **)((s32)a0 + 0x20); + if (s == 0) { + return; + } + + if (*(s32 *)((s32)a0 + 0x34) != 0) { + func_8001E094(); + } else { + func_8001E378(a0); + } + + base.vx = *(u16 *)((s32)a0 + 0x2E); + base.vy = *(u16 *)((s32)a0 + 0x30); + base.vz = *(u16 *)((s32)a0 + 0x32); + + gte_ldv0(&base); + gte_rtps(); + gte_stsxy(&buf[0]); + gte_stflg(&flag); + gte_stszotz(&otz); + + if (flag & ~0x1000) { + return; + } + + w = *(u16 *)((s32)a0 + 0x2C); + z = otz + 1; + if ((w & 0xC000) != 0) { + if ((w & 0xC000) == 0xC000) { + z -= (w & 0xFFF); + if (z < 0) { + z = 0; + } + } else { + z += (w & 0xFFF); + } + } + if (z >= 0x1000) { + return; + } + + if (*(s16 *)((s32)a0 + 0x1E) & 0x8000) { + for (i = 0; i < 12; i += 6) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + v[1].vx = base.vx + s->pt[i + 2].vx; + v[1].vy = base.vy + s->pt[i + 2].vy; + v[1].vz = base.vz; + v[2].vx = base.vx + s->pt[i + 4].vx; + v[2].vy = base.vy + s->pt[i + 4].vy; + v[2].vz = base.vz; + gte_ldv3(&v[0], &v[1], &v[2]); + gte_rtpt(); + gte_stsxy3(&buf[i + 1], &buf[i + 3], &buf[i + 5]); + } + for (i = 1; i < 12; i += 2) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + gte_ldv0(&v[0]); + gte_rtps(); + gte_stsxy(&buf[i + 1]); + gte_stflg(&flag2); + gte_stszotz(&otz); + buf[13 + (i >> 1)] = otz + 1; + } + func_8017E910(a0, a1, &buf[0], ot); + } else { + for (i = 0; i < 12; i += 3) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + v[1].vx = base.vx + s->pt[i + 1].vx; + v[1].vy = base.vy + s->pt[i + 1].vy; + v[1].vz = base.vz; + v[2].vx = base.vx + s->pt[i + 2].vx; + v[2].vy = base.vy + s->pt[i + 2].vy; + v[2].vz = base.vz; + gte_ldv3(&v[0], &v[1], &v[2]); + gte_rtpt(); + gte_stsxy3(&buf[i + 1], &buf[i + 2], &buf[i + 3]); + } + func_8017E910(a0, a1, &buf[0], ot + z); + } +} + #define ADDPRIM_801833F0(o, p) \ (((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \ diff --git a/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c b/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c index 82c633fdc..9c00c2840 100644 --- a/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c +++ b/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c @@ -5747,7 +5747,206 @@ INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_80180EF INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_80180FF8); -INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_80181054); + + +#define gte_ldv0(r0) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 )" \ + : \ + : "r"( r0 ) ) +#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 );" \ + "lwc2 $2, 0( %1 );" \ + "lwc2 $3, 4( %1 );" \ + "lwc2 $4, 0( %2 );" \ + "lwc2 $5, 4( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) ) +#define gte_rtps() __asm__ volatile ("nop;nop;rtps") +#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt") +#define gte_stsxy(r0) __asm__ volatile ( \ + "swc2 $14, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) +#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \ + "swc2 $12, 0( %0 );" \ + "swc2 $13, 0( %1 );" \ + "swc2 $14, 0( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ + : "memory" ) +#define gte_stszotz(r0) __asm__ volatile ( \ + "mfc2 $12, $19;" \ + "nop;" \ + "sra $12, $12, 2;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_stflg(r0) __asm__ volatile ( \ + "cfc2 $12, $31;" \ + "nop;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_ldv0(r0) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 )" \ + : \ + : "r"( r0 ) ) +#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 );" \ + "lwc2 $2, 0( %1 );" \ + "lwc2 $3, 4( %1 );" \ + "lwc2 $4, 0( %2 );" \ + "lwc2 $5, 4( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) ) +#define gte_rtps() __asm__ volatile ("nop;nop;rtps") +#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt") +#define gte_stsxy(r0) __asm__ volatile ( \ + "swc2 $14, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) +#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \ + "swc2 $12, 0( %0 );" \ + "swc2 $13, 0( %1 );" \ + "swc2 $14, 0( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ + : "memory" ) +#define gte_stszotz(r0) __asm__ volatile ( \ + "mfc2 $12, $19;" \ + "nop;" \ + "sra $12, $12, 2;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_stflg(r0) __asm__ volatile ( \ + "cfc2 $12, $31;" \ + "nop;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) + +void func_80181054(void *a0, void *a1) +{ + + extern void func_8001E094(void); + extern void func_8001E378(void *a0); + extern void func_80181470(void *a0, void *a1, u32 *a2, u32 *a3); + extern u8 D_800A6610[]; + extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0); + * unsigned access forced at the use — §8d sub-class (b) */ + + Vec8_80182FD4 base; + Vec8_80182FD4 v[3]; + u32 buf[19]; + long flag; + long otz; + long flag2; + + Src_80182FD4 *s; + u32 *ot; + s32 z; + s32 i; + u16 w; + + ot = (u32 *)&D_800A6610[(*(u16 *)&D_800B9A02) << 14]; + s = *(Src_80182FD4 **)((s32)a0 + 0x20); + if (s == 0) { + return; + } + + if (*(s32 *)((s32)a0 + 0x34) != 0) { + func_8001E094(); + } else { + func_8001E378(a0); + } + + base.vx = *(u16 *)((s32)a0 + 0x2E); + base.vy = *(u16 *)((s32)a0 + 0x30); + base.vz = *(u16 *)((s32)a0 + 0x32); + + gte_ldv0(&base); + gte_rtps(); + gte_stsxy(&buf[0]); + gte_stflg(&flag); + gte_stszotz(&otz); + + if (flag & ~0x1000) { + return; + } + + w = *(u16 *)((s32)a0 + 0x2C); + z = otz + 1; + if ((w & 0xC000) != 0) { + if ((w & 0xC000) == 0xC000) { + z -= (w & 0xFFF); + if (z < 0) { + z = 0; + } + } else { + z += (w & 0xFFF); + } + } + if (z >= 0x1000) { + return; + } + + if (*(s16 *)((s32)a0 + 0x1E) & 0x8000) { + for (i = 0; i < 12; i += 6) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + v[1].vx = base.vx + s->pt[i + 2].vx; + v[1].vy = base.vy + s->pt[i + 2].vy; + v[1].vz = base.vz; + v[2].vx = base.vx + s->pt[i + 4].vx; + v[2].vy = base.vy + s->pt[i + 4].vy; + v[2].vz = base.vz; + gte_ldv3(&v[0], &v[1], &v[2]); + gte_rtpt(); + gte_stsxy3(&buf[i + 1], &buf[i + 3], &buf[i + 5]); + } + for (i = 1; i < 12; i += 2) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + gte_ldv0(&v[0]); + gte_rtps(); + gte_stsxy(&buf[i + 1]); + gte_stflg(&flag2); + gte_stszotz(&otz); + buf[13 + (i >> 1)] = otz + 1; + } + func_80181470(a0, a1, &buf[0], ot); + } else { + for (i = 0; i < 12; i += 3) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + v[1].vx = base.vx + s->pt[i + 1].vx; + v[1].vy = base.vy + s->pt[i + 1].vy; + v[1].vz = base.vz; + v[2].vx = base.vx + s->pt[i + 2].vx; + v[2].vy = base.vy + s->pt[i + 2].vy; + v[2].vz = base.vz; + gte_ldv3(&v[0], &v[1], &v[2]); + gte_rtpt(); + gte_stsxy3(&buf[i + 1], &buf[i + 2], &buf[i + 3]); + } + func_80181470(a0, a1, &buf[0], ot + z); + } +} + #define ADDPRIM_801833F0(o, p) \ (((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \ diff --git a/src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c b/src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c index 927896240..7a63faaf8 100644 --- a/src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c +++ b/src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c @@ -5116,7 +5116,206 @@ INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_8017FDB INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_8017FEAC); -INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_8017FF08); + + +#define gte_ldv0(r0) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 )" \ + : \ + : "r"( r0 ) ) +#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 );" \ + "lwc2 $2, 0( %1 );" \ + "lwc2 $3, 4( %1 );" \ + "lwc2 $4, 0( %2 );" \ + "lwc2 $5, 4( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) ) +#define gte_rtps() __asm__ volatile ("nop;nop;rtps") +#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt") +#define gte_stsxy(r0) __asm__ volatile ( \ + "swc2 $14, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) +#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \ + "swc2 $12, 0( %0 );" \ + "swc2 $13, 0( %1 );" \ + "swc2 $14, 0( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ + : "memory" ) +#define gte_stszotz(r0) __asm__ volatile ( \ + "mfc2 $12, $19;" \ + "nop;" \ + "sra $12, $12, 2;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_stflg(r0) __asm__ volatile ( \ + "cfc2 $12, $31;" \ + "nop;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_ldv0(r0) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 )" \ + : \ + : "r"( r0 ) ) +#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \ + "lwc2 $0, 0( %0 );" \ + "lwc2 $1, 4( %0 );" \ + "lwc2 $2, 0( %1 );" \ + "lwc2 $3, 4( %1 );" \ + "lwc2 $4, 0( %2 );" \ + "lwc2 $5, 4( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) ) +#define gte_rtps() __asm__ volatile ("nop;nop;rtps") +#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt") +#define gte_stsxy(r0) __asm__ volatile ( \ + "swc2 $14, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) +#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \ + "swc2 $12, 0( %0 );" \ + "swc2 $13, 0( %1 );" \ + "swc2 $14, 0( %2 )" \ + : \ + : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ + : "memory" ) +#define gte_stszotz(r0) __asm__ volatile ( \ + "mfc2 $12, $19;" \ + "nop;" \ + "sra $12, $12, 2;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) +#define gte_stflg(r0) __asm__ volatile ( \ + "cfc2 $12, $31;" \ + "nop;" \ + "sw $12, 0( %0 )" \ + : \ + : "r"( r0 ) \ + : "$12", "memory" ) + +void func_8017FF08(void *a0, void *a1) +{ + + extern void func_8001E094(void); + extern void func_8001E378(void *a0); + extern void func_80180324(void *a0, void *a1, u32 *a2, u32 *a3); + extern u8 D_800A6610[]; + extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0); + * unsigned access forced at the use — §8d sub-class (b) */ + + Vec8_80182FD4 base; + Vec8_80182FD4 v[3]; + u32 buf[19]; + long flag; + long otz; + long flag2; + + Src_80182FD4 *s; + u32 *ot; + s32 z; + s32 i; + u16 w; + + ot = (u32 *)&D_800A6610[(*(u16 *)&D_800B9A02) << 14]; + s = *(Src_80182FD4 **)((s32)a0 + 0x20); + if (s == 0) { + return; + } + + if (*(s32 *)((s32)a0 + 0x34) != 0) { + func_8001E094(); + } else { + func_8001E378(a0); + } + + base.vx = *(u16 *)((s32)a0 + 0x2E); + base.vy = *(u16 *)((s32)a0 + 0x30); + base.vz = *(u16 *)((s32)a0 + 0x32); + + gte_ldv0(&base); + gte_rtps(); + gte_stsxy(&buf[0]); + gte_stflg(&flag); + gte_stszotz(&otz); + + if (flag & ~0x1000) { + return; + } + + w = *(u16 *)((s32)a0 + 0x2C); + z = otz + 1; + if ((w & 0xC000) != 0) { + if ((w & 0xC000) == 0xC000) { + z -= (w & 0xFFF); + if (z < 0) { + z = 0; + } + } else { + z += (w & 0xFFF); + } + } + if (z >= 0x1000) { + return; + } + + if (*(s16 *)((s32)a0 + 0x1E) & 0x8000) { + for (i = 0; i < 12; i += 6) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + v[1].vx = base.vx + s->pt[i + 2].vx; + v[1].vy = base.vy + s->pt[i + 2].vy; + v[1].vz = base.vz; + v[2].vx = base.vx + s->pt[i + 4].vx; + v[2].vy = base.vy + s->pt[i + 4].vy; + v[2].vz = base.vz; + gte_ldv3(&v[0], &v[1], &v[2]); + gte_rtpt(); + gte_stsxy3(&buf[i + 1], &buf[i + 3], &buf[i + 5]); + } + for (i = 1; i < 12; i += 2) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + gte_ldv0(&v[0]); + gte_rtps(); + gte_stsxy(&buf[i + 1]); + gte_stflg(&flag2); + gte_stszotz(&otz); + buf[13 + (i >> 1)] = otz + 1; + } + func_80180324(a0, a1, &buf[0], ot); + } else { + for (i = 0; i < 12; i += 3) { + v[0].vx = base.vx + s->pt[i].vx; + v[0].vy = base.vy + s->pt[i].vy; + v[0].vz = base.vz; + v[1].vx = base.vx + s->pt[i + 1].vx; + v[1].vy = base.vy + s->pt[i + 1].vy; + v[1].vz = base.vz; + v[2].vx = base.vx + s->pt[i + 2].vx; + v[2].vy = base.vy + s->pt[i + 2].vy; + v[2].vz = base.vz; + gte_ldv3(&v[0], &v[1], &v[2]); + gte_rtpt(); + gte_stsxy3(&buf[i + 1], &buf[i + 2], &buf[i + 3]); + } + func_80180324(a0, a1, &buf[0], ot + z); + } +} + #define ADDPRIM_801833F0(o, p) \