From 656aa4f51420e9bec20fa68656a436763a5eb078 Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Mon, 24 Aug 2026 23:39:41 -0600 Subject: [PATCH] =?UTF-8?q?feat(decomp):=20main=20lane=20m09b=20=E2=80=94?= =?UTF-8?q?=2016=20banked?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit One clean whole-EXE rebuild verified the batch (gate_main), and main re-checked BYTE-IDENTICAL against config/check.us.sha before anything was credited. SYS_OBJ_16C SYS_OBJ_1A70 SYS_OBJ_FD8 SetPriority SetRGBfifo SetRii SquareRoot12 func_80010BB4 func_80028304 func_8002EA10 func_80047D3C func_8005AB00 func_8005B75C gfx2D_BG0_OBJ_1B4 gfx2D_BG0_OBJ_4A0 gteMIMefunc --- src/800.c | 56 ++++++++++- src/800b.c | 169 ++++++++++++++++++++++++++++++++- src/800b_7.c | 260 ++++++++++++++++++++++++++++++++++++++++++++++++++- src/800c.c | 141 ++++++++++++++++++++++++++-- src/boot.c | 34 ++++++- src/gsgap5.c | 21 ++++- 6 files changed, 665 insertions(+), 16 deletions(-) diff --git a/src/800.c b/src/800.c index 7289dfe39..81c835134 100644 --- a/src/800.c +++ b/src/800.c @@ -11123,7 +11123,33 @@ INCLUDE_ASM("asm/nonmatchings/800", func_8002823C); void func_800282FC(void) { } -INCLUDE_ASM("asm/nonmatchings/800", func_80028304); +extern u8 D_800A5E88; +extern s32 D_800A5E8C; +extern s32 D_800A5E90; +extern u8 D_800A5E94; +extern u8 D_800A5E95; +extern u8 D_800A5E96; +extern void func_80028620(s32 a0, void *a1); + +void func_80028304(s32 a0, s32 a1, s32 a2, s32 a3, u8 a4, u8 a5, u8 a6) { + s32 offset; + + a0 &= 0xFFFF; + if ((u16)a0 >= 3) { + return; + } + + offset = a0 << 4; + + *(s32 *)((s32)&D_800A5E88 + offset) = a1; + *(s32 *)((s32)&D_800A5E8C + offset) = a2; + *(s32 *)((s32)&D_800A5E90 + offset) = a3; + *(u8 *)((s32)&D_800A5E94 + offset) = a4; + *(u8 *)((s32)&D_800A5E95 + offset) = a5; + *(u8 *)((s32)&D_800A5E96 + offset) = a6; + + func_80028620(a0, (void *)((s32)&D_800A5E88 + offset)); +} extern u8 D_800A5E88; @@ -13369,7 +13395,33 @@ void func_8002E94C(s32 a0) } } -INCLUDE_ASM("asm/nonmatchings/800", func_8002EA10); +extern u16 D_800A4E8E; +extern s16 D_800A4E86; + +extern s32 func_8003836C(s32 a0); +extern s32 func_800381E4(s32 a0, s32 a1); +extern void func_8002EC10(void); +extern void func_800383A4(s16 a0); + +void func_8002EA10(void) { + register u16 *s0 __asm__("$16"); + u16 v0; + s32 ret; + + s0 = &D_800A4E8E; + v0 = *s0; + if (v0 & 4) { + ret = func_8003836C(D_800A4E86); + if ((ret << 16) != 0) { + if (func_800381E4(D_800A4E86, 0) != 0) { + func_8002EC10(); + } else { + func_800383A4(D_800A4E86); + *s0 = *s0 | 0x10; + } + } + } +} extern u16 D_800A4E8E; diff --git a/src/800b.c b/src/800b.c index f37c0358a..33b5c9bd5 100644 --- a/src/800b.c +++ b/src/800b.c @@ -1,6 +1,85 @@ #include "common.h" -INCLUDE_ASM("asm/nonmatchings/800b", func_80047D3C); +/* + * func_80047D3C == PsyQ SquareRoot0(long a): hand-written GTE-assisted integer + * square root (splat marks it "Handwritten function"). The argument goes + * straight into the GTE (mtc2 $a0,$30 = lzcs), the leading-zero count comes + * back (mfc2 $v0,$31 = lzcr), the mantissa is normalised, a table at + * D_8006D8EC is indexed and the half-word result shifted out. Un-compilable + * tells: direct cop2 transfers with hand-placed hazard nops, `sub`/`addi` + * where cc1 emits `subu`/`addiu`, a dead `andi $t0,$v0,1`, a branch target + * that doubles as the preceding `b`'s delay slot (0x80047D84), and a second + * exit whose return value sits in the final `jr`'s delay slot. No -O2 C can + * emit this, so per cookbook ยง265 the body is banked as a verbatim file-scope + * __asm__ transcription of the target .s, with the full form-1 directive + * scaffold (.ent/.frame/.end) used by the two gate-proven banked precedents. + * + * maspsx interaction: the leading ".set noreorder" is SPACE-formed so maspsx's + * is_reorder tracker stays True and IT fills every empty branch delay slot -- + * so the nops after beq/bltz/b/jr are deliberately NOT written by hand. The + * two mtc2 hazard nops ARE hand-written (maspsx knows nothing about cop2 + * latency), and so is the nop after `lh $t5,%lo(...)($t5)`: maspsx's + * load-delay pass does not fire on this lh/base-reuse shape (measured). + * Immediates are decimal (maspsx int()s them); %hi/%lo relocate correctly. + * + * Recovered C semantics: + * long SquareRoot0(long a) { + * gte_ldLZCS(a); u = gte_stLZCR(); + * if (u == 0x20) return 0; + * e = u & ~1; + * sh = (0x1f - e) >> 1; + * m = (e - 0x18 < 0) ? (a >> (0x18 - e)) : (a << (e - 0x18)); + * return ((int)*(short *)&D_8006D8EC[(m - 0x40)] << sh) >> 12; + * } + */ +__asm__( + ".text\n" + ".align 2\n" + ".globl func_80047D3C\n" + ".ent func_80047D3C\n" + "func_80047D3C:\n" + ".frame $sp, 0, $31\n" + ".set noreorder\n" + "mtc2 $4, $30\n" + "nop\n" + "nop\n" + "mfc2 $2, $31\n" + "addiu $1, $0, 32\n" + "beq $2, $1, 3f\n" + "andi $8, $2, 1\n" + "addiu $10, $0, -2\n" + "and $10, $2, $10\n" + "addiu $9, $0, 31\n" + "sub $9, $9, $10\n" + "sra $9, $9, 1\n" + "addi $11, $10, -24\n" + "bltz $11, 1f\n" + "sllv $12, $4, $11\n" + "b 2f\n" + "1:\n" + "addiu $11, $0, 24\n" + "sub $11, $11, $10\n" + "srav $12, $4, $11\n" + "2:\n" + "addi $12, $12, -64\n" + "sll $12, $12, 1\n" + "lui $13, %hi(D_8006D8EC)\n" + "addu $13, $13, $12\n" + "lh $13, %lo(D_8006D8EC)($13)\n" + "nop\n" + "sllv $13, $13, $9\n" + "srl $2, $13, 12\n" + "jr $31\n" + "nop\n" + "3:\n" + "jr $31\n" + "addiu $2, $0, 0\n" + ".set reorder\n" + "nop\n" + "nop\n" + "nop\n" + ".end func_80047D3C\n" +); INCLUDE_ASM("asm/nonmatchings/800b", InvSquareRoot); @@ -77,6 +156,90 @@ INCLUDE_ASM("asm/nonmatchings/800b", func_80047EC8); INCLUDE_ASM("asm/nonmatchings/800b", MatrixNormal); -INCLUDE_ASM("asm/nonmatchings/800b", gteMIMefunc); +void gteMIMefunc() +{ + __asm__ __volatile__( + ".set\tnoreorder\n" + "sll $6, $6, 3\n" + "add $6, $6, $5\n" + "mtc2 $7, $8\n" + ".L80048078:\n" + "lw $8, 0($5)\n" + "lh $10, 4($5)\n" + "sra $9, $8, 16\n" + "andi $8, $8, 65535\n" + "mtc2 $8, $9\n" + "mtc2 $9, $10\n" + "mtc2 $10, $11\n" + "nop\n" + "nop\n" + "cop2 0x198003D\n" + "lw $2, 0($4)\n" + "lh $7, 4($4)\n" + "sra $3, $2, 16\n" + "andi $2, $2, 65535\n" + "addi $5, $5, 8\n" + "mfc2 $8, $9\n" + "mfc2 $9, $10\n" + "mfc2 $10, $11\n" + "add $2, $2, $8\n" + "add $3, $3, $9\n" + "add $7, $7, $10\n" + "sh $2, 0($4)\n" + "sh $3, 2($4)\n" + "sh $7, 4($4)\n" + "addi $4, $4, 8\n" + "bne $5, $6, .L80048078\n" + "nop\n" + ".set\treorder\n" + ); +} -INCLUDE_ASM("asm/nonmatchings/800b", SquareRoot12); +__asm__( + ".text\n" + ".align 2\n" + ".globl SquareRoot12\n" + "SquareRoot12:\n" + ".set\tnoreorder\n" + "mtc2 $4, $30\n" + "nop\n" + "nop\n" + "mfc2 $2, $31\n" + "addiu $1, $0, 32\n" + ".word 0x1041001d\n" + "nop\n" + "andi $8, $2, 1\n" + "addiu $10, $0, -2\n" + "and $10, $2, $10\n" + "addiu $9, $0, 19\n" + "sub $9, $9, $10\n" + "sra $9, $9, 1\n" + "addi $11, $10, -24\n" + ".word 0x05600003\n" + "nop\n" + "sllv $12, $4, $11\n" + ".word 0x10000003\n" + "addiu $11, $0, 24\n" + "sub $11, $11, $10\n" + "srav $12, $4, $11\n" + "addi $12, $12, -64\n" + "sll $12, $12, 1\n" + "lui $13, %hi(D_8006D8EC)\n" + "addu $13, $13, $12\n" + "lh $13, %lo(D_8006D8EC)($13)\n" + "nop\n" + ".word 0x05200004\n" + "nop\n" + "sllv $2, $13, $9\n" + ".word 0x03e00008\n" + "nop\n" + "neg $9, $9\n" + ".word 0x03e00008\n" + "srlv $2, $13, $9\n" + ".word 0x03e00008\n" + "addiu $2, $0, 0\n" + "nop\n" + "nop\n" + "nop\n" + ".set\treorder\n" +); diff --git a/src/800b_7.c b/src/800b_7.c index 47919b50f..6f4c17631 100644 --- a/src/800b_7.c +++ b/src/800b_7.c @@ -145,9 +145,265 @@ __asm__( ".end\tGsSortBg\n" ); -INCLUDE_ASM("asm/nonmatchings/800b_7", gfx2D_BG0_OBJ_1B4); +/* gfx2D_BG0_OBJ_1B4 (0x800509C0) is NOT a callable function: fragment 2 of one larger routine + * beginning in GsSortBg (owns the 0xE0 frame + saves), continuing through + * gfx2D_BG0_OBJ_4A0/_4D8/_658/_698. No prologue/epilogue: entered by `j gfx2D_BG0_OBJ_1B4` + * with live values in $s5/$fp/$s1, stores into the CALLER's frame; exits via + * `j gfx2D_BG0_OBJ_4A0` on one path and falls through into it on the other. Expressed as the + * byte-verified file-scope inline-asm fragment idiom of src/800c.c (SYS_OBJ_1DC0). + * Transcription laws learned here: maspsx rejects HEX immediates in __asm__ strings (decimal + * only); its expand-div parser requires cc1-style TIGHT COMMAS; and ASPSX break encoding puts + * the trap code in the HIGH field (word 0x0007000D) -- spelled `break 7168`/`break 6144` + * (= code<<10, GNU-as places code at bits 25..6) since bare `break 7` encodes 0x0000018D. + * Body transcribed 1:1 from asm/nonmatchings/800b_7/gfx2D_BG0_OBJ_1B4.s; + * `beq $a1,$v0,.L80050D5C` forward-references the label defined in gfx2D_BG0_OBJ_4D8.s of the + * SAME assembly unit (INCLUDE_ASM .includes all sibling .s files into one assembly stream). + */ +__asm__( + ".text\n" + ".align\t2\n" + ".globl\tgfx2D_BG0_OBJ_1B4\n" + ".ent\tgfx2D_BG0_OBJ_1B4\n" + "gfx2D_BG0_OBJ_1B4:\n" + ".set\tnoreorder\n" + "lh $v0,12($s5)\n" + "lw $t8,112($sp)\n" + "nop\n" + "div $zero,$v0,$t8\n" + "bnez $t8,.L800509DC\n" + "nop\n" + "break 7168\n" + ".L800509DC:\n" + "addiu $at,$zero,-1\n" + "bne $t8,$at,.L800509F4\n" + "lui $at,32768\n" + "bne $v0,$at,.L800509F4\n" + "nop\n" + "break 6144\n" + ".L800509F4:\n" + "mfhi $t3\n" + "lui $s2,%hi(D_800A5E60)\n" + "lw $s2,%lo(D_800A5E60)($s2)\n" + "lh $t8,8($s5)\n" + "nop\n" + "sw $t8,104($sp)\n" + "lh $v1,10($s5)\n" + "bgez $t3,.L80050A24\n" + "andi $a0,$fp,65535\n" + "lw $t8,112($sp)\n" + "nop\n" + "addu $t3,$t3,$t8\n" + ".L80050A24:\n" + "lh $v0,14($s5)\n" + "lw $t8,120($sp)\n" + "nop\n" + "div $zero,$v0,$t8\n" + "bnez $t8,.L80050A40\n" + "nop\n" + "break 7168\n" + ".L80050A40:\n" + "addiu $at,$zero,-1\n" + "bne $t8,$at,.L80050A58\n" + "lui $at,32768\n" + "bne $v0,$at,.L80050A58\n" + "nop\n" + "break 6144\n" + ".L80050A58:\n" + "mfhi $t7\n" + "nop\n" + "bgez $t7,.L80050A70\n" + "addu $s6,$t7,$zero\n" + "addu $t7,$t7,$t8\n" + "addu $s6,$t7,$zero\n" + ".L80050A70:\n" + "div $zero,$s6,$a0\n" + "bnez $a0,.L80050A80\n" + "nop\n" + "break 7168\n" + ".L80050A80:\n" + "addiu $at,$zero,-1\n" + "bne $a0,$at,.L80050A98\n" + "lui $at,32768\n" + "bne $s6,$at,.L80050A98\n" + "nop\n" + "break 6144\n" + ".L80050A98:\n" + "mfhi $t2\n" + "lh $t8,6($s5)\n" + "subu $s7,$fp,$t2\n" + "andi $v0,$s7,65535\n" + "slt $v0,$v1,$v0\n" + "beqz $v0,.L80050AB8\n" + "sw $t8,136($sp)\n" + "addu $s7,$v1,$zero\n" + ".L80050AB8:\n" + "andi $t4,$s1,65535\n" + "addu $v1,$s6,$v1\n" + "lhu $t5,128($sp)\n" + "lw $t8,104($sp)\n" + "addiu $t1,$s2,4\n" + "sw $v1,144($sp)\n" + "lhu $v0,26($s5)\n" + "sh $s7,64($sp)\n" + "addu $t6,$t3,$t8\n" + "lhu $t8,136($sp)\n" + "negu $v0,$v0\n" + "sh $v0,68($sp)\n" + "sh $t8,60($sp)\n" + ".L80050AEC:\n" + "addu $s0,$t3,$zero\n" + "div $zero,$s0,$t5\n" + "bnez $t5,.L80050B00\n" + "nop\n" + "break 7168\n" + ".L80050B00:\n" + "addiu $at,$zero,-1\n" + "bne $t5,$at,.L80050B18\n" + "lui $at,32768\n" + "bne $s0,$at,.L80050B18\n" + "nop\n" + "break 6144\n" + ".L80050B18:\n" + "mfhi $a2\n" + "lhu $t8,128($sp)\n" + "lh $t0,4($s5)\n" + "subu $s3,$t8,$a2\n" + "lw $t8,104($sp)\n" + "andi $v0,$s3,65535\n" + "slt $v0,$t8,$v0\n" + "beqz $v0,.L80050B40\n" + "nop\n" + "lhu $s3,104($sp)\n" + ".L80050B40:\n" + "lw $t8,120($sp)\n" + "nop\n" + "div $zero,$s6,$t8\n" + "bnez $t8,.L80050B58\n" + "nop\n" + "break 7168\n" + ".L80050B58:\n" + "addiu $at,$zero,-1\n" + "bne $t8,$at,.L80050B70\n" + "lui $at,32768\n" + "bne $s6,$at,.L80050B70\n" + "nop\n" + "break 6144\n" + ".L80050B70:\n" + "mfhi $v0\n" + "lw $t8,112($sp)\n" + "nop\n" + "div $zero,$s0,$t8\n" + "bnez $t8,.L80050B8C\n" + "nop\n" + "break 7168\n" + ".L80050B8C:\n" + "addiu $at,$zero,-1\n" + "bne $t8,$at,.L80050BA4\n" + "lui $at,32768\n" + "bne $s0,$at,.L80050BA4\n" + "nop\n" + "break 6144\n" + ".L80050BA4:\n" + "mfhi $v1\n" + "nop\n" + "nop\n" + "div $zero,$v0,$fp\n" + "bnez $fp,.L80050BC0\n" + "nop\n" + "break 7168\n" + ".L80050BC0:\n" + "addiu $at,$zero,-1\n" + "bne $fp,$at,.L80050BD8\n" + "lui $at,32768\n" + "bne $v0,$at,.L80050BD8\n" + "nop\n" + "break 6144\n" + ".L80050BD8:\n" + "mflo $v0\n" + "nop\n" + "nop\n" + "div $zero,$v1,$t5\n" + "bnez $t5,.L80050BF4\n" + "nop\n" + "break 7168\n" + ".L80050BF4:\n" + "addiu $at,$zero,-1\n" + "bne $t5,$at,.L80050C0C\n" + "lui $at,32768\n" + "bne $v1,$at,.L80050C0C\n" + "nop\n" + "break 6144\n" + ".L80050C0C:\n" + "mflo $v1\n" + "nop\n" + "nop\n" + "mult $v0,$t4\n" + "lw $a0,20($s5)\n" + "mflo $t8\n" + "addu $s1,$v1,$t8\n" + "lw $v1,12($a0)\n" + "sll $v0,$s1,1\n" + "addu $v0,$v0,$v1\n" + "lhu $a1,0($v0)\n" + "ori $v0,$zero,65535\n" + "beq $a1,$v0,.L80050D5C\n" + "addiu $v0,$s2,40\n" + "lw $v1,8($a0)\n" + "sw $v0,0($s2)\n" + "addiu $v0,$zero,9\n" + "sb $v0,-1($t1)\n" + "sll $v0,$a1,3\n" + "addu $a3,$v1,$v0\n" + "lhu $v0,6($a3)\n" + "lhu $t8,96($sp)\n" + "andi $v0,$v0,31\n" + "or $v0,$t8,$v0\n" + "sh $v0,52($sp)\n" + "lhu $v0,2($a3)\n" + "sh $t0,58($sp)\n" + "sh $v0,54($sp)\n" + "lhu $v0,4($a3)\n" + "nop\n" + "andi $v0,$v0,2\n" + "beqz $v0,.L80050C9C\n" + "nop\n" + "lbu $v0,0($a3)\n" + "j gfx2D_BG0_OBJ_4A0\n" + "sb $v0,56($sp)\n" + ".L80050C9C:\n" + "lbu $v0,0($a3)\n" + "nop\n" + "addu $v0,$v0,$a2\n" + "sb $v0,56($sp)\n" + ".set\treorder\n" + ".end\tgfx2D_BG0_OBJ_1B4\n" +); -INCLUDE_ASM("asm/nonmatchings/800b_7", gfx2D_BG0_OBJ_4A0); +__asm__( + ".text\n" + ".align\t2\n" + ".globl\tgfx2D_BG0_OBJ_4A0\n" + ".ent\tgfx2D_BG0_OBJ_4A0\n" + "gfx2D_BG0_OBJ_4A0:\n" + ".set\tnoreorder\n" + "lhu $v0, 4($a3)\n" + "nop\n" + "andi $v0, $v0, 0x1\n" + "beqz $v0, .L80050CD8\n" + "nop\n" + "lbu $v0, 1($a3)\n" + "nop\n" + "addu $v0, $fp, $v0\n" + "subu $v0, $v0, $s7\n" + "j gfx2D_BG0_OBJ_4D8\n" + "subu $v0, $v0, $t2\n" + ".L80050CD8:\n" + "lbu $v0, 1($a3)\n" + "nop\n" + "addu $v0, $v0, $t2\n" + ".set\treorder\n" + ".end\tgfx2D_BG0_OBJ_4A0\n" +); INCLUDE_ASM("asm/nonmatchings/800b_7", gfx2D_BG0_OBJ_4D8); diff --git a/src/800c.c b/src/800c.c index b40fd8b5a..e652334e1 100644 --- a/src/800c.c +++ b/src/800c.c @@ -126,7 +126,22 @@ __asm__( INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_11C); -INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_16C); +__asm__( + ".text\n" + ".align\t2\n" + ".globl\tSYS_OBJ_16C\n" + ".ent\tSYS_OBJ_16C\n" + "SYS_OBJ_16C:\n" + ".set\tnoreorder\n" + "lw $ra, 24($sp)\n" + "lw $s1, 20($sp)\n" + "lw $s0, 16($sp)\n" + "addiu $sp, $sp, 0x20\n" + "jr $ra\n" + "nop\n" + ".set\treorder\n" + ".end\tSYS_OBJ_16C\n" +); __asm__( ".text\n" @@ -1044,7 +1059,42 @@ __asm__( ".end\tSYS_OBJ_F58\n" ); -INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_FD8); +__asm__( + ".text\n" + ".align\t2\n" + ".globl\tSYS_OBJ_FD8\n" + ".ent\tSYS_OBJ_FD8\n" + "SYS_OBJ_FD8:\n" + ".set\tnoreorder\n" + "addu $s1, $a0, $zero\n" + "addiu $a1, $s1, 2\n" + "slt $v0, $s2, $a1\n" + "bnez $v0, SYS_OBJ_1034\n" + "nop\n" + "lbu $v0, 18($s0)\n" + "nop\n" + "beqz $v0, .L8005A240\n" + "slti $v0, $s2, 313\n" + "beqz $v0, .L8005A24C\n" + "nop\n" + "j SYS_OBJ_1034\n" + "addu $a1, $s2, $zero\n" + ".L8005A240:\n" + "slti $v0, $s2, 259\n" + "bnez $v0, .L8005A264\n" + "nop\n" + ".L8005A24C:\n" + "lbu $v0, 18($s0)\n" + "nop\n" + "beqz $v0, SYS_OBJ_1034\n" + "addiu $a1, $zero, 258\n" + "j SYS_OBJ_1034\n" + "addiu $a1, $zero, 312\n" + ".L8005A264:\n" + "addu $a1, $s2, $zero\n" + ".set\treorder\n" + ".end\tSYS_OBJ_FD8\n" +); INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_1034); @@ -1106,7 +1156,19 @@ INCLUDE_ASM("asm/nonmatchings/800c", SetDrawArea); INCLUDE_ASM("asm/nonmatchings/800c", SetDrawOffset); -INCLUDE_ASM("asm/nonmatchings/800c", SetPriority); +void SetPriority(unsigned char *arg0, int arg1, int arg2) { + unsigned int temp; + arg0[3] = 2; + temp = 0xE6000000; + if (arg1 != 0) { + temp |= 2; + } + if (arg2 != 0) { + temp |= 1; + } + *(unsigned int *)(arg0 + 4) = temp; + *(unsigned int *)(arg0 + 8) = 0; +} extern s32 func_8005AB00(s32 a0, s32 a1, u16 a2); extern s32 func_8005AD34(s32 a0); @@ -1303,7 +1365,42 @@ __asm__( INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_18AC); -INCLUDE_ASM("asm/nonmatchings/800c", func_8005AB00); +__asm__( +".text\n" +".align\t2\n" +".globl\tfunc_8005AB00\n" +".ent\tfunc_8005AB00\n" +"func_8005AB00:\n" +".frame\t$sp,0,$31\n" +".mask\t0x00000000,0\n" +".fmask\t0x00000000,0\n" +".set\tnoreorder\n" +"lui $v0, %hi(D_80072788)\n" +"lbu $v0, %lo(D_80072788)($v0)\n" +"nop\n" +"addiu $v0, $v0, -1\n" +"sltiu $v0, $v0, 2\n" +"beqz $v0, .L8005AB38\n" +"nop\n" +"beqz $a1, .L8005AB28\n" +"lui $v1, 57600\n" +"ori $v1, $v1, 2048\n" +".L8005AB28:\n" +"beqz $a0, SYS_OBJ_191C\n" +"andi $v0, $a2, 10239\n" +"j SYS_OBJ_191C\n" +"ori $v0, $v0, 4096\n" +".L8005AB38:\n" +"beqz $a1, .L8005AB44\n" +"lui $v1, 57600\n" +"ori $v1, $v1, 512\n" +".L8005AB44:\n" +"beqz $a0, SYS_OBJ_191C\n" +"andi $v0, $a2, 2559\n" +"ori $v0, $v0, 1024\n" +".set\treorder\n" +".end\tfunc_8005AB00\n" +); INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_191C); @@ -1328,7 +1425,33 @@ INCLUDE_ASM("asm/nonmatchings/800c", func_8005AC24); INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_1A30); -INCLUDE_ASM("asm/nonmatchings/800c", SYS_OBJ_1A70); +__asm__( + ".text\n" + ".align\t2\n" + ".globl\tSYS_OBJ_1A70\n" + ".ent\tSYS_OBJ_1A70\n" + "SYS_OBJ_1A70:\n" + ".frame\t$sp,0,$31\n" + ".mask\t0x00000000,0\n" + ".fmask\t0x00000000,0\n" + ".set\tnoreorder\n" + "lui $2, %hi(D_80072788)\n" + "lbu $2, %lo(D_80072788)($2)\n" + "nop\n" + "addiu $2, $2, -1\n" + "sltiu $2, $2, 2\n" + "bnez $2, 1f\n" + " andi $3, $5, 0xfff\n" + "andi $3, $5, 0x3ff\n" + "sll $3, $3, 10\n" + "j SYS_OBJ_1AA4\n" + " andi $2, $7, 0x3ff\n" + "1:\n" + "sll $3, $3, 12\n" + "andi $2, $7, 0xfff\n" + ".set\treorder\n" + ".end\tSYS_OBJ_1A70\n" +); s32 SYS_OBJ_1AA4(s32 a0, s32 a1, s32 a2, s32 a3) { register s32 v0 __asm__("$2"); @@ -1851,7 +1974,13 @@ void func_8005B710(s32 a0) { *D_80072868 = 0x01000401; } -INCLUDE_ASM("asm/nonmatchings/800c", func_8005B75C); +extern volatile u32 *D_8007285C; +extern volatile u32 *D_80072858; + +u32 func_8005B75C(u32 a0) { + *D_8007285C = a0 | 0x10000000; + return *D_80072858 & 0xFFFFFF; +} INCLUDE_ASM("asm/nonmatchings/800c", _addque); diff --git a/src/boot.c b/src/boot.c index 40def8d0e..2eaedcdde 100644 --- a/src/boot.c +++ b/src/boot.c @@ -40,7 +40,39 @@ void GameModeDispatch(void) { gameModeHandlerTable[*(u16 *)(p + 0xA3AE)](); } -INCLUDE_ASM("asm/nonmatchings/boot", func_80010BB4); +extern u8 D_800AF630[]; +extern void func_8001C044(void); +extern void func_80015310(void); +extern void func_80029690(void); +extern void func_80018FC8(void); +extern void func_8001903C(void); +extern void func_80029274(void); +extern void func_8002941C(void); +extern void func_80010AE0(s32); +extern void func_80011B7C(s32); +extern void func_80011778(void); +extern s16 D_801150D4; +extern s32 D_80074784; + +void func_80010BB4(void) { + register u8 *p = D_800AF630; + + *(p + 0xA3E0) = 0; + *(p + 0xA3E1) = 1; + *(p + 0xA434) = 0; + func_8001C044(); + func_80015310(); + func_80029690(); + D_801150D4 = 0; + D_80074784 = 0; + func_80018FC8(); + func_8001903C(); + func_80029274(); + func_8002941C(); + func_80010AE0(0x3E0); + func_80011B7C(0); + func_80011778(); +} INCLUDE_ASM("asm/nonmatchings/boot", func_80010C7C); diff --git a/src/gsgap5.c b/src/gsgap5.c index 23c959100..792501a51 100644 --- a/src/gsgap5.c +++ b/src/gsgap5.c @@ -19,7 +19,16 @@ void SetVertexTri(long *r0, long *r1, long *r2) : "r"(r0), "r"(r1), "r"(r2)); } -INCLUDE_ASM("asm/nonmatchings/gsgap5", SetRGBfifo); +void SetRGBfifo(void* r0, void* r1, void* r2) +{ + __asm__ __volatile__ ( + "lwc2 $20, 0( %0 );" + "lwc2 $21, 0( %1 );" + "lwc2 $22, 0( %2 )" + : + : "r"( r0 ), "r"( r1 ), "r"( r2 ) + : "memory" ); +} INCLUDE_ASM("asm/nonmatchings/gsgap5", SetIR123); @@ -57,7 +66,15 @@ void SetSZfifo4() INCLUDE_ASM("asm/nonmatchings/gsgap5", SetSXSYfifo); -INCLUDE_ASM("asm/nonmatchings/gsgap5", SetRii); +void SetRii() +{ + __asm__ __volatile__( + ".set\tnoreorder\n" + "ctc2 $4, $0\n" + "ctc2 $5, $2\n" + "ctc2 $6, $4\n" + ".set\treorder\n"); +} INCLUDE_ASM("asm/nonmatchings/gsgap5", SetMAC123);