diff --git a/.run/P36/agents/ov_SC05_001__func_8017EF88/body.c b/.run/P36/agents/ov_SC05_001__func_8017EF88/body.c new file mode 100644 index 000000000..f8ac9c057 --- /dev/null +++ b/.run/P36/agents/ov_SC05_001__func_8017EF88/body.c @@ -0,0 +1,35 @@ +u32 func_8017EF88(s16 *param_1, s16 *param_2, s16 *param_3) { + union { + struct { + s16 x, y; + } v; + s32 sxy; + } a, b, c; + s16 ax, ay, bx, by, cx, cy; + + ax = param_1[0]; + cx = param_3[0]; + if (cx < ax) { + return 0; + } + bx = param_2[0]; + if (bx < cx) { + return 1; + } + by = param_2[1]; + cy = param_3[2]; + if (cy < by) { + return 0; + } + ay = param_1[1]; + if (ay >= cy) { + a.v.x = ax; + a.v.y = ay; + b.v.x = bx; + b.v.y = by; + c.v.x = cx; + c.v.y = cy; + return func_800495EC(a.sxy, b.sxy, c.sxy) >= 0; + } + return 1; +} diff --git a/.run/P36/agents/ov_SC05_001__func_8017EF88/body_free.c b/.run/P36/agents/ov_SC05_001__func_8017EF88/body_free.c new file mode 100644 index 000000000..21b055993 --- /dev/null +++ b/.run/P36/agents/ov_SC05_001__func_8017EF88/body_free.c @@ -0,0 +1,35 @@ +u32 func_8017EF88(s16 *param_1, s16 *param_2, s16 *param_3) { + s16 ax, ay, bx, by, cx, cy; + s32 la; + s32 lb; + s32 lc; + u32 r; + s32 pad[2]; + + ax = param_1[0]; + cx = param_3[0]; + if (cx < ax) { + return 0; + } + bx = param_2[0]; + if (bx < cx) { + return 1; + } + by = param_2[1]; + do { + cy = param_3[2]; + if (cy < by) { + return 0; + } + ay = param_1[1]; + if (ay >= cy) { + la = (u16)ax; + lb = (u16)bx; + lc = (u16)cx; + r = func_800495EC(la | ((u16)ay << 16), lb | ((u16)by << 16), + lc | ((u16)cy << 16)); + return ~r >> 31; + } + return 1; + } while (0); +} diff --git a/.run/P36/agents/ov_SC05_001__func_8017EF88/body_tree.c b/.run/P36/agents/ov_SC05_001__func_8017EF88/body_tree.c new file mode 100644 index 000000000..a9c333554 --- /dev/null +++ b/.run/P36/agents/ov_SC05_001__func_8017EF88/body_tree.c @@ -0,0 +1,37 @@ +u32 func_8017EF88(s16 *param_1, s16 *param_2, s16 *param_3) { + s16 ax, ay, bx, by, cx, cy; + register s32 la __asm__("$8"); // !FAKE: pin $8 — NEEDED DIFFERS (P36 rung B tus8) + register s32 lb __asm__("$7"); // !FAKE: pin $7 — NEEDED DIFFERS (P36 rung B tus8) + register s32 lc __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus8) + u32 r; + s32 pad[2]; + + ax = param_1[0]; + cx = param_3[0]; + if (cx < ax) { + return 0; + } + __asm__ __volatile__("" : : "r"(la), "r"(lb), "r"(lc)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus8) + bx = param_2[0]; + if (bx < cx) { + return 1; + } + by = param_2[1]; + do { + cy = param_3[2]; + if (cy < by) { + return 0; + } + ay = param_1[1]; + if (ay >= cy) { + la = (u16)ax; + lb = (u16)bx; + lc = (u16)cx; + __asm__ __volatile__("" : : "r"(ax), "r"(bx), "r"(cx)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus8) + r = func_800495EC(la | ((u16)ay << 16), lb | ((u16)by << 16), + lc | ((u16)cy << 16)); + return ~r >> 31; + } + return 1; + } while (0); +} diff --git a/.run/P36/agents/ov_SC05_001__func_8017EF88/history.txt b/.run/P36/agents/ov_SC05_001__func_8017EF88/history.txt new file mode 100644 index 000000000..52a566f8a --- /dev/null +++ b/.run/P36/agents/ov_SC05_001__func_8017EF88/history.txt @@ -0,0 +1,14 @@ +g6b: verdict NO-MATCH start 14 best 12 compiles 320 path R9 swap-stmts @4369 +best-scoring single candidates of the last trace (move -> score [residual class]): + R9 swap-stmts @4369 -> 12 [REG] (from 14) + R10 param-copy param_1 @4351 -> 12 [REG] (from 12) + R7 block @4367 -> 12 [REG] (from 12) + R9 swap-stmts @4352 -> 12 [REG] (from 12) + R2 decl-order 0,2,1 -> 12 [REG] (from 12) + R4 decl-move la 0->3 -> 12 [REG] (from 12) + R10 param-copy param_2 @4351 -> 12 [REG] (from 12) + R7 do-while @4367 -> 12 [REG] (from 12) + R2 decl-order 1,0,2 -> 12 [REG] (from 12) + R4 decl-move la 0->4 -> 12 [REG] (from 12) + R10 param-copy param_3 @4351 -> 12 [REG] (from 12) + R7 block @4352 -> 12 [REG] (from 12) diff --git a/.run/P36/agents/ov_SC05_001__func_8017EF88/mechanism.md b/.run/P36/agents/ov_SC05_001__func_8017EF88/mechanism.md new file mode 100644 index 000000000..7ff4227ea --- /dev/null +++ b/.run/P36/agents/ov_SC05_001__func_8017EF88/mechanism.md @@ -0,0 +1,82 @@ +# func_8017EF88 (src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c) — d10, P36 S104 + +**RESULT: score 0 in plain C, zero levers** (before: 3 pins `$8/$7/$3` + 2 keepalives + `do { } while (0)` + dead +`s32 pad[2]`; after: none of them). The sibling **func_8017F040 (same TU) closes by the same move at score 0** +(`scratch/f040_body.c`). Both verified with `tools/delever_search.py --try … --body`. + +## (a) The residual +REG only, 46 = 46 instructions. Target: the three packed arguments sit in `$t0/$a3/$v1` (arg0/arg1/arg2) and EVERY +other global — the cx load temp, the ax/bx/cx/cy s16 copies — avoids those three registers (`$t1..$t4`). The free +body gave the packs `$v0/$v1/$a3` (local-alloc, block 8 only) and let the globals use `$v1/$a3/$t0`. The frame +(vars=56) matched only because of the dead `pad[2]`. + +## (b) Mechanism (proved on bytes and in the dumps, `scratch/dumps_win/`) +The original builds each NCLIP argument as a **register union** (`union { struct { s16 x, y; } v; s32 sxy; }`) +by storing its two fields, then passes the word. +1. A 4-byte union with an `s32` member has SImode, so it lives in a pseudo. A field store into a REG goes through + `store_bit_field`; MIPS `insv` FAILs for a non-MEM operand (`config/mips/mips.md:2901-2921`), so + `store_fixed_bit_field` emits read-modify-write `u = (u & mask) | value` (`expmed.c:689-697` and, ior below it). +2. The first field store READS the uninitialised union, so flow marks all three union pseudos live at the + function entry and at the start of every block down to the call (`.flow`: "Registers live at start: 4 5 6 29 30 + 75 76 77", blocks 0 through 8). +3. combine folds each insert pair into `andi`/`sll`/`or`, so the read vanishes from the insns. But global.c seeds + each block's conflict scan from flow's **pre-combine** `basic_block_live_at_start` (`global.c:640-660`), so the + three unions still conflict with every pseudo in the function (`.greg`: 75/76/77 conflict with 72-85, 95). + They are allocated as globals in priority order 77 (c) → `$v1`, 76 (b) → `$a3`, 75 (a) → `$t0`. `$v0` is + skipped because the block-local `slt`/load temps hold it, and `$a0-$a2` because the parameters conflict. Every + later global then skips `$v1/$a3/$t0`. That is exactly what the `$8/$7/$3` pins plus the "live from entry" + keepalive were faking. The second keepalive (ax/bx/cx live past the masks) was faking the same conflicts. +4. The frame: the 7th "ST_REGS or none" pseudo (flow counts it, combine eliminates it, reload gives it an 8-byte slot) + is reg 106 = the shared `0xFFFF0000` clear mask of the three x-inserts. That is what `s32 pad[2]` was faking. The + other six are the `ashift` halves of the s16 sign extensions (the free body had those six too, hence vars=48+8). + +## (c) The move (one line) +Replace the three `la/lb/lc = (u16)x` masks + `x | ((u16)y << 16)` packs (and the pins, both keepalives, the +`do/while(0)` and `pad[2]`) with three body-local unions `a, b, c` whose `.v.x/.v.y` are assigned from the s16 +locals just before the call, passing `a.sxy, b.sxy, c.sxy`. Readability extras, both byte-neutral: +`return func_800495EC(...) >= 0;` replaces `r = …; return ~r >> 31;` (emit_store_flag gives the same `nor; srl`), +and the `do { } while (0)` is simply dropped. +Also verified at 0: `union { DVECTOR2 v; s32 sxy; }` with `.v.vx/.v.vy` (`DVECTOR2` is in src/shared/engine_types.h:759) +(`scratch/dv.c`). body.c keeps the self-contained anonymous struct so the four shared copies need no header. + +## (d) Generator proposal +When a body pins N values that are packed as `(u16)lo | (hi << 16)` (or any byte/half insert into a word) AND has a +keepalive `__asm__("" :: "r"(v))` reading those pinned variables BEFORE they are assigned (live-from-entry), rewrite +each packed word as a register union `{ struct { s16 lo, hi; } v; s32 w; }` (or `{ u8 b[4]; s32 w; }` for byte packs) +whose fields are assigned where the pack was, and pass `.w`. More generally, **a keepalive on a not-yet-assigned +variable near the entry means "live at entry" in the original. In plain C that is an aggregate kept in a register +and built by field stores** (store_fixed_bit_field's read-modify-write of the uninitialised word). + +## (e) What did not work (bytes) +- body_free.c: 14. Free sweep's best (free_004, swap-stmts): 12. Neither can reach 0, because no statement-order or + width move makes a local-alloc'd mask conflict with block-0 globals. +- Inlining the packs into the call (`(u16)ax | ((u16)ay << 16)` as arguments): 16/20 (COUNT, the order changes). +- `u16 la/lb/lc`: 18/20. Compare-operand flips (16 permutations): 18-24 (lose 1-2 insns). +- `y << 16` without the `(u16)` cast or `x & 0xFFFF`: 45 insns and one zombie fewer (vars=40). +- Field-only unions (loads straight into `a.v.x`, compares on the fields, no s16 locals): 57 (56 insns). +- An early-return tail `if (ay < cy) return 1; ` instead of `if (ay >= cy) { …call… } return 1;`: 5 + (47 insns). The if-block tail is load-bearing (`scratch/early.c`). +- The union WITHOUT the `s32` member (2-aligned struct only, passed as `*(s32 *)&a`): 25, vars=72 (BLKmode, so it + lives on the stack; `scratch/bare.c`). The s32 member is what makes the aggregate a register. +- R71 check: no lever-free same-name variant in src/ (SC05_003/SC03_029/SC05_018's func_8017EF88 are other + functions). All copies of this text (shared headers func_8017D5F4__014cbc20.h / func_8017D6AC__703b5fd0.h, + ov_SC03_112 / ov_SC05_005 jr_*) carry the same levers and should take the same rewrite (D5F4 = EF88's shape, + D6AC = F040's). + +## (f) Where the method fell short / what found it +The allocation table and residual pointed at "why do globals avoid three registers that local-alloc hands out +later". No statement-level move could explain a block-0 temp conflicting with block-8 values. The clue was the +FRAME. `pad[2]` was fake: the free body's vars=48 were six stale pseudos (each "ST_REGS or none", flow-counted, +combine-eliminated) and the target needed one more. That said the original had an extra eliminated temp. Together +with the keepalive's "live from entry" reading, that led to field stores into a register aggregate, and the first +`--try` of that closed. Method addition: **a dead `pad[N]` lever is evidence — count the ST_REGS/no-hard-reg pseudos +in `.lreg` (8 frame bytes each) before accepting a dead local. The missing ones name the missing construct.** + +## (g) Structs question — YES, and this is the proof case +The lever existed only because the packed arguments were written as integer arithmetic instead of the aggregate the +original used. The struct/union type moves the decision in flow → global (live-at-entry from the read-modify-write +field insert, `expmed.c:689-697`, and pre-combine live sets feeding `global.c:640-660`), not the expr.c/sched +aggregate-alias channel. The struct is a 4-byte SImode union `{ struct { s16 x, y; } v; s32 sxy; }` (PsyQ DVECTOR +overlaid with a long, i.e. an SXY GTE register value), one per NCLIP argument. It must contain a 32-bit-aligned +member so the aggregate is SImode (a bare `DVECTOR` is 2-aligned, BLKmode under STRICT_ALIGNMENT, and would go to the stack). +Tested on bytes with a body-local declaration: score 0. diff --git a/.run/P36/agents/ov_SC05_001__func_8017EF88/neighbours.txt b/.run/P36/agents/ov_SC05_001__func_8017EF88/neighbours.txt new file mode 100644 index 000000000..d5268514a --- /dev/null +++ b/.run/P36/agents/ov_SC05_001__func_8017EF88/neighbours.txt @@ -0,0 +1,9 @@ +--- every @class/@stuck/@crack note in this translation unit --- +// @class: plumbing +// @stuck: none — signed s32 counter at 0x1C, delay-slot store is the unconditional bump +// @class: straight-derive +// @stuck: none — MATCH (52 ins) on iteration 1, confirmed by rtu_match. +// @class: structural (STRENGTH/mflo!=lw -> MATCH) +// @stuck: none - MATCH (41 ins), match_one + rtu_match. +// @class: regalloc (WIDTH/li!=addu -> MATCH) +// @stuck: none — MATCH (58 ins), match_one + rtu_match. PIN-FREE (no register __asm__). diff --git a/.run/P36/agents/ov_SC05_001__func_8017EF88/related.txt b/.run/P36/agents/ov_SC05_001__func_8017EF88/related.txt new file mode 100644 index 000000000..7872c5976 --- /dev/null +++ b/.run/P36/agents/ov_SC05_001__func_8017EF88/related.txt @@ -0,0 +1 @@ +=== lever-free bodies in ov_SC05_001 sharing a callee or global with func_8017EF88 (0 found; top 6 by shared symbols) — read them for the SHAPE === diff --git a/.run/P36/agents/ov_SC05_001__func_8017EF88/residual.txt b/.run/P36/agents/ov_SC05_001__func_8017EF88/residual.txt new file mode 100644 index 000000000..d34e61baf --- /dev/null +++ b/.run/P36/agents/ov_SC05_001__func_8017EF88/residual.txt @@ -0,0 +1,24 @@ +src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c:func_8017EF88: score 14 (REG-caller; mine 46 ins, target 46) — not yet + register pairs (mine -> target, count): t0->t1 x6, t1->t3 x2, a3->t4 x2, v1->t2 x2, v0->t0 x2, v1->a3 x2, a3->v1 x2 + replace mine[2:3] target[2:3] + 2 lh t0,0(a2) | lh t1,0(a2) + replace mine[5:7] target[5:7] + 5 move t1,v0 | move t3,v0 + 6 slt v0,t0,v0 | slt v0,t1,v0 + replace mine[8:9] target[8:9] + 8 move a3,t0 | move t4,t1 + replace mine[11:13] target[11:13] + 11 move v1,v0 | move t2,v0 + 12 slt v0,v0,t0 | slt v0,v0,t1 + replace mine[21:22] target[21:22] + 21 move t0,a2 | move t1,a2 + replace mine[30:33] target[30:33] + 30 andi v0,t1,0xffff | andi t0,t3,0xffff + 31 andi v1,v1,0xffff | andi a3,t2,0xffff + 32 andi a3,a3,0xffff | andi v1,t4,0xffff + replace mine[35:38] target[35:38] + 35 sll a2,t0,0x10 | sll a2,t1,0x10 + 36 or a0,v0,a0 | or a0,t0,a0 + 37 or a1,v1,a1 | or a1,a3,a1 + replace mine[39:40] target[39:40] + 39 or a2,a3,a2 | or a2,v1,a2 diff --git a/.run/P36/agents/ov_SC05_001__func_8017EF88/sites.txt b/.run/P36/agents/ov_SC05_001__func_8017EF88/sites.txt new file mode 100644 index 000000000..4d9038fc2 --- /dev/null +++ b/.run/P36/agents/ov_SC05_001__func_8017EF88/sites.txt @@ -0,0 +1,5 @@ +NEEDED pin $8 line 4447 +NEEDED pin $7 line 4448 +NEEDED pin $3 line 4449 +NEEDED keepalive line 4458 +NEEDED keepalive line 4474 diff --git a/.run/P36/agents/ov_SC05_001__func_8017EF88/tu.txt b/.run/P36/agents/ov_SC05_001__func_8017EF88/tu.txt new file mode 100644 index 000000000..8c10fc7a2 --- /dev/null +++ b/.run/P36/agents/ov_SC05_001__func_8017EF88/tu.txt @@ -0,0 +1,2 @@ +src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c +func_8017EF88 diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index de1780169..d83ae4ab6 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,7 +1,7 @@ { - "head": "910875139", + "head": "30fd6796f", "stamp": "15956e4a96c4", - "generated": "2026-09-10 21:31", + "generated": "2026-09-10 21:43", "aliases": [ "main", "ov_SC03_014", @@ -21,207 +21,207 @@ "main": { "objects": 85, "identical": 85, - "seconds": 12.299000000000005, - "mean_s": 0.145 + "seconds": 23.41900000000001, + "mean_s": 0.276 }, "ov_SC03_014": { "objects": 32, "identical": 32, - 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"build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.184, + "build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.747, + "build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.502, + "build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.221, + "build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.41, + "build/src/ov_SC04_011/ov_SC04_011_jr_801789AC.o": 0.186, + "build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.192, + "build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.132, + "build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.257, + "build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 1.103, + "build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.12, + "build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.138 }, "ok": true, - "seconds": 4.4 + "seconds": 24.1 } diff --git a/.run/P36/delever/ledger.jsonl b/.run/P36/delever/ledger.jsonl index 854079b6a..5a43c9c54 100644 --- a/.run/P36/delever/ledger.jsonl +++ b/.run/P36/delever/ledger.jsonl @@ -29087,3 +29087,7 @@ {"ts": "2026-09-10 21:30:40", "label": "s104_d4", "rung": "E", "calib": {"head": "29c857eaa", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c", "fn": "func_8018691C", "addr": 2149083420, "aliases": null, "header": false, "includers": 0, "nhash_before": "5e2d865d3fdb85d89d6108f32fbd6255db46ef0b", "nhash_after": "ec9cb5d83708e91832764723fcfe97f2562b78cc", "source": "propagate:src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c:func_80182358", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.341, "objects": ["build/src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.o"], "before_text": "s32 func_8018691C(s32 a0, u16 a1) {\n s16 sp10[4];\n s16 sp18[4];\n s16 sp20[4];\n s16 sp28[4];\n s16 pan;\n s16 vol;\n s32 v;\n s32 d;\n u16 *p;\n\n p = (u16 *)&D_80126B58;\n pan = 7;\n vol = 0x7F;\n sp10[0] = *(u16 *)(a0 + 0x6);\n sp10[1] = *(u16 *)(a0 + 0xA);\n sp10[2] = *(u16 *)(a0 + 0xE);\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp10, sp18);\n sp18[2] = 0;\n __asm__(\"\" : \"=r\"(pan) : \"0\"(pan)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus8)\n\n v = sp18[0];\n if (v < 0) v = -v;\n if (v >= 0xA0) return 0;\n\n if (sp18[1] >= 0 ? sp18[1] >= 0x78 : -sp18[1] >= 0x78) return 0;\n\n pan += sp18[0] / 20;\n if (pan < 0) pan = 0;\n else if (pan >= 0x10) pan = 0xF;\n\n sp20[0] = p[3];\n sp20[1] = p[5];\n sp20[2] = p[7];\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp20, sp28);\n sp28[2] = 0;\n\n d = ((s32 (*)(s16 *, s16 *))func_800132BC)(sp18, sp28) - 0x100;\n if (d > 0) {\n vol -= (d * 127) / 25600;\n if (vol < 0) vol = 0;\n }\n func_8002D4C8(a1, (u16)(vol | ((pan << 8) | 0x3000)));\n return 1;\n}\n", "after_text": "s32 func_8018691C(s32 a0, u16 a1) {\n s16 sp10[4];\n s16 sp18[4];\n s16 sp20[4];\n s16 sp28[4];\n s16 pan;\n s16 vol;\n s32 v;\n s32 d;\n u16 *p;\n\n p = (u16 *)&D_80126B58;\n pan = 7;\n vol = 0x7F;\n sp10[0] = *(u16 *)(a0 + 0x6);\n sp10[1] = *(u16 *)(a0 + 0xA);\n sp10[2] = *(u16 *)(a0 + 0xE);\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp10, sp18);\n v = sp18[0];\n do { sp18[2] = 0; } while (0); // !FAKE: do-while \u2014 sched1 LOOP-note barrier keeps the sh after the lh so no mem-unit stall pulls vol=0x7F past the jal (sched.c:2058-2074, schedule_select :2616) (P36 S104 d4)\n if (v < 0) v = -v;\n if (v >= 0xA0) return 0;\n\n if (sp18[1] >= 0 ? sp18[1] >= 0x78 : -sp18[1] >= 0x78) return 0;\n\n pan += sp18[0] / 20;\n if (pan < 0) pan = 0;\n else if (pan >= 0x10) pan = 0xF;\n\n sp20[0] = p[3];\n sp20[1] = p[5];\n sp20[2] = p[7];\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp20, sp28);\n sp28[2] = 0;\n\n d = ((s32 (*)(s16 *, s16 *))func_800132BC)(sp18, sp28) - 0x100;\n if (d > 0) {\n vol -= (d * 127) / 25600;\n if (vol < 0) vol = 0;\n }\n func_8002D4C8(a1, (u16)(vol | ((pan << 8) | 0x3000)));\n return 1;\n}\n"} {"ts": "2026-09-10 21:30:46", "label": "s104_d4", "rung": "E", "calib": {"head": "29c857eaa", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c", "fn": "func_80185CEC", "addr": 2149080300, "aliases": null, "header": false, "includers": 0, "nhash_before": "5e2d865d3fdb85d89d6108f32fbd6255db46ef0b", "nhash_after": "ec9cb5d83708e91832764723fcfe97f2562b78cc", "source": "propagate:src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c:func_80182358", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.473, "objects": ["build/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.o"], "before_text": "s32 func_80185CEC(s32 a0, u16 a1) {\n s16 sp10[4];\n s16 sp18[4];\n s16 sp20[4];\n s16 sp28[4];\n s16 pan;\n s16 vol;\n s32 v;\n s32 d;\n u16 *p;\n\n p = (u16 *)&D_80126B58;\n pan = 7;\n vol = 0x7F;\n sp10[0] = *(u16 *)(a0 + 0x6);\n sp10[1] = *(u16 *)(a0 + 0xA);\n sp10[2] = *(u16 *)(a0 + 0xE);\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp10, sp18);\n sp18[2] = 0;\n __asm__(\"\" : \"=r\"(pan) : \"0\"(pan)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus8)\n\n v = sp18[0];\n if (v < 0) v = -v;\n if (v >= 0xA0) return 0;\n\n if (sp18[1] >= 0 ? sp18[1] >= 0x78 : -sp18[1] >= 0x78) return 0;\n\n pan += sp18[0] / 20;\n if (pan < 0) pan = 0;\n else if (pan >= 0x10) pan = 0xF;\n\n sp20[0] = p[3];\n sp20[1] = p[5];\n sp20[2] = p[7];\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp20, sp28);\n sp28[2] = 0;\n\n d = ((s32 (*)(s16 *, s16 *))func_800132BC)(sp18, sp28) - 0x100;\n if (d > 0) {\n vol -= (d * 127) / 25600;\n if (vol < 0) vol = 0;\n }\n func_8002D4C8(a1, (u16)(vol | ((pan << 8) | 0x3000)));\n return 1;\n}\n", "after_text": "s32 func_80185CEC(s32 a0, u16 a1) {\n s16 sp10[4];\n s16 sp18[4];\n s16 sp20[4];\n s16 sp28[4];\n s16 pan;\n s16 vol;\n s32 v;\n s32 d;\n u16 *p;\n\n p = (u16 *)&D_80126B58;\n pan = 7;\n vol = 0x7F;\n sp10[0] = *(u16 *)(a0 + 0x6);\n sp10[1] = *(u16 *)(a0 + 0xA);\n sp10[2] = *(u16 *)(a0 + 0xE);\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp10, sp18);\n v = sp18[0];\n do { sp18[2] = 0; } while (0); // !FAKE: do-while \u2014 sched1 LOOP-note barrier keeps the sh after the lh so no mem-unit stall pulls vol=0x7F past the jal (sched.c:2058-2074, schedule_select :2616) (P36 S104 d4)\n if (v < 0) v = -v;\n if (v >= 0xA0) return 0;\n\n if (sp18[1] >= 0 ? sp18[1] >= 0x78 : -sp18[1] >= 0x78) return 0;\n\n pan += sp18[0] / 20;\n if (pan < 0) pan = 0;\n else if (pan >= 0x10) pan = 0xF;\n\n sp20[0] = p[3];\n sp20[1] = p[5];\n sp20[2] = p[7];\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp20, sp28);\n sp28[2] = 0;\n\n d = ((s32 (*)(s16 *, s16 *))func_800132BC)(sp18, sp28) - 0x100;\n if (d > 0) {\n vol -= (d * 127) / 25600;\n if (vol < 0) vol = 0;\n }\n func_8002D4C8(a1, (u16)(vol | ((pan << 8) | 0x3000)));\n return 1;\n}\n"} {"ts": "2026-09-10 21:30:47", "label": "s104_d4", "rung": "E", "calib": {"head": "29c857eaa", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c", "fn": "func_801832F8", "addr": 2149069560, "aliases": null, "header": false, "includers": 0, "nhash_before": "5e2d865d3fdb85d89d6108f32fbd6255db46ef0b", "nhash_after": "ec9cb5d83708e91832764723fcfe97f2562b78cc", "source": "propagate:src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c:func_80182358", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.417, "objects": ["build/src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.o"], "before_text": "s32 func_801832F8(s32 a0, u16 a1) {\n s16 sp10[4];\n s16 sp18[4];\n s16 sp20[4];\n s16 sp28[4];\n s16 pan;\n s16 vol;\n s32 v;\n s32 d;\n u16 *p;\n\n p = (u16 *)&D_80126B58;\n pan = 7;\n vol = 0x7F;\n sp10[0] = *(u16 *)(a0 + 0x6);\n sp10[1] = *(u16 *)(a0 + 0xA);\n sp10[2] = *(u16 *)(a0 + 0xE);\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp10, sp18);\n sp18[2] = 0;\n __asm__(\"\" : \"=r\"(pan) : \"0\"(pan)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n v = sp18[0];\n if (v < 0) v = -v;\n if (v >= 0xA0) return 0;\n\n if (sp18[1] >= 0 ? sp18[1] >= 0x78 : -sp18[1] >= 0x78) return 0;\n\n pan += sp18[0] / 20;\n if (pan < 0) pan = 0;\n else if (pan >= 0x10) pan = 0xF;\n\n sp20[0] = p[3];\n sp20[1] = p[5];\n sp20[2] = p[7];\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp20, sp28);\n sp28[2] = 0;\n\n d = ((s32 (*)(s16 *, s16 *))func_800132BC)(sp18, sp28) - 0x100;\n if (d > 0) {\n vol -= (d * 127) / 25600;\n if (vol < 0) vol = 0;\n }\n func_8002D4C8(a1, (u16)(vol | ((pan << 8) | 0x3000)));\n return 1;\n}\n", "after_text": "s32 func_801832F8(s32 a0, u16 a1) {\n s16 sp10[4];\n s16 sp18[4];\n s16 sp20[4];\n s16 sp28[4];\n s16 pan;\n s16 vol;\n s32 v;\n s32 d;\n u16 *p;\n\n p = (u16 *)&D_80126B58;\n pan = 7;\n vol = 0x7F;\n sp10[0] = *(u16 *)(a0 + 0x6);\n sp10[1] = *(u16 *)(a0 + 0xA);\n sp10[2] = *(u16 *)(a0 + 0xE);\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp10, sp18);\n v = sp18[0];\n do { sp18[2] = 0; } while (0); // !FAKE: do-while \u2014 sched1 LOOP-note barrier keeps the sh after the lh so no mem-unit stall pulls vol=0x7F past the jal (sched.c:2058-2074, schedule_select :2616) (P36 S104 d4)\n if (v < 0) v = -v;\n if (v >= 0xA0) return 0;\n\n if (sp18[1] >= 0 ? sp18[1] >= 0x78 : -sp18[1] >= 0x78) return 0;\n\n pan += sp18[0] / 20;\n if (pan < 0) pan = 0;\n else if (pan >= 0x10) pan = 0xF;\n\n sp20[0] = p[3];\n sp20[1] = p[5];\n sp20[2] = p[7];\n ((void (*)(s16 *, s16 *))func_8012EFB8)(sp20, sp28);\n sp28[2] = 0;\n\n d = ((s32 (*)(s16 *, s16 *))func_800132BC)(sp18, sp28) - 0x100;\n if (d > 0) {\n vol -= (d * 127) / 25600;\n if (vol < 0) vol = 0;\n }\n func_8002D4C8(a1, (u16)(vol | ((pan << 8) | 0x3000)));\n return 1;\n}\n"} +{"ts": "2026-09-10 21:44:18", "label": "s104_d10", "rung": "E", "calib": {"head": "30fd6796f", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c", "fn": "func_8017EF88", "addr": 2149052296, "aliases": null, "header": false, "includers": 0, "nhash_before": "ad5f90e75ee4e8f79fe0dfdc5728f96da39252ba", "nhash_after": "d8afd79867f8ed03438daee8de25d714489c134a", "source": ".run/P36/agents/ov_SC05_001__func_8017EF88/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.457, "objects": ["build/src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.o"], "before_text": "u32 func_8017EF88(s16 *param_1, s16 *param_2, s16 *param_3) {\n s16 ax, ay, bx, by, cx, cy;\n register s32 la __asm__(\"$8\"); // !FAKE: pin $8 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n register s32 lb __asm__(\"$7\"); // !FAKE: pin $7 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n register s32 lc __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n u32 r;\n s32 pad[2];\n\n ax = param_1[0];\n cx = param_3[0];\n if (cx < ax) {\n return 0;\n }\n __asm__ __volatile__(\"\" : : \"r\"(la), \"r\"(lb), \"r\"(lc)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus8)\n bx = param_2[0];\n if (bx < cx) {\n return 1;\n }\n by = param_2[1];\n do {\n cy = param_3[2];\n if (cy < by) {\n return 0;\n }\n ay = param_1[1];\n if (ay >= cy) {\n la = (u16)ax;\n lb = (u16)bx;\n lc = (u16)cx;\n __asm__ __volatile__(\"\" : : \"r\"(ax), \"r\"(bx), \"r\"(cx)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus8)\n r = func_800495EC(la | ((u16)ay << 16), lb | ((u16)by << 16),\n lc | ((u16)cy << 16));\n return ~r >> 31;\n }\n return 1;\n } while (0);\n}\n", "after_text": "u32 func_8017EF88(s16 *param_1, s16 *param_2, s16 *param_3) {\n union {\n struct {\n s16 x, y;\n } v;\n s32 sxy;\n } a, b, c;\n s16 ax, ay, bx, by, cx, cy;\n\n ax = param_1[0];\n cx = param_3[0];\n if (cx < ax) {\n return 0;\n }\n bx = param_2[0];\n if (bx < cx) {\n return 1;\n }\n by = param_2[1];\n cy = param_3[2];\n if (cy < by) {\n return 0;\n }\n ay = param_1[1];\n if (ay >= cy) {\n a.v.x = ax;\n a.v.y = ay;\n b.v.x = bx;\n b.v.y = by;\n c.v.x = cx;\n c.v.y = cy;\n return func_800495EC(a.sxy, b.sxy, c.sxy) >= 0;\n }\n return 1;\n}\n"} +{"ts": "2026-09-10 21:44:43", "label": "s104_d10", "rung": "E", "calib": {"head": "30fd6796f", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_112/ov_SC03_112_jr_8017C294.c", "fn": "func_8017E654", "addr": 2149049940, "aliases": null, "header": false, "includers": 0, "nhash_before": "ad5f90e75ee4e8f79fe0dfdc5728f96da39252ba", "nhash_after": "d8afd79867f8ed03438daee8de25d714489c134a", "source": "propagate:src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c:func_8017EF88", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.432, "objects": ["build/src/ov_SC03_112/ov_SC03_112_jr_8017C294.o"], "before_text": "u32 func_8017E654(s16 *param_1, s16 *param_2, s16 *param_3) {\n s16 ax, ay, bx, by, cx, cy;\n register s32 la __asm__(\"$8\"); // !FAKE: pin $8 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n register s32 lb __asm__(\"$7\"); // !FAKE: pin $7 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n register s32 lc __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n u32 r;\n s32 pad[2];\n\n ax = param_1[0];\n cx = param_3[0];\n if (cx < ax) {\n return 0;\n }\n __asm__ __volatile__(\"\" : : \"r\"(la), \"r\"(lb), \"r\"(lc)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus9)\n bx = param_2[0];\n if (bx < cx) {\n return 1;\n }\n by = param_2[1];\n do {\n cy = param_3[2];\n if (cy < by) {\n return 0;\n }\n ay = param_1[1];\n if (ay >= cy) {\n la = (u16)ax;\n lb = (u16)bx;\n lc = (u16)cx;\n __asm__ __volatile__(\"\" : : \"r\"(ax), \"r\"(bx), \"r\"(cx)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus9)\n r = func_800495EC(la | ((u16)ay << 16), lb | ((u16)by << 16),\n lc | ((u16)cy << 16));\n return ~r >> 31;\n }\n return 1;\n } while (0);\n}\n", "after_text": "u32 func_8017E654(s16 *param_1, s16 *param_2, s16 *param_3) {\n union {\n struct {\n s16 x, y;\n } v;\n s32 sxy;\n } a, b, c;\n s16 ax, ay, bx, by, cx, cy;\n\n ax = param_1[0];\n cx = param_3[0];\n if (cx < ax) {\n return 0;\n }\n bx = param_2[0];\n if (bx < cx) {\n return 1;\n }\n by = param_2[1];\n cy = param_3[2];\n if (cy < by) {\n return 0;\n }\n ay = param_1[1];\n if (ay >= cy) {\n a.v.x = ax;\n a.v.y = ay;\n b.v.x = bx;\n b.v.y = by;\n c.v.x = cx;\n c.v.y = cy;\n return func_800495EC(a.sxy, b.sxy, c.sxy) >= 0;\n }\n return 1;\n}\n"} +{"ts": "2026-09-10 21:44:44", "label": "s104_d10", "rung": "E", "calib": {"head": "30fd6796f", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC05_005/ov_SC05_005_jr_8017D898.c", "fn": "func_8017EFF4", "addr": 2149052404, "aliases": null, "header": false, "includers": 0, "nhash_before": "ad5f90e75ee4e8f79fe0dfdc5728f96da39252ba", "nhash_after": "d8afd79867f8ed03438daee8de25d714489c134a", "source": "propagate:src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c:func_8017EF88", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.332, "objects": ["build/src/ov_SC05_005/ov_SC05_005_jr_8017D898.o"], "before_text": "u32 func_8017EFF4(s16 *param_1, s16 *param_2, s16 *param_3) {\n s16 ax, ay, bx, by, cx, cy;\n register s32 la __asm__(\"$8\"); // !FAKE: pin $8 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n register s32 lb __asm__(\"$7\"); // !FAKE: pin $7 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n register s32 lc __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n u32 r;\n s32 pad[2];\n\n ax = param_1[0];\n cx = param_3[0];\n if (cx < ax) {\n return 0;\n }\n __asm__ __volatile__(\"\" : : \"r\"(la), \"r\"(lb), \"r\"(lc)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus9)\n bx = param_2[0];\n if (bx < cx) {\n return 1;\n }\n by = param_2[1];\n do {\n cy = param_3[2];\n if (cy < by) {\n return 0;\n }\n ay = param_1[1];\n if (ay >= cy) {\n la = (u16)ax;\n lb = (u16)bx;\n lc = (u16)cx;\n __asm__ __volatile__(\"\" : : \"r\"(ax), \"r\"(bx), \"r\"(cx)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus9)\n r = func_800495EC(la | ((u16)ay << 16), lb | ((u16)by << 16),\n lc | ((u16)cy << 16));\n return ~r >> 31;\n }\n return 1;\n } while (0);\n}\n", "after_text": "u32 func_8017EFF4(s16 *param_1, s16 *param_2, s16 *param_3) {\n union {\n struct {\n s16 x, y;\n } v;\n s32 sxy;\n } a, b, c;\n s16 ax, ay, bx, by, cx, cy;\n\n ax = param_1[0];\n cx = param_3[0];\n if (cx < ax) {\n return 0;\n }\n bx = param_2[0];\n if (bx < cx) {\n return 1;\n }\n by = param_2[1];\n cy = param_3[2];\n if (cy < by) {\n return 0;\n }\n ay = param_1[1];\n if (ay >= cy) {\n a.v.x = ax;\n a.v.y = ay;\n b.v.x = bx;\n b.v.y = by;\n c.v.x = cx;\n c.v.y = cy;\n return func_800495EC(a.sxy, b.sxy, c.sxy) >= 0;\n }\n return 1;\n}\n"} +{"ts": "2026-09-10 21:44:45", "label": "s104_d10", "rung": "E", "calib": {"head": "30fd6796f", "stamp": "15956e4a96c4"}, "tu": "src/shared/ov/func_8017D5F4__014cbc20.h", "fn": "func_8017D5F4", "addr": 2149045748, "aliases": null, "header": true, "includers": 2, "nhash_before": "ad5f90e75ee4e8f79fe0dfdc5728f96da39252ba", "nhash_after": "d8afd79867f8ed03438daee8de25d714489c134a", "source": "propagate:src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c:func_8017EF88", "verdict": "LEVER-FREE", "sites": [], "compiles": 2, "seconds": 0.461, "objects": ["build/src/ov_SC02_039/ov_SC02_039_jr_8017BEBC.o", "build/src/ov_SC03_108/ov_SC03_108_jr_8017BEBC.o"], "before_text": "u32 func_8017D5F4(s16 *param_1, s16 *param_2, s16 *param_3) {\n s16 ax, ay, bx, by, cx, cy;\n register s32 la __asm__(\"$8\"); // !FAKE: pin $8 \u2014 NEEDED DIFFERS (P36 rung B headers2)\n register s32 lb __asm__(\"$7\"); // !FAKE: pin $7 \u2014 NEEDED DIFFERS (P36 rung B headers2)\n register s32 lc __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B headers2)\n u32 r;\n s32 pad[2];\n ax = param_1[0];\n cx = param_3[0];\n if (cx < ax) {\n return 0;\n }\n __asm__ __volatile__(\"\" : : \"r\"(la), \"r\"(lb), \"r\"(lc)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B headers2)\n bx = param_2[0];\n if (bx < cx) {\n return 1;\n }\n by = param_2[1];\n do {\n cy = param_3[2];\n if (cy < by) {\n return 0;\n }\n ay = param_1[1];\n if (ay >= cy) {\n la = (u16)ax;\n lb = (u16)bx;\n lc = (u16)cx;\n __asm__ __volatile__(\"\" : : \"r\"(ax), \"r\"(bx), \"r\"(cx)); // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B headers2)\n r = func_800495EC(la | ((u16)ay << 16), lb | ((u16)by << 16),\n lc | ((u16)cy << 16));\n return ~r >> 31;\n }\n return 1;\n } while (0);\n}\n", "after_text": "u32 func_8017D5F4(s16 *param_1, s16 *param_2, s16 *param_3) {\n union {\n struct {\n s16 x, y;\n } v;\n s32 sxy;\n } a, b, c;\n s16 ax, ay, bx, by, cx, cy;\n\n ax = param_1[0];\n cx = param_3[0];\n if (cx < ax) {\n return 0;\n }\n bx = param_2[0];\n if (bx < cx) {\n return 1;\n }\n by = param_2[1];\n cy = param_3[2];\n if (cy < by) {\n return 0;\n }\n ay = param_1[1];\n if (ay >= cy) {\n a.v.x = ax;\n a.v.y = ay;\n b.v.x = bx;\n b.v.y = by;\n c.v.x = cx;\n c.v.y = cy;\n return func_800495EC(a.sxy, b.sxy, c.sxy) >= 0;\n }\n return 1;\n}\n"} diff --git a/src/ov_SC03_112/ov_SC03_112_jr_8017C294.c b/src/ov_SC03_112/ov_SC03_112_jr_8017C294.c index 4f1bc6f45..150975645 100644 --- a/src/ov_SC03_112/ov_SC03_112_jr_8017C294.c +++ b/src/ov_SC03_112/ov_SC03_112_jr_8017C294.c @@ -3391,41 +3391,39 @@ s32 func_8017E4B4(u8 *param_1, s16 *param_2, s16 *param_3) { extern s32 func_800495EC(s32 a0, s32 a1, s32 a2); u32 func_8017E654(s16 *param_1, s16 *param_2, s16 *param_3) { + union { + struct { + s16 x, y; + } v; + s32 sxy; + } a, b, c; s16 ax, ay, bx, by, cx, cy; - register s32 la __asm__("$8"); // !FAKE: pin $8 — NEEDED DIFFERS (P36 rung B tus9) - register s32 lb __asm__("$7"); // !FAKE: pin $7 — NEEDED DIFFERS (P36 rung B tus9) - register s32 lc __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus9) - u32 r; - s32 pad[2]; ax = param_1[0]; cx = param_3[0]; if (cx < ax) { return 0; } - __asm__ __volatile__("" : : "r"(la), "r"(lb), "r"(lc)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus9) bx = param_2[0]; if (bx < cx) { return 1; } by = param_2[1]; - do { - cy = param_3[2]; - if (cy < by) { - return 0; - } - ay = param_1[1]; - if (ay >= cy) { - la = (u16)ax; - lb = (u16)bx; - lc = (u16)cx; - __asm__ __volatile__("" : : "r"(ax), "r"(bx), "r"(cx)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus9) - r = func_800495EC(la | ((u16)ay << 16), lb | ((u16)by << 16), - lc | ((u16)cy << 16)); - return ~r >> 31; - } - return 1; - } while (0); + cy = param_3[2]; + if (cy < by) { + return 0; + } + ay = param_1[1]; + if (ay >= cy) { + a.v.x = ax; + a.v.y = ay; + b.v.x = bx; + b.v.y = by; + c.v.x = cx; + c.v.y = cy; + return func_800495EC(a.sxy, b.sxy, c.sxy) >= 0; + } + return 1; } diff --git a/src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c b/src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c index 3a6625ef5..3df6b4d09 100644 --- a/src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c +++ b/src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c @@ -4342,41 +4342,39 @@ s32 func_8017EE08(struct ZnRec *param_1, s16 *param_2, s16 *param_3) { extern s32 func_800495EC(s32 a0, s32 a1, s32 a2); u32 func_8017EF88(s16 *param_1, s16 *param_2, s16 *param_3) { + union { + struct { + s16 x, y; + } v; + s32 sxy; + } a, b, c; s16 ax, ay, bx, by, cx, cy; - register s32 la __asm__("$8"); // !FAKE: pin $8 — NEEDED DIFFERS (P36 rung B tus8) - register s32 lb __asm__("$7"); // !FAKE: pin $7 — NEEDED DIFFERS (P36 rung B tus8) - register s32 lc __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus8) - u32 r; - s32 pad[2]; ax = param_1[0]; cx = param_3[0]; if (cx < ax) { return 0; } - __asm__ __volatile__("" : : "r"(la), "r"(lb), "r"(lc)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus8) bx = param_2[0]; if (bx < cx) { return 1; } by = param_2[1]; - do { - cy = param_3[2]; - if (cy < by) { - return 0; - } - ay = param_1[1]; - if (ay >= cy) { - la = (u16)ax; - lb = (u16)bx; - lc = (u16)cx; - __asm__ __volatile__("" : : "r"(ax), "r"(bx), "r"(cx)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus8) - r = func_800495EC(la | ((u16)ay << 16), lb | ((u16)by << 16), - lc | ((u16)cy << 16)); - return ~r >> 31; - } - return 1; - } while (0); + cy = param_3[2]; + if (cy < by) { + return 0; + } + ay = param_1[1]; + if (ay >= cy) { + a.v.x = ax; + a.v.y = ay; + b.v.x = bx; + b.v.y = by; + c.v.x = cx; + c.v.y = cy; + return func_800495EC(a.sxy, b.sxy, c.sxy) >= 0; + } + return 1; } diff --git a/src/ov_SC05_005/ov_SC05_005_jr_8017D898.c b/src/ov_SC05_005/ov_SC05_005_jr_8017D898.c index ba95922fa..9f3856340 100644 --- a/src/ov_SC05_005/ov_SC05_005_jr_8017D898.c +++ b/src/ov_SC05_005/ov_SC05_005_jr_8017D898.c @@ -3069,41 +3069,39 @@ s32 func_8017EE64(u8 *param_1, s16 *param_2, s16 *param_3) { extern s32 func_800495EC(s32 a0, s32 a1, s32 a2); u32 func_8017EFF4(s16 *param_1, s16 *param_2, s16 *param_3) { + union { + struct { + s16 x, y; + } v; + s32 sxy; + } a, b, c; s16 ax, ay, bx, by, cx, cy; - register s32 la __asm__("$8"); // !FAKE: pin $8 — NEEDED DIFFERS (P36 rung B tus9) - register s32 lb __asm__("$7"); // !FAKE: pin $7 — NEEDED DIFFERS (P36 rung B tus9) - register s32 lc __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus9) - u32 r; - s32 pad[2]; ax = param_1[0]; cx = param_3[0]; if (cx < ax) { return 0; } - __asm__ __volatile__("" : : "r"(la), "r"(lb), "r"(lc)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus9) bx = param_2[0]; if (bx < cx) { return 1; } by = param_2[1]; - do { - cy = param_3[2]; - if (cy < by) { - return 0; - } - ay = param_1[1]; - if (ay >= cy) { - la = (u16)ax; - lb = (u16)bx; - lc = (u16)cx; - __asm__ __volatile__("" : : "r"(ax), "r"(bx), "r"(cx)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus9) - r = func_800495EC(la | ((u16)ay << 16), lb | ((u16)by << 16), - lc | ((u16)cy << 16)); - return ~r >> 31; - } - return 1; - } while (0); + cy = param_3[2]; + if (cy < by) { + return 0; + } + ay = param_1[1]; + if (ay >= cy) { + a.v.x = ax; + a.v.y = ay; + b.v.x = bx; + b.v.y = by; + c.v.x = cx; + c.v.y = cy; + return func_800495EC(a.sxy, b.sxy, c.sxy) >= 0; + } + return 1; } diff --git a/src/shared/ov/func_8017D5F4__014cbc20.h b/src/shared/ov/func_8017D5F4__014cbc20.h index 3c5b814f0..add0614ed 100644 --- a/src/shared/ov/func_8017D5F4__014cbc20.h +++ b/src/shared/ov/func_8017D5F4__014cbc20.h @@ -2,38 +2,37 @@ * member's site in address order; the members are recorded in config/dedup.us.yaml (Phase 35). */ extern s32 func_800495EC(s32 a0, s32 a1, s32 a2); u32 func_8017D5F4(s16 *param_1, s16 *param_2, s16 *param_3) { + union { + struct { + s16 x, y; + } v; + s32 sxy; + } a, b, c; s16 ax, ay, bx, by, cx, cy; - register s32 la __asm__("$8"); // !FAKE: pin $8 — NEEDED DIFFERS (P36 rung B headers2) - register s32 lb __asm__("$7"); // !FAKE: pin $7 — NEEDED DIFFERS (P36 rung B headers2) - register s32 lc __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B headers2) - u32 r; - s32 pad[2]; + ax = param_1[0]; cx = param_3[0]; if (cx < ax) { return 0; } - __asm__ __volatile__("" : : "r"(la), "r"(lb), "r"(lc)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B headers2) bx = param_2[0]; if (bx < cx) { return 1; } by = param_2[1]; - do { - cy = param_3[2]; - if (cy < by) { - return 0; - } - ay = param_1[1]; - if (ay >= cy) { - la = (u16)ax; - lb = (u16)bx; - lc = (u16)cx; - __asm__ __volatile__("" : : "r"(ax), "r"(bx), "r"(cx)); // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B headers2) - r = func_800495EC(la | ((u16)ay << 16), lb | ((u16)by << 16), - lc | ((u16)cy << 16)); - return ~r >> 31; - } - return 1; - } while (0); + cy = param_3[2]; + if (cy < by) { + return 0; + } + ay = param_1[1]; + if (ay >= cy) { + a.v.x = ax; + a.v.y = ay; + b.v.x = bx; + b.v.y = by; + c.v.x = cx; + c.v.y = cy; + return func_800495EC(a.sxy, b.sxy, c.sxy) >= 0; + } + return 1; }