From 834dd2f1bd49b0a644e0041f026ec5f5efc98978 Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 11 Sep 2026 04:02:40 -0600 Subject: [PATCH] =?UTF-8?q?phase-36:=20S104=20s104=5Fe26=20=E2=80=94=20fun?= =?UTF-8?q?c=5F8017E764=20banked=20at=200=20through=20the=20whole-object?= =?UTF-8?q?=20gate=20+=20propagated=20=E2=80=94=20$3=20pin=20=E2=86=92=200?= =?UTF-8?q?:=20the=20early=20temp=20renamed=20to=20val=20(sched.c:2489-249?= =?UTF-8?q?0)=20+=20i=20=3D=200=20moved=20up;=20the=20byte-needed=20volati?= =?UTF-8?q?le=20kept=20unmarked=20(decision=203)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../agents/ov_SC06_000__func_801823BC/body.c | 21 + .../ov_SC06_000__func_801823BC/mechanism.md | 41 ++ .../agents/ov_SC06_000__func_80182464/body.c | 19 + .../ov_SC06_000__func_80182464/mechanism.md | 41 ++ .../agents/ov_SC06_000__func_801842CC/body.c | 35 ++ .../ov_SC06_000__func_801842CC/mechanism.md | 78 ++++ .../agents/ov_SC06_000__func_80185354/body.c | 17 + .../ov_SC06_000__func_80185354/mechanism.md | 43 ++ .run/P36/delever/calibration.json | 370 +++++++++--------- .run/P36/delever/ledger.jsonl | 1 + src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c | 14 +- 11 files changed, 489 insertions(+), 191 deletions(-) create mode 100644 .run/P36/agents/ov_SC06_000__func_801823BC/body.c create mode 100644 .run/P36/agents/ov_SC06_000__func_801823BC/mechanism.md create mode 100644 .run/P36/agents/ov_SC06_000__func_80182464/body.c create mode 100644 .run/P36/agents/ov_SC06_000__func_80182464/mechanism.md create mode 100644 .run/P36/agents/ov_SC06_000__func_801842CC/body.c create mode 100644 .run/P36/agents/ov_SC06_000__func_801842CC/mechanism.md create mode 100644 .run/P36/agents/ov_SC06_000__func_80185354/body.c create mode 100644 .run/P36/agents/ov_SC06_000__func_80185354/mechanism.md diff --git a/.run/P36/agents/ov_SC06_000__func_801823BC/body.c b/.run/P36/agents/ov_SC06_000__func_801823BC/body.c new file mode 100644 index 0000000000..170c6b02bb --- /dev/null +++ b/.run/P36/agents/ov_SC06_000__func_801823BC/body.c @@ -0,0 +1,21 @@ +void func_801823BC(a0, a1) +s32 a0; +s32 a1; +{ + extern void func_80049CAC(s32 a0, s32 a1); + extern void func_8017EF68(s32 a0, s32 a1, s32 a2); + extern s16 D_801AEB52[]; + extern s32 D_801B20E0; + extern s32 D_801A158C; + extern s32 D_801AEB1C; + s16 *q; + s32 *r; + + q = D_801AEB52; + *q = a0; + func_80049CAC((s32)q - 2, (s32)q - 78); + D_801AEB1C = (s16)a1; + r = (s32 *)((s32)q - 82); + *r = 0; + func_8017EF68((s32)&D_801B20E0, (s32)&D_801A158C, (s32)r); +} diff --git a/.run/P36/agents/ov_SC06_000__func_801823BC/mechanism.md b/.run/P36/agents/ov_SC06_000__func_801823BC/mechanism.md new file mode 100644 index 0000000000..e7cbb69590 --- /dev/null +++ b/.run/P36/agents/ov_SC06_000__func_801823BC/mechanism.md @@ -0,0 +1,41 @@ +# func_801823BC (ov_SC06_000_jr_8017AE2C.c) — e28, P36 T7 S104 + +**Score: 4 (sweep best 2) -> 0, zero levers** (the `$17` pin AND the launder asm both deleted; plain C). First `--try`. + +## (a) Residual +COUNT +1 (29 vs 28): the store `*(s32 *)((s32)q - 82) = 0` came out absolute (`lui at,%hi(D_801AEB52-82); sw zero,..(at)`) +where the target stores through the callee-saved register holding `&D_801AEB52` (`sw zero,-82(s1)`, in the `jal` delay +slot, after `addiu a2,s1,-82`). The pin was only there because the launder needed q in a known register; the register +itself (`$s1`) is what global alloc gives q anyway once the call argument keeps it live across the first call. + +## (b) Pass and decision (the e12 mechanism, same TU; e12 proved it on .cse dumps for func_80182560) +cse1 `find_best_addr` (gcc-2.7.2 cse.c:2622): the free text's address `(plus (reg q) -82)` is not a REG, so `fold_rtx` +runs first (cse.c:2662-2664), substitutes q's constant equivalent `(symbol_ref D_801AEB52)` and folds the address to +`(const (plus sym -82))` — a CONSTANT address, never replaced again (cse.c:2656) -> `lui at; sw`. A REG address +`(mem (reg r))`, `r = q - 41`, is not folded; the lookup of r's class finds `(plus (reg q) -82)` at the same ADDRESS_COST +as a REG (1: mips.h:2895, mips.c:1652-1653) and a higher rtx cost, which the tie-break prefers (cse.c:2711-2721); the +symbolic constant costs 2 (mips.c:1631) and loses. r stays live as the third call argument, so cse2 does not re-fold +(e12's func_80184A68 (b)3: a derived pointer with no other live use is re-folded in cse2). +Proven on bytes here (score 0); the dump reading is e12's (not re-dumped for this function). + +## (c) Move +Name the derived pointer and pass it: `r = (s32 *)((s32)q - 82); *r = 0; func_8017EF68(&D_801B20E0, &D_801A158C, (s32)r);` +(`r = (s32 *)(q - 41);` also scores 0 — scratch/v2.c.) + +## (d) Generator proposal +When a launder/`la` pointer's constant-offset access comes out as `lui at; sw/lw %lo(SYM+k)(at)` where the target has +`sw k(reg)`, and the same `p + k` is also passed to a later call, name `r = p + k`, access `*r` and pass `r`. + +## (e) What did not work +The sweep's R4/R7/R9/R12 moves stay at 2 (ORDER): none of them turns the address into a REG. Nothing else was needed. + +## (f) Method +Counting first + e12's sibling text closed it on the first try; the method worked as written (brief + neighbours). + +## (g) Structs +A struct on the global would give CONSTANT field addresses (cse.c:2656), the opposite of the target; a struct pointer +based at D_801AEB52 with fields at -2/-78/-82 is not expressible (negative offsets) — the base would move to +D_801AEB52-82 and the offsets change. The deciding fact is REG vs `reg+const` address in find_best_addr, not aliasing. + +## Copies +func_80182464 (same TU) closes with the identical text (its own pack). No other copy of the `q - 2, q - 78` call in src/. diff --git a/.run/P36/agents/ov_SC06_000__func_80182464/body.c b/.run/P36/agents/ov_SC06_000__func_80182464/body.c new file mode 100644 index 0000000000..6f6cfb693b --- /dev/null +++ b/.run/P36/agents/ov_SC06_000__func_80182464/body.c @@ -0,0 +1,19 @@ +void func_80182464(s32 a0, s32 a1) +{ + extern void func_80049CAC(s32 a0, s32 a1); + extern void func_8017EF68(s32 a0, s32 a1, s32 a2); + extern s16 D_801AEBAA[]; + extern s32 D_801B20E0; + extern s32 D_801A3A0C; + extern s32 D_801AEB74; + s16 *q; + s32 *r; + + q = D_801AEBAA; + *q = a0; + func_80049CAC((s32)q - 2, (s32)q - 78); + D_801AEB74 = (s16)a1; + r = (s32 *)((s32)q - 82); + *r = 0; + func_8017EF68((s32)&D_801B20E0, (s32)&D_801A3A0C, (s32)r); +} diff --git a/.run/P36/agents/ov_SC06_000__func_80182464/mechanism.md b/.run/P36/agents/ov_SC06_000__func_80182464/mechanism.md new file mode 100644 index 0000000000..a4a73561e0 --- /dev/null +++ b/.run/P36/agents/ov_SC06_000__func_80182464/mechanism.md @@ -0,0 +1,41 @@ +# func_80182464 (ov_SC06_000_jr_8017AE2C.c) — e28, P36 T7 S104 + +**Score: 4 (sweep best 2) -> 0, zero levers** (the `$17` pin AND the launder asm both deleted; plain C). First `--try`. + +## (a) Residual +COUNT +1 (29 vs 28): the store `*(s32 *)((s32)q - 82) = 0` came out absolute (`lui at,%hi(D_801AEBAA-82); sw zero,..(at)`) +where the target stores through the callee-saved register holding `&D_801AEBAA` (`sw zero,-82(s1)`, in the `jal` delay +slot, after `addiu a2,s1,-82`). The pin was only there because the launder needed q in a known register; the register +itself (`$s1`) is what global alloc gives q anyway once the call argument keeps it live across the first call. + +## (b) Pass and decision (the e12 mechanism, same TU; e12 proved it on .cse dumps for func_80182560) +cse1 `find_best_addr` (gcc-2.7.2 cse.c:2622): the free text's address `(plus (reg q) -82)` is not a REG, so `fold_rtx` +runs first (cse.c:2662-2664), substitutes q's constant equivalent `(symbol_ref D_801AEBAA)` and folds the address to +`(const (plus sym -82))` — a CONSTANT address, never replaced again (cse.c:2656) -> `lui at; sw`. A REG address +`(mem (reg r))`, `r = q - 41`, is not folded; the lookup of r's class finds `(plus (reg q) -82)` at the same ADDRESS_COST +as a REG (1: mips.h:2895, mips.c:1652-1653) and a higher rtx cost, which the tie-break prefers (cse.c:2711-2721); the +symbolic constant costs 2 (mips.c:1631) and loses. r stays live as the third call argument, so cse2 does not re-fold +(e12's func_80184A68 (b)3: a derived pointer with no other live use is re-folded in cse2). +Proven on bytes here (score 0); the dump reading is e12's (not re-dumped for this function). + +## (c) Move +Name the derived pointer and pass it: `r = (s32 *)((s32)q - 82); *r = 0; func_8017EF68(&D_801B20E0, &D_801A3A0C, (s32)r);` +(`r = (s32 *)(q - 41);` scored 0 on func_801823BC.) + +## (d) Generator proposal +When a launder/`la` pointer's constant-offset access comes out as `lui at; sw/lw %lo(SYM+k)(at)` where the target has +`sw k(reg)`, and the same `p + k` is also passed to a later call, name `r = p + k`, access `*r` and pass `r`. + +## (e) What did not work +The sweep's R4/R7/R9/R12 moves stay at 2 (ORDER): none of them turns the address into a REG. Nothing else was needed. + +## (f) Method +Counting first + e12's sibling text closed it on the first try; the method worked as written (brief + neighbours). + +## (g) Structs +A struct on the global would give CONSTANT field addresses (cse.c:2656), the opposite of the target; a struct pointer +based at D_801AEBAA with fields at -2/-78/-82 is not expressible (negative offsets) — the base would move to +D_801AEBAA-82 and the offsets change. The deciding fact is REG vs `reg+const` address in find_best_addr, not aliasing. + +## Copies +func_801823BC (same TU) closes with the identical text (its own pack). No other copy of the `q - 2, q - 78` call in src/. diff --git a/.run/P36/agents/ov_SC06_000__func_801842CC/body.c b/.run/P36/agents/ov_SC06_000__func_801842CC/body.c new file mode 100644 index 0000000000..548f8ec744 --- /dev/null +++ b/.run/P36/agents/ov_SC06_000__func_801842CC/body.c @@ -0,0 +1,35 @@ +void func_801842CC(s32 arg0) +{ + s32 i; + for (i = 0; i < 0x49; i += 0x18) { + s32 e = func_80132EF4(arg0, 0x22); + if (e != 0) { + s32 t; + s32 v; + s32 d; + s32 z; + t = *(u16 *)(arg0 + 0x84) & 4; + z = *(u16 *)(e + 0xE); + d = i + t * 3 - 0x2A; + do { // !FAKE: do-while — its LOOP notes are sched1 barriers (sched.c:2053-2080): the +6 load stays after d, the +E store before the sign extension (P36 S104 e28) + v = *(u16 *)(e + 0x6); + z += 0x28; + *(u16 *)(e + 0xE) = z; + } while (0); + v -= d; + *(u16 *)(e + 0x6) = v; + v = *(u16 *)(e + 0xA); + v -= 0x20; + *(u16 *)(e + 0xA) = v; + v = (s16)d; + if (v >= 0) { + v = v << 7; + } else { + v = -(v << 7); + } + *(u16 *)(e + 0x34) = v + 0x1000; + *(s32 *)(e + 0x14) = 0xFFFE0000; + *(s32 *)(e + 0x18) = 0x30000; + } + } +} diff --git a/.run/P36/agents/ov_SC06_000__func_801842CC/mechanism.md b/.run/P36/agents/ov_SC06_000__func_801842CC/mechanism.md new file mode 100644 index 0000000000..b161102378 --- /dev/null +++ b/.run/P36/agents/ov_SC06_000__func_801842CC/mechanism.md @@ -0,0 +1,78 @@ +# func_801842CC (ov_SC06_000_jr_8017AE2C.c) — e28, P36 T7 S104 + +**Score: 24 free (sweep best 5) -> 0 with ZERO pins/asm and ONE marked `do { … } while (0)`** (step 8's allowed-but-marked +construct). Tree: 3 levers (pin v1 + pin a0 + launder) -> 0 levers + 1 marked do-while. NOT a strict plain-C close: every +do-while-free spelling I found stays at >= 21 (see (e)). + +The same text closes the class's two other copies (`--try` 0 each; rename + the copy's own constants): +ov_SC03_024 `func_80182108` (identical) and ov_SC03_014 `func_801889B4` (`z -= 0x28`, `0xFFFD0000`) — +scratch/copy_80182108_dw.c, scratch/copy_801889B4_dw.c. + +Alternative at 0 (kept for the coordinator's choice): the tree's shape with ONE pin, `register s32 v0 __asm__("v0")` on +the reused variable, launder and the v1/a0 pins deleted — scratch/body_onepin.c (also 0 on both copies: +scratch/copy_80182108.c, copy_801889B4.c). And two pins (v1, a0) + no launder: scratch/t4.c. + +## (a) Residual +COUNT-equal register rotation in the loop body: free text x/(x&4) in `a0`, d in `v0`, the +E value in `v1`; the target has +x in `v0`, d in `v1`, +E in `a0`, and (consequence) `sh v0,52(a1)` sinks below the `lui v0` constants. Plus +`addu v0,v0,s0` vs the target's `addu v1,s0,v1`. + +## (b) Passes and decisions (PROVEN on dumps: scratch/dumps_free, dumps_c1, dumps_c2, dumps_e2, dumps_h1; localalloc_sim) +1. **local-alloc** (eligibility local-alloc.c:472 = one block AND one death; qty order :1486-1507; find_free_reg lowest + free). In the free text ONE variable `v0` holds x, x&4, the +6 value, the +A value and the sign-extended result: it + dies in 4 places -> global. Block 2 then has two local qtys, d (33846) and +E (15000): d takes `$2`, +E `$3`, global + gives v0 `$4`. The target needs a `$2` holder that local-alloc SEES. +2. Giving x its own variable `t` makes THREE local qtys, t=q0, +E=q1, d=q2; the three-qty switch (it compares qty + NUMBERS 0/1/2 while swapping POSITIONS, :1489-1500) orders them [t, d, +E] -> `$2/$3/$4`, the target's + (localalloc_sim on dumps_h1: q0 37500 v0, q2 33846 v1, q1 20625 a0, 0 mismatches). +3. **sched1** then breaks it. `priority()` (sched.c:1425) = max over LOG_LINKS of pred priority + cost - 1. With x in the + same pseudo as the +6 load, that load carried REG_DEP_ANTI links to the x uses (priority 2) and stayed after the d + chain; with `t` split it has no predecessor, priority 1, and is hoisted above the d chain (dumps_c2 trace T-11: + "58 (2) 62 (1)" -> 58), overlapping t, so global cannot give the reused `v` `$2`; the subu then gets 2, the `sll d,16` + ties the +E store at 2 and the store wins the potential-hazard tie (schedule_select sched.c:2616-2686, "insn 68 has a + greater potential hazard"). Needs 1-2 (x its own single-death local) and 3 (x sharing the +6 load's pseudo) contradict + in plain C. +4. **The do-while**: its NOTE_INSN_LOOP_BEG/END are sched1 barriers (sched.c:2053-2080: the insn after a loop note gets a + dependence on every earlier set/use, `reg_pending_sets_all`, `flush_pending_lists`). LOOP_BEG makes the +6 load depend + on the d chain (stays after it); LOOP_END makes the +E store the barrier, so the sign extension and everything after + it must follow the store. dumps_h1's block-2 trace is serialised to single-element ready lists. One note is not enough: + a lone barrier before the +6 load (scratch/e1-e5.c) scores 2 — the barrier insn is then the LOAD, every later insn + inherits its latency (+40 gets priority 3) and the +E store again ties the `sll` and wins by potential hazard. +5. `addu v1,s0,v1`: expand_binop swaps a commutative op whose target equals op1 (optabs.c:409-418), so `v1 = s0 + v1` + became `(plus v1 s0)`; one expression `d = i + t * 3 - 0x2A` keeps the counter first. The launder's only job was to keep + combine from turning `(v0<<1) + v0` (disjoint bits of `x & 4`) into `or` (score 1 without it, scratch/t1.c); `t * 3` + in one expression keeps `addu` — proven on bytes; which combine test declines the ior was NOT dumped. + +## (c) Moves (body.c) +- x split into its own `t = *(u16 *)(arg0 + 0x84) & 4;` (the rest of the reused variable is `v`); +- `v1 = v0 * 2; launder; v1 = v1 + v0; v1 = s0 + v1; v1 = v1 - 0x2A;` -> `d = i + t * 3 - 0x2A;`; +- the +6 load and the +E update wrapped in a marked `do { v = *(u16 *)(e + 6); z += 0x28; *(u16 *)(e + 0xE) = z; } while (0);` +- readability: `if (e != 0) { … }` instead of `continue`, `v = (s16)d;` instead of `<< 16`/`>> 16`, `v = -(v << 7);`, + `*(u16 *)(e + 0x34) = v + 0x1000;` — each proven neutral on bytes (scratch/g3, g4, g8, g9, g10 -> h1 = body.c). +- Not neutral (keep as written): `*(u16 *)(e + 6) = v - d;` (21), `*(u16 *)(e + 0xE) = z + 0x28;` inside the do (21), + `*(u16 *)(e + 0xA) -= 0x20;` (30). + +## (d) Generator proposal +When a register residual needs a variable SPLIT for local-alloc (a multi-death local, :472) but the split lets sched1 +hoist a load that the shared variable used to pin with anti-dependences, wrap [that load .. the next statement group the +hazard tie reorders] in a marked `do { … } while (0)` — and try the two pins -> one pin on the reused variable as the +lever-count fallback. + +## (e) What did not work (bytes) +- 2160-body plain-C sweep (scratch/gen.py -> gen_results.txt): x split / fused, three d spellings, three +E spellings, + +6 and +A updates inline / via temp, both sign-extension spellings, all 6 field-update orders, +E load before/after + the x load: best 21. s16 `d` (d1-d5.c): 21-27. Single pin on v1 or a0 (t7/t8.c): 21. +- do-while around the d chain only, empty do-while, do-while around the +6 load only (e1-e5.c): 2. +- do-while around only the +40 with the +6 load before it (f3.c): 21. + +## (f) Method +Counting first said "no missing instruction"; alloc_table.py was the wrong tool (the decider is local-alloc) — +`tools/localalloc_sim.py` + the `.sched` trace settled it. The method has no row for "a variable reuse that the +SCHEDULER needs (anti-dependences) but LOCAL-ALLOC forbids (multi-death)"; that contradiction is what the tree's pins, +the one-pin fallback and the do-while each resolve. + +## (g) Structs +Plausibly NO for this decision: typing `e` as an entity struct (`e->x -= d; e->y -= 0x20; e->z += 0x28; …`) produces the +fresh-temp form (the sweep's inline `*(u16 *)(e + K) -= …` spellings: 21+). The aggregate channel (expr.c:4568-4577) only +changes MEMORY dependences; here every load/store pair is already disambiguated by base+offset (memrefs_conflict_p) and +the deciding links are a REGISTER anti-dependence and sched1's loop-note barrier. Not tested with a body-local struct. diff --git a/.run/P36/agents/ov_SC06_000__func_80185354/body.c b/.run/P36/agents/ov_SC06_000__func_80185354/body.c new file mode 100644 index 0000000000..bcfdfc6e5a --- /dev/null +++ b/.run/P36/agents/ov_SC06_000__func_80185354/body.c @@ -0,0 +1,17 @@ +void func_80185354(void *param_1) +{ + s32 i; + u8 *e; + u32 vA, vB; + + for (i = 0; i < 200; i++) { + e = D_801AED08 + i * 0x2C; + ((void (*)(void *, s32))func_80185520)(e, i); + vA = rand() & 0x1F; + *(u32 *)(e + 0x18) = (vA << 2) | ((vA << 0x12) | (vA << 10)); + vB = rand() & 7; + *(u32 *)(e + 0x20) = vB; + } + func_8012BF4C((s32 *)param_1, 4); + func_8012AD50(param_1); +} diff --git a/.run/P36/agents/ov_SC06_000__func_80185354/mechanism.md b/.run/P36/agents/ov_SC06_000__func_80185354/mechanism.md new file mode 100644 index 0000000000..abbc4924e2 --- /dev/null +++ b/.run/P36/agents/ov_SC06_000__func_80185354/mechanism.md @@ -0,0 +1,43 @@ +# func_80185354 (ov_SC06_000_jr_8017AE2C.c) — e28, P36 T7 S104 + +**Score: 22 free (sweep best 18) -> 0, zero levers** (the `$16` pin deleted; plain C). Second `--try`. + +## (a) Residual +COUNT +4 (43 vs 39) and one extra callee-saved register: the free text walks TWO pointers — `s2` = `e` (the call +argument, stepped `+44`) and `s0` = `e + 32` (`addiu s0,s2,32`, stores at `-8(s0)`/`0(s0)`) — plus an extra `s3` for the +parameter. The target walks ONE pointer `s0` (initialised `lui/addiu` to `D_801AED08`, stepped `+44` in the branch delay +slot) and addresses both stores as `24(s0)`/`32(s0)`. + +## (b) Pass and decision +loop.c strength reduction (`strength_reduce`, gcc-2.7.2 loop.c; givs recorded by `record_giv` :4341, merged by +`combine_givs` :5494). In the free text `e` is itself a BIV (`e = e + 0x2C`); its field addresses `e+0x18`/`e+0x20` are +DEST_ADDR givs of that biv, and the pass reduces one of them into a new register (`s0 = e + 32`) while `e` must survive +for the call argument — two stepped registers. The tree's `$16` pin hid `e` from loop.c (a hard register is never a biv), +which is why the pin was NEEDED. In the target, `e` is a GIV of the counter biv `i` (`D_801AED08 + i*0x2C`): the call +argument and both field addresses are givs with the same multiplier, `combine_givs` folds them into ONE reduced register +with constant offsets, and `i` stays as the call's second argument and the exit test (`slti v0,s1,200`). +Proven on bytes (score 0); the `-dL` dump was NOT taken (the prediction from S103 c2/d16 closed on the first spelling). + +## (c) Move +Index the array by the loop counter instead of walking a pointer: +`for (i = 0; i < 200; i++) { e = D_801AED08 + i * 0x2C; func_80185520(e, i); … }` (the do-while and `e += 0x2C` deleted). +A do-while with the same indexed `e` (scratch/a3.c) scores 23 — the `for` (rotated loop, loop.c sees the canonical +biv/giv shape) is part of the close; writing each access as `D_801AED08 + (i-1)*0x2C + K` (a2.c) scores 32. + +## (d) Generator proposal +When the residual shows two callee-saved registers stepped by the same stride (one `addiu sK,sJ,K` before the loop) and +the tree pins the walked pointer, rewrite `p = BASE; do { … p += S; } while (++i < N)` as +`for (i = 0; i < N; i++) { p = BASE + i * S; … }` — the pointer becomes a giv of the counter and combines into one. + +## (e) What did not work +The sweep's R4/R6/R7/R8/R9/R10/R12 moves reach 18-19: none turns the walked pointer into a counter giv. + +## (f) Method +S103 c2 / S104 d16-d18 in METHOD_S103.md named this exact class ("a walked destination pointer -> index the array by the +loop counter"); counting first (+4, one extra `$s`) pointed straight at it. Worked as written. + +## (g) Structs +Yes, plausibly the ORIGINAL shape: `D_801AED08` is an array of 0x2C-byte records (`struct { u8 pad[0x18]; u32 f18; +u32 pad1c; u32 f20; … } D_801AED08[200];`, see func_801853F0's `+0x1C/+0x20/+0x24` fields) and `&D_801AED08[i]` is +exactly the indexed giv the close needs. A struct type would not change the pass decision beyond what the indexed form +already does (the decisive fact is biv vs giv in loop.c, not aliasing); not tested with a body-local struct. diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index 4a2b6a9f45..de2f72df90 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,7 +1,7 @@ { - "head": "6b2e585dd", + "head": "32f641aca", "stamp": "15956e4a96c4", - "generated": "2026-09-11 04:01", + "generated": "2026-09-11 04:02", "aliases": [ "main", "ov_SC03_014", @@ -21,207 +21,207 @@ "main": { "objects": 85, "identical": 85, - "seconds": 8.579999999999998, - "mean_s": 0.101 + "seconds": 7.531999999999999, + "mean_s": 0.089 }, "ov_SC03_014": { "objects": 32, "identical": 32, - "seconds": 5.74, - "mean_s": 0.179 + "seconds": 4.885999999999999, + "mean_s": 0.153 }, "ov_SC03_015": { "objects": 32, "identical": 32, - "seconds": 5.2860000000000005, - "mean_s": 0.165 + "seconds": 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"aliases": null, "header": false, "includers": 0, "nhash_before": "b5e764c2049e6646eaef80476f93bb53e49f1589", "nhash_after": "b5cd1ef833ec12711fb18ddbb4f5edd347b073d0", "source": ".run/P36/agents/ov_SC06_010__func_8017F438/scratch/other/func_80182944_d.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.051, "objects": ["build/src/ov_SC03_112/ov_SC03_112_jr_80181F74.o"], "before_text": "void func_80182944(void *arg0) {\n register s32 v0 __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 s0;\n s32 s1 = (s32)arg0;\n u8 *s2 = (u8 *)D_800AF630;\n s32 sp10[4];\n\n v0 = *(s32 *)(s1 + 0xD0);\n if (v0 != 0) {\n s0 = v0;\n func_8012F214((s32)arg0, (s32)&D_801A8338, (s32)sp10);\n *(V8x_80180D2C *)(s0 + 8) = *(V8x_80180D2C *)sp10;\n\n if (*(s32 *)(*(s32 *)(s1 + 0x20) + 4) < 0) {\n *(s32 *)(s0 + 4) |= (s32)0x80000000;\n } else {\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n *(s32 *)(s0 + 4) &= 0x7FFFFFFF;\n }\n\n {\n u16 x = *(u16 *)(s2 + 0xA3AA);\n s16 r = (func_8004787C(((x * 7) << 3) & 0x7F8) >> 4) + 0x455;\n *(s16 *)(s0 + 0x1A) = r;\n *(s16 *)(s0 + 0x18) = r;\n }\n }\n}\n", "after_text": "void func_80182944(void *arg0) {\n s32 v0;\n s32 s0;\n s32 s1 = (s32)arg0;\n u8 *s2 = (u8 *)D_800AF630;\n V8x_80180D2C out;\n\n v0 = *(s32 *)(s1 + 0xD0);\n if (v0 != 0) {\n s0 = v0;\n func_8012F214((s32)arg0, (s32)&D_801A8338, (s32)&out);\n *(V8x_80180D2C *)(s0 + 8) = out;\n\n if (*(u32 *)(*(s32 *)(s1 + 0x20) + 4) & 0x80000000) {\n *(s32 *)(s0 + 4) |= 0x80000000;\n } else {\n *(s32 *)(s0 + 4) &= 0x7FFFFFFF;\n }\n\n {\n u16 x = *(u16 *)(s2 + 0xA3AA);\n s16 r = (func_8004787C(((x * 7) << 3) & 0x7F8) >> 4) + 0x455;\n *(s16 *)(s0 + 0x1A) = r;\n *(s16 *)(s0 + 0x18) = r;\n }\n }\n}\n"} {"ts": "2026-09-11 04:01:39", "label": "s104_e26", "rung": "E", "calib": {"head": "6853b1604", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_110/ov_SC03_110_jr_8017FBC8.c", "fn": "func_80180D2C", "addr": 2149059884, "aliases": null, "header": false, "includers": 0, "nhash_before": "b5e764c2049e6646eaef80476f93bb53e49f1589", "nhash_after": "b5cd1ef833ec12711fb18ddbb4f5edd347b073d0", "source": "propagate:src/ov_SC03_112/ov_SC03_112_jr_80181F74.c:func_80182944", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.087, "objects": ["build/src/ov_SC03_110/ov_SC03_110_jr_8017FBC8.o"], "before_text": "void func_80180D2C(void *arg0) {\n register s32 v0 __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 s0;\n s32 s1 = (s32)arg0;\n u8 *s2 = (u8 *)D_800AF630;\n s32 sp10[4];\n\n v0 = *(s32 *)(s1 + 0xD0);\n if (v0 != 0) {\n s0 = v0;\n func_8012F214((s32)arg0, (s32)&D_8019BFFC, (s32)sp10);\n *(V8x_80180D2C *)(s0 + 8) = *(V8x_80180D2C *)sp10;\n\n if (*(s32 *)(*(s32 *)(s1 + 0x20) + 4) < 0) {\n *(s32 *)(s0 + 4) |= (s32)0x80000000;\n } else {\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n *(s32 *)(s0 + 4) &= 0x7FFFFFFF;\n }\n\n {\n u16 x = *(u16 *)(s2 + 0xA3AA);\n s16 r = (func_8004787C(((x * 7) << 3) & 0x7F8) >> 4) + 0x455;\n *(s16 *)(s0 + 0x1A) = r;\n *(s16 *)(s0 + 0x18) = r;\n }\n }\n}\n", "after_text": "void func_80180D2C(void *arg0) {\n s32 v0;\n s32 s0;\n s32 s1 = (s32)arg0;\n u8 *s2 = (u8 *)D_800AF630;\n V8x_80180D2C out;\n\n v0 = *(s32 *)(s1 + 0xD0);\n if (v0 != 0) {\n s0 = v0;\n func_8012F214((s32)arg0, (s32)&D_8019BFFC, (s32)&out);\n *(V8x_80180D2C *)(s0 + 8) = out;\n\n if (*(u32 *)(*(s32 *)(s1 + 0x20) + 4) & 0x80000000) {\n *(s32 *)(s0 + 4) |= 0x80000000;\n } else {\n *(s32 *)(s0 + 4) &= 0x7FFFFFFF;\n }\n\n {\n u16 x = *(u16 *)(s2 + 0xA3AA);\n s16 r = (func_8004787C(((x * 7) << 3) & 0x7F8) >> 4) + 0x455;\n *(s16 *)(s0 + 0x1A) = r;\n *(s16 *)(s0 + 0x18) = r;\n }\n }\n}\n"} {"ts": "2026-09-11 04:02:01", "label": "s104_e26", "rung": "E", "calib": {"head": "6b2e585dd", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_108/ov_SC03_108_jr_8017F83C.c", "fn": "func_801809A0", "addr": 2149058976, "aliases": null, "header": false, "includers": 0, "nhash_before": "f715c2c945431b556d1768aa63d0f248bac9d826", "nhash_after": "93f4fd362dbe03afc89ed29709a89625dd6d9f7f", "source": ".run/P36/agents/ov_SC06_010__func_8017F438/scratch/other/func_801809A0_d.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.064, "objects": ["build/src/ov_SC03_108/ov_SC03_108_jr_8017F83C.o"], "before_text": "s32 func_801809A0(void *arg0)\n{\n register s32 v0 __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 s0;\n s32 s1 = (s32)arg0;\n u8 *s2 = (u8 *)D_800AF630;\n s32 sp10[4];\n\n v0 = *(s32 *)(s1 + 0xD0);\n if (v0 != 0) {\n s0 = v0;\n func_8012F214((s32)arg0, (s32)&D_8019E6FC, (s32)sp10);\n *(V8x_80180D2C *)(s0 + 8) = *(V8x_80180D2C *)sp10;\n\n if (*(s32 *)(*(s32 *)(s1 + 0x20) + 4) < 0) {\n *(s32 *)(s0 + 4) |= (s32)0x80000000;\n } else {\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n *(s32 *)(s0 + 4) &= 0x7FFFFFFF;\n }\n\n {\n u16 x = *(u16 *)(s2 + 0xA3AA);\n s16 r = (func_8004787C(((x * 7) << 3) & 0x7F8) >> 4) + 0x455;\n *(s16 *)(s0 + 0x1A) = r;\n *(s16 *)(s0 + 0x18) = r;\n }\n }\n}\n", "after_text": "s32 func_801809A0(void *arg0)\n{\n s32 v0;\n s32 s0;\n s32 s1 = (s32)arg0;\n u8 *s2 = (u8 *)D_800AF630;\n V8x_80180D2C out;\n\n v0 = *(s32 *)(s1 + 0xD0);\n if (v0 != 0) {\n s0 = v0;\n func_8012F214((s32)arg0, (s32)&D_8019E6FC, (s32)&out);\n *(V8x_80180D2C *)(s0 + 8) = out;\n\n if (*(u32 *)(*(s32 *)(s1 + 0x20) + 4) & 0x80000000) {\n *(s32 *)(s0 + 4) |= 0x80000000;\n } else {\n *(s32 *)(s0 + 4) &= 0x7FFFFFFF;\n }\n\n {\n u16 x = *(u16 *)(s2 + 0xA3AA);\n s16 r = (func_8004787C(((x * 7) << 3) & 0x7F8) >> 4) + 0x455;\n *(s16 *)(s0 + 0x1A) = r;\n *(s16 *)(s0 + 0x18) = r;\n }\n }\n}\n"} +{"ts": "2026-09-11 04:02:38", "label": "s104_e26", "rung": "E", "calib": {"head": "32f641aca", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c", "fn": "func_8017E764", "addr": 2149050212, "aliases": null, "header": false, "includers": 0, "nhash_before": "85ccbf86475eb6cb878cd24c98fb5e78eb213fe5", "nhash_after": "05e15c2a22084e23bfef1c49d10e45ddb56bc792", "source": ".run/P36/agents/ov_SC06_010__func_8017E764/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.277, "objects": ["build/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.o"], "before_text": "void func_8017E764(s32 param_1)\n{\n s16 pos[4];\n s16 adv[4];\n s16 mv[4];\n s32 src3[4];\n s32 dst2[4];\n s32 mid[4];\n u16 angle;\n s32 angle2;\n s32 t;\n s32 i;\n s32 j;\n s32 k;\n s32 m;\n s32 self;\n s32 found;\n s32 flag;\n s32 val;\n s32 hundred;\n u16 *row;\n u16 *np;\n s32 *midp;\n u8 *ent;\n\n i = *(s16 *)&D_80126B66;\n if ((u32)(i - 0x44E) >= 0x32C5U) {\n if (*(s16 *)(param_1 + 0x84) != 0) {\n *(s16 *)(param_1 + 0x84) = 0;\n func_8002D4C8(4, 0x931);\n }\n } else {\n *(s16 *)(param_1 + 0x84) = 1;\n if (i < 0x5CE) {\n func_8002D4C8(0x931, (((i - 0x44E) * 0x7F / 0x180) | 0x1000) & 0xFFFF);\n } else if (i >= 0x3593) {\n func_8002D4C8(0x931, (((i - 0x3592) * 0x7F / 0x180) | 0x1000) & 0xFFFF);\n } else {\n func_8002D4C8(0x931, 0x107F);\n }\n }\n\n if (*(u16 *)(param_1 + 2) == 0) {\n hundred = 100;\n row = &D_8018A5A2;\n for (i = 0x13F; i >= 0; i--) {\n *row = hundred;\n row += 4;\n }\n *(s32 *)(param_1 + 0xCC) = func_8012C658(0x238, 0xA, param_1);\n *(u16 *)(param_1 + 2) += 1;\n *(u16 *)(param_1 + 0xE) += 0x5F0;\n }\n\n ent = D_801202A0;\n pos[0] = *(u16 *)(param_1 + 6);\n {\n register u16 *vp __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus7)\n u16 t;\n vp = (u16 *)&D_80126B66;\n t = *(volatile u16 *)vp;\n pos[1] = *(u16 *)(param_1 + 0xA);\n pos[2] = t + 8;\n }\n i = 0;\n np = (u16 *)D_801152A8;\n t = (ratan2(*(s16 *)&D_80126B62 - *(s16 *)(param_1 + 0xA),\n *(s16 *)&D_80126B5E - *(s16 *)(param_1 + 6)) - 0x400) & 0xFFF;\n angle = t;\n adv[0] = pos[0] - (func_8004787C(t) >> 3);\n adv[1] = pos[1] + (func_80047948(t) >> 3);\n adv[2] = pos[2];\n self = *(s32 *)(param_1 + 0xCC);\n angle2 = t;\n *(u16 *)(self + 0x5C) = 0;\n\n for (; i < 0x60; ent += 0x10C, i++) {\n if (*(u16 *)ent != 0x238) {\n continue;\n }\n flag = *(u16 *)(ent + 0x34);\n if (flag != 1) {\n continue;\n }\n if (func_80135888(*(s32 *)(ent + 0x20), *(s32 *)(ent + 0x58), (s32)pos, (s32)adv) == 0) {\n continue;\n }\n found = 0;\n *(u16 *)(self + 0x5C) = 0x4C08;\n if (*(u8 *)(self + 0x74) != 0) {\n *(s32 *)(param_1 + 0xDC) = flag;\n if (*(s16 *)(ent + 0x70) == 0) {\n mv[0] = D_80126B5E;\n mv[1] = D_80126B62;\n mv[2] = D_80126B66;\n np[0] = -np[0];\n np[1] = -np[1];\n np[2] = -np[2];\n func_8012F568(1, 0x4018, 0, 0x20, (s32)mv, (s32)np);\n }\n j = *(s16 *)&D_80126B66 - *(s16 *)(param_1 + 0xE) + 0x98;\n j = j / 0x130;\n val = (&D_8018A5A0)[j * 0x20];\n if (val == flag) {\n goto Lup;\n }\n if (val < 2) {\n if (val == 0) {\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle;\n }\n goto Ldone;\n }\n if (val == 2) {\n goto Ldown;\n }\n goto Ldone;\n Lup:\n *(s16 *)(*(s32 *)(self + 0x20) + 0x14) =\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) + 0x10;\n found = 1;\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) &= 0xFFF;\n goto Ldone;\n Ldown:\n *(s16 *)(*(s32 *)(self + 0x20) + 0x14) =\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) - 0x10;\n found = 1;\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) &= 0xFFF;\n } else {\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle;\n }\n Ldone:\n *(s32 *)(self + 4) = *(s32 *)(param_1 + 4)\n - func_8004787C(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40;\n *(s32 *)(self + 8) = *(s32 *)(param_1 + 8)\n + func_80047948(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40;\n *(s32 *)(self + 0xC) = D_80126B64;\n if (found != 0) {\n src3[0] = *(s32 *)&D_80126B5C;\n src3[1] = D_80126B60;\n src3[2] = *(s32 *)(&D_80126B5C + 8);\n midp = mid;\n func_8012F0BC((s32 *)(*(s32 *)(self + 0x20) + 0x34), src3, midp);\n midp = 0;\n func_8012B2CC(self);\n func_8012F1A4((s32 *)(*(s32 *)(self + 0x20) + 0x34), mid, dst2);\n *(s32 *)&D_80126B5C = dst2[0];\n D_80126B60 = dst2[1];\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle;\n *(s32 *)(self + 4) = *(s32 *)(param_1 + 4)\n - func_8004787C(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40;\n *(s32 *)(self + 8) = *(s32 *)(param_1 + 8)\n + func_80047948(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40;\n func_8012B2CC(self);\n }\n if (*(s32 *)(param_1 + 0xDC) != 0) {\n i = *(s16 *)&D_80126B5E - *(s16 *)(param_1 + 6);\n j = *(s16 *)&D_80126B62 - *(s16 *)(param_1 + 0xA);\n if (i * i + j * j > 0x14D10) {\n *(s32 *)&D_80126B5C = *(s32 *)(param_1 + 4) - func_8004787C(angle2) * 0x1240;\n D_80126B60 = *(s32 *)(param_1 + 8) + func_80047948(angle2) * 0x1240;\n }\n }\n }\n\n if (*(u16 *)(self + 0x5C) == 0) {\n *(s32 *)(param_1 + 0xDC) = 0;\n }\n *(u16 *)(param_1 + 0xFC) = (*(u16 *)(param_1 + 0xFC) + 0x10) & 0xFFF;\n i = *(s16 *)&D_80126B66 - *(s16 *)(param_1 + 0xE);\n j = i / 0x130;\n j -= 2;\n row = &D_8018A59C + j * 0x20;\n for (k = 0; k < 7; k++, j++) {\n if ((u32)j < 0x28) {\n for (m = 0; m < 8; m++) {\n row += 3;\n if (*row == 100) {\n row -= 3;\n ent = (u8 *)func_8012C658(0x238, *row, param_1);\n if (ent == 0) {\n return;\n }\n *(s32 *)(ent + 0xCC) = (s32)row;\n row += 3;\n }\n *row = j;\n row++;\n }\n } else {\n row += 0x20;\n }\n }\n}\n", "after_text": "void func_8017E764(s32 param_1)\n{\n s16 pos[4];\n s16 adv[4];\n s16 mv[4];\n s32 src3[4];\n s32 dst2[4];\n s32 mid[4];\n u16 angle;\n s32 angle2;\n s32 t;\n s32 i;\n s32 j;\n s32 k;\n s32 m;\n s32 self;\n s32 found;\n s32 flag;\n s32 val;\n s32 hundred;\n u16 *row;\n u16 *np;\n s32 *midp;\n u8 *ent;\n\n i = *(s16 *)&D_80126B66;\n if ((u32)(i - 0x44E) >= 0x32C5U) {\n if (*(s16 *)(param_1 + 0x84) != 0) {\n *(s16 *)(param_1 + 0x84) = 0;\n func_8002D4C8(4, 0x931);\n }\n } else {\n *(s16 *)(param_1 + 0x84) = 1;\n if (i < 0x5CE) {\n func_8002D4C8(0x931, (((i - 0x44E) * 0x7F / 0x180) | 0x1000) & 0xFFFF);\n } else if (i >= 0x3593) {\n func_8002D4C8(0x931, (((i - 0x3592) * 0x7F / 0x180) | 0x1000) & 0xFFFF);\n } else {\n func_8002D4C8(0x931, 0x107F);\n }\n }\n\n if (*(u16 *)(param_1 + 2) == 0) {\n hundred = 100;\n row = &D_8018A5A2;\n for (i = 0x13F; i >= 0; i--) {\n *row = hundred;\n row += 4;\n }\n *(s32 *)(param_1 + 0xCC) = func_8012C658(0x238, 0xA, param_1);\n *(u16 *)(param_1 + 2) += 1;\n *(u16 *)(param_1 + 0xE) += 0x5F0;\n }\n\n ent = D_801202A0;\n i = 0;\n pos[0] = *(u16 *)(param_1 + 6);\n {\n u16 tt;\n /* `val` is the loop's table-value temp reused here (both live in $v1 in the target): its second set keeps\n * this address load from sched1's birthing priority (sched.c:2469-2545), so it is scheduled above the pos[0]\n * store and global-alloc gives it $v1 (P36 S104 e26). */\n val = (s32)&D_80126B66;\n tt = *(volatile u16 *)val; /* a byte-needed volatile, kept as ordinary C (gate-1 decision 3): a volatile MEM fails combine's recog (combine.c:491 init_recog_no_volatile, recog.c:807), so the address stays in a register (la + lhu 0(reg)) (P36 S104 e26 minimum-lever) */\n pos[1] = *(u16 *)(param_1 + 0xA);\n pos[2] = tt + 8;\n }\n np = (u16 *)D_801152A8;\n t = (ratan2(*(s16 *)&D_80126B62 - *(s16 *)(param_1 + 0xA),\n *(s16 *)&D_80126B5E - *(s16 *)(param_1 + 6)) - 0x400) & 0xFFF;\n angle = t;\n adv[0] = pos[0] - (func_8004787C(t) >> 3);\n adv[1] = pos[1] + (func_80047948(t) >> 3);\n adv[2] = pos[2];\n self = *(s32 *)(param_1 + 0xCC);\n angle2 = t;\n *(u16 *)(self + 0x5C) = 0;\n\n for (; i < 0x60; ent += 0x10C, i++) {\n if (*(u16 *)ent != 0x238) {\n continue;\n }\n flag = *(u16 *)(ent + 0x34);\n if (flag != 1) {\n continue;\n }\n if (func_80135888(*(s32 *)(ent + 0x20), *(s32 *)(ent + 0x58), (s32)pos, (s32)adv) == 0) {\n continue;\n }\n found = 0;\n *(u16 *)(self + 0x5C) = 0x4C08;\n if (*(u8 *)(self + 0x74) != 0) {\n *(s32 *)(param_1 + 0xDC) = flag;\n if (*(s16 *)(ent + 0x70) == 0) {\n mv[0] = D_80126B5E;\n mv[1] = D_80126B62;\n mv[2] = D_80126B66;\n np[0] = -np[0];\n np[1] = -np[1];\n np[2] = -np[2];\n func_8012F568(1, 0x4018, 0, 0x20, (s32)mv, (s32)np);\n }\n j = *(s16 *)&D_80126B66 - *(s16 *)(param_1 + 0xE) + 0x98;\n j = j / 0x130;\n val = (&D_8018A5A0)[j * 0x20];\n if (val == flag) {\n goto Lup;\n }\n if (val < 2) {\n if (val == 0) {\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle;\n }\n goto Ldone;\n }\n if (val == 2) {\n goto Ldown;\n }\n goto Ldone;\n Lup:\n *(s16 *)(*(s32 *)(self + 0x20) + 0x14) =\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) + 0x10;\n found = 1;\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) &= 0xFFF;\n goto Ldone;\n Ldown:\n *(s16 *)(*(s32 *)(self + 0x20) + 0x14) =\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) - 0x10;\n found = 1;\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) &= 0xFFF;\n } else {\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle;\n }\n Ldone:\n *(s32 *)(self + 4) = *(s32 *)(param_1 + 4)\n - func_8004787C(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40;\n *(s32 *)(self + 8) = *(s32 *)(param_1 + 8)\n + func_80047948(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40;\n *(s32 *)(self + 0xC) = D_80126B64;\n if (found != 0) {\n src3[0] = *(s32 *)&D_80126B5C;\n src3[1] = D_80126B60;\n src3[2] = *(s32 *)(&D_80126B5C + 8);\n midp = mid;\n func_8012F0BC((s32 *)(*(s32 *)(self + 0x20) + 0x34), src3, midp);\n midp = 0;\n func_8012B2CC(self);\n func_8012F1A4((s32 *)(*(s32 *)(self + 0x20) + 0x34), mid, dst2);\n *(s32 *)&D_80126B5C = dst2[0];\n D_80126B60 = dst2[1];\n *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle;\n *(s32 *)(self + 4) = *(s32 *)(param_1 + 4)\n - func_8004787C(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40;\n *(s32 *)(self + 8) = *(s32 *)(param_1 + 8)\n + func_80047948(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40;\n func_8012B2CC(self);\n }\n if (*(s32 *)(param_1 + 0xDC) != 0) {\n i = *(s16 *)&D_80126B5E - *(s16 *)(param_1 + 6);\n j = *(s16 *)&D_80126B62 - *(s16 *)(param_1 + 0xA);\n if (i * i + j * j > 0x14D10) {\n *(s32 *)&D_80126B5C = *(s32 *)(param_1 + 4) - func_8004787C(angle2) * 0x1240;\n D_80126B60 = *(s32 *)(param_1 + 8) + func_80047948(angle2) * 0x1240;\n }\n }\n }\n\n if (*(u16 *)(self + 0x5C) == 0) {\n *(s32 *)(param_1 + 0xDC) = 0;\n }\n *(u16 *)(param_1 + 0xFC) = (*(u16 *)(param_1 + 0xFC) + 0x10) & 0xFFF;\n i = *(s16 *)&D_80126B66 - *(s16 *)(param_1 + 0xE);\n j = i / 0x130;\n j -= 2;\n row = &D_8018A59C + j * 0x20;\n for (k = 0; k < 7; k++, j++) {\n if ((u32)j < 0x28) {\n for (m = 0; m < 8; m++) {\n row += 3;\n if (*row == 100) {\n row -= 3;\n ent = (u8 *)func_8012C658(0x238, *row, param_1);\n if (ent == 0) {\n return;\n }\n *(s32 *)(ent + 0xCC) = (s32)row;\n row += 3;\n }\n *row = j;\n row++;\n }\n } else {\n row += 0x20;\n }\n }\n}\n"} diff --git a/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c b/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c index c482c021f5..b8ed3f3646 100644 --- a/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c +++ b/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c @@ -5117,16 +5117,18 @@ void func_8017E764(s32 param_1) } ent = D_801202A0; + i = 0; pos[0] = *(u16 *)(param_1 + 6); { - register u16 *vp __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus7) - u16 t; - vp = (u16 *)&D_80126B66; - t = *(volatile u16 *)vp; + u16 tt; + /* `val` is the loop's table-value temp reused here (both live in $v1 in the target): its second set keeps + * this address load from sched1's birthing priority (sched.c:2469-2545), so it is scheduled above the pos[0] + * store and global-alloc gives it $v1 (P36 S104 e26). */ + val = (s32)&D_80126B66; + tt = *(volatile u16 *)val; /* a byte-needed volatile, kept as ordinary C (gate-1 decision 3): a volatile MEM fails combine's recog (combine.c:491 init_recog_no_volatile, recog.c:807), so the address stays in a register (la + lhu 0(reg)) (P36 S104 e26 minimum-lever) */ pos[1] = *(u16 *)(param_1 + 0xA); - pos[2] = t + 8; + pos[2] = tt + 8; } - i = 0; np = (u16 *)D_801152A8; t = (ratan2(*(s16 *)&D_80126B62 - *(s16 *)(param_1 + 0xA), *(s16 *)&D_80126B5E - *(s16 *)(param_1 + 6)) - 0x400) & 0xFFF;