From 951b60ab05882877b2eb064c7ccad181543e1a8f Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 11 Sep 2026 13:17:02 -0600 Subject: [PATCH] =?UTF-8?q?phase-36:=20S105=20s105=5Ff4=20=E2=80=94=20func?= =?UTF-8?q?=5F80182BBC=20banked=20at=200=20through=20the=20whole-object=20?= =?UTF-8?q?gate=20+=20propagated=20=E2=80=94=20f4=20plain=20C=20(a=20u16?= =?UTF-8?q?=20counter=20tied=20with=20a=20symbol=20=E2=86=92=20s32)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .run/P36/delever/calibration.json | 364 +++++++++++----------- .run/P36/delever/ledger.jsonl | 1 + src/ov_SC04_011/ov_SC04_011_jr_8017D494.c | 4 +- 3 files changed, 185 insertions(+), 184 deletions(-) diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index e2200d9942..5486814041 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,5 +1,5 @@ { - "head": "a59914878", + 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"seconds": 2.3 + "seconds": 2.2 } diff --git a/.run/P36/delever/ledger.jsonl b/.run/P36/delever/ledger.jsonl index dd5f982462..4ca83b0f86 100644 --- a/.run/P36/delever/ledger.jsonl +++ b/.run/P36/delever/ledger.jsonl @@ -29598,3 +29598,4 @@ {"ts": "2026-09-11 13:07:44", "label": "s105_f3_minlever", "rung": "E", "calib": {"head": "71e32fed0", "stamp": "15956e4a96c4"}, "tu": "src/md_SC07_004/md_SC07_004.c", "fn": "func_801ADF5C", "addr": 2149244764, "aliases": null, "header": false, "includers": 0, "nhash_before": "5fe4a1e02a9494e91b8615408e7eaa308ecbc7ea", "nhash_after": "5fe4a1e02a9494e91b8615408e7eaa308ecbc7ea", "source": ".run/P36/agents/md_SC07_004__func_801ADF5C/body.c", "verdict": "LEVER-FREE", "sites": [{"ord": 0, "kind": "pin", "cls": "A", "detail": "$2", "via": "", "line": 9663, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 1, "kind": "pin", "cls": "A", "detail": "$3", "via": "", "line": 9664, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 2, "kind": "pin", "cls": "A", "detail": "$5", "via": "", "line": 9665, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 3, "kind": "barrier", "cls": "B", "detail": "", "via": "", "line": 9669, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}, {"ord": 4, "kind": "barrier", "cls": "B", "detail": "", "via": "", "line": 9685, "verdict": "NEEDED", "why": "left by the author", "oracle": ""}], "compiles": 1, "seconds": 0.308, "objects": ["build/src/md_SC07_004/md_SC07_004.o"], "before_text": "void func_801ADF5C(void *a0)\n{\n void *s0;\n struct { s16 x, y, w, h; } rect;\n\n void *p;\n\n s0 = a0;\n\n /* D_800B9AC4/D_800B9AC8 are fields of the struct rooted at D_800B9A78\n * (see engine_core.h's Ent_956C / func_8012956C); the func_801298F4\n * call target is that struct's base, computed as p - 0x4C so the\n * compiler reuses the already-materialized D_800B9AC4 address instead\n * of emitting a second relocation. A plain `&D_800B9AC4 - 0x4C`\n * constant-folds at compile time into a FRESH symbolic constant\n * (its own lui/addiu, computed before the stores) instead of runtime\n * register arithmetic, so the address is pinned into a real pseudo\n * with the same zero-byte re-tie idiom func_8012956C uses for its\n * `base` pointer. */\n p = &D_800B9AC4;\n *(void **)p = &D_801F76B0;\n D_800B9AC8 = &D_801F74A8;\n func_801298F4((void *)((u8 *)p - 0x4C));\n\n {\n s32 mask;\n s16 one;\n register s32 rv0 __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n register s32 rv1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n register s32 ra1 __asm__(\"$5\"); // !FAKE: pin $5 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n mask = 0xF7FFFFFF;\n one = 1;\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n rv0 = 0x2000;\n rv1 = 0x118;\n\n D_800B9AA4 = (s16)rv0;\n D_800B9AA6 = (s16)rv0;\n\n rv0 = 0x8C;\n\n D_800B9A90 = (s16)rv1;\n D_800B9A92 = (s16)rv1;\n D_800B9AB4 = (s16)rv1;\n D_800B9AB6 = (s16)rv1;\n\n\n rv1 = D_800B9A88;\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus9)\n ra1 = 0x100;\n\n D_800B9AA0 = (s16)rv0;\n D_800B9AA2 = (s16)rv0;\n\n rv0 = 0x1E0;\n\n rect.x = (s16)ra1;\n rect.w = (s16)ra1;\n\n ra1 = (s32)&D_801F8B18;\n\n D_800B9AAE = one;\n D_800B9ABA = 0;\n D_800B9AB8 = 0;\n\n rect.y = (s16)rv0;\n rect.h = one;\n\n D_800B9A88 = rv1 & mask;\n\n StoreImage((s32)&rect, (void *)ra1);\n }\n\n func_8012AD50(s0);\n}\n", "after_text": "void func_801ADF5C(void *a0)\n{\n void *s0;\n struct { s16 x, y, w, h; } rect;\n\n void *p;\n\n s0 = a0;\n\n /* D_800B9AC4/D_800B9AC8 are fields of the struct rooted at D_800B9A78\n * (see engine_core.h's Ent_956C / func_8012956C); the func_801298F4\n * call target is that struct's base, computed as p - 0x4C so the\n * compiler reuses the already-materialized D_800B9AC4 address instead\n * of emitting a second relocation. A plain `&D_800B9AC4 - 0x4C`\n * constant-folds at compile time into a FRESH symbolic constant\n * (its own lui/addiu, computed before the stores) instead of runtime\n * register arithmetic, so the address is pinned into a real pseudo\n * with the same zero-byte re-tie idiom func_8012956C uses for its\n * `base` pointer. */\n p = &D_800B9AC4;\n *(void **)p = &D_801F76B0;\n D_800B9AC8 = &D_801F74A8;\n func_801298F4((void *)((u8 *)p - 0x4C));\n\n {\n s32 mask;\n s16 one;\n register s32 rv0 __asm__(\"$2\"); // !FAKE: pin $2 rv0 \u2014 the 0x2000/0x8C/0x1E0 holder is a 3-death pseudo, global.c find_reg (global.c:945-990) hands it $a2 once the single-death locals hold $v0/$v1 (P36 S105 f3 minimum-lever)\n register s32 rv1 __asm__(\"$3\"); // !FAKE: pin $3 rv1 \u2014 the 0x118/D_800B9A88 holder, same global.c:945-990 contest (P36 S105 f3 minimum-lever)\n register s32 ra1 __asm__(\"$5\"); // !FAKE: pin $5 ra1 \u2014 keeps `ra1 = &D_801F8B18` a second SET of one pseudo (combine.c:1460 otherwise folds it into the call argument and the 0x100 load becomes a birthing insn, sched.c:2477-2490) (P36 S105 f3 minimum-lever)\n\n mask = 0xF7FFFFFF;\n one = 1;\n __asm__ __volatile__(\"\"); // !FAKE: barrier after one/mask \u2014 sched1 birthing boost (sched.c:2477-2544) would sink `li 1` to its first store; the target keeps it at the block top (P36 S105 f3 minimum-lever)\n rv0 = 0x2000;\n rv1 = 0x118;\n\n D_800B9AA4 = (s16)rv0;\n D_800B9AA6 = (s16)rv0;\n\n rv0 = 0x8C;\n\n D_800B9A90 = (s16)rv1;\n D_800B9A92 = (s16)rv1;\n D_800B9AB4 = (s16)rv1;\n D_800B9AB6 = (s16)rv1;\n\n\n rv1 = D_800B9A88;\n __asm__ __volatile__(\"\"); // !FAKE: barrier after the D_800B9A88 load \u2014 keeps the 0x8C/0x100 group below the load (sched1 hazard tie-break, sched.c:2620-2690, otherwise lifts the load and the 0x118 stores past it) (P36 S105 f3 minimum-lever)\n ra1 = 0x100;\n\n D_800B9AA0 = (s16)rv0;\n D_800B9AA2 = (s16)rv0;\n\n rv0 = 0x1E0;\n\n rect.x = (s16)ra1;\n rect.w = (s16)ra1;\n\n ra1 = (s32)&D_801F8B18;\n\n D_800B9AAE = one;\n D_800B9ABA = 0;\n D_800B9AB8 = 0;\n\n rect.y = (s16)rv0;\n rect.h = one;\n\n D_800B9A88 = rv1 & mask;\n\n StoreImage((s32)&rect, (void *)ra1);\n }\n\n func_8012AD50(s0);\n}\n"} {"ts": "2026-09-11 13:16:24", "label": "s105_f4", "rung": "E", "calib": {"head": "310cea91f", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_011/ov_SC04_011_jr_8017D494.c", "fn": "func_801835B0", "addr": 2149070256, "aliases": null, "header": false, "includers": 0, "nhash_before": "cf754f55211cfd7815057357e76cbc8644b45f08", "nhash_after": "ecdbae9cdde6fc5053c5622c0a3ebfd21ba70abb", "source": ".run/P36/agents/ov_SC04_011__func_801835B0/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.412, "objects": ["build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o"], "before_text": "void func_801835B0(s32 a0)\n{\n s32 obj;\n s16 *p;\n s32 t;\n s16 u;\n s16 m;\n s16 c;\n s32 pad[6]; /* \u00a7333: sets the 0x18 frame */\n\n obj = aFC4C[D_801EFD20];\n p = (s16 *)(a0 + 0xEC);\n if ((a0 + 0xE4) != 0) {\n *(u16 *)(a0 + 0xEC) = *(u16 *)(a0 + 0xE4) - *(u16 *)(obj + 6);\n *(u16 *)(a0 + 0xEE) = *(u16 *)(a0 + 0xE6) - *(u16 *)(obj + 0xA);\n *(u16 *)(a0 + 0xF0) = *(u16 *)(a0 + 0xE8) - *(u16 *)(obj + 0xE);\n } else {\n *(u16 *)(a0 + 0xF0) = 0;\n *(u16 *)(a0 + 0xEE) = 0;\n *(u16 *)(a0 + 0xEC) = 0;\n }\n *(u16 *)(a0 + 0xEA) = 0x1E0;\n\n t = p[0];\n u = t;\n if (t < 0) {\n __asm__(\"\" : \"=r\"(u) : \"0\"(u)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B t3_tus1)\n m = -u;\n } else {\n m = u;\n }\n *(u16 *)(a0 + 0xE2) = 0;\n\n t = p[1];\n u = t;\n if (t < 0) {\n __asm__(\"\" : \"=r\"(u) : \"0\"(u)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B t3_tus1)\n c = -u;\n } else {\n c = u;\n }\n if (m < c) {\n m = c;\n *(u16 *)(a0 + 0xE2) = 1;\n }\n\n t = p[2];\n u = t;\n if (t < 0) {\n __asm__(\"\" : \"=r\"(u) : \"0\"(u)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B t3_tus1)\n c = -u;\n } else {\n c = u;\n }\n if (m < c) {\n *(u16 *)(a0 + 0xE2) = 2;\n }\n}\n", "after_text": "void func_801835B0(s32 a0)\n{\n s32 obj;\n s16 *p;\n s16 x;\n s16 y;\n s16 z;\n s16 m;\n s16 c;\n\n obj = aFC4C[D_801EFD20];\n p = (s16 *)(a0 + 0xEC);\n if ((a0 + 0xE4) != 0) {\n *(u16 *)(a0 + 0xEC) = *(u16 *)(a0 + 0xE4) - *(u16 *)(obj + 6);\n *(u16 *)(a0 + 0xEE) = *(u16 *)(a0 + 0xE6) - *(u16 *)(obj + 0xA);\n *(u16 *)(a0 + 0xF0) = *(u16 *)(a0 + 0xE8) - *(u16 *)(obj + 0xE);\n } else {\n *(u16 *)(a0 + 0xF0) = 0;\n *(u16 *)(a0 + 0xEE) = 0;\n *(u16 *)(a0 + 0xEC) = 0;\n }\n *(u16 *)(a0 + 0xEA) = 0x1E0;\n\n x = p[0];\n if (x < 0) {\n m = -x;\n } else {\n m = x;\n }\n *(u16 *)(a0 + 0xE2) = 0;\n\n y = p[1];\n if (y < 0) {\n c = -y;\n } else {\n c = y;\n }\n if (m < c) {\n m = c;\n *(u16 *)(a0 + 0xE2) = 1;\n }\n\n z = p[2];\n if (z < 0) {\n c = -z;\n } else {\n c = z;\n }\n if (m < c) {\n *(u16 *)(a0 + 0xE2) = 2;\n }\n}\n"} {"ts": "2026-09-11 13:16:42", "label": "s105_f4", "rung": "E", "calib": {"head": "a59914878", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_011/ov_SC04_011_jr_8017D494.c", "fn": "func_8018315C", "addr": 2149069148, "aliases": null, "header": false, "includers": 0, "nhash_before": "a34007e012f5ba3a806284388a249725b2d5b79f", "nhash_after": "0e0a8cad45835f35a3ef222092132bdc067ffc59", "source": ".run/P36/agents/ov_SC04_011__func_8018315C/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.386, "objects": ["build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o"], "before_text": "s32 func_8018315C(s32 *a0) {\n s32 s0;\n s32 v0;\n register s32 v1 __asm__(\"$3\"); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B t3_tus1)\n s32 frame_pad[2];\n extern int func_8001AAA0(void);\n (void)&frame_pad;\n\n s0 = (s32)a0;\n\n func_80016450(*(u8 *)(s0 + 0xF2), 1);\n\n v0 = *(s32 *)(s0 + 0x1C);\n if (v0 != 0) {\n v0 -= 1;\n *(s32 *)(s0 + 0x1C) = v0;\n if (v0 != 0) {\n goto ret0;\n }\n\n func_8018BC08();\n\n if (D_801EFD1C != 0) {\n func_8012C218(D_801EFD1C);\n D_801EFD1C = 0;\n }\n\n func_80186CD8(s0);\n\n v0 = *(s32 *)(s0 + 0x1C);\n /* unconditional \u2014 this store shares the delay slot of the branch\n * that tests the reloaded 0x1C counter below */\n *(u16 *)(s0 + 0x10A) = 0;\n if (v0 != 0) {\n goto ret0;\n }\n }\n\n v0 = *(s16 *)(s0 + 0x84);\n if (v0 == 0) {\n if (((int (*)(int))func_8001AAA0)(0x68) != 0) {\n v0 = 1;\n *(s16 *)(s0 + 0x84) = v0;\n }\n }\n\n v0 = *(s16 *)(s0 + 0xF2);\n if (v0 != 0) {\n register s32 zr __asm__(\"$0\"); // !FAKE: pin $0 \u2014 NEEDED DIFFERS (P36 rung B t3_tus1)\n v1 = v0 + zr;\n v0 = v1 - 2;\n *(s16 *)(s0 + 0xF2) = v0;\n if ((s16)v0 < 0) {\n *(s16 *)(s0 + 0xF2) = 0;\n }\n v0 = *(s16 *)(s0 + 0xF2);\n if (v0 != 0) {\n goto ret0;\n }\n }\n\n v0 = *(s16 *)(s0 + 0x84);\n if (v0 != 0) {\n v0 = 1;\n goto ret;\n }\nret0:\n v0 = 0;\nret:\n return v0;\n}\n", "after_text": "s32 func_8018315C(s32 *a0) {\n s32 s0;\n s32 v0;\n s16 x;\n s16 y;\n extern int func_8001AAA0(void);\n\n s0 = (s32)a0;\n\n func_80016450(*(u8 *)(s0 + 0xF2), 1);\n\n v0 = *(s32 *)(s0 + 0x1C);\n if (v0 != 0) {\n v0 -= 1;\n *(s32 *)(s0 + 0x1C) = v0;\n if (v0 != 0) {\n goto ret0;\n }\n\n func_8018BC08();\n\n if (D_801EFD1C != 0) {\n func_8012C218(D_801EFD1C);\n D_801EFD1C = 0;\n }\n\n func_80186CD8(s0);\n\n v0 = *(s32 *)(s0 + 0x1C);\n /* unconditional \u2014 this store shares the delay slot of the branch\n * that tests the reloaded 0x1C counter below */\n *(u16 *)(s0 + 0x10A) = 0;\n if (v0 != 0) {\n goto ret0;\n }\n }\n\n v0 = *(s16 *)(s0 + 0x84);\n if (v0 == 0) {\n if (((int (*)(int))func_8001AAA0)(0x68) != 0) {\n v0 = 1;\n *(s16 *)(s0 + 0x84) = v0;\n }\n }\n\n x = *(s16 *)(s0 + 0xF2);\n if (x != 0) {\n y = x - 2;\n *(s16 *)(s0 + 0xF2) = y;\n if (y < 0) {\n *(s16 *)(s0 + 0xF2) = 0;\n }\n v0 = *(s16 *)(s0 + 0xF2);\n if (v0 != 0) {\n goto ret0;\n }\n }\n\n v0 = *(s16 *)(s0 + 0x84);\n if (v0 != 0) {\n v0 = 1;\n goto ret;\n }\nret0:\n v0 = 0;\nret:\n return v0;\n}\n"} +{"ts": "2026-09-11 13:17:01", "label": "s105_f4", "rung": "E", "calib": {"head": "0e8ec9df7", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_011/ov_SC04_011_jr_8017D494.c", "fn": "func_80182BBC", "addr": 2149067708, "aliases": null, "header": false, "includers": 0, "nhash_before": "0d3bea7f3411dff109d645d2477892d6fe88fdbc", "nhash_after": "688f0bd3ea1cf1fa7f9cb776207025d3d6d7600c", "source": ".run/P36/agents/ov_SC04_011__func_80182BBC/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.388, "objects": ["build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o"], "before_text": "void func_80182BBC(u8 *self) {\n int state = *(u16 *)(self + 0x34);\n s32 pad[2];\n (void)pad;\n\n if (state < 0) {\n goto L_end;\n }\n if (state < 2) {\n goto L_BF8;\n }\n if (state == 2) {\n goto L_C44;\n }\n goto L_end;\n\nL_BF8:\n if (((s32 (*)(int, int))func_801833D4)((int)self, 0) == 0) {\n goto L_D14;\n } else {\n register u16 f __asm__(\"$3\") = *(u16 *)(self + 0xF4); // !FAKE: pin $3 \u2014 NEEDED DIFFERS (P36 rung B t3_tus1)\n register s32 off __asm__(\"$5\"); // !FAKE: pin $5 \u2014 NEEDED DIFFERS (P36 rung B t3_tus1)\n u8 *addr;\n f = f + 1;\n off = (s16)f * 8;\n addr = D_80194538 + off;\n *(u16 *)(self + 0xF4) = f;\n func_80183564((s32)self, (s16 *)addr);\n *(u16 *)(self + 0x34) = *(u16 *)(self + 0x34) + 1;\n goto L_end;\n }\n\nL_C44:\n if (((s32 (*)(int, int))func_801833D4)((int)self, 0) == 0) {\n goto L_D14;\n } else {\n s32 obj;\n s32 vp;\n\n obj = aFC4C[D_801EFD20];\n if (!(D_801EFD40 & 0x400)) {\n D_801EFD18 = func_80188E00(obj, D_801944D0);\n }\n vp = *(s32 *)(obj + 0x20);\n *(s16 *)(obj + 6) = 0x500;\n *(s16 *)(obj + 0xA) = -0xD88;\n *(s16 *)(obj + 0xE) = 0x1980;\n *(s16 *)(vp + 0x12) = 0;\n vp = *(s32 *)(obj + 0x20);\n *(s16 *)(vp + 0x10) = 0x380;\n *(s16 *)(self + 0xFE) = 0x380;\n func_80186710();\n func_80183BD0(self);\n D_801EFD40 = D_801EFD40 & 0xFFF7;\n func_80183564((s32)self, (s16 *)D_801944D0);\n func_80186BD8();\n func_8012AD44((s32 *)self, 7);\n goto L_end;\n }\n\nL_D14:\n func_80183A28(self);\n\nL_end:\n return;\n}\n", "after_text": "void func_80182BBC(u8 *self) {\n int state = *(u16 *)(self + 0x34);\n s32 pad[2];\n (void)pad;\n\n if (state < 0) {\n goto L_end;\n }\n if (state < 2) {\n goto L_BF8;\n }\n if (state == 2) {\n goto L_C44;\n }\n goto L_end;\n\nL_BF8:\n if (((s32 (*)(int, int))func_801833D4)((int)self, 0) == 0) {\n goto L_D14;\n } else {\n s32 f = *(u16 *)(self + 0xF4);\n s32 off;\n u8 *addr;\n f = f + 1;\n off = (s16)f * 8;\n addr = D_80194538 + off;\n *(u16 *)(self + 0xF4) = f;\n func_80183564((s32)self, (s16 *)addr);\n *(u16 *)(self + 0x34) = *(u16 *)(self + 0x34) + 1;\n goto L_end;\n }\n\nL_C44:\n if (((s32 (*)(int, int))func_801833D4)((int)self, 0) == 0) {\n goto L_D14;\n } else {\n s32 obj;\n s32 vp;\n\n obj = aFC4C[D_801EFD20];\n if (!(D_801EFD40 & 0x400)) {\n D_801EFD18 = func_80188E00(obj, D_801944D0);\n }\n vp = *(s32 *)(obj + 0x20);\n *(s16 *)(obj + 6) = 0x500;\n *(s16 *)(obj + 0xA) = -0xD88;\n *(s16 *)(obj + 0xE) = 0x1980;\n *(s16 *)(vp + 0x12) = 0;\n vp = *(s32 *)(obj + 0x20);\n *(s16 *)(vp + 0x10) = 0x380;\n *(s16 *)(self + 0xFE) = 0x380;\n func_80186710();\n func_80183BD0(self);\n D_801EFD40 = D_801EFD40 & 0xFFF7;\n func_80183564((s32)self, (s16 *)D_801944D0);\n func_80186BD8();\n func_8012AD44((s32 *)self, 7);\n goto L_end;\n }\n\nL_D14:\n func_80183A28(self);\n\nL_end:\n return;\n}\n"} diff --git a/src/ov_SC04_011/ov_SC04_011_jr_8017D494.c b/src/ov_SC04_011/ov_SC04_011_jr_8017D494.c index f8e75cdf86..30fb6800c9 100644 --- a/src/ov_SC04_011/ov_SC04_011_jr_8017D494.c +++ b/src/ov_SC04_011/ov_SC04_011_jr_8017D494.c @@ -6354,8 +6354,8 @@ L_BF8: if (((s32 (*)(int, int))func_801833D4)((int)self, 0) == 0) { goto L_D14; } else { - register u16 f __asm__("$3") = *(u16 *)(self + 0xF4); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B t3_tus1) - register s32 off __asm__("$5"); // !FAKE: pin $5 — NEEDED DIFFERS (P36 rung B t3_tus1) + s32 f = *(u16 *)(self + 0xF4); + s32 off; u8 *addr; f = f + 1; off = (s16)f * 8;