diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index d0a2ba5e4..c47f9d38b 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,7 +1,7 @@ { - "head": "8030518bc", + "head": "d5111014d", "stamp": "15956e4a96c4", - "generated": "2026-09-10 21:21", + "generated": "2026-09-10 21:22", "aliases": [ "main", "ov_SC03_014", @@ -21,207 +21,207 @@ "main": { "objects": 85, "identical": 85, - "seconds": 8.824000000000003, - "mean_s": 0.104 + "seconds": 11.025000000000007, + "mean_s": 0.13 }, "ov_SC03_014": { "objects": 32, "identical": 32, - "seconds": 6.2299999999999995, - "mean_s": 0.195 + "seconds": 6.949999999999999, + "mean_s": 0.217 }, "ov_SC03_015": { "objects": 32, "identical": 32, - "seconds": 5.5, - "mean_s": 0.172 + "seconds": 6.853999999999999, + "mean_s": 0.214 }, "ov_SC04_011": { "objects": 28, "identical": 28, - "seconds": 5.965000000000001, - "mean_s": 0.213 + "seconds": 6.151999999999999, + "mean_s": 0.22 } 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"aliases": null, "header": false, "includers": 0, "nhash_before": "608d12388b66b61aecd843f587d51ec86594d07b", "nhash_after": "f300e1ba88cd17117db287e15306fb81e90de536", "source": "propagate:src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c:func_8017B614", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.247, "objects": ["build/src/ov_SC01_077/ov_SC01_077_jr_8017AE2C.o"], "before_text": "s32 func_8017B614(s32 param_1, s32 param_2)\n{\n extern void func_8012F214(s32 a0, s32 a1, s32 a2);\n extern void func_80129CF8(void);\n extern s32 func_8017BE60(void *a0);\n extern u8 D_8018A45C[];\n extern s16 D_801DA794;\n extern s16 D_801DA796;\n extern s16 D_801DA798;\n extern s16 D_801DA78C;\n extern s16 D_801DA78E;\n extern s16 D_801DA790;\n extern u8 D_8012694C;\n extern s32 D_80126998;\n extern s32 D_80126984;\n extern s32 D_80126988;\n extern s32 D_8012698C;\n\n u8 buf[16];\n\n if (((u32)param_2) >= 0xB) {\n register u8 *src __asm__(\"$16\"); // !FAKE: pin $16 \u2014 NEEDED DIFFERS (P36 rung B tus7)\n __asm__ __volatile__(\"\" : \"=r\"(src) : \"0\"((u8 *)((u32)param_2))); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus7)\n *(Blk8_8017B614 *)&buf[0] = *(Blk8_8017B614 *)src;\n *(Blk8_8017B614 *)&buf[8] = *(Blk8_8017B614 *)(src + 8);\n } else {\n s32 a1addr = (s32)&D_8018A45C[((u32)param_2) * 0x10];\n s32 a2addr = (s32)&D_8018A45C[((u32)param_2) * 0x10 + 8];\n func_8012F214(param_1, a1addr, (s32)&buf[0]);\n func_8012F214(param_1, a2addr, (s32)&buf[8]);\n }\n {\n s16 *p794 = &D_801DA794;\n s16 *p78C = &D_801DA78C;\n *(Blk8_8017B614 *)p794 = *(Blk8_8017B614 *)&buf[0];\n *(Blk8_8017B614 *)p78C = *(Blk8_8017B614 *)&buf[8];\n func_8012A018((s32)func_8017BE60, 0);\n {\n s32 v794, v796, v798, v78C, v78E, v790;\n D_8012694C = 0;\n v794 = *p794;\n v796 = D_801DA796;\n v798 = D_801DA798;\n v78C = *p78C;\n v78E = D_801DA78E;\n v790 = D_801DA790;\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus7)\n D_801DAAB8 = 1;\n D_801DA71C = 0x1E;\n D_80126990 = v794;\n D_80126994 = v796;\n D_80126998 = v798;\n D_80126984 = v78C;\n D_80126988 = v78E;\n D_8012698C = v790;\n }\n func_80129CF8();\n }\n}\n", "after_text": "s32 func_8017B614(s32 param_1, s32 param_2)\n{\n extern s32 D_80126990;\n extern s32 D_80126994;\n extern s16 D_801DA71C;\n extern s16 D_801DAAB8;\n extern void func_8012F214(s32 a0, s32 a1, s32 a2);\n extern void func_80129CF8(void);\n extern s32 func_8017BE60(void *a0);\n extern u8 D_8018A45C[];\n extern s16 D_801DA794;\n extern s16 D_801DA796;\n extern s16 D_801DA798;\n extern s16 D_801DA78C;\n extern s16 D_801DA78E;\n extern s16 D_801DA790;\n extern u8 D_8012694C[];\n extern s32 D_80126998;\n extern s32 D_80126984;\n extern s32 D_80126988;\n extern s32 D_8012698C;\n\n u8 buf[16];\n u8 *src;\n\n if (((u32)param_2) >= 0xB) {\n src = (u8 *)((u32)param_2);\n *(Blk8_8017B614 *)&buf[0] = *(Blk8_8017B614 *)src;\n *(Blk8_8017B614 *)&buf[8] = *(Blk8_8017B614 *)(src + 8);\n } else {\n s32 a2addr;\n\n src = &D_8018A45C[((u32)param_2) * 0x10];\n a2addr = (s32)&D_8018A45C[((u32)param_2) * 0x10 + 8];\n func_8012F214(param_1, (s32)src, (s32)&buf[0]);\n func_8012F214(param_1, a2addr, (s32)&buf[8]);\n }\n *(Blk8_8017B614 *)&D_801DA794 = *(Blk8_8017B614 *)&buf[0];\n *(Blk8_8017B614 *)&D_801DA78C = *(Blk8_8017B614 *)&buf[8];\n func_8012A018((s32)func_8017BE60, 0);\n D_8012694C[0] = 0;\n D_801DAAB8 = 1;\n D_801DA71C = 0x1E;\n D_80126990 = ((SV4_8017B368 *)&D_801DA794)->a;\n D_80126994 = D_801DA796;\n D_80126998 = D_801DA798;\n D_80126984 = ((SV4_8017B368 *)&D_801DA78C)->a;\n D_80126988 = D_801DA78E;\n D_8012698C = D_801DA790;\n func_80129CF8();\n}\n"} {"ts": "2026-09-10 21:22:42", "label": "s104_d6", "rung": "E", "calib": {"head": "8030518bc", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC07_006/ov_SC07_006_jr_8017AE2C.c", "fn": "func_8017B614", "addr": 2149037588, "aliases": null, "header": false, "includers": 0, "nhash_before": "8e49c9e454cfad4ff7675aa82eda06f1db057406", "nhash_after": "f300e1ba88cd17117db287e15306fb81e90de536", "source": "propagate:src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c:func_8017B614", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.097, "objects": ["build/src/ov_SC07_006/ov_SC07_006_jr_8017AE2C.o"], "before_text": "s32 func_8017B614(s32 param_1, s32 param_2)\n{\n\n extern s32 D_80126990;\n extern s32 D_80126994;\n extern s16 D_801F5FF4;\n extern s16 D_801F62F8;\n extern void func_8012F214(s32 a0, s32 a1, s32 a2);\n extern void func_80129CF8(void);\n extern void func_8017BE60(void*);\n extern u8 D_8018DD4C[];\n extern s16 D_801F606C;\n extern s16 D_801F606E;\n extern s16 D_801F6070;\n extern s16 D_801F6064;\n extern s16 D_801F6066;\n extern s16 D_801F6068;\n extern u8 D_8012694C;\n extern s32 D_80126998;\n extern s32 D_80126984;\n extern s32 D_80126988;\n extern s32 D_8012698C;\n\n u8 buf[16];\n\n if (((u32)param_2) >= 0xB) {\n register u8 *src __asm__(\"$16\"); // !FAKE: pin $16 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n __asm__ __volatile__(\"\" : \"=r\"(src) : \"0\"((u8 *)((u32)param_2))); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus8)\n *(Blk8_8017B614 *)&buf[0] = *(Blk8_8017B614 *)src;\n *(Blk8_8017B614 *)&buf[8] = *(Blk8_8017B614 *)(src + 8);\n } else {\n s32 a1addr = (s32)&D_8018DD4C[((u32)param_2) * 0x10];\n s32 a2addr = (s32)&D_8018DD4C[((u32)param_2) * 0x10 + 8];\n func_8012F214(param_1, a1addr, (s32)&buf[0]);\n func_8012F214(param_1, a2addr, (s32)&buf[8]);\n }\n {\n s16 *p794 = &D_801F606C;\n s16 *p78C = &D_801F6064;\n *(Blk8_8017B614 *)p794 = *(Blk8_8017B614 *)&buf[0];\n *(Blk8_8017B614 *)p78C = *(Blk8_8017B614 *)&buf[8];\n func_8012A018((s32)func_8017BE60, 0);\n {\n s32 v794, v796, v798, v78C, v78E, v790;\n D_8012694C = 0;\n v794 = *p794;\n v796 = D_801F606E;\n v798 = D_801F6070;\n v78C = *p78C;\n v78E = D_801F6066;\n v790 = D_801F6068;\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus8)\n D_801F62F8 = 1;\n D_801F5FF4 = 0x1E;\n D_80126990 = v794;\n D_80126994 = v796;\n D_80126998 = v798;\n D_80126984 = v78C;\n D_80126988 = v78E;\n D_8012698C = v790;\n }\n func_80129CF8();\n }\n}\n", "after_text": "s32 func_8017B614(s32 param_1, s32 param_2)\n{\n extern s32 D_80126990;\n extern s32 D_80126994;\n extern s16 D_801F5FF4;\n extern s16 D_801F62F8;\n extern void func_8012F214(s32 a0, s32 a1, s32 a2);\n extern void func_80129CF8(void);\n extern s32 func_8017BE60(void *a0);\n extern u8 D_8018DD4C[];\n extern s16 D_801F606C;\n extern s16 D_801F606E;\n extern s16 D_801F6070;\n extern s16 D_801F6064;\n extern s16 D_801F6066;\n extern s16 D_801F6068;\n extern u8 D_8012694C[];\n extern s32 D_80126998;\n extern s32 D_80126984;\n extern s32 D_80126988;\n extern s32 D_8012698C;\n\n u8 buf[16];\n u8 *src;\n\n if (((u32)param_2) >= 0xB) {\n src = (u8 *)((u32)param_2);\n *(Blk8_8017B614 *)&buf[0] = *(Blk8_8017B614 *)src;\n *(Blk8_8017B614 *)&buf[8] = *(Blk8_8017B614 *)(src + 8);\n } else {\n s32 a2addr;\n\n src = &D_8018DD4C[((u32)param_2) * 0x10];\n a2addr = (s32)&D_8018DD4C[((u32)param_2) * 0x10 + 8];\n func_8012F214(param_1, (s32)src, (s32)&buf[0]);\n func_8012F214(param_1, a2addr, (s32)&buf[8]);\n }\n *(Blk8_8017B614 *)&D_801F606C = *(Blk8_8017B614 *)&buf[0];\n *(Blk8_8017B614 *)&D_801F6064 = *(Blk8_8017B614 *)&buf[8];\n func_8012A018((s32)func_8017BE60, 0);\n D_8012694C[0] = 0;\n D_801F62F8 = 1;\n D_801F5FF4 = 0x1E;\n D_80126990 = ((SV4_8017B368 *)&D_801F606C)->a;\n D_80126994 = D_801F606E;\n D_80126998 = D_801F6070;\n D_80126984 = ((SV4_8017B368 *)&D_801F6064)->a;\n D_80126988 = D_801F6066;\n D_8012698C = D_801F6068;\n func_80129CF8();\n}\n"} {"ts": "2026-09-10 21:22:43", "label": "s104_d6", "rung": "E", "calib": {"head": "8030518bc", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC07_007/ov_SC07_007_jr_8017AE2C.c", "fn": "func_8017B614", "addr": 2149037588, "aliases": null, "header": false, "includers": 0, "nhash_before": "8e49c9e454cfad4ff7675aa82eda06f1db057406", "nhash_after": "f300e1ba88cd17117db287e15306fb81e90de536", "source": "propagate:src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c:func_8017B614", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.099, "objects": ["build/src/ov_SC07_007/ov_SC07_007_jr_8017AE2C.o"], "before_text": "s32 func_8017B614(s32 param_1, s32 param_2)\n{\n\n extern s32 D_80126990;\n extern s32 D_80126994;\n extern s16 D_801C775C;\n extern s16 D_801C7AC0;\n extern void func_8012F214(s32 a0, s32 a1, s32 a2);\n extern void func_80129CF8(void);\n extern void func_8017BE60(void*);\n extern u8 D_80186870[];\n extern s16 D_801C77D4;\n extern s16 D_801C77D6;\n extern s16 D_801C77D8;\n extern s16 D_801C77CC;\n extern s16 D_801C77CE;\n extern s16 D_801C77D0;\n extern u8 D_8012694C;\n extern s32 D_80126998;\n extern s32 D_80126984;\n extern s32 D_80126988;\n extern s32 D_8012698C;\n\n u8 buf[16];\n\n if (((u32)param_2) >= 0xB) {\n register u8 *src __asm__(\"$16\"); // !FAKE: pin $16 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n __asm__ __volatile__(\"\" : \"=r\"(src) : \"0\"((u8 *)((u32)param_2))); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus8)\n *(Blk8_8017B614 *)&buf[0] = *(Blk8_8017B614 *)src;\n *(Blk8_8017B614 *)&buf[8] = *(Blk8_8017B614 *)(src + 8);\n } else {\n s32 a1addr = (s32)&D_80186870[((u32)param_2) * 0x10];\n s32 a2addr = (s32)&D_80186870[((u32)param_2) * 0x10 + 8];\n func_8012F214(param_1, a1addr, (s32)&buf[0]);\n func_8012F214(param_1, a2addr, (s32)&buf[8]);\n }\n {\n s16 *p794 = &D_801C77D4;\n s16 *p78C = &D_801C77CC;\n *(Blk8_8017B614 *)p794 = *(Blk8_8017B614 *)&buf[0];\n *(Blk8_8017B614 *)p78C = *(Blk8_8017B614 *)&buf[8];\n func_8012A018((s32)func_8017BE60, 0);\n {\n s32 v794, v796, v798, v78C, v78E, v790;\n D_8012694C = 0;\n v794 = *p794;\n v796 = D_801C77D6;\n v798 = D_801C77D8;\n v78C = *p78C;\n v78E = D_801C77CE;\n v790 = D_801C77D0;\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus8)\n D_801C7AC0 = 1;\n D_801C775C = 0x1E;\n D_80126990 = v794;\n D_80126994 = v796;\n D_80126998 = v798;\n D_80126984 = v78C;\n D_80126988 = v78E;\n D_8012698C = v790;\n }\n func_80129CF8();\n }\n}\n", "after_text": "s32 func_8017B614(s32 param_1, s32 param_2)\n{\n extern s32 D_80126990;\n extern s32 D_80126994;\n extern s16 D_801C775C;\n extern s16 D_801C7AC0;\n extern void func_8012F214(s32 a0, s32 a1, s32 a2);\n extern void func_80129CF8(void);\n extern s32 func_8017BE60(void *a0);\n extern u8 D_80186870[];\n extern s16 D_801C77D4;\n extern s16 D_801C77D6;\n extern s16 D_801C77D8;\n extern s16 D_801C77CC;\n extern s16 D_801C77CE;\n extern s16 D_801C77D0;\n extern u8 D_8012694C[];\n extern s32 D_80126998;\n extern s32 D_80126984;\n extern s32 D_80126988;\n extern s32 D_8012698C;\n\n u8 buf[16];\n u8 *src;\n\n if (((u32)param_2) >= 0xB) {\n src = (u8 *)((u32)param_2);\n *(Blk8_8017B614 *)&buf[0] = *(Blk8_8017B614 *)src;\n *(Blk8_8017B614 *)&buf[8] = *(Blk8_8017B614 *)(src + 8);\n } else {\n s32 a2addr;\n\n src = &D_80186870[((u32)param_2) * 0x10];\n a2addr = (s32)&D_80186870[((u32)param_2) * 0x10 + 8];\n func_8012F214(param_1, (s32)src, (s32)&buf[0]);\n func_8012F214(param_1, a2addr, (s32)&buf[8]);\n }\n *(Blk8_8017B614 *)&D_801C77D4 = *(Blk8_8017B614 *)&buf[0];\n *(Blk8_8017B614 *)&D_801C77CC = *(Blk8_8017B614 *)&buf[8];\n func_8012A018((s32)func_8017BE60, 0);\n D_8012694C[0] = 0;\n D_801C7AC0 = 1;\n D_801C775C = 0x1E;\n D_80126990 = ((SV4_8017B368 *)&D_801C77D4)->a;\n D_80126994 = D_801C77D6;\n D_80126998 = D_801C77D8;\n D_80126984 = ((SV4_8017B368 *)&D_801C77CC)->a;\n D_80126988 = D_801C77CE;\n D_8012698C = D_801C77D0;\n func_80129CF8();\n}\n"} +{"ts": "2026-09-10 21:23:19", "label": "s104_d8", "rung": "E", "calib": {"head": "d5111014d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_091/ov_SC03_091_jr_8018326C.c", "fn": "func_80186440", "addr": 2149082176, "aliases": null, "header": false, "includers": 0, "nhash_before": "dfec119e98bb9fd8eed5a82b7f69d126758ff3c2", "nhash_after": "cad09b6ffe4970541700e6e6c499d620d248877e", "source": ".run/P36/agents/ov_SC03_091__func_80186440/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.268, "objects": ["build/src/ov_SC03_091/ov_SC03_091_jr_8018326C.o"], "before_text": "void func_80186440(s32 param_1) {\n\n s32 unused[2]; /* dead 8-byte local \u2014 frame padding (cookbook idiom 6) */\n s32 obj;\n s16 raw;\n s32 r;\n s32 sgn;\n s32 v;\n s32 q;\n s32 w;\n /* The `register ... __asm__(\"$4\")` pin on the tail's +2-field counter is\n * load-bearing (matching-cookbook idiom 9 / L-lever family): unpinned, gcc\n * puts the 0x50000000 OR-mask constant in $a0 and the field value in $v1\n * (register-swapped vs. the target) and schedules the field's `lhu` right\n * before the `or` instead of hoisting it ahead of the 0xFC/FD/FE `sb`\n * stores. Pinning $4/$a0 to this value AND folding the `+1` into the same\n * statement as the load (`cnt = *(u16*)(param_1+2) + 1;`, store separate)\n * reproduces both the register choice and the exact schedule position. */\n register s32 cnt __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n obj = ((s32 (*)(void))func_8012C1B8)();\n if (obj == 0) {\n func_8012CAE4((void *)param_1);\n return;\n }\n *(s32 *)(param_1 + 0x20) = obj;\n func_8001C214(obj, 0);\n\n raw = rand();\n r = raw;\n *(u16 *)(obj + 0x2C) = *(u16 *)(obj + 0x2C) | 0x10;\n v = r % 384 + 0x400;\n *(s16 *)(obj + 0x1C) = v;\n *(s16 *)(obj + 0x1A) = v;\n *(s16 *)(obj + 0x18) = v;\n sgn = -1;\n if (raw & 1) {\n sgn = 1;\n }\n *(s16 *)(obj + 0x10) = sgn * (r % 128) - 0x300;\n *(s16 *)(obj + 0x12) = r % 4096;\n *(u16 *)(obj + 0x14) = 0;\n\n *(u16 *)(param_1 + 0xA) = *(u16 *)(param_1 + 0xA) - 0x19;\n func_8012B2CC(param_1);\n func_8012B23C((void *)param_1);\n func_8012B178(param_1, -0xC0000 - ((r % 8) << 16));\n\n *(s32 *)(param_1 + 0x1C) = 0x5A;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xDC) = w;\n *(s16 *)(param_1 + 0xDE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xE4) = w;\n *(s16 *)(param_1 + 0xE6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE8) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xEC) = w;\n *(s16 *)(param_1 + 0xEE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF4) = w;\n *(s16 *)(param_1 + 0xF6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF8) = w;\n\n cnt = *(u16 *)(param_1 + 2) + 1;\n *(u8 *)(param_1 + 0xFC) = 0x80;\n *(u8 *)(param_1 + 0xFD) = 0x80;\n *(u8 *)(param_1 + 0xFE) = 0x80;\n *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000;\n *(u16 *)(param_1 + 2) = cnt;\n}\n", "after_text": "void func_80186440(s32 param_1) {\n\n s32 unused[2]; /* dead 8-byte local \u2014 frame padding (cookbook idiom 6) */\n s32 obj;\n s16 raw;\n s32 r;\n s32 sgn;\n s32 v;\n s32 q;\n s32 w;\n\n obj = ((s32 (*)(void))func_8012C1B8)();\n if (obj == 0) {\n func_8012CAE4((void *)param_1);\n return;\n }\n *(s32 *)(param_1 + 0x20) = obj;\n func_8001C214(obj, 0);\n\n raw = rand();\n r = raw;\n *(u16 *)(obj + 0x2C) = *(u16 *)(obj + 0x2C) | 0x10;\n v = r % 384 + 0x400;\n *(s16 *)(obj + 0x1C) = v;\n *(s16 *)(obj + 0x1A) = v;\n *(s16 *)(obj + 0x18) = v;\n sgn = -1;\n if (raw & 1) {\n sgn = 1;\n }\n *(s16 *)(obj + 0x10) = sgn * (r % 128) - 0x300;\n *(s16 *)(obj + 0x12) = r % 4096;\n *(u16 *)(obj + 0x14) = 0;\n\n *(u16 *)(param_1 + 0xA) = *(u16 *)(param_1 + 0xA) - 0x19;\n func_8012B2CC(param_1);\n func_8012B23C((void *)param_1);\n func_8012B178(param_1, -0xC0000 - ((r % 8) << 16));\n\n *(s32 *)(param_1 + 0x1C) = 0x5A;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xDC) = w;\n *(s16 *)(param_1 + 0xDE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xE4) = w;\n *(s16 *)(param_1 + 0xE6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE8) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xEC) = w;\n *(s16 *)(param_1 + 0xEE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF4) = w;\n *(s16 *)(param_1 + 0xF6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF8) = w;\n\n *(u8 *)(param_1 + 0xFC) = 0x80;\n *(u8 *)(param_1 + 0xFD) = 0x80;\n *(u8 *)(param_1 + 0xFE) = 0x80;\n *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000;\n /* A u16 `++` (not `+= 1`): expand_increment adds in HImode through a\n * widened SImode add (expr.c:8662), combine rewrites the HImode copy as a\n * SUBREG destination (combine.c:4376-4402), and sched1's birthing_insn_p\n * (sched.c:2477-2478) no longer boosts the addiu next to the store, so the\n * lhu is scheduled ahead of the 0xFC-0xFE byte stores and takes $a0\n * (P36 S104 d8; formerly a `register __asm__(\"$4\")` pin on a s32 local). */\n (*(u16 *)(param_1 + 2))++;\n}\n"} +{"ts": "2026-09-10 21:23:38", "label": "s104_d8", "rung": "E", "calib": {"head": "d5111014d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c", "fn": "func_80185598", "addr": 2149078424, "aliases": null, "header": false, "includers": 0, "nhash_before": "dfec119e98bb9fd8eed5a82b7f69d126758ff3c2", "nhash_after": "cad09b6ffe4970541700e6e6c499d620d248877e", "source": "propagate:src/ov_SC03_091/ov_SC03_091_jr_8018326C.c:func_80186440", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.482, "objects": ["build/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.o"], "before_text": "void func_80185598(s32 param_1) {\n\n s32 unused[2]; /* dead 8-byte local \u2014 frame padding (cookbook idiom 6) */\n s32 obj;\n s16 raw;\n s32 r;\n s32 sgn;\n s32 v;\n s32 q;\n s32 w;\n /* The `register ... __asm__(\"$4\")` pin on the tail's +2-field counter is\n * load-bearing (matching-cookbook idiom 9 / L-lever family): unpinned, gcc\n * puts the 0x50000000 OR-mask constant in $a0 and the field value in $v1\n * (register-swapped vs. the target) and schedules the field's `lhu` right\n * before the `or` instead of hoisting it ahead of the 0xFC/FD/FE `sb`\n * stores. Pinning $4/$a0 to this value AND folding the `+1` into the same\n * statement as the load (`cnt = *(u16*)(param_1+2) + 1;`, store separate)\n * reproduces both the register choice and the exact schedule position. */\n register s32 cnt __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n obj = ((s32 (*)(void))func_8012C1B8)();\n if (obj == 0) {\n func_8012CAE4((void *)param_1);\n return;\n }\n *(s32 *)(param_1 + 0x20) = obj;\n func_8001C214(obj, 0);\n\n raw = rand();\n r = raw;\n *(u16 *)(obj + 0x2C) = *(u16 *)(obj + 0x2C) | 0x10;\n v = r % 384 + 0x400;\n *(s16 *)(obj + 0x1C) = v;\n *(s16 *)(obj + 0x1A) = v;\n *(s16 *)(obj + 0x18) = v;\n sgn = -1;\n if (raw & 1) {\n sgn = 1;\n }\n *(s16 *)(obj + 0x10) = sgn * (r % 128) - 0x300;\n *(s16 *)(obj + 0x12) = r % 4096;\n *(u16 *)(obj + 0x14) = 0;\n\n *(u16 *)(param_1 + 0xA) = *(u16 *)(param_1 + 0xA) - 0x19;\n func_8012B2CC(param_1);\n func_8012B23C((void *)param_1);\n func_8012B178(param_1, -0xC0000 - ((r % 8) << 16));\n\n *(s32 *)(param_1 + 0x1C) = 0x5A;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xDC) = w;\n *(s16 *)(param_1 + 0xDE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xE4) = w;\n *(s16 *)(param_1 + 0xE6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE8) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xEC) = w;\n *(s16 *)(param_1 + 0xEE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF4) = w;\n *(s16 *)(param_1 + 0xF6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF8) = w;\n\n cnt = *(u16 *)(param_1 + 2) + 1;\n *(u8 *)(param_1 + 0xFC) = 0x80;\n *(u8 *)(param_1 + 0xFD) = 0x80;\n *(u8 *)(param_1 + 0xFE) = 0x80;\n *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000;\n *(u16 *)(param_1 + 2) = cnt;\n}\n", "after_text": "void func_80185598(s32 param_1) {\n\n s32 unused[2]; /* dead 8-byte local \u2014 frame padding (cookbook idiom 6) */\n s32 obj;\n s16 raw;\n s32 r;\n s32 sgn;\n s32 v;\n s32 q;\n s32 w;\n\n obj = ((s32 (*)(void))func_8012C1B8)();\n if (obj == 0) {\n func_8012CAE4((void *)param_1);\n return;\n }\n *(s32 *)(param_1 + 0x20) = obj;\n func_8001C214(obj, 0);\n\n raw = rand();\n r = raw;\n *(u16 *)(obj + 0x2C) = *(u16 *)(obj + 0x2C) | 0x10;\n v = r % 384 + 0x400;\n *(s16 *)(obj + 0x1C) = v;\n *(s16 *)(obj + 0x1A) = v;\n *(s16 *)(obj + 0x18) = v;\n sgn = -1;\n if (raw & 1) {\n sgn = 1;\n }\n *(s16 *)(obj + 0x10) = sgn * (r % 128) - 0x300;\n *(s16 *)(obj + 0x12) = r % 4096;\n *(u16 *)(obj + 0x14) = 0;\n\n *(u16 *)(param_1 + 0xA) = *(u16 *)(param_1 + 0xA) - 0x19;\n func_8012B2CC(param_1);\n func_8012B23C((void *)param_1);\n func_8012B178(param_1, -0xC0000 - ((r % 8) << 16));\n\n *(s32 *)(param_1 + 0x1C) = 0x5A;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xDC) = w;\n *(s16 *)(param_1 + 0xDE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xE4) = w;\n *(s16 *)(param_1 + 0xE6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE8) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xEC) = w;\n *(s16 *)(param_1 + 0xEE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF4) = w;\n *(s16 *)(param_1 + 0xF6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF8) = w;\n\n *(u8 *)(param_1 + 0xFC) = 0x80;\n *(u8 *)(param_1 + 0xFD) = 0x80;\n *(u8 *)(param_1 + 0xFE) = 0x80;\n *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000;\n /* A u16 `++` (not `+= 1`): expand_increment adds in HImode through a\n * widened SImode add (expr.c:8662), combine rewrites the HImode copy as a\n * SUBREG destination (combine.c:4376-4402), and sched1's birthing_insn_p\n * (sched.c:2477-2478) no longer boosts the addiu next to the store, so the\n * lhu is scheduled ahead of the 0xFC-0xFE byte stores and takes $a0\n * (P36 S104 d8; formerly a `register __asm__(\"$4\")` pin on a s32 local). */\n (*(u16 *)(param_1 + 2))++;\n}\n"} +{"ts": "2026-09-10 21:23:39", "label": "s104_d8", "rung": "E", "calib": {"head": "d5111014d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_104/ov_SC03_104_jr_80182038.c", "fn": "func_8018342C", "addr": 2149069868, "aliases": null, "header": false, "includers": 0, "nhash_before": "dfec119e98bb9fd8eed5a82b7f69d126758ff3c2", "nhash_after": "cad09b6ffe4970541700e6e6c499d620d248877e", "source": "propagate:src/ov_SC03_091/ov_SC03_091_jr_8018326C.c:func_80186440", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.209, "objects": ["build/src/ov_SC03_104/ov_SC03_104_jr_80182038.o"], "before_text": "void func_8018342C(s32 param_1) {\n\n s32 unused[2]; /* dead 8-byte local \u2014 frame padding (cookbook idiom 6) */\n s32 obj;\n s16 raw;\n s32 r;\n s32 sgn;\n s32 v;\n s32 q;\n s32 w;\n /* The `register ... __asm__(\"$4\")` pin on the tail's +2-field counter is\n * load-bearing (matching-cookbook idiom 9 / L-lever family): unpinned, gcc\n * puts the 0x50000000 OR-mask constant in $a0 and the field value in $v1\n * (register-swapped vs. the target) and schedules the field's `lhu` right\n * before the `or` instead of hoisting it ahead of the 0xFC/FD/FE `sb`\n * stores. Pinning $4/$a0 to this value AND folding the `+1` into the same\n * statement as the load (`cnt = *(u16*)(param_1+2) + 1;`, store separate)\n * reproduces both the register choice and the exact schedule position. */\n register s32 cnt __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n obj = ((s32 (*)(void))func_8012C1B8)();\n if (obj == 0) {\n func_8012CAE4((void *)param_1);\n return;\n }\n *(s32 *)(param_1 + 0x20) = obj;\n func_8001C214(obj, 0);\n\n raw = rand();\n r = raw;\n *(u16 *)(obj + 0x2C) = *(u16 *)(obj + 0x2C) | 0x10;\n v = r % 384 + 0x400;\n *(s16 *)(obj + 0x1C) = v;\n *(s16 *)(obj + 0x1A) = v;\n *(s16 *)(obj + 0x18) = v;\n sgn = -1;\n if (raw & 1) {\n sgn = 1;\n }\n *(s16 *)(obj + 0x10) = sgn * (r % 128) - 0x300;\n *(s16 *)(obj + 0x12) = r % 4096;\n *(u16 *)(obj + 0x14) = 0;\n\n *(u16 *)(param_1 + 0xA) = *(u16 *)(param_1 + 0xA) - 0x19;\n func_8012B2CC(param_1);\n func_8012B23C((void *)param_1);\n func_8012B178(param_1, -0xC0000 - ((r % 8) << 16));\n\n *(s32 *)(param_1 + 0x1C) = 0x5A;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xDC) = w;\n *(s16 *)(param_1 + 0xDE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xE4) = w;\n *(s16 *)(param_1 + 0xE6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE8) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xEC) = w;\n *(s16 *)(param_1 + 0xEE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF4) = w;\n *(s16 *)(param_1 + 0xF6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF8) = w;\n\n cnt = *(u16 *)(param_1 + 2) + 1;\n *(u8 *)(param_1 + 0xFC) = 0x80;\n *(u8 *)(param_1 + 0xFD) = 0x80;\n *(u8 *)(param_1 + 0xFE) = 0x80;\n *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000;\n *(u16 *)(param_1 + 2) = cnt;\n}\n", "after_text": "void func_8018342C(s32 param_1) {\n\n s32 unused[2]; /* dead 8-byte local \u2014 frame padding (cookbook idiom 6) */\n s32 obj;\n s16 raw;\n s32 r;\n s32 sgn;\n s32 v;\n s32 q;\n s32 w;\n\n obj = ((s32 (*)(void))func_8012C1B8)();\n if (obj == 0) {\n func_8012CAE4((void *)param_1);\n return;\n }\n *(s32 *)(param_1 + 0x20) = obj;\n func_8001C214(obj, 0);\n\n raw = rand();\n r = raw;\n *(u16 *)(obj + 0x2C) = *(u16 *)(obj + 0x2C) | 0x10;\n v = r % 384 + 0x400;\n *(s16 *)(obj + 0x1C) = v;\n *(s16 *)(obj + 0x1A) = v;\n *(s16 *)(obj + 0x18) = v;\n sgn = -1;\n if (raw & 1) {\n sgn = 1;\n }\n *(s16 *)(obj + 0x10) = sgn * (r % 128) - 0x300;\n *(s16 *)(obj + 0x12) = r % 4096;\n *(u16 *)(obj + 0x14) = 0;\n\n *(u16 *)(param_1 + 0xA) = *(u16 *)(param_1 + 0xA) - 0x19;\n func_8012B2CC(param_1);\n func_8012B23C((void *)param_1);\n func_8012B178(param_1, -0xC0000 - ((r % 8) << 16));\n\n *(s32 *)(param_1 + 0x1C) = 0x5A;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xDC) = w;\n *(s16 *)(param_1 + 0xDE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xE4) = w;\n *(s16 *)(param_1 + 0xE6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE8) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xEC) = w;\n *(s16 *)(param_1 + 0xEE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF4) = w;\n *(s16 *)(param_1 + 0xF6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF8) = w;\n\n *(u8 *)(param_1 + 0xFC) = 0x80;\n *(u8 *)(param_1 + 0xFD) = 0x80;\n *(u8 *)(param_1 + 0xFE) = 0x80;\n *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000;\n /* A u16 `++` (not `+= 1`): expand_increment adds in HImode through a\n * widened SImode add (expr.c:8662), combine rewrites the HImode copy as a\n * SUBREG destination (combine.c:4376-4402), and sched1's birthing_insn_p\n * (sched.c:2477-2478) no longer boosts the addiu next to the store, so the\n * lhu is scheduled ahead of the 0xFC-0xFE byte stores and takes $a0\n * (P36 S104 d8; formerly a `register __asm__(\"$4\")` pin on a s32 local). */\n (*(u16 *)(param_1 + 2))++;\n}\n"} +{"ts": "2026-09-10 21:23:40", "label": "s104_d8", "rung": "E", "calib": {"head": "d5111014d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c", "fn": "func_801858BC", "addr": 2149079228, "aliases": null, "header": false, "includers": 0, "nhash_before": "dfec119e98bb9fd8eed5a82b7f69d126758ff3c2", "nhash_after": "cad09b6ffe4970541700e6e6c499d620d248877e", "source": "propagate:src/ov_SC03_091/ov_SC03_091_jr_8018326C.c:func_80186440", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.409, "objects": ["build/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.o"], "before_text": "void func_801858BC(s32 param_1) {\n\n s32 unused[2]; /* dead 8-byte local \u2014 frame padding (cookbook idiom 6) */\n s32 obj;\n s16 raw;\n s32 r;\n s32 sgn;\n s32 v;\n s32 q;\n s32 w;\n /* The `register ... __asm__(\"$4\")` pin on the tail's +2-field counter is\n * load-bearing (matching-cookbook idiom 9 / L-lever family): unpinned, gcc\n * puts the 0x50000000 OR-mask constant in $a0 and the field value in $v1\n * (register-swapped vs. the target) and schedules the field's `lhu` right\n * before the `or` instead of hoisting it ahead of the 0xFC/FD/FE `sb`\n * stores. Pinning $4/$a0 to this value AND folding the `+1` into the same\n * statement as the load (`cnt = *(u16*)(param_1+2) + 1;`, store separate)\n * reproduces both the register choice and the exact schedule position. */\n register s32 cnt __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n\n obj = ((s32 (*)(void))func_8012C1B8)();\n if (obj == 0) {\n func_8012CAE4((void *)param_1);\n return;\n }\n *(s32 *)(param_1 + 0x20) = obj;\n func_8001C214(obj, 0);\n\n raw = rand();\n r = raw;\n *(u16 *)(obj + 0x2C) = *(u16 *)(obj + 0x2C) | 0x10;\n v = r % 384 + 0x400;\n *(s16 *)(obj + 0x1C) = v;\n *(s16 *)(obj + 0x1A) = v;\n *(s16 *)(obj + 0x18) = v;\n sgn = -1;\n if (raw & 1) {\n sgn = 1;\n }\n *(s16 *)(obj + 0x10) = sgn * (r % 128) - 0x300;\n *(s16 *)(obj + 0x12) = r % 4096;\n *(u16 *)(obj + 0x14) = 0;\n\n *(u16 *)(param_1 + 0xA) = *(u16 *)(param_1 + 0xA) - 0x19;\n func_8012B2CC(param_1);\n func_8012B23C((void *)param_1);\n func_8012B178(param_1, -0xC0000 - ((r % 8) << 16));\n\n *(s32 *)(param_1 + 0x1C) = 0x5A;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xDC) = w;\n *(s16 *)(param_1 + 0xDE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xE4) = w;\n *(s16 *)(param_1 + 0xE6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE8) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xEC) = w;\n *(s16 *)(param_1 + 0xEE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF4) = w;\n *(s16 *)(param_1 + 0xF6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF8) = w;\n\n cnt = *(u16 *)(param_1 + 2) + 1;\n *(u8 *)(param_1 + 0xFC) = 0x80;\n *(u8 *)(param_1 + 0xFD) = 0x80;\n *(u8 *)(param_1 + 0xFE) = 0x80;\n *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000;\n *(u16 *)(param_1 + 2) = cnt;\n}\n", "after_text": "void func_801858BC(s32 param_1) {\n\n s32 unused[2]; /* dead 8-byte local \u2014 frame padding (cookbook idiom 6) */\n s32 obj;\n s16 raw;\n s32 r;\n s32 sgn;\n s32 v;\n s32 q;\n s32 w;\n\n obj = ((s32 (*)(void))func_8012C1B8)();\n if (obj == 0) {\n func_8012CAE4((void *)param_1);\n return;\n }\n *(s32 *)(param_1 + 0x20) = obj;\n func_8001C214(obj, 0);\n\n raw = rand();\n r = raw;\n *(u16 *)(obj + 0x2C) = *(u16 *)(obj + 0x2C) | 0x10;\n v = r % 384 + 0x400;\n *(s16 *)(obj + 0x1C) = v;\n *(s16 *)(obj + 0x1A) = v;\n *(s16 *)(obj + 0x18) = v;\n sgn = -1;\n if (raw & 1) {\n sgn = 1;\n }\n *(s16 *)(obj + 0x10) = sgn * (r % 128) - 0x300;\n *(s16 *)(obj + 0x12) = r % 4096;\n *(u16 *)(obj + 0x14) = 0;\n\n *(u16 *)(param_1 + 0xA) = *(u16 *)(param_1 + 0xA) - 0x19;\n func_8012B2CC(param_1);\n func_8012B23C((void *)param_1);\n func_8012B178(param_1, -0xC0000 - ((r % 8) << 16));\n\n *(s32 *)(param_1 + 0x1C) = 0x5A;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xDC) = w;\n *(s16 *)(param_1 + 0xDE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xE4) = w;\n *(s16 *)(param_1 + 0xE6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xE8) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q - 0x10;\n } else {\n w = q - 0x10;\n }\n *(s16 *)(param_1 + 0xEC) = w;\n *(s16 *)(param_1 + 0xEE) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF0) = w;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF4) = w;\n *(s16 *)(param_1 + 0xF6) = 0;\n\n q = rand() % 8;\n if ((rand() & 1) == 0) {\n w = -q + 0x10;\n } else {\n w = q + 0x10;\n }\n *(s16 *)(param_1 + 0xF8) = w;\n\n *(u8 *)(param_1 + 0xFC) = 0x80;\n *(u8 *)(param_1 + 0xFD) = 0x80;\n *(u8 *)(param_1 + 0xFE) = 0x80;\n *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000;\n /* A u16 `++` (not `+= 1`): expand_increment adds in HImode through a\n * widened SImode add (expr.c:8662), combine rewrites the HImode copy as a\n * SUBREG destination (combine.c:4376-4402), and sched1's birthing_insn_p\n * (sched.c:2477-2478) no longer boosts the addiu next to the store, so the\n * lhu is scheduled ahead of the 0xFC-0xFE byte stores and takes $a0\n * (P36 S104 d8; formerly a `register __asm__(\"$4\")` pin on a s32 local). */\n (*(u16 *)(param_1 + 2))++;\n}\n"} diff --git a/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c b/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c index 372877f91..734b2d96d 100644 --- a/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c +++ b/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c @@ -6566,15 +6566,6 @@ void func_801858BC(s32 param_1) { s32 v; s32 q; s32 w; - /* The `register ... __asm__("$4")` pin on the tail's +2-field counter is - * load-bearing (matching-cookbook idiom 9 / L-lever family): unpinned, gcc - * puts the 0x50000000 OR-mask constant in $a0 and the field value in $v1 - * (register-swapped vs. the target) and schedules the field's `lhu` right - * before the `or` instead of hoisting it ahead of the 0xFC/FD/FE `sb` - * stores. Pinning $4/$a0 to this value AND folding the `+1` into the same - * statement as the load (`cnt = *(u16*)(param_1+2) + 1;`, store separate) - * reproduces both the register choice and the exact schedule position. */ - register s32 cnt __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) obj = ((s32 (*)(void))func_8012C1B8)(); if (obj == 0) { @@ -6674,12 +6665,17 @@ void func_801858BC(s32 param_1) { } *(s16 *)(param_1 + 0xF8) = w; - cnt = *(u16 *)(param_1 + 2) + 1; *(u8 *)(param_1 + 0xFC) = 0x80; *(u8 *)(param_1 + 0xFD) = 0x80; *(u8 *)(param_1 + 0xFE) = 0x80; *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000; - *(u16 *)(param_1 + 2) = cnt; + /* A u16 `++` (not `+= 1`): expand_increment adds in HImode through a + * widened SImode add (expr.c:8662), combine rewrites the HImode copy as a + * SUBREG destination (combine.c:4376-4402), and sched1's birthing_insn_p + * (sched.c:2477-2478) no longer boosts the addiu next to the store, so the + * lhu is scheduled ahead of the 0xFC-0xFE byte stores and takes $a0 + * (P36 S104 d8; formerly a `register __asm__("$4")` pin on a s32 local). */ + (*(u16 *)(param_1 + 2))++; } diff --git a/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c b/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c index 4ca67baa3..ef885b4e0 100644 --- a/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c +++ b/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c @@ -6530,15 +6530,6 @@ void func_80185598(s32 param_1) { s32 v; s32 q; s32 w; - /* The `register ... __asm__("$4")` pin on the tail's +2-field counter is - * load-bearing (matching-cookbook idiom 9 / L-lever family): unpinned, gcc - * puts the 0x50000000 OR-mask constant in $a0 and the field value in $v1 - * (register-swapped vs. the target) and schedules the field's `lhu` right - * before the `or` instead of hoisting it ahead of the 0xFC/FD/FE `sb` - * stores. Pinning $4/$a0 to this value AND folding the `+1` into the same - * statement as the load (`cnt = *(u16*)(param_1+2) + 1;`, store separate) - * reproduces both the register choice and the exact schedule position. */ - register s32 cnt __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) obj = ((s32 (*)(void))func_8012C1B8)(); if (obj == 0) { @@ -6638,12 +6629,17 @@ void func_80185598(s32 param_1) { } *(s16 *)(param_1 + 0xF8) = w; - cnt = *(u16 *)(param_1 + 2) + 1; *(u8 *)(param_1 + 0xFC) = 0x80; *(u8 *)(param_1 + 0xFD) = 0x80; *(u8 *)(param_1 + 0xFE) = 0x80; *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000; - *(u16 *)(param_1 + 2) = cnt; + /* A u16 `++` (not `+= 1`): expand_increment adds in HImode through a + * widened SImode add (expr.c:8662), combine rewrites the HImode copy as a + * SUBREG destination (combine.c:4376-4402), and sched1's birthing_insn_p + * (sched.c:2477-2478) no longer boosts the addiu next to the store, so the + * lhu is scheduled ahead of the 0xFC-0xFE byte stores and takes $a0 + * (P36 S104 d8; formerly a `register __asm__("$4")` pin on a s32 local). */ + (*(u16 *)(param_1 + 2))++; } diff --git a/src/ov_SC03_091/ov_SC03_091_jr_8018326C.c b/src/ov_SC03_091/ov_SC03_091_jr_8018326C.c index c6f431562..cbdda4594 100644 --- a/src/ov_SC03_091/ov_SC03_091_jr_8018326C.c +++ b/src/ov_SC03_091/ov_SC03_091_jr_8018326C.c @@ -4866,15 +4866,6 @@ void func_80186440(s32 param_1) { s32 v; s32 q; s32 w; - /* The `register ... __asm__("$4")` pin on the tail's +2-field counter is - * load-bearing (matching-cookbook idiom 9 / L-lever family): unpinned, gcc - * puts the 0x50000000 OR-mask constant in $a0 and the field value in $v1 - * (register-swapped vs. the target) and schedules the field's `lhu` right - * before the `or` instead of hoisting it ahead of the 0xFC/FD/FE `sb` - * stores. Pinning $4/$a0 to this value AND folding the `+1` into the same - * statement as the load (`cnt = *(u16*)(param_1+2) + 1;`, store separate) - * reproduces both the register choice and the exact schedule position. */ - register s32 cnt __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) obj = ((s32 (*)(void))func_8012C1B8)(); if (obj == 0) { @@ -4974,12 +4965,17 @@ void func_80186440(s32 param_1) { } *(s16 *)(param_1 + 0xF8) = w; - cnt = *(u16 *)(param_1 + 2) + 1; *(u8 *)(param_1 + 0xFC) = 0x80; *(u8 *)(param_1 + 0xFD) = 0x80; *(u8 *)(param_1 + 0xFE) = 0x80; *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000; - *(u16 *)(param_1 + 2) = cnt; + /* A u16 `++` (not `+= 1`): expand_increment adds in HImode through a + * widened SImode add (expr.c:8662), combine rewrites the HImode copy as a + * SUBREG destination (combine.c:4376-4402), and sched1's birthing_insn_p + * (sched.c:2477-2478) no longer boosts the addiu next to the store, so the + * lhu is scheduled ahead of the 0xFC-0xFE byte stores and takes $a0 + * (P36 S104 d8; formerly a `register __asm__("$4")` pin on a s32 local). */ + (*(u16 *)(param_1 + 2))++; } diff --git a/src/ov_SC03_104/ov_SC03_104_jr_80182038.c b/src/ov_SC03_104/ov_SC03_104_jr_80182038.c index a4b07c69e..b315fa180 100644 --- a/src/ov_SC03_104/ov_SC03_104_jr_80182038.c +++ b/src/ov_SC03_104/ov_SC03_104_jr_80182038.c @@ -3754,15 +3754,6 @@ void func_8018342C(s32 param_1) { s32 v; s32 q; s32 w; - /* The `register ... __asm__("$4")` pin on the tail's +2-field counter is - * load-bearing (matching-cookbook idiom 9 / L-lever family): unpinned, gcc - * puts the 0x50000000 OR-mask constant in $a0 and the field value in $v1 - * (register-swapped vs. the target) and schedules the field's `lhu` right - * before the `or` instead of hoisting it ahead of the 0xFC/FD/FE `sb` - * stores. Pinning $4/$a0 to this value AND folding the `+1` into the same - * statement as the load (`cnt = *(u16*)(param_1+2) + 1;`, store separate) - * reproduces both the register choice and the exact schedule position. */ - register s32 cnt __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9) obj = ((s32 (*)(void))func_8012C1B8)(); if (obj == 0) { @@ -3862,12 +3853,17 @@ void func_8018342C(s32 param_1) { } *(s16 *)(param_1 + 0xF8) = w; - cnt = *(u16 *)(param_1 + 2) + 1; *(u8 *)(param_1 + 0xFC) = 0x80; *(u8 *)(param_1 + 0xFD) = 0x80; *(u8 *)(param_1 + 0xFE) = 0x80; *(u32 *)(param_1 + 0x100) = *(u32 *)(param_1 + 0x100) | 0x50000000; - *(u16 *)(param_1 + 2) = cnt; + /* A u16 `++` (not `+= 1`): expand_increment adds in HImode through a + * widened SImode add (expr.c:8662), combine rewrites the HImode copy as a + * SUBREG destination (combine.c:4376-4402), and sched1's birthing_insn_p + * (sched.c:2477-2478) no longer boosts the addiu next to the store, so the + * lhu is scheduled ahead of the 0xFC-0xFE byte stores and takes $a0 + * (P36 S104 d8; formerly a `register __asm__("$4")` pin on a s32 local). */ + (*(u16 *)(param_1 + 2))++; }