From a2e8a892486ef33130ecc66a9629343b42ec91b0 Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 11 Sep 2026 01:06:00 -0600 Subject: [PATCH] =?UTF-8?q?phase-36:=20S104=20s104=5Fe3=20=E2=80=94=20func?= =?UTF-8?q?=5F80036FB0=20banked=20at=200=20through=20the=20whole-object=20?= =?UTF-8?q?gate=20+=20propagated=20=E2=80=94=20keepalive=20+=20dead=20f64?= =?UTF-8?q?=20=E2=86=92=200:=20the=20TU's=20own=20for-loop=20idiom=20over?= =?UTF-8?q?=20an=20indexed=20array=20(duplicate=5Floop=5Fexit=5Ftest=20jum?= =?UTF-8?q?p.c:2131;=20combine.c:2306=20=E2=86=92=20reload1.c:2331=20slot)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .run/P36/agents/main__func_80036FB0/body.c | 9 + .../agents/main__func_80036FB0/mechanism.md | 66 ++++ .run/P36/agents/main__func_80037144/body.c | 54 +++ .../main__func_80037144/body_minlever.c | 58 +++ .../agents/main__func_80037144/mechanism.md | 71 ++++ .../agents/main__func_800384A8/mechanism.md | 39 ++ .run/P36/delever/calibration.json | 372 +++++++++--------- .run/P36/delever/ledger.jsonl | 1 + src/800_c.c | 22 +- 9 files changed, 488 insertions(+), 204 deletions(-) create mode 100644 .run/P36/agents/main__func_80036FB0/body.c create mode 100644 .run/P36/agents/main__func_80036FB0/mechanism.md create mode 100644 .run/P36/agents/main__func_80037144/body.c create mode 100644 .run/P36/agents/main__func_80037144/body_minlever.c create mode 100644 .run/P36/agents/main__func_80037144/mechanism.md create mode 100644 .run/P36/agents/main__func_800384A8/mechanism.md diff --git a/.run/P36/agents/main__func_80036FB0/body.c b/.run/P36/agents/main__func_80036FB0/body.c new file mode 100644 index 000000000..674dab256 --- /dev/null +++ b/.run/P36/agents/main__func_80036FB0/body.c @@ -0,0 +1,9 @@ +void func_80036FB0(s32 arg0, s32 arg1) { + s32 i; + + for (i = 0; i < D_8006AEE8; i++) { + if ((&D_80078F10)[i] == arg0) { + (&D_80078F10)[i] = arg1; + } + } +} diff --git a/.run/P36/agents/main__func_80036FB0/mechanism.md b/.run/P36/agents/main__func_80036FB0/mechanism.md new file mode 100644 index 000000000..f7ab156a0 --- /dev/null +++ b/.run/P36/agents/main__func_80036FB0/mechanism.md @@ -0,0 +1,66 @@ +# func_80036FB0 (src/800_c.c) — P36 S104 agent e3 — score 4 -> 0, ZERO levers (the keepalive + `f64 hole` removed) + +## (a) The residual +FRAME-only + one delay slot: the target has an 8-byte frame (`addiu sp,sp,-8` / `+8`) that no instruction touches, and +its first `blez` carries `move a2,zero` (i = 0) in the delay slot where the lever-free do-while body has `nop`. Same 20 +other instructions. The tree faked the frame with `f64 hole` + `asm volatile("" :: "m"(hole))` (the asm also stopped +reorg's backward delay-slot scan from pulling the prologue's `addiu sp` into the slot — `stop_search_p`, reorg.c). + +## (b) The pass decisions (all read on the `-d` dumps of the closing body, `scratch/dumps_u1/`) +1. The original is a plain `for (i = 0; i < D_8006AEE8; i++)` loop, not an `if (D > 0) { count = D; do … while }`: + - jump.c `duplicate_loop_exit_test` (jump.c:2131; new pseudos for the copied test at :2223) copies the exit test + `t = i < D; if (t == 0) goto end` in front of the rotated loop. + - combine then merges `i = 0` (i1) + `t = (lt i D)` (i2) + the branch (i3) into `blez` with `i = 0` KEPT as newi2pat. + Because `newi2pat != 0`, combine.c:2306-2314 does NOT zero `reg_n_refs` of `t` (pseudo 87): `.flow` says + "Register 87 used 2 times across 2 insns", `.greg` lists `87 conflicts:` EMPTY and no disposition -> `alter_reg` + (reload1.c:2331-2352) gives it a stack slot -> the 8-byte frame that nothing references (the S103 c35 / §16Xy + orphan-slot class, new source: a rotated loop's duplicated exit test). + - The delay slot then comes out as the target's (`move a2,zero`, bytes). WHY reorg does not pull the prologue + `addiu sp` into that slot here while it does for the `pad[2]` probe in (e) was NOT examined (`.dbr` not read) — + most likely the `i = 0` insn kept by combine now sits between the load and the branch; unproven. +2. The loop bound `D_8006AEE8` is read in the loop condition and loop.c HOISTS it (`.loop`: "Insn 17: regno 75 … moved"): + `invariant_p` (loop.c:2779) asks `true_dependence` (sched.c:817, the `MEM_IN_STRUCT_P && rtx_addr_varies_p` clauses at + :834/:858) whether the store `(&D_80078F10)[i] = arg1` can alias the scalar `D_8006AEE8` — an ARRAY store at a varying + address never conflicts with a fixed-address scalar, so the load moves to the loop preheader, and cse2 turns it into + the copy `move a3,v0` of the pre-test load. That is why the target has `lw v0 … blez v0 … move a3,v0` (two pseudos) + — the tree's `count = D_8006AEE8` local was the decompiler's reading of the hoisted invariant. +3. The walked pointer `$v1` is loop.c's strength-reduced giv of `(&D_80078F10)[i]` (`giv at 47 reduced to (reg:SI 89)`). + +Proven on bytes: `--try` score 0 (21/21). Proven on dumps: the orphan pseudo 87 (.flow/.greg), the hoist (.loop). + +## (c) The move that closed it +The whole do-while + `count` + walked `p` + `if` guard rewritten as the TU's own idiom (func_80036D24 at +src/800_c.c:1445 spells the same loop over the same two globals this way): + + for (i = 0; i < D_8006AEE8; i++) { + if ((&D_80078F10)[i] == arg0) { + (&D_80078F10)[i] = arg1; + } + } + +`p = &D_80078F10; … p[i]` scores 0 too (u2). Walking `p++` in the for header does NOT (u3, 15: the pointer store is +scalar-to-scalar, no hoist). + +## (d) GENERATOR PROPOSAL +When the residual is FRAME-only (+8, no slot referenced) on a guarded `if (G > 0) { count = G; … do { … } while (i < count); }` +loop, rewrite it as `for (i = 0; i < G; i++)` over an indexed array access (delete the guard, the `count` local and the +walked pointer): the rotated loop's duplicated exit test orphans one pseudo in combine (8 bytes of frame) and the +aggregate-vs-scalar alias rule hoists `G` into the `count` copy. + +## (e) What did not work (bytes) +- `count = G; if (count > 0) { for … }` / `if (G > 0) { count = G; for … }` (w1-w5, v1, v3): 7-8 — the frame appears but + cse cannot fold the duplicated `0 < count` test against the guard (`fold_rtx` only checks dominance when arg0 is a REG, + cse.c:5411-5431; here arg0 is the constant 0), so a second `blez` survives. +- `count = G; for (…; i < count; …)` without a guard (v4, w6, w7): 14 — `count` IS the load, no copy, order differs. +- Unused `s32 pad[2]` on the free body: 3 — the frame appears but reorg pulls the prologue `addiu sp` into the `blez` slot. + +## (f) Where the method fell short +neighbours.txt and related.txt were empty; the answer was a sibling in the same TU (func_80036D24, same globals) — the +"grep the TU for the other functions that touch the same global" step (S103 c2) found it. The generator families never +propose deleting a guard + a local together (a structural rewrite: guarded do-while -> for). + +## (g) Structs question +No struct needed; the channel IS the aggregate rule, but it is reached with an array access (`(&D_80078F10)[i]`), which +is already `MEM_IN_STRUCT_P` (expr.c:4568-4577). Declaring `D_80078F10` as `s32 D_80078F10[]` would read better and +should give the same bytes (same aggregate flag) — not tested because the file-scope `extern s32 D_80078F10;` is shared +with other functions in the TU (a structs-phase cleanup). diff --git a/.run/P36/agents/main__func_80037144/body.c b/.run/P36/agents/main__func_80037144/body.c new file mode 100644 index 000000000..a98c4121f --- /dev/null +++ b/.run/P36/agents/main__func_80037144/body.c @@ -0,0 +1,54 @@ +void func_80037144(s32 idx) { + s32 i; + s32 k; + s32 t; + s32 v; + s32 one; + s32 ent; + + for (i = 0; i < 5; i++) { + if (D_80076244[i].unk0D == 0) { + break; + } + } + if (i < 5) { + one = 1; + /* the word at +0 is written through the D_80076240 view (as func_80037028 does): a + * non-zero offset from its base keeps the store ordered before the table loads below */ + D_80076240[i].unk04 = (s32)D_800BA320; + D_80076244[i].unk0C = 0; + D_80076244[i].unk0D = one; + D_80076244[i].unk04 = idx | 0x2000; + D_80076244[i].unk0E = 4; + v = D_800652F0[D_80065438[idx].f0]; + D_800A469C = v; + D_80076244[i].unk08 = v; + k = 4; + if (D_800A46B0 == 0) { + if (D_800A46A0 == (D_80065438[idx].f0 | 0x4000)) { + D_80076244[i].unk04 |= 0x1000; + goto after; + } + t = D_800A46A2; + D_800A46B0 = one; + } else { + t = D_800A46A2; + } + if (t >= 0) { + func_800415A8(t); + D_800A46A2 = -1; + } + after: + if (i == 0) { + D_8007622C[0] = (s32)D_800BA320; + ent = D_800A463C[k].unk00; + D_80076228.v = (s32)D_800BA320; + D_80076240[0].unk00 = 0; + D_80076243.v = 1; + D_80076242.v = 0; + D_80076294.v = 0; + D_80076238.v = ent; + } + } + D_8007629C = 0; +} diff --git a/.run/P36/agents/main__func_80037144/body_minlever.c b/.run/P36/agents/main__func_80037144/body_minlever.c new file mode 100644 index 000000000..f623ca9cf --- /dev/null +++ b/.run/P36/agents/main__func_80037144/body_minlever.c @@ -0,0 +1,58 @@ +void func_80037144(s32 idx) { + s32 i; + s32 k; + s32 t; + s32 v; + s32 one; + s32 ent; + + for (i = 0; i < 5; i++) { + if (D_80076244[i].unk0D == 0) { + break; + } + } + if (i < 5) { + one = 1; + D_80076244[i].unk00 = (s32)D_800BA320; + /* scheduling barrier: the slot stores and the D_80065438 load DO disambiguate here + * (both /s and both varying -> memrefs_conflict_p:614 falls through to + * find_symbolic_term and the two symbols differ), so without this gcc hoists the + * D_80065438 load above all the slot stores and permutes the head block. + * Emits zero instructions. */ + __asm__ __volatile__("" ::: "memory"); // !FAKE: barrier memory after the unk00 store — sched.c:817 true_dependence via memrefs_conflict_p/find_symbolic_term sched.c:700 (P36 S104 e3 minimum-lever) + D_80076244[i].unk0C = 0; + D_80076244[i].unk0D = one; + D_80076244[i].unk04 = idx | 0x2000; + D_80076244[i].unk0E = 4; + v = D_800652F0[D_80065438[idx].f0]; + D_800A469C = v; + D_80076244[i].unk08 = v; + k = 4; + if (D_800A46B0 == 0) { + if (D_800A46A0 == (D_80065438[idx].f0 | 0x4000)) { + D_80076244[i].unk04 |= 0x1000; + goto after; + } + t = D_800A46A2; + D_800A46B0 = one; + } else { + t = D_800A46A2; + } + if (t >= 0) { + func_800415A8(t); + D_800A46A2 = -1; + } + after: + if (i == 0) { + D_8007622C[0] = (s32)D_800BA320; + ent = D_800A463C[k].unk00; + D_80076228.v = (s32)D_800BA320; + D_80076240[0].unk00 = 0; + D_80076243.v = 1; + D_80076242.v = 0; + D_80076294.v = 0; + D_80076238.v = ent; + } + } + D_8007629C = 0; +} diff --git a/.run/P36/agents/main__func_80037144/mechanism.md b/.run/P36/agents/main__func_80037144/mechanism.md new file mode 100644 index 000000000..f4ccb602b --- /dev/null +++ b/.run/P36/agents/main__func_80037144/mechanism.md @@ -0,0 +1,71 @@ +# func_80037144 (src/800_c.c) — P36 S104 agent e3 + +**Result.** No levers: `body.c` is byte-identical ONCE LINKED; `--try` scores it **2**, and both points are relocation +naming (`sw v0,4(at)` against `D_80076240` where the baseline has `sw v0,0(at)` against `D_80076244`, and +0x80076240+4 == 0x80076244 per build/us/SLUS_007.26.map). The scheduling is otherwise exact. main banks on the linked +SHA1 (`tools/gate_main.py:220`), and func_80037028, the sibling in the same TU, is already banked with exactly this +`D_80076240+4` relocation form. Fallback: `body_minlever.c` scores **0** at object level with 1 marked lever (the tree's +barrier, re-marked). Levers: 1 -> 0 (body.c), or 1 -> 1 (body_minlever.c). +Best object-level plain-C text: `scratch/best_plainC_objlevel_t1.c`, score 2 (one `li a2,1` out of place, see (e)). + +## (a) The residual +Count 123 vs 124 with a permuted head block. Without the barrier, the store `D_80076244[i].unk00 = (s32)D_800BA320` +sinks below the `D_80065438`/`D_800652F0` table loads (sched1). The table value then lands in `v1` rather than `v0`, and the store fills +the load-delay slot the target leaves as a `nop`. That `nop` is the one-instruction count difference, not a missing +operation. + +## (b) The pass decision (proven on dumps and bytes) +sched1's dependence builder, `true_dependence` (sched.c:817), calls `memrefs_conflict_p`. Both addresses are +`(plus reg X)`. For the unk00 store X = `(symbol_ref D_80076244)`, which is offset 0. For the load X = +`(symbol_ref D_80065438)`. Neither the registers nor the X terms are equal, so the call reaches `find_symbolic_term` +(sched.c:700). That finds two different symbols and reports "no conflict", so the load does not depend on the store. +Every OTHER slot store has a NON-ZERO offset, `(const (plus sym K))`. `find_symbolic_term` returns 0 on a CONST +(`GET_RTX_CLASS == 'o'`, sched.c:571) and that means "conflict" (sched.c:700-702). So only the offset-0 store is free to +float, and it floats down into the load-latency hole: the `.sched` trace shows it chosen alone at T-6 while the load +stalls. func_80037028's header (src/800_c.c:1649-1661, note 2) records the same law for the same table. +**Proof on dumps:** with the D_80076240 view, the lhu `insn 126` gains `LOG_LINKS insn_list 72` (the unk00 store) in +`scratch/s1.sched`. Without it, it does not. + +## (c) The move +`D_80076244[i].unk00 = (s32)D_800BA320;` -> `D_80076240[i].unk04 = (s32)D_800BA320;`. This is the same word, written +through the TU's other declared view of the table (`extern Slot16A D_80076240[]`, 0x80076240, unk04 at +4). The address +becomes `(const (plus D_80076240 4))`, the store conflicts with the loads, and sched1/sched2 reproduce the target order, +including `li a2,1`. Writing all three word fields through D_80076240, the sibling's own convention (scratch/v/s2.c), +gives a byte-identical schedule too, with 5 relocation-only differences (--try 10). + +## (d) GENERATOR PROPOSAL +When a zero-offset store `A[i].f0 = …` into a symbol+scaled-index array drifts past later varying loads of OTHER +symbols (ORDER residual, count ±1), and the TU declares an overlapping view `B` of the same memory at a lower address, +rewrite the store through `B[i].`. Score it on the linked image (reloc-only diff), not on the object. + +## (e) What did not work (bytes, --try at object level) +- All 120 orders of the five slot stores (scratch/v/perm_*): 16-19. Order cannot create a memory dependence. +- A marked `do { } while (0)` around every contiguous range of the head statements (55 + 78 files): best 2 + (free_127 from the sweep: `sll a0,a0,1` misplaced). +- **Register anchoring (t1, the best object-level plain C, 2).** Reuse `v` for `&D_800BA320` and for + `idx | 0x2000` (`v = (s32)D_800BA320; …unk00 = v; … v = idx | 0x2000; …unk04 = v;`). The second set of `v` is an + anti-dependence that holds the unk00 store above the `ori`. That fixes the whole head block except `li a2,1` (`one`), + which lands after the `ori` instead of before the store. The cause: `one = 1` is a birthing insn + (`birthing_insn_p`, sched.c:2465-2488, via `adjust_priority` :2539). sched1 therefore places it directly before its + only in-block use (the `unk0D` store). sched2's LUID tie-break (`rank_for_schedule`, sched.c:2428) then keeps it + after the `ori`. I tried `one` as u8/s8/u16/s16, as a literal `1`, and in all 360 orders of the units: all 2 or worse. + Not a close. +- An unused `v` reuse for `D_800BA320` in the tail too (r2): 40. + +## (f) Where the method fell short +neighbours.txt and related.txt were EMPTY, but the answer was spelled out in English in the header of the function 90 +lines above (func_80037028, src/800_c.c:1639-1674). related.txt should include same-TU functions that share a GLOBAL, +not only a callee. The scorer compares relocation symbols, so a linked-identical close through an overlapping base is +reported as not matching. A linked-image mode for `--try` (resolve symbol+addend before diffing) would have scored this +body 0. + +## (g) Structs question — YES, this is the struct case +The memory at 0x80076228..0x800762A0 is ONE object in the original. This function touches D_80076228, D_8007622C, +D_80076238, D_80076240, D_80076242, D_80076243, the 5x16 slots at D_80076244, D_80076294 and D_8007629C. A single struct +(e.g. `struct { s32 f00; s32 f04[3]; s32 f10; …; u16 f18; u8 f1A, f1B; Slot16 slot[5]; s32 f6C; …; s32 f74; }` at +D_80076228) makes EVERY field access `(const (plus D_80076228 K))` with K != 0, apart from f00. By sched.c:571/700 +every slot store then conflicts with every varying table load. That is exactly the dependence the barrier fakes, and the +one func_80037028 fakes with its second base. It also plausibly removes the W8/W32 one-field-struct wrappers +(src/800_c.c:1740-1752) whose only job is to set MEM_IN_STRUCT_P. Tested on bytes only through the D_80076240 view +(body.c, linked-identical). The full struct changes every relocation in the TU's six users of this memory, so it belongs +to the structs phase. diff --git a/.run/P36/agents/main__func_800384A8/mechanism.md b/.run/P36/agents/main__func_800384A8/mechanism.md new file mode 100644 index 000000000..4cb3752d4 --- /dev/null +++ b/.run/P36/agents/main__func_800384A8/mechanism.md @@ -0,0 +1,39 @@ +# func_800384A8 (src/800_c.c) — P36 S104 agent e3 — score 2 -> 0, ZERO levers, BUT A SIGNATURE CHANGE (parked) + +## (a) The residual +Two instructions: the target indexes `D_800B9CD8` with the raw `$a0` (`sll v0,a0,7; subu v0,v0,a0`), the lever-free body +has no value for `raw` at all (it read an uninitialised local, landing in `$v1`). The tree faked it with +`register s32 raw __asm__("$4")` next to an UNUSED `s16 arg0` parameter. + +## (b) The pass decision +Not a pass: the parameter's declared width. `mips.h:1153` defines `PROMOTE_PROTOTYPES`, so a prototyped `s16` parameter +arrives as an int and is narrowed at entry (`assign_parms`, function.c:3664-3676); every SImode use then re-extends it — +`--try` of `s16 arg0` + `arg0 * 0x1FC` gives exactly `sll a0,a0,16; sra a0,a0,16` extra (score 2, 72 vs 70 ins, +`scratch/s16.c`). The target has no extension, so the parameter is a full `s32` in the original. No plain-C spelling of +an `s16` parameter can drop that extension (the incoming value is not known to be sign-extended). + +## (c) The move +`void func_800384A8(s16 arg0)` -> `void func_800384A8(s32 arg0)`, the pinned `raw` deleted, `arg0 * 0x1FC` indexes the +table. Score 0 (70/70). Nothing else changed. + +SIGNATURE CHANGE: the only other declaration is `extern void func_800384A8(s16 a0);` at src/800_b_2.c:1884, a different +TU. Its one caller, func_8002EC10, passes `*s0` with `s16 *s0` (src/800_b_2.c:1889). That is an `lh` value, already +sign-extended, so moving that prototype to `s32` should not change the caller's bytes. I did not test this (800_b_2.c is +another agent's TU). The definition's parameter type alone decides this function's bytes, and the mismatched `s16` +prototype in the other TU compiles regardless. Parked for the structs phase per Drew S104 (d). + +## (d) GENERATOR PROPOSAL +When a `register … __asm__("$4"..."$7")` pin is the ONLY reader of an incoming argument register and the matching +parameter is narrow (s16/u16/s8/u8) and unused, delete the pin, widen the parameter to `s32` and substitute it for the +pinned local (a signature move; flag it for the caller TUs' prototypes). + +## (e) What did not work +The sweep's R14 (param-width s16->s32) alone scored 2 because it widened `arg0` without routing the pinned `raw` to it +(the pin's local is a SEPARATE uninitialised variable in body_free.c). Keeping `s16 arg0` and using it: 2 (above). + +## (f) Where the method fell short +body_free.c's `raw` is an uninitialised read — the lever remover should map a `$aN` pin to parameter N when the +parameter is otherwise unused (then R14 would have closed this on its own). + +## (g) Structs question +No. The defect is a parameter width, not an access shape; no struct type changes the entry narrowing. diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index 1c92f3696..41b9ac052 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,7 +1,7 @@ { - "head": "bb7973c04", + "head": "c4c60c917", "stamp": "15956e4a96c4", - "generated": "2026-09-11 00:46", + "generated": "2026-09-11 01:05", "aliases": [ "main", "ov_SC03_014", @@ -21,207 +21,207 @@ "main": { "objects": 85, "identical": 85, - "seconds": 14.434999999999997, - "mean_s": 0.17 + "seconds": 10.372000000000005, + "mean_s": 0.122 }, "ov_SC03_014": { "objects": 32, "identical": 32, - "seconds": 6.408, - "mean_s": 0.2 + "seconds": 7.037999999999999, + "mean_s": 0.22 }, "ov_SC03_015": { "objects": 32, "identical": 32, - "seconds": 7.257000000000001, - "mean_s": 0.227 + "seconds": 6.893000000000001, + "mean_s": 0.215 }, "ov_SC04_011": { "objects": 28, "identical": 28, - "seconds": 6.631, - "mean_s": 0.237 + "seconds": 6.444999999999999, + "mean_s": 0.23 } }, "per_object_seconds": { - "build/src/800.o": 1.308, - "build/src/800_b.o": 0.14, - "build/src/800_b_2.o": 1.102, - "build/src/800_b_o0a.o": 0.11, - "build/src/800_c.o": 0.24, - "build/src/800b2.o": 0.146, - "build/src/apicard1.o": 0.134, - "build/src/apicard2.o": 0.075, - "build/src/apicard3.o": 0.121, - "build/src/apicard4.o": 0.154, - "build/src/apicard5.o": 0.132, - "build/src/apicard6.o": 0.14, - "build/src/apicard7.o": 0.151, - "build/src/boot.o": 0.161, - "build/src/gap.o": 0.121, - "build/src/libapi1.o": 0.15, - "build/src/libapi2.o": 0.069, - "build/src/libc2_1.o": 0.077, + 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+29369,4 @@ {"ts": "2026-09-11 00:45:18", "label": "s104_e4", "rung": "E", "calib": {"head": "2ae8a5a6a", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c", "fn": "func_80183B9C", "addr": 2149071772, "aliases": null, "header": false, "includers": 0, "nhash_before": "14d21df93cea44d138c665d2c64d5ff61ffe358e", "nhash_after": "671943dc221e1ebbe5ca46c4819a1307adecd4ba", "source": ".run/P36/agents/ov_SC02_017__func_80183B9C/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.36, "objects": ["build/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.o"], "before_text": "void func_80183B9C(u8 *arg0) {\n extern int func_80178970(void);\n extern void func_80178D18(void);\n extern void func_8017F644(void);\n extern s32 D_801270C8;\n extern s32 D_801EF9F8;\n extern void func_8002D4C8(s32 a0, s32 a1);\n extern void func_801836A8(void*);\n\n D_801270C8 = 1;\n if (*(u16 *)(arg0 + 0x34) == 0) {\n if (func_80178970() != 0) {\n ((void (*)(s32))func_80178D18)((s32)arg0);\n if (D_801EF9F8 != 0) {\n func_8017F644();\n }\n *(u16 *)(arg0 + 0x34) = 1;\n }\n } else {\n __asm__ __volatile__(\"\"); // !FAKE: barrier \u2014 NEEDED DIFFERS (P36 rung B tus8)\n func_8002D4C8(0x13, 0);\n ((s32 (*)(u8 *))func_801836A8)(arg0);\n }\n}\n", "after_text": "void func_80183B9C(u8 *arg0) {\n extern int func_80178970(void);\n extern void func_80178D18(void);\n extern void func_8017F644(void);\n extern s32 D_801270C8;\n extern s32 D_801EF9F8;\n extern void func_8002D4C8(s32 a0, s32 a1);\n extern void func_801836A8(void*);\n\n D_801270C8 = 1;\n if (*(u16 *)(arg0 + 0x34) == 0) {\n if (((s32 (*)(u8 *))func_80178970)(arg0) != 0) {\n ((void (*)(s32))func_80178D18)((s32)arg0);\n if (D_801EF9F8 != 0) {\n func_8017F644();\n }\n *(u16 *)(arg0 + 0x34) = 1;\n }\n } else {\n func_8002D4C8(0x13, 0);\n ((s32 (*)(u8 *))func_801836A8)(arg0);\n }\n}\n"} {"ts": "2026-09-11 00:46:07", "label": "s104_e4", "rung": "E", "calib": {"head": "b06062ac1", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c", "fn": "func_80184754", "addr": 2149074772, "aliases": null, "header": false, "includers": 0, "nhash_before": "c2a6f3a0b78c04029745eb0b1c8d287949aa509d", "nhash_after": "72986c87550de892e6d998262e855e559cec0512", "source": ".run/P36/agents/ov_SC02_017__func_80184754/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.274, "objects": ["build/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.o"], "before_text": "void func_80184754(void *a0)\n{\n s32 s0 = (s32)a0;\n s32 s1;\n\n __asm__ __volatile__(\"\" : \"=r\"(s0) : \"0\"(s0)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus8)\n\n s1 = *(s32 *)(s0 + 0x64);\n\n if (*(s16 *)(s0 + 0xFC) != *(s16 *)(s1 + 0x36)) {\n ((void (*)(void))func_8012C218)();\n return;\n }\n\n if (*(s32 *)(s1 + 0x1C) == 0) {\n func_80132288(&D_801EFA68, &D_801CC38C, D_801CCE84);\n } else {\n *(s32 *)(s0 + 0x4) = *(s32 *)(s1 + 0x4);\n *(s32 *)(s0 + 0x8) = *(s32 *)(s1 + 0x8);\n *(s32 *)(s0 + 0xC) = *(s32 *)(s1 + 0xC);\n *(SV4x_80184754 *)(*(s32 *)(s0 + 0x20) + 0x10) = *(SV4x_80184754 *)(*(s32 *)(s1 + 0x20) + 0x10);\n *(SV4x_80184754 *)(*(s32 *)(s0 + 0x20) + 0x18) = *(SV4x_80184754 *)(*(s32 *)(s1 + 0x20) + 0x18);\n *(u16 *)(*(s32 *)(s0 + 0x20) + 0x2C) = *(u16 *)(*(s32 *)(s1 + 0x20) + 0x2C);\n *(s32 *)(*(s32 *)(s0 + 0x20) + 0x4) = *(s32 *)(*(s32 *)(s1 + 0x20) + 0x4);\n func_8013240C((s32)&D_801EFA68);\n }\n}\n", "after_text": "void func_80184754(void *a0)\n{\n s32 s1;\n\n s1 = *(s32 *)((s32)a0 + 0x64);\n\n if (*(s16 *)((s32)a0 + 0xFC) != *(s16 *)(s1 + 0x36)) {\n func_8012C218(a0);\n return;\n }\n\n if (*(s32 *)(s1 + 0x1C) == 0) {\n func_80132288(&D_801EFA68, &D_801CC38C, D_801CCE84);\n } else {\n *(s32 *)((s32)a0 + 0x4) = *(s32 *)(s1 + 0x4);\n *(s32 *)((s32)a0 + 0x8) = *(s32 *)(s1 + 0x8);\n *(s32 *)((s32)a0 + 0xC) = *(s32 *)(s1 + 0xC);\n *(SV4x_80184754 *)(*(s32 *)((s32)a0 + 0x20) + 0x10) = *(SV4x_80184754 *)(*(s32 *)(s1 + 0x20) + 0x10);\n *(SV4x_80184754 *)(*(s32 *)((s32)a0 + 0x20) + 0x18) = *(SV4x_80184754 *)(*(s32 *)(s1 + 0x20) + 0x18);\n *(u16 *)(*(s32 *)((s32)a0 + 0x20) + 0x2C) = *(u16 *)(*(s32 *)(s1 + 0x20) + 0x2C);\n *(s32 *)(*(s32 *)((s32)a0 + 0x20) + 0x4) = *(s32 *)(*(s32 *)(s1 + 0x20) + 0x4);\n func_8013240C((s32)&D_801EFA68);\n }\n}\n"} {"ts": "2026-09-11 00:47:00", "label": "s104_e4", "rung": "E", "calib": {"head": "bb7973c04", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c", "fn": "func_80186770", "addr": 2149082992, "aliases": null, "header": false, "includers": 0, "nhash_before": "7fc443e8e9bc6f61af024b9adeedc7849902e6d2", "nhash_after": "1d413cb518a360b40a4f9860d3a2f58a76725efc", "source": ".run/P36/agents/ov_SC02_017__func_80186770/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.363, "objects": ["build/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.o"], "before_text": "void func_80186770(s32 param_1)\n{\n struct { s32 vx, vy, vz, pad; } vec;\n s32 v;\n s32 d;\n s32 b178arg;\n void *target;\n\n switch (*(u16 *)(param_1 + 0x34)) {\n case 0:\n v = func_8012B8E4(param_1, 4);\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) += v;\n if (*(s32 *)(param_1 + 0x1C) == 0xF) {\n func_80142414(param_1, -0x78);\n func_8002D4C8(0x6A9, 0);\n }\n if (func_8012BEE8(param_1) != 0) {\n *(s16 *)(param_1 + 0x2) = 3;\n if ((*(u16 *)(param_1 + 0x86) & 2) != 0) {\n *(s16 *)(param_1 + 0x34) = 1;\n *(s32 *)(param_1 + 0x1C) = 0x28;\n if ((*(u16 *)(param_1 + 0x70) & 0x200) != 0) {\n func_8012A828(param_1, &D_801E1AFC);\n } else {\n func_8012A828(param_1, &D_801E11DC);\n }\n *(u16 *)(param_1 + 0xFE) = 0;\n } else {\n *(s16 *)(param_1 + 0x34) = 0;\n func_8012A828(param_1, &D_801E1264);\n *(s32 *)(param_1 + 0x1C) = 0x19;\n *(u16 *)(param_1 + 0x86) |= 2;\n }\n }\n break;\n case 1:\n v = func_8012B8E4(param_1, 6);\n b178arg = D_801D619C;\n {\n u16 *pp;\n register s32 nv __asm__(\"$6\"); // !FAKE: pin $6 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n\n pp = (u16 *)(*(s32 *)(param_1 + 0x20) + 0x12);\n nv = *pp + v;\n *pp = nv;\n }\n func_8012B178(param_1, b178arg);\n d = ((s32 (*)(s32))func_8012CBA4)(param_1);\n if ((d & 0x1000) != 0) {\n func_80131E00(param_1, 0x12);\n } else if (d != 0x2000) {\n func_8012ADE4((u8 *)param_1);\n }\n func_80185F88(param_1);\n v = *(u16 *)(param_1 + 0xFE) - 1;\n *(u16 *)(param_1 + 0xFE) = v;\n if ((v << 16) <= 0) {\n func_80143B6C(param_1, 0);\n *(u16 *)(param_1 + 0xFE) = 8;\n }\n if ((*(u16 *)(param_1 + 0x70) & 0x200) != 0) {\n func_80186C38(param_1, 0x11);\n }\n target = (void *)(param_1 + 0x88);\n vec.vx = *(s16 *)(param_1 + 6) - *(s16 *)(param_1 + 0x88);\n vec.vy = 0;\n vec.vz = *(s16 *)(param_1 + 0xE) - *(s16 *)(param_1 + 0x8C);\n Square0(&vec.vx, &vec.vx);\n if (vec.vx + vec.vz > 0x8FFFF || (d = func_8012BCCC(param_1), d > 0x24000)) {\n *(s16 *)(param_1 + 0x2) = 1;\n *(s16 *)(param_1 + 0x34) = 0;\n *(u16 *)(param_1 + 0x5C) = 0xAA10;\n *(s32 *)(param_1 + 0x1C) = (rand() & 0x1F) + 0x28;\n vec.vx = *(s16 *)(param_1 + 6) - *(s16 *)(param_1 + 0x88);\n vec.vy = 0;\n vec.vz = *(s16 *)(param_1 + 0xE) - *(s16 *)(param_1 + 0x8C);\n Square0(&vec.vx, &vec.vx);\n if (vec.vx + vec.vz > 0x8FFFF) {\n *(u16 *)(param_1 + 0xFC) = func_8012B744((void *)(param_1 + 4), target);\n } else {\n s32 t = rand() & 0x3FF;\n s32 off = t - 0x200;\n\n if (off < 0) {\n off = t - 0x500;\n } else {\n off = t + 0x100;\n }\n *(u16 *)(param_1 + 0xFC) =\n (*(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) + off) & 0xFFF;\n }\n func_8012A828(param_1, &D_801E1134);\n }\n if ((*(u16 *)(param_1 + 0x70) & 0x100) == 0) {\n if (func_8012BD3C(param_1, 0x400, 0x1000) != 0) {\n if ((*(u16 *)(param_1 + 0x70) & 0xF00) == 0) {\n ((void (*)(s32))func_80186B08)(param_1);\n } else {\n func_80186B34(param_1);\n }\n }\n } else {\n if (func_8012BD3C(param_1, 0x400, 0x40000) != 0) {\n func_80186B7C(param_1);\n }\n }\n break;\n }\n}\n", "after_text": "void func_80186770(s32 param_1)\n{\n struct { s32 vx, vy, vz, pad; } vec;\n s32 v;\n s32 d;\n void *target;\n\n switch (*(u16 *)(param_1 + 0x34)) {\n case 0:\n v = func_8012B8E4(param_1, 4);\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) += v;\n if (*(s32 *)(param_1 + 0x1C) == 0xF) {\n func_80142414(param_1, -0x78);\n func_8002D4C8(0x6A9, 0);\n }\n if (func_8012BEE8(param_1) != 0) {\n *(s16 *)(param_1 + 0x2) = 3;\n if ((*(u16 *)(param_1 + 0x86) & 2) != 0) {\n *(s16 *)(param_1 + 0x34) = 1;\n *(s32 *)(param_1 + 0x1C) = 0x28;\n if ((*(u16 *)(param_1 + 0x70) & 0x200) != 0) {\n func_8012A828(param_1, &D_801E1AFC);\n } else {\n func_8012A828(param_1, &D_801E11DC);\n }\n *(u16 *)(param_1 + 0xFE) = 0;\n } else {\n *(s16 *)(param_1 + 0x34) = 0;\n func_8012A828(param_1, &D_801E1264);\n *(s32 *)(param_1 + 0x1C) = 0x19;\n *(u16 *)(param_1 + 0x86) |= 2;\n }\n }\n break;\n case 1:\n v = func_8012B8E4(param_1, 6);\n (*(u16 **)(param_1 + 0x20))[9] += v;\n func_8012B178(param_1, D_801D619C);\n d = ((s32 (*)(s32))func_8012CBA4)(param_1);\n if ((d & 0x1000) != 0) {\n func_80131E00(param_1, 0x12);\n } else if (d != 0x2000) {\n func_8012ADE4((u8 *)param_1);\n }\n func_80185F88(param_1);\n v = *(u16 *)(param_1 + 0xFE) - 1;\n *(u16 *)(param_1 + 0xFE) = v;\n if ((v << 16) <= 0) {\n func_80143B6C(param_1, 0);\n *(u16 *)(param_1 + 0xFE) = 8;\n }\n if ((*(u16 *)(param_1 + 0x70) & 0x200) != 0) {\n func_80186C38(param_1, 0x11);\n }\n target = (void *)(param_1 + 0x88);\n vec.vx = *(s16 *)(param_1 + 6) - *(s16 *)(param_1 + 0x88);\n vec.vy = 0;\n vec.vz = *(s16 *)(param_1 + 0xE) - *(s16 *)(param_1 + 0x8C);\n Square0(&vec.vx, &vec.vx);\n if (vec.vx + vec.vz > 0x8FFFF || (d = func_8012BCCC(param_1), d > 0x24000)) {\n *(s16 *)(param_1 + 0x2) = 1;\n *(s16 *)(param_1 + 0x34) = 0;\n *(u16 *)(param_1 + 0x5C) = 0xAA10;\n *(s32 *)(param_1 + 0x1C) = (rand() & 0x1F) + 0x28;\n vec.vx = *(s16 *)(param_1 + 6) - *(s16 *)(param_1 + 0x88);\n vec.vy = 0;\n vec.vz = *(s16 *)(param_1 + 0xE) - *(s16 *)(param_1 + 0x8C);\n Square0(&vec.vx, &vec.vx);\n if (vec.vx + vec.vz > 0x8FFFF) {\n *(u16 *)(param_1 + 0xFC) = func_8012B744((void *)(param_1 + 4), target);\n } else {\n s32 t = rand() & 0x3FF;\n s32 off = t - 0x200;\n\n if (off < 0) {\n off = t - 0x500;\n } else {\n off = t + 0x100;\n }\n *(u16 *)(param_1 + 0xFC) =\n (*(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) + off) & 0xFFF;\n }\n func_8012A828(param_1, &D_801E1134);\n }\n if ((*(u16 *)(param_1 + 0x70) & 0x100) == 0) {\n if (func_8012BD3C(param_1, 0x400, 0x1000) != 0) {\n if ((*(u16 *)(param_1 + 0x70) & 0xF00) == 0) {\n ((void (*)(s32))func_80186B08)(param_1);\n } else {\n func_80186B34(param_1);\n }\n }\n } else {\n if (func_8012BD3C(param_1, 0x400, 0x40000) != 0) {\n func_80186B7C(param_1);\n }\n }\n break;\n }\n}\n"} +{"ts": "2026-09-11 01:05:57", "label": "s104_e3", "rung": "E", "calib": {"head": "c4c60c917", "stamp": "15956e4a96c4"}, "tu": "src/800_c.c", "fn": "func_80036FB0", "addr": 2147708848, "aliases": null, "header": false, "includers": 0, "nhash_before": "4c9ae2c827bb1e0345b6af0f0de266b44d262aa8", "nhash_after": "ea847aa1537017f7171e23041f21172a7eedd9c1", "source": ".run/P36/agents/main__func_80036FB0/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.262, "objects": ["build/src/800_c.o"], "before_text": "void func_80036FB0(s32 arg0, s32 arg1) {\n extern s32 D_8006AEE8;\n extern s32 D_80078F10;\n f64 hole;\n s32 count;\n s32 i;\n s32 *p;\n\n __asm__ volatile(\"\" :: // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus9)\n \"m\"(hole));\n if (D_8006AEE8 > 0) {\n i = 0;\n count = D_8006AEE8;\n p = &D_80078F10;\n do {\n if (*p == arg0) {\n *p = arg1;\n }\n p++;\n i++;\n } while (i < count);\n }\n}\n", "after_text": "void func_80036FB0(s32 arg0, s32 arg1) {\n s32 i;\n\n for (i = 0; i < D_8006AEE8; i++) {\n if ((&D_80078F10)[i] == arg0) {\n (&D_80078F10)[i] = arg1;\n }\n }\n}\n"} diff --git a/src/800_c.c b/src/800_c.c index 098acdd1a..e589c7b61 100644 --- a/src/800_c.c +++ b/src/800_c.c @@ -1608,26 +1608,12 @@ void func_80036F98(void) { } void func_80036FB0(s32 arg0, s32 arg1) { - extern s32 D_8006AEE8; - extern s32 D_80078F10; - f64 hole; - s32 count; s32 i; - s32 *p; - __asm__ volatile("" :: // !FAKE: keepalive — NEEDED DIFFERS (P36 rung B tus9) - "m"(hole)); - if (D_8006AEE8 > 0) { - i = 0; - count = D_8006AEE8; - p = &D_80078F10; - do { - if (*p == arg0) { - *p = arg1; - } - p++; - i++; - } while (i < count); + for (i = 0; i < D_8006AEE8; i++) { + if ((&D_80078F10)[i] == arg0) { + (&D_80078F10)[i] = arg1; + } } }