From aca8ff0bfe1278c0fa0004b860e99f8ee70c4184 Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Wed, 26 Aug 2026 07:18:53 -0600 Subject: [PATCH] =?UTF-8?q?feat(decomp):=20ox=20wave=20g0e=20overlays=20?= =?UTF-8?q?=E2=80=94=202=20banked?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Committed before the main batch: gate_main reverts on failure and would take these with it. --- config/overlays.mk | 3 +- config/splat.ov_SC06_016.yaml | 3 +- src/md_MAIN_011/md_MAIN_011.c | 12 ++++- src/ov_SC06_016/ov_SC06_016_jr_801816DC.c | 56 ++++++++++++++++++++++- 4 files changed, 69 insertions(+), 5 deletions(-) diff --git a/config/overlays.mk b/config/overlays.mk index 180360246f..98685e57b1 100644 --- a/config/overlays.mk +++ b/config/overlays.mk @@ -4301,7 +4301,7 @@ ov_SC06_016_ELF := $(ov_SC06_016_OUT).elf ov_SC06_016_MAPFILE := $(ov_SC06_016_OUT).map ov_SC06_016_LD_SCRIPT := $(ov_SC06_016_OUT).ld ov_SC06_016_SPLAT_YAML := config/splat.ov_SC06_016.yaml -ov_SC06_016_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_016.o,ov_SC06_016_jr_8012ACE0.o,tail2.data.o,ov_SC06_016_jr_80135888.o,tail3.data.o,ov_SC06_016_jr_80135A4C.o,tail4.data.o,ov_SC06_016_jr_80135D20.o,tail5.data.o,ov_SC06_016_jr_801380E0.o,ov_SC06_016_o0c.o,tail6.data.o,ov_SC06_016_jr_8013F350.o,tail7.data.o,ov_SC06_016_jr_8013FFD8.o,tail8.data.o,ov_SC06_016_jr_80140608.o,tail9.data.o,ov_SC06_016_jr_8015444C.o,ov_SC06_016_jr_80154C24.o,ov_SC06_016_jr_801588CC.o,ov_SC06_016_jr_80159C84.o,tail10.data.o,ov_SC06_016_jr_8015A3C8.o,tail11.data.o,ov_SC06_016_jr_8015AE2C.o,tail12.data.o,ov_SC06_016_jr_8015C32C.o,tail13.data.o,ov_SC06_016_jr_8016AB6C.o,tail14.data.o,ov_SC06_016_jr_80171B4C.o,ov_SC06_016_jr_801734BC.o,tail15.data.o,ov_SC06_016_jr_801789AC.o,ov_SC06_016_jr_80178D40.o,tail16.data.o,ov_SC06_016_jr_8017A4AC.o,tail17.data.o,ov_SC06_016_jr_8017AE2C.o,tail18.data.o,ov_SC06_016_jr_8017C8D0.o,tail19.data.o,ov_SC06_016_jr_801816DC.o,tail20.data.o,ov_SC06_016_jr_801839D0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_016_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_016.o,ov_SC06_016_jr_8012ACE0.o,tail2.data.o,ov_SC06_016_jr_80135888.o,tail3.data.o,ov_SC06_016_jr_80135A4C.o,tail4.data.o,ov_SC06_016_jr_80135D20.o,tail5.data.o,ov_SC06_016_jr_801380E0.o,ov_SC06_016_o0c.o,tail6.data.o,ov_SC06_016_jr_8013F350.o,tail7.data.o,ov_SC06_016_jr_8013FFD8.o,tail8.data.o,ov_SC06_016_jr_80140608.o,tail9.data.o,ov_SC06_016_jr_8015444C.o,ov_SC06_016_jr_80154C24.o,ov_SC06_016_jr_801588CC.o,ov_SC06_016_jr_80159C84.o,tail10.data.o,ov_SC06_016_jr_8015A3C8.o,tail11.data.o,ov_SC06_016_jr_8015AE2C.o,tail12.data.o,ov_SC06_016_jr_8015C32C.o,tail13.data.o,ov_SC06_016_jr_8016AB6C.o,tail14.data.o,ov_SC06_016_jr_80171B4C.o,ov_SC06_016_jr_801734BC.o,tail15.data.o,ov_SC06_016_jr_801789AC.o,ov_SC06_016_jr_80178D40.o,tail16.data.o,ov_SC06_016_jr_8017A4AC.o,tail17.data.o,ov_SC06_016_jr_8017AE2C.o,tail18.data.o,ov_SC06_016_jr_8017C8D0.o,tail19.data.o,ov_SC06_016_jr_801816DC.o,ov_SC06_016_jr_801839D0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_016/ov_SC06_016.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_016/ov_SC06_016_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_016/ov_SC06_016_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 @@ -4314,6 +4314,7 @@ build/src/ov_SC06_016/ov_SC06_016_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_016/ov_SC06_016_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_016/ov_SC06_016_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_016/ov_SC06_016_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_016/ov_SC06_016_jr_801816DC.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_016/ov_SC06_016_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118 ov_SC06_016_CHECK_SHA := config/check.ov_SC06_016.sha ov_SC06_016_SYMBOLS := config/symbols.ov_SC06_016.txt diff --git a/config/splat.ov_SC06_016.yaml b/config/splat.ov_SC06_016.yaml index 03769f36e3..43f83ff68c 100644 --- a/config/splat.ov_SC06_016.yaml +++ b/config/splat.ov_SC06_016.yaml @@ -168,9 +168,8 @@ segments: - [0x76110, .rodata, ov_SC06_016_jr_8017C8D0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76130, data, tail19] - [0x76150, .rodata, ov_SC06_016_jr_801816DC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76168, data, tail20] - [0x7617c, .rodata, ov_SC06_016_jr_801839D0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76190, data, tail21] + - [0x76190, data, tail20] - [0x78114, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x78117] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/src/md_MAIN_011/md_MAIN_011.c b/src/md_MAIN_011/md_MAIN_011.c index 3348aeb126..b58f897717 100644 --- a/src/md_MAIN_011/md_MAIN_011.c +++ b/src/md_MAIN_011/md_MAIN_011.c @@ -102,7 +102,17 @@ void func_800CFBF0(void) { } -INCLUDE_ASM("asm/md_MAIN_011/nonmatchings/md_MAIN_011", func_800CFC58); +extern s32 func_800167F0(s32 a0); + +void func_800CFC58(void) { + if ((func_800167F0(4) & 0xffff) != 0) { + func_800118AC(); + func_80011B7C(0); + func_8001C044(); + func_80015310(); + } +} + void func_800CFCBC(void) { extern s32 D_800D4C94; diff --git a/src/ov_SC06_016/ov_SC06_016_jr_801816DC.c b/src/ov_SC06_016/ov_SC06_016_jr_801816DC.c index 681fa590f9..cf032e552e 100644 --- a/src/ov_SC06_016/ov_SC06_016_jr_801816DC.c +++ b/src/ov_SC06_016/ov_SC06_016_jr_801816DC.c @@ -3110,7 +3110,61 @@ extern s16 D_8019F71C; void func_80181B60(void) { } -INCLUDE_ASM("asm/ov_SC06_016/nonmatchings/ov_SC06_016_jr_801816DC", func_80181B68); +extern int func_80178970(void); +extern void func_80178D18(void); +extern int func_8001AAA0(void); +extern s32 func_80178B18(s32 param_1, s32 param_2); +extern s32 func_8012BEE8(s32 a0); +extern void func_8017BF08(void *a0, void *a1, s32 a2, s32 a3); +extern void func_8017E114(s32 arg0); + +extern s32 D_80126B58; +extern s32 D_80188AC4; +extern s16 D_8019F724; + +void func_80181B68(s32 arg0) { + register s32 s0 __asm__("$16"); + register s32 a0 __asm__("$4"); + + s0 = arg0; + a0 = (s32)&D_80126B58; + + switch (*(u16 *)(s0 + 0x34)) { + case 0: + if (*(s16 *)(a0 + 0xE) >= 0x81) { + func_80178B18(s0, (s32)&D_80188AC4); + *(u16 *)(s0 + 0x34) = *(u16 *)(s0 + 0x34) + 1; + } + return; + + case 1: + *(u16 *)(s0 + 0x34) = *(u16 *)(s0 + 0x34) + 1; + /* fall through */ + case 2: + if (((s32 (*)(s32))func_80178970)(s0) == 0) { + return; + } + ((void (*)(s32))func_80178D18)(s0); + *(s32 *)(s0 + 0x1C) = 3; + *(s32 *)(s0 + 0xDC) = 1; + *(u16 *)(s0 + 0x34) = *(u16 *)(s0 + 0x34) + 1; + return; + + case 3: + if (((s32 (*)(s32))func_8001AAA0)(0x7D) != 0) { + *(u16 *)(s0 + 0x34) = *(u16 *)(s0 + 0x34) + 1; + } + return; + + case 4: + if (func_8012BEE8(s0)) { + func_8017BF08((void *)(s0 + 0x76), (void *)&D_8019F724, 7, 0xDC); + func_8017E114(s0); + } + return; + } +} + extern s32 func_8012BEE8(s32 a0); extern void func_8017E114(s32 a0);