From afd1aeea4f10ff25100b68a2dd16694fc447cee5 Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Thu, 16 Jul 2026 19:35:18 -0600 Subject: [PATCH] feat(phase-29 T6): broad --fix-def-sig harvest +19 (def-sig lever tapped beyond the mega-pools) - fleet-wide --band substantial (17) + tiny (2) with --fix-def-sig (all families) = 19 more members; the def-sig conflict was concentrated in the 2 tiny-IMM mega-pools (already banked, now not-stub) - R22 clean-fleet 140/140 byte-identical; pure-reduction; dedup 1840/0; 0 NON_MATCHING (G4) - fleet instr 71.0% (steady) / distinct 53.2->53.3% / fn-count 86.30%. Task-6 mega-pool track complete; permuter backlog (grinder/permuter_ils close-1..4) remains as the other Task-6 half --- docs/progress.fleet.md | 14 +- phase-ends/CURRENT_PHASE.md | 6 + src/ov_SC07_010/ov_SC07_010.c | 335 ++++++++++++++- src/ov_SC07_010/ov_SC07_010_o2b.c | 666 +++++++++++++++++++++++++++++- src/ov_SC07_011/ov_SC07_011.c | 311 +++++++++++++- 5 files changed, 1306 insertions(+), 26 deletions(-) diff --git a/docs/progress.fleet.md b/docs/progress.fleet.md index 67778f70a..c8ecdf94e 100644 --- a/docs/progress.fleet.md +++ b/docs/progress.fleet.md @@ -4,15 +4,15 @@ # cross-binary collapsible-byte leverage: docs/duplicates.cross.md. # THREE progress metrics (all matter — see the labels): -FLEET fn-count byte-ident: 305250 / 353722 = 86.30% (REAL+LINKED+empties; FUNCTION-count, ×134-inflated — one crack counts per overlay) -FLEET instr-weighted : 9283489 / 13081451 = 71.0% (shipped .text across resident+138 overlays; the decomp.dev-DISPLAY number) -FLEET distinct-code(uniq): 2968120 / 5574674 = 53.2% (59884/87459 unique fns; the DISTINCT-RE number) +FLEET fn-count byte-ident: 305269 / 353722 = 86.30% (REAL+LINKED+empties; FUNCTION-count, ×134-inflated — one crack counts per overlay) +FLEET instr-weighted : 9285844 / 13081451 = 71.0% (shipped .text across resident+138 overlays; the decomp.dev-DISPLAY number) +FLEET distinct-code(uniq): 2969937 / 5574674 = 53.3% (59896/87459 unique fns; the DISTINCT-RE number) MAIN game-code weighted : 436 / 60201 = 0.7% (Phase-27 T10; SEPARATE — LINKED-excluding Ghidra sig dated 2026-06-14, PROVISIONAL until a fresh/complete main sig; NOT folded into the fleet number) -FLEET REAL substantive : 303395 (of which dedup-shared 233341 via 1840 groups / 233385 instances) +FLEET REAL substantive : 303414 (of which dedup-shared 233341 via 1840 groups / 233385 instances) FLEET LINKED PsyQ objs : 959 FLEET NON_MATCHING : 7 (0 in any default build — G4) -FLEET INCLUDE_ASM stubs : 48465 +FLEET INCLUDE_ASM stubs : 48446 FLEET matchable : 353722 | binary | REAL | shared | LINKED | byte-ident | matchable | byte-ident % | @@ -155,5 +155,5 @@ FLEET matchable : 353722 | ov_SC07_007 | 1974 | 1544 | 0 | 2058 | 2614 | 78.7% | | ov_SC07_008 | 2166 | 1693 | 0 | 2166 | 2386 | 90.8% | | ov_SC07_009 | 2176 | 1693 | 0 | 2178 | 2430 | 89.6% | -| ov_SC07_010 | 1972 | 1544 | 0 | 2055 | 2526 | 81.4% | -| ov_SC07_011 | 1970 | 1543 | 0 | 2050 | 2450 | 83.7% | +| ov_SC07_010 | 1987 | 1544 | 0 | 2070 | 2526 | 81.9% | +| ov_SC07_011 | 1974 | 1543 | 0 | 2054 | 2450 | 83.8% | diff --git a/phase-ends/CURRENT_PHASE.md b/phase-ends/CURRENT_PHASE.md index 37f81f505..693dc41a2 100644 --- a/phase-ends/CURRENT_PHASE.md +++ b/phase-ends/CURRENT_PHASE.md @@ -160,6 +160,12 @@ conditional) · main-EXE/B9 + GLM/B6 + resident's 14 walls (P30) · behemoths B7 fleet **instr 70.4→71.0% · distinct 52.3→53.2% · fn-count 84.94→86.30%**; dedup 1840/0; 0 NON_MATCHING. §54 cookbook + R31 decision-log. The 4th "reproduce the build step" instance (§53-carve, -O0-flag, now the member's canonical DECLARATION). `--fix-def-sig` likely should be default-on for the h_seq path. +- **2026-07-16 — broad `--fix-def-sig` harvest = TAPPED beyond the mega-pools (+19).** Fleet-wide + `--band substantial` (17) + `--band tiny` (2) with `--fix-def-sig` (all families, not just the 2 pools) = + **19 more members** banked (the def-sig conflict was highly concentrated in the 2 tiny-IMM mega-pools; + 8491 tiny members now skip as not-stub). R22 clean-fleet **140/140**; fleet instr 71.0% (steady) / + distinct 53.2→53.3% / fn-count 86.30%. Task 6 mega-pool track COMPLETE. **Remaining Task 6:** the permuter + backlog sweep (the 550 close-1..4 drafts via grinder/permuter_ils) — separate track, not yet run. - **2026-07-16 — Task 2 (Arm A) DONE = swing verdict → banked fact + wall characterized.** New tool `tools/rollout_o0_cluster.py` + Makefile `O0_CLUSTER_OBJS` -O0 wildcard. Carved 4 SC07 tail overlays; byte-neutrality gate (clean R22): **ov_SC07_010 byte-identical, 006/007/011 FAIL** (+0x20 splat diff --git a/src/ov_SC07_010/ov_SC07_010.c b/src/ov_SC07_010/ov_SC07_010.c index 1d5ff460c..82cf4723e 100644 --- a/src/ov_SC07_010/ov_SC07_010.c +++ b/src/ov_SC07_010/ov_SC07_010.c @@ -1552,7 +1552,78 @@ INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_80131A34); DEFINE_func_80131AC8() /* dedup: shared engine-core @0x80131ac8 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_80131B14); +extern void func_80019064(void *a0); +extern void func_8012B23C(s32 a0); +extern void func_8012B2CC(s32 a0); +extern void func_8016AA50(int, int); +extern void func_8016B428(int); + +// @class: regalloc-order +// @stuck: none — MATCH (89 ins). Reconcile: TU canonical decl is `void func_80131B14(void)` +// (ov_SC01_077_a.c L1676/L1756; callers cast to (void(*)(int)) when passing p), so the def MUST be +// (void) or cc1 hard-errors `conflicting types` (exit 33). §42c lever #6: capture incoming $a0 into a +// NORMAL pseudo (`register u8 *a0v __asm__("$4"); u8 *p = a0v;`) so p gets a callee-saved home ($s0). +// func_8012B2CC/func_8012B23C are file-scope DEFINE'd here (split L740/L744) as void(s32) — do NOT redeclare; +// the (void(*)(void*)) cast on the bare name is byte-neutral. Body keys: e(0x5E) as s32 not u8 (kills the +// compare-time andi 0xff); f76 dual-width via per-access casts (lhu in the decrement, lh in the <=0 compare); +// the p->f20 reload split into TWO separate temps so the 2nd load takes $v0 not $v1. + +void func_80131B14() { + register u8 *a0v __asm__("$4"); + u8 *p = a0v; + + extern void func_8002A520(void *); + extern void func_8002A790(void *); + extern u8 D_80182480; + + s32 e = *(u8 *)(p + 0x5E); + + if (*(s16 *)(p + 0x60) != 0) { + if (e == 0x1D) { + *(s16 *)(p + 0x82) = 0; + *(s16 *)(p + 0x7C) = *(u16 *)(p + 0x06); + *(s16 *)(p + 0x7E) = *(u16 *)(p + 0x0A); + *(s16 *)(p + 0x80) = *(u16 *)(p + 0x0E); + } + { + s32 dec; + s32 q = *(s32 *)(p + 0x78); + if (q != 0) { + dec = ((s32)*(s16 *)(p + 0x60) * (s32)*(s16 *)(q + 0x30)) >> 12; + if (dec <= 0) dec = 1; + } + *(u16 *)(p + 0x76) = *(u16 *)(p + 0x76) - dec; + } + ((void (*)(void *))func_8016AA50)(p); + if (*(u16 *)(p + 0x82) & 1) { + ((void (*)(void *))func_8016B428)(p); + ((void(*)(void *))func_80019064)(&D_80182480); + } + } + + *(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE; + + if (e != 0x1D) { + if (*(u8 *)(p + 0xC8)) func_8002A520(p); + if (*(u8 *)(p + 0xC9)) func_8002A790(p); + } + + if (*(s16 *)(p + 0x76) <= 0) *(s16 *)(p + 0x5C) = 0; + + { + s32 r = *(s32 *)(p + 0x20); + *(s16 *)(r + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF; + { + s32 r2 = *(s32 *)(p + 0x20); + *(s16 *)(r2 + 0x14) = 0; + *(s16 *)(r2 + 0x10) = 0; + } + } + + ((void (*)(void *))func_8012B2CC)(p); + ((void (*)(void *))func_8012B23C)(p); +} + DEFINE_func_80131C78() /* dedup: shared engine-core @0x80131c78 (src/shared) */ @@ -2620,11 +2691,267 @@ INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_80135D20); INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_80135EB0); -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_80136334); -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_801365B8); +s32 func_80136334(void *arg0, s32 arg1, s32 arg2) { + + extern u8 D_80126720[]; + extern Box_80133784 * D_80182550; + extern Box_80133784 * D_80182554; + extern s16 *D_80182558; + extern u8 D_8018255C; + extern u8 D_801152A8[]; + extern s16 D_801152AA; + extern s16 D_801152AC; + extern s16 D_80126722; + extern s16 D_80126724; + register s32 a1v __asm__("$11"); + register s32 a2v __asm__("$12"); + register s32 n __asm__("$5"); + register s16 *b4 __asm__("$7"); + s32 d; + s32 dx; + s32 denom; + s32 result; + s32 frame_pad[2]; + (void)&frame_pad; + __asm__("" : "=r"(a1v) : "0"(arg1)); + a2v = arg2; + + if (!(arg1 & 1)) { + dx = (s16) arg2 - (*(s16 **)&D_80182550)[2]; + d = dx; + denom = -(*(s16 **)&D_8018255C)[2]; + } else { + denom = (*(s16 **)&D_8018255C)[2]; + d = (*(s16 **)&D_80182550)[2] - (s16) arg2; + dx = -d; + } + n = -d; + { + register s16 *b8 __asm__("$6") = *(s16 **)&D_8018255C; + u16 *ac = *(u16 **)&D_80182550; + b4 = D_80182558; + b4[0] = ac[0] + n * b8[0] / denom; + b4[1] = ac[1] + n * b8[1] / denom; + b4[2] = ac[2] + dx; + } + + if (b4[0] < M2C_FIELD(arg0, s16 *, 4)) return 0; + if (M2C_FIELD(arg0, s16 *, 6) < b4[0]) return 0; + if (b4[1] < M2C_FIELD(arg0, s16 *, 8)) return 0; + if (M2C_FIELD(arg0, s16 *, 0xA) < b4[1]) return 0; + if (a1v & 0x8000) { + u16 *b0 = *(u16 **)&D_80182554; + b4[0] = b0[0]; + b4[1] = b0[1]; + } + D_801152AA = 0; + (*(s16 *)D_801152A8) = 0; + if (a1v & 1) { + D_80182558[2] = a2v + 2; + __asm__ __volatile__(""); + D_801152AC = 0xFFF; + } else { + D_801152AC = -0xFFF; + D_80182558[2] = a2v - 2; + } + __asm__ __volatile__("" :: "r"(a1v), "r"(a2v)); + (*(s16 *)D_80126720) = (M2C_FIELD(arg0, s16 *, 4) + M2C_FIELD(arg0, s16 *, 6)) >> 1; + D_80126722 = (M2C_FIELD(arg0, s16 *, 8) + M2C_FIELD(arg0, s16 *, 0xA)) >> 1; + result = 1; + D_80126724 = (M2C_FIELD(arg0, s16 *, 0xC) + M2C_FIELD(arg0, s16 *, 0xE)) >> 1; + return result; +} + + + +// @class: regalloc-order — F-band exemplar func_801365B8 (x134). Real-TU reconciled (rtu_match). +// D_80182550/B0/B8 file-scope `extern u8` holding pointers -> read via *(T**)&sym (§42c-2). +// D_80182558 file-scope `extern s16*` -> use directly. D_80126720 file-scope `extern u8[]` +// -> single store via *(s16*)D_80126720. D_801152A8/AA/AC, D_80126722/24 block-scope externs +// (siblings use block-scope; gcc-2.7.2 does not cross-conflict block-scope externs). +s32 func_801365B8(void *arg0, s32 arg1, s32 arg2) { + + extern u8 D_80126720[]; + extern Box_80133784 * D_80182550; + extern Box_80133784 * D_80182554; + extern s16 *D_80182558; + extern u8 D_8018255C; + extern u8 D_801152A8[]; + extern s16 D_801152AA; + extern s16 D_801152AC; + extern s16 D_80126722; + extern s16 D_80126724; + u16 *ac; + s16 *b8; + s16 *b4; + s16 temp_v0; + s16 temp_v1; + s32 var_a3; + s32 temp_a1; + s32 var_a1; + s32 var_v0; + s32 var_v1; + s32 a1c; + s32 a2c; + s32 cond; + register u32 zr __asm__("$0"); + + __asm__("addu %0,%1,$zero" : "=r"(a1c) : "r"(arg1)); + cond = arg1 & 1; + a2c = arg2 + zr; + if (!cond) { + var_v1 = (s16) arg2 - (*(s16 **)&D_80182550)[0]; + var_a1 = var_v1; + var_a3 = -(*(s16 **)&D_8018255C)[0]; + } else { + var_a3 = (*(s16 **)&D_8018255C)[0]; + var_v1 = (*(s16 **)&D_80182550)[0] - (s16) arg2; + var_a1 = -var_v1; + } + ac = *(u16 **)&D_80182550; + b4 = D_80182558; + b8 = *(s16 **)&D_8018255C; + b4[0] = ac[0] + var_a1; + temp_a1 = -var_v1; + b4[1] = ac[1] + (temp_a1 * b8[1]) / var_a3; + temp_v0 = ac[2] + (temp_a1 * b8[2]) / var_a3; + b4[2] = temp_v0; + var_v0 = 0; + if (temp_v0 < M2C_FIELD(arg0, s16 *, 0xC)) { + return var_v0; + } + if (M2C_FIELD(arg0, s16 *, 0xE) < temp_v0) { + return var_v0; + } + temp_v1 = b4[1]; + if (temp_v1 < M2C_FIELD(arg0, s16 *, 8)) { + return var_v0; + } + if (M2C_FIELD(arg0, s16 *, 0xA) < temp_v1) { + return var_v0; + } + __asm__("" :: "r"(a1c)); + __asm__("" :: "r"(a1c)); + if (a1c & 0x8000) { + b4[1] = (s16) (*(u16 **)&D_80182554)[1]; + b4[2] = (s16) (*(u16 **)&D_80182554)[2]; + } + D_801152AC = 0; + D_801152AA = 0; + if ((a1c & 1) != 0) { + *(s16 *)D_801152A8 = 0xFFF; + M2C_FIELD(D_80182558, s16 *, 0) = a2c + 2; + } else { + *(s16 *)D_801152A8 = -0xFFF; + M2C_FIELD(D_80182558, s16 *, 0) = a2c - 2; + } + *(s16 *)D_80126720 = (s16) ((s32) (M2C_FIELD(arg0, s16 *, 4) + M2C_FIELD(arg0, s16 *, 6)) >> 1); + D_80126722 = (s16) ((s32) (M2C_FIELD(arg0, s16 *, 8) + M2C_FIELD(arg0, s16 *, 0xA)) >> 1); + var_v0 = 1; + D_80126724 = (s16) ((s32) (M2C_FIELD(arg0, s16 *, 0xC) + M2C_FIELD(arg0, s16 *, 0xE)) >> 1); + return var_v0; +} + + + +// @class: pointer-type — pointer-vs-array reconcile for func_80136824 (ov_SC01_077_a) +// D_80182550/B0/B8 are file-scope `extern u8`, D_80182558 is `extern s32 []`; each HOLDS a +// pointer value that the target loads via lw then derefs. Read as pointer via *(T**)&sym. +// D_80182558 must be a SCALAR pointer (not s32[]) — as an array it decays and gcc CSEs the +// base address into a held reg (lui;addiu;lw 0(reg)) across the 3 reloads; as a scalar +// pointer it folds %lo (lui;lw %lo). Retype all 3 file-TU occurrences (byte-neutral: the +// siblings read it once via *(u16**)&sym == direct lw either way). + +s32 func_80136824(s32 arg0, s32 arg1, s32 arg2) { + + extern u8 D_80126720[]; + extern Box_80133784 * D_80182550; + extern Box_80133784 * D_80182554; + extern s16 *D_80182558; + extern u8 D_8018255C; + extern u8 D_801152A8[]; + extern s16 D_801152AA; + extern s16 D_801152AC; + extern s16 D_80126722; + extern s16 D_80126724; + + register u16 *ac __asm__("$4"); + register s16 *b8 __asm__("$6"); + register s16 *b4 __asm__("$9"); + register s32 r __asm__("$3"); + register s32 pos __asm__("$12"); + register s32 a1v __asm__("$5"); + s16 temp_v0; + s16 temp_v1; + s32 var_a3; + s16 var_v0_3; + s32 temp_a1; + s32 var_t0; + s32 var_v1; + s16 *b4b; + u16 *p; + + __asm__ ("" : "=r"(a1v) : "0"(arg1)); + pos = arg2; + if (!(a1v & 1)) { + var_t0 = (s16) arg2 - (*(s16 **)&D_80182550)[1]; + var_v1 = var_t0; + var_a3 = -(*(s16 **)&D_8018255C)[1]; + } else { + var_a3 = (*(s16 **)&D_8018255C)[1]; + var_v1 = (*(s16 **)&D_80182550)[1] - (s16) arg2; + var_t0 = -var_v1; + } + b8 = (*(s16 **)&D_8018255C); + ac = (*(u16 **)&D_80182550); + b4 = D_80182558; + temp_a1 = -var_v1; + r = (temp_a1 * b8[0]) / var_a3; + b4[0] = ac[0] + r; + b4[1] = ac[1] + var_t0; + r = (temp_a1 * b8[2]) / var_a3; + temp_v0 = ac[2] + r; + b4[2] = temp_v0; + temp_v1 = b4[0]; + if (temp_v1 < M2C_FIELD(((void *)arg0), s16 *, 4)) { + return 0; + } + if (M2C_FIELD(((void *)arg0), s16 *, 6) < temp_v1) { + return 0; + } + if (temp_v0 < M2C_FIELD(((void *)arg0), s16 *, 0xC)) { + return 0; + } + if (M2C_FIELD(((void *)arg0), s16 *, 0xE) < temp_v0) { + return 0; + } + if (arg1 & 0x8000) { + p = (*(u16 **)&D_80182554); + b4[0] = (s16) p[0]; + b4[2] = (s16) p[2]; + } + D_801152AC = 0; + (*(s16 *)D_801152A8) = 0; + if (arg1 & 1) { + b4b = D_80182558; + D_801152AA = 0xFFF; + __asm__ __volatile__(""); + var_v0_3 = pos + 2; + } else { + b4b = D_80182558; + D_801152AA = -0xFFF; + __asm__ __volatile__(""); + var_v0_3 = pos - 2; + } + b4b[1] = var_v0_3; + __asm__ __volatile__("" :: "r"(pos)); + (*(s16 *)D_80126720) = (s16) ((s32) (M2C_FIELD(((void *)arg0), s16 *, 4) + M2C_FIELD(((void *)arg0), s16 *, 6)) >> 1); + D_80126722 = (s16) ((s32) (M2C_FIELD(((void *)arg0), s16 *, 8) + M2C_FIELD(((void *)arg0), s16 *, 0xA)) >> 1); + D_80126724 = (s16) ((s32) (M2C_FIELD(((void *)arg0), s16 *, 0xC) + M2C_FIELD(((void *)arg0), s16 *, 0xE)) >> 1); + return 1; +} -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010", func_80136824); // @class: schedule diff --git a/src/ov_SC07_010/ov_SC07_010_o2b.c b/src/ov_SC07_010/ov_SC07_010_o2b.c index 4ce9b0dc8..ac7795e6f 100644 --- a/src/ov_SC07_010/ov_SC07_010_o2b.c +++ b/src/ov_SC07_010/ov_SC07_010_o2b.c @@ -382,7 +382,149 @@ INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_8013D53C); INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_8013D8FC); -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_8013D9B0); +extern void func_800599B8(s32 a0, s32 a1); +#define gte_ldIR0z() __asm__ __volatile__("mtc2 $0, $8") +#define gte_ldrgb(p) __asm__ __volatile__("lwc2 $6, 0(%0)" :: "r"(p) : "memory") +#define gte_ldIRGB(p) __asm__ __volatile__("lwc2 $28, 0(%0)" :: "r"(p) : "memory") +#define gte_dpcl() __asm__ __volatile__("nop\n\tnop\n\tdpcl") +#define gte_stORGB(p) __asm__ __volatile__("swc2 $29, 0(%0)" :: "r"(p) : "memory") + +void func_8013D9B0(int param_1) +{ + + extern void *D_801A6AAC; + extern s16 *D_801A6AB4; + extern s32 D_801A6AC4; + extern s32 D_801A6ACC; + + u8 buf[0x20]; + register s32 uVar13 __asm__("$16"); + register u16 *psVar14 __asm__("$17"); + register u16 *psVar15 __asm__("$18"); + register s32 uVar16 __asm__("$19"); + register void *r0 __asm__("$20"); + register u16 *puVar10 __asm__("$11"); + register u16 *puVar9 __asm__("$10"); + register s32 iVar11 __asm__("$13"); + register s32 iVar12 __asm__("$14"); + u16 sVar4; + register u32 uVar5 __asm__("$3"); + register u32 uVar7 __asm__("$6"); + register u32 uVar1 __asm__("$7"); + register u32 uVar6 __asm__("$4"); + register u32 uVar8 __asm__("$8"); + register u32 uVar3 __asm__("$9"); + + psVar15 = (*(u16 * *)&D_801A6AB4); + if (psVar15 != 0) { + sVar4 = *psVar15; + *(u32 *)(buf + 8) = (*(u32 * *)&D_801A6AAC)[param_1]; + D_801A6ACC = -1; + uVar16 = 0; + if (sVar4 != 0xff) { + r0 = buf + 8; + psVar14 = psVar15 + 6; + do { + iVar11 = 0; + if (sVar4 == 9) { + *(s16 *)(buf + 0) = psVar14[-4]; + __asm__ __volatile__("" ::: "memory"); + *(s16 *)(buf + 2) = psVar14[-3]; + __asm__ __volatile__("" ::: "memory"); + *(s16 *)(buf + 4) = psVar14[-2]; + __asm__ __volatile__("" ::: "memory"); + *(s16 *)(buf + 6) = psVar14[-1]; + __asm__ __volatile__("" ::: "memory"); + { + register s32 mw __asm__("$3") = (s32)((s16 *)psVar14)[-2]; + register s32 mh __asm__("$2") = (s32)((s16 *)psVar14)[-1]; + iVar12 = mw * mh; + } + uVar13 = 0; + puVar10 = *(u16 **)psVar14; + { + register s32 boff __asm__("$2") = iVar12 * 2; + register u16 *pi __asm__("$5"); + pi = (u16 *)((s32)puVar10 + boff); + __asm__ __volatile__("" : "=r"(pi) : "0"(pi)); + puVar9 = pi; + } + if (0 < iVar12) { + do { + register u32 pix __asm__("$2"); + register u32 out __asm__("$2"); + u32 result; + *(u32 *)(buf + 0xc) = (u32)*puVar10; + pix = (u32)*puVar9; + uVar5 = pix & 0x1f; + uVar7 = pix & 0x3e0; + uVar1 = pix & 0x7c00; + { + void *p1; + register void *pa __asm__("$2"); + register void *pb __asm__("$12"); + __asm__ __volatile__(""); + p1 = buf + 0xc; + __asm__ __volatile__("" : "=r"(p1) : "0"(p1)); + gte_ldIR0z(); + gte_ldrgb(r0); + gte_ldIRGB(p1); + gte_dpcl(); + pa = buf + 0x10; + __asm__ __volatile__("" : "=r"(pa) : "0"(pa)); + pb = pa; + gte_stORGB(pb); + } + out = *(u32 *)(buf + 0x10); + uVar6 = out & 0x1f; + uVar8 = out & 0x3e0; + uVar3 = out & 0x7c00; + if (uVar5 != uVar6) { + register s32 c __asm__("$2"); + uVar13 = 1; + if ((s32)uVar5 < (s32)uVar6) uVar5 = uVar5 + 1; + c = (s32)uVar6 < (s32)uVar5; + if (c) uVar5 = uVar5 - 1; + } + if (uVar7 != uVar8) { + register s32 c __asm__("$2"); + uVar13 = 1; + if ((s32)uVar7 < (s32)uVar8) uVar7 = uVar7 + 0x20; + c = (s32)uVar8 < (s32)uVar7; + if (c) uVar7 = uVar7 - 0x20; + } + if (uVar1 != uVar3) { + register s32 c __asm__("$2"); + uVar13 = 1; + if ((s32)uVar1 < (s32)uVar3) uVar1 = uVar1 + 0x400; + c = (s32)uVar3 < (s32)uVar1; + if (c) uVar1 = uVar1 - 0x400; + } + result = uVar5 | uVar7 | uVar1 | (*(u32 *)(buf + 0xc) & 0x8000); + if (result == 0 && *(u32 *)(buf + 0xc) != 0) { + result = 0x8000; + } + *puVar9 = (u16)result; + puVar9 = puVar9 + 1; + iVar11 = iVar11 + 1; + puVar10 = puVar10 + 1; + } while (iVar11 < iVar12); + } + if (uVar13 != 0) { + ((void (*)(void *))func_800599B8)(buf); + } + uVar16 = uVar16 | uVar13; + } + psVar15 = psVar15 + 8; + sVar4 = *psVar15; + psVar14 = psVar14 + 8; + } while (sVar4 != 0xff); + } + D_801A6AC4 = uVar16; + } + return; +} + // @class: struct @@ -1799,7 +1941,55 @@ void func_80143C98(void *a0) { DEFINE_func_80143CD4() /* dedup: shared engine-core @0x80143cd4 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_80143D28); + +// @class: regalloc-order +// @stuck: none — MATCH (80 ins, relocation-masked). iVar2/iVar3 pinned $s1/$s2; sVar4 is an +// int set BEFORE the call so it naturally takes callee-saved $s3; chained assignment +// a=b=c=sVar4 materializes the value once (the addu $v0,$s3,$zero move) + delay-slot store. + + /* size 0x0c */ + +extern void ApplyMatrixSV(void *a0, void *a1, void *a2); +extern s32 func_8012BEE8(s32 a0); +extern void func_8012C218(void *a0); + +void func_80143D28(s32 param_1) { + + extern MatEntry D_8018391C[]; + register s32 iVar3 __asm__("$18") = *(s32 *)(param_1 + 0x20); /* $s2 */ + register s32 iVar2 __asm__("$17") = *(s32 *)(param_1 + 0x64); /* $s1 */ + MatEntry *p = &D_8018391C[*(s16 *)(param_1 + 0x70)]; + s32 sVar4; + s32 iVar1; + + *(s16 *)(iVar3 + 0x14) = p->f8; + *(u16 *)(iVar3 + 0x12) = *(u16 *)(iVar3 + 0x12) + p->fa; + sVar4 = 0x1000; + ApplyMatrixSV((void *)(*(s32 *)(param_1 + 0x20) + 0x34), p, (void *)(param_1 + 0x50)); + + if (*(s16 *)(param_1 + 0xfe) == 0 && + (iVar2 == 0 || *(s16 *)(iVar2 + 0x36) != *(s16 *)(param_1 + 0xfc) || + *(u8 *)(iVar2 + 0xc1) != 6)) { + if (0x10 < *(s32 *)(param_1 + 0x1c)) { + *(s32 *)(param_1 + 0x1c) = 0x10; + } + *(s16 *)(param_1 + 0xfe) = 1; + } + + iVar1 = *(s32 *)(param_1 + 0x1c); + if (iVar1 < 0x11) { + sVar4 = iVar1 << 8; + } + if (0x73 < iVar1) { + sVar4 = (0x78 - iVar1) << 10; + } + *(s16 *)(iVar3 + 0x18) = *(s16 *)(iVar3 + 0x1a) = *(s16 *)(iVar3 + 0x1c) = sVar4; + + if (func_8012BEE8(param_1)) { + func_8012C218((void *)param_1); + } +} + @@ -1831,7 +2021,80 @@ void func_80144054(void *a0) { } -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_80144090); + +// @class: regalloc-order +// @stuck: 154/154 ins structural match (callees/consts/ctrl-flow/stack/GPU-packet all byte-correct); residual 25 = caller-saved temp-reg coalescing in the final ring-vertex block (target reuses dead $s0=iVar3 for iVar3-(iVar4>>6) subu where gcc reuses iVar4>>6's reg; iVar4 mflo -> $a3 vs target $v0) + 2-ins schedule swap of giv-increment vs iVar2*4 -> permuter grinder territory (§27 step-5) + + /* 0x14 stride */ + +extern void *func_80010A08(s32); +extern void func_8004914C(void *a0); +extern void func_800491AC(void *a0); +extern s32 RotTransPers(s32, s32, s32 *, s32 *); +extern s32 func_8004787C(s32 a0); +extern s32 func_80047948(s32 a0); +extern s32 AddPrim(s32, void *); + +void func_80144090(s32 param_1) { + + extern OtBlk D_800A651C[]; + extern u8 D_800AF648; + extern short D_800B9A02; + void *iVar1; + s32 iVar2; + s32 iVar3; + s32 iVar4; + s32 iVar5; + s32 iVar6; + struct { + s16 v10[4]; + u16 sxy[2]; + s32 p; + s32 flag; + } L; + + iVar1 = func_80010A08(0x140); + if (iVar1 != 0) { + *(s32 *)(param_1 + 4) = *(s32 *)(param_1 + 4) + *(s32 *)(param_1 + 0x10); + *(s32 *)(param_1 + 8) = *(s32 *)(param_1 + 8) + *(s32 *)(param_1 + 0x14); + *(s32 *)(param_1 + 0xc) = *(s32 *)(param_1 + 0xc) + *(s32 *)(param_1 + 0x18); + L.v10[0] = *(u16 *)(param_1 + 6); + L.v10[1] = *(u16 *)(param_1 + 0xa); + L.v10[2] = *(u16 *)(param_1 + 0xe); + func_8004914C(&D_800AF648); + func_800491AC(&D_800AF648); + iVar2 = RotTransPers((s32)L.v10, (s32)L.sxy, &L.p, &L.flag); + iVar2 = iVar2 + 4; + if (iVar2 < 0) { + iVar2 = 0; + } + iVar6 = 0; + do { + *(s32 *)((u8 *)iVar1 + 4) = 0xffffff; + *(u8 *)((u8 *)iVar1 + 3) = 4; + *(u8 *)((u8 *)iVar1 + 7) = 0x20; + if (*(s32 *)(param_1 + 0x1c) - 6 < 1) { + *(s16 *)((u8 *)iVar1 + 8) = L.sxy[0]; + *(s16 *)((u8 *)iVar1 + 0xa) = L.sxy[1]; + } else { + iVar5 = func_8004787C(iVar6); + *(s16 *)((u8 *)iVar1 + 8) = L.sxy[0] + ((iVar5 * ((*(s32 *)(param_1 + 0x1c) - 6) << 4)) >> 0xc); + iVar5 = func_80047948(iVar6); + *(s16 *)((u8 *)iVar1 + 0xa) = L.sxy[1] + ((iVar5 * ((*(s32 *)(param_1 + 0x1c) - 6) << 4)) >> 0xc); + } + iVar3 = func_8004787C(iVar6) * (*(s32 *)(param_1 + 0x1c) << 4); + iVar4 = func_80047948(iVar6) * (*(s32 *)(param_1 + 0x1c) << 4); + iVar6 = iVar6 + 0x100; + *(s16 *)((u8 *)iVar1 + 0x10) = L.sxy[0] + ((iVar3 + (iVar4 >> 6)) >> 0xc); + *(s16 *)((u8 *)iVar1 + 0x12) = L.sxy[1] + ((iVar4 + (iVar3 >> 6)) >> 0xc); + *(s16 *)((u8 *)iVar1 + 0xc) = L.sxy[0] + ((iVar3 - (iVar4 >> 6)) >> 0xc); + *(s16 *)((u8 *)iVar1 + 0xe) = L.sxy[1] + ((iVar4 - (iVar3 >> 6)) >> 0xc); + AddPrim(D_800A651C[(u16)D_800B9A02].a + (iVar2 * 4), iVar1); + iVar1 = (u8 *)iVar1 + 0x14; + } while (iVar6 < 0x1000); + } +} + extern void func_8012C218(void *a0); @@ -2849,13 +3112,21 @@ DEFINE_func_80149284() /* dedup: shared engine-core @0x80149284 (src/shared) */ DEFINE_func_80149290() /* dedup: shared engine-core @0x80149290 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_80149350); +extern void func_8012F14C(s32); +void func_80149350(s32 arg0) { + func_8012F14C(*(s32 *)(arg0 + 0x20) + 0x34); +} + INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_80149374); INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_801493D0); -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_8014942C); +extern void func_8012F038(s32); +void func_8014942C(s32 arg0) { + func_8012F038(*(s32 *)(arg0 + 0x20) + 0x34); +} + INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_80149450); @@ -2992,7 +3263,61 @@ s32 func_80149FB0(s32 a0) { } -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_8014A048); +extern u8 func_8014BEF8(void); +extern void func_8012F14C(s32); +extern s32 func_80135260(s32, s32, s32, s32); +extern void func_8014A1B0(s32 a0, s32 a1); +s32 func_8014A048(s32 param_1) { + + extern u8 D_801202A0[]; + Loc L; + s32 s0; + s32 s2; + u32 s3; + if ((*(u32 *)(param_1 + 0x44) & 0x400) != 0) { + return 0; + } + if ((*(u16 *)(param_1 + 0xAC) & 0x80) == 0) { + if ((*(u16 *)(param_1 + 0xAC) & 0x10) == 0) { + return 0; + } + if (((s32 (*)(s32))func_8014BEF8)(param_1) == 0) { + goto ret0; + } + } + L.a30 = *(s16 *)(param_1 + 6); + L.a2e = *(s16 *)(param_1 + 0xA); + L.a2c = *(s16 *)(param_1 + 0xE); + L.a1e = -0x10; + L.a20 = 0; + L.a1c = -0x20; + ((void (*)(s32, s32, s32))func_8012F14C)(*(s32 *)(param_1 + 0x20) + 0x34, (s32)&L.a20, (s32)L.buf); + s3 = 0; + s2 = 0; + while (1) { + s0 = (s32)D_801202A0 + s2; + __asm__ __volatile__("" : "=r"(s0) : "0"(s0)); + if ((*(u16 *)s0 != 0) && + (*(s32 *)(s0 + 0x58) != 0) && + (*(s16 *)(s0 + 0xAA) == 0) && + (*(s32 *)(param_1 + 0x184) != s0) && + ((*(u16 *)(s0 + 0x5C) & 0x200) != 0) && + (((s32 (*)(s32, s32, s32, s32))func_80135260)(*(s32 *)(s0 + 0x20), *(s32 *)(s0 + 0x58), (s32)&L.a30, (s32)L.buf) != 0)) { + break; + } + s3++; + s2 += 0x10C; + if (s3 >= 0x60) { + return 0; + } + } + *(s32 *)(param_1 + 0x178) = s0; + func_8014A1B0(param_1, s0); + return 1; +ret0: + return 0; +} + DEFINE_func_8014A1B0() /* dedup: shared engine-core @0x8014a1b0 (src/shared) */ @@ -8720,7 +9045,136 @@ void func_80166654(void *a0) { INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_80166690); -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_80166994); +extern void func_801484B0(s32 a0, s32 a1); +extern void func_80148534(s32 a0, s32 a1); +extern void func_80149350(s32 arg0); +extern s32 func_80165FA4(s32 a0, s32 a1, s32 a2); + +/* func_80166994 — trail/afterimage ring recorder (0xC4-stride Trail records at D_801A6D20). + * param_2: 0=init, 1=advance(record), 2=fadeout; param_3: trail index (s16); param_4: divisor (s16). + * + * K&R definition: true s16 params => callee-side lazy per-use narrow/extend with raw pseudos + * (s3/t0/s4 hold raw a1/a2/a3; first-use extension allocates IN PLACE into the arg reg), while + * the promoted K&R type (int x4) stays compatible with the canon-sig s32 prototype in the TU. + * Returns s32 (v0=1 when the fadeout completes, else 0) => the //@EDIT above flips the split's + * canon-sig prototype return type, AND engine_core.h needs the once-global ec_edit (all 5 sites, + * byte-neutral: every caller discards the result): + * ec_edit old: "extern void func_80166994(s32 a0, s32 a1, s32 a2, s32 a3); \" + * ec_edit new: "extern s32 func_80166994(s32 a0, s32 a1, s32 a2, s32 a3); \" + * Without the ec_edit, cc1 hard-errors (conflicting types vs the void decls in DEFINE_ macros). + * + * Fully block-scoped (typedefs + externs inside the body) so the crack propagates ×134 via + * family_remap with zero file-scope footprint. No register pins. + */ +s32 func_80166994(param_1, param_2, param_3, param_4) + s32 param_1; + s16 param_2; + s16 param_3; + s16 param_4; +{ + typedef struct { s16 f0, f1, f2, f3, f4, f5; } TrailEntry; + typedef struct { u8 flag, idx, count, timer; TrailEntry e[16]; } Trail; + extern u8 D_801A6D20[]; + extern void RotTransSV(void *a0, void *a1, void *a2); + extern s32 VectorNormalSS(void *a0, void *a1); + + Trail *p = &((Trail *)D_801A6D20)[param_3]; + s32 uVar6 = *(s32 *)(param_1 + 0x34); + s16 v10[4]; + s16 v18[4]; + s16 v20[4]; + s16 v28[4]; + s16 out[4]; + s32 c; + + switch (param_2) { + case 0: + p->flag = 1; + p->count = 0; + p->idx = 0; + p->timer = 0xf4; + break; + case 1: + v20[0] = p->e[p->idx].f0; + v20[1] = p->e[p->idx].f1; + v20[2] = p->e[p->idx].f2; + v28[0] = p->e[p->idx].f3; + v28[1] = p->e[p->idx].f4; + v28[2] = p->e[p->idx].f5; + c = p->idx; + p->idx = c + 1; + if ((u8)(c + 1) > 0xf) { + p->idx = 0; + } + if (p->count < 0xf) { + p->count = p->count + 1; + } + break; + case 2: { + u8 bVar3 = p->timer - 0x10; + p->timer = bVar3; + if (bVar3 < 0x10) { + p->flag = 0; + return 1; + } + { + u8 bVar1 = p->count; + if (bVar1 >= 2 && (bVar3 >> 4) < bVar1) { + p->count = bVar1 - 1; + } + } + return 0; + } + } + + if (param_3 < 2) { + func_801484B0((s32)v10, (s32)v18); + } else { + func_80148534((s32)v10, (s32)v18); + } + func_80165FA4(uVar6, (s32)v10, (s32)v18); + ((void (*)(s32, s32, s32))func_80149350)(uVar6, (s32)v10, (s32)v10); + RotTransSV(v18, v18, out); + + if (param_2 != 0) { + v20[0] = (v10[0] + v20[0]) >> 1; + v20[1] = (v10[1] + v20[1]) >> 1; + v20[2] = (v10[2] + v20[2]) >> 1; + v28[0] = (v18[0] + v28[0]) >> 1; + v28[1] = (v18[1] + v28[1]) >> 1; + v28[2] = (v18[2] + v28[2]) >> 1; + v20[0] = v20[0] - v28[0]; + v20[1] = v20[1] - v28[1]; + v20[2] = v20[2] - v28[2]; + VectorNormalSS(v20, v20); + v20[0] = v28[0] + v20[0] / param_4; + v20[1] = v28[1] + v20[1] / param_4; + v20[2] = v28[2] + v20[2] / param_4; + p->e[p->idx].f0 = v20[0]; + p->e[p->idx].f1 = v20[1]; + p->e[p->idx].f2 = v20[2]; + p->e[p->idx].f3 = v28[0]; + p->e[p->idx].f4 = v28[1]; + p->e[p->idx].f5 = v28[2]; + c = p->idx; + p->idx = c + 1; + if ((u8)(c + 1) > 0xf) { + p->idx = 0; + } + if (p->count < 0xf) { + p->count = p->count + 1; + } + } + + p->e[p->idx].f0 = v10[0]; + p->e[p->idx].f1 = v10[1]; + p->e[p->idx].f2 = v10[2]; + p->e[p->idx].f3 = v18[0]; + p->e[p->idx].f4 = v18[1]; + p->e[p->idx].f5 = v18[2]; + return 0; +} + INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_80166F58); @@ -8851,7 +9305,42 @@ s32 func_80167DBC(s32 arg0, s32 arg1, s32 arg2) { } -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_80168070); +extern void func_80149350(s32 arg0); +extern void func_800D20C0(void *a0, void *a1, s32 a2); +extern void func_80017E68(void *a0, void *a1); +extern void func_800D23D0(void *a0); +extern void ApplyMatrixSV(void *a0, void *a1, void *a2); +extern void ApplyTransposeMatrixLV(void *a0, void *a1, void *a2); +extern void RotMatrixYXZ(void *a0, void *a1); +extern s32 ratan2(s32 a0, s32 a1); +void func_80168070(s32 param_1, s16 *param_2, s16 *param_3, void *param_4) { + + extern s32 D_801269A4; + extern s32 D_801269A8; + extern s32 D_801269AC; + s16 mid[3]; + s16 dir[3]; + s32 pos[3]; + mid[0] = (param_2[0] + param_3[0]) >> 1; + mid[1] = (param_2[1] + param_3[1]) >> 1; + mid[2] = (param_2[2] + param_3[2]) >> 1; + ((void (*)(s32, void *, void *))func_80149350)(param_1, mid, mid); + func_800D20C0(mid, dir, 8); + func_80017E68(mid, param_4); + dir[0] = (u16)param_3[0] - (u16)param_2[0]; + dir[1] = (u16)param_3[1] - (u16)param_2[1]; + dir[2] = (u16)param_3[2] - (u16)param_2[2]; + ApplyMatrixSV((void *)(*(s32 *)(param_1 + 0x20) + 0x34), dir, dir); + func_800D23D0(dir); + RotMatrixYXZ(dir, param_4); + pos[0] = D_801269A4 - mid[0]; + pos[1] = D_801269A8 - mid[1]; + pos[2] = D_801269AC - mid[2]; + ApplyTransposeMatrixLV(param_4, pos, pos); + dir[2] = -ratan2(pos[0], pos[1]); + RotMatrixYXZ(dir, param_4); +} + extern s32 func_80029178(s32 arg); @@ -8985,7 +9474,62 @@ void func_8016901C(void *a0) { } -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_80169058); +extern void func_800D20C0(void *a0, void *a1, s32 a2); +extern void func_800D23D0(void *a0); +extern void RotMatrixYXZ(void *a0, void *a1); +extern void func_80048EAC(void *a0, void *a1); +extern s32 rand(void); +extern void ApplyMatrixSV(void *a0, void *a1, void *a2); +void func_80169058(s32 a0) { + s32 s1 = a0; + s16 v10[4]; /* sp+0x10 SVECTOR */ + s16 v18[4]; /* sp+0x18 SVECTOR */ + s16 v20[16]; /* sp+0x20 MATRIX */ + s16 v40[16]; /* sp+0x40 MATRIX */ + register s32 v1 __asm__("$3"); + register s32 v0 __asm__("$2"); + v10[0] = *(u16 *)(s1 + 0x6); + v10[1] = *(u16 *)(s1 + 0xA); + v10[2] = *(u16 *)(s1 + 0xE); + func_800D20C0(v10, v18, 1); + func_800D23D0(v18); + RotMatrixYXZ(v18, (void *)(s1 + 0x38)); + v10[0] = *(u16 *)(s1 + 0x12); + v10[1] = *(u16 *)(s1 + 0x16); + v10[2] = *(u16 *)(s1 + 0x1A); + RotMatrixYXZ(v10, v40); + if ((*(s32 *)(s1 + 0x2C) & 0x2) == 0) { + v0 = rand(); + v1 = (v0 & 0x7F) << 3; + v0 = ((u32)(v0 & 0x7F00)) >> 5; + __asm__ __volatile__("" : "=r"(v0) : "0"(v0)); + v0 = v0 + 0xC00; + } else { + v0 = rand(); + v1 = ((v0 & 0x7F) << 3) + 0xE40; + v0 = (((u32)(v0 & 0x7F00)) >> 5) + 0xE00; + } + v10[0] = v1; + v10[1] = v0; + __asm__ __volatile__("" : : "r"(v1), "r"(v0)); + v10[2] = 0; + RotMatrixYXZ(v10, v20); + func_80048EAC(v40, v20); + v10[0] = 0; + v10[1] = 0; + v10[2] = 0xA; + ApplyMatrixSV(v20, v10, v10); + *(u16 *)(s1 + 0x12) = v10[0]; + *(u16 *)(s1 + 0x16) = v10[1]; + { + s32 c = *(u16 *)(s1 + 0x2); + s32 z = (u16)v10[2]; + *(s32 *)(s1 + 0x1C) = 0; + *(u16 *)(s1 + 0x2) = c + 1; + *(u16 *)(s1 + 0x1A) = z; + } +} + INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_801691B8); @@ -9019,7 +9563,60 @@ void func_80169830(void *a0) { } -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_8016986C); +extern void func_800D20C0(void *a0, void *a1, s32 a2); +extern void func_800D23D0(void *a0); +extern void RotMatrixYXZ(void *a0, void *a1); +extern void func_80048EAC(void *a0, void *a1); +extern s32 rand(void); +extern void ApplyMatrixSV(void *a0, void *a1, void *a2); +void func_8016986C(s32 a0) { + s32 s1 = a0; + s16 v10[4]; /* sp+0x10 SVECTOR */ + s16 v18[4]; /* sp+0x18 SVECTOR */ + s16 v20[16]; /* sp+0x20 MATRIX */ + s16 v40[16]; /* sp+0x40 MATRIX */ + s32 v1; + s32 t; + v10[0] = *(u16 *)(s1 + 0x6); + v10[1] = *(u16 *)(s1 + 0xA); + v10[2] = *(u16 *)(s1 + 0xE); + func_800D20C0(v10, v18, 1); + func_800D23D0(v18); + RotMatrixYXZ(v18, (void *)(s1 + 0x38)); + v10[0] = *(u16 *)(s1 + 0x12); + v10[1] = *(u16 *)(s1 + 0x16); + v10[2] = *(u16 *)(s1 + 0x1A); + RotMatrixYXZ(v10, v40); + v1 = rand(); + v10[0] = (v1 & 0x1FC) + 0x180; + if (*(s32 *)(s1 + 0x2C) & 0x2) { + v10[1] = (((u32)(v1 & 0x7F00)) >> 6) + 0x200; + } else { + v10[1] = (((u32)(v1 & 0x7F00)) >> 6) + 0xC00; + } + v10[2] = 0; + RotMatrixYXZ(v10, v20); + func_80048EAC(v40, v20); + if ((*(s32 *)(s1 + 0x2C) & 0x1) == 0) { + *(s32 *)(s1 + 0x2C) = 0xE00; + } else { + *(s32 *)(s1 + 0x2C) = 0xA00; + } + v10[0] = 0; + v10[1] = 0; + v10[2] = 0xA; + ApplyMatrixSV(v20, v10, v10); + *(u16 *)(s1 + 0x12) = v10[0]; + *(u16 *)(s1 + 0x16) = v10[1]; + { + s32 tmp = *(u16 *)(s1 + 0x2); + s32 z = (u16)v10[2]; + *(s32 *)(s1 + 0x1C) = 0; + *(u16 *)(s1 + 0x2) = tmp + 1; + *(u16 *)(s1 + 0x1A) = z; + } +} + INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_801699D0); @@ -11925,7 +12522,54 @@ s32 func_8017B368(s32 param) } -INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_o2b", func_8017B490); + + +s32 func_8017B490(s32 param) +{ + extern void func_8017BA3C(s32 param_1, s32 param_2); + extern void func_8012F214(s32 a0, s32 a1, s32 a2); + extern SV4_8017B368 D_801A7C74; + extern SV4_8017B368 D_801A7C7C; + extern s16 D_801A7CCC; + extern s16 D_801A7CC4; + extern u16 D_80185900; + extern s16 D_801A7C54; + extern s16 D_801A94D0; + extern s32 D_80126984; + extern s32 D_80126988; + extern s32 D_8012698C; + extern s32 D_80126990; + extern s32 D_80126994; + extern s32 D_80126998; + + SV4_8017B368 loc0; + SV4_8017B368 loc1; + u32 n = (u32)&D_801A7C74; + + ((void (*)(void))func_8017BA3C)(); + + if (n >= 0xB) { + loc0 = *(SV4_8017B368 *)n; + loc1 = D_801A7C7C; + } else { + s32 ax = (s32)&((Pair16 *)&D_80185900)[n].x; + s32 ay = (s32)&((Pair16 *)&D_80185900)[n].y; + func_8012F214(param, ax, (s32)&loc0); + func_8012F214(param, ay, (s32)&loc1); + } + + (*(SV4_8017B368 *)&D_801A7CCC) = loc0; + (*(SV4_8017B368 *)&D_801A7CC4) = loc1; + D_801A94D0 = 1; + D_801A7C54 = 0x1E; + D_80126990 = (*(SV4_8017B368 *)&D_801A7CCC).a; + D_80126994 = (*(SV4_8017B368 *)&D_801A7CCC).b; + D_80126998 = (*(SV4_8017B368 *)&D_801A7CCC).c; + D_80126984 = (*(SV4_8017B368 *)&D_801A7CC4).a; + D_80126988 = (*(SV4_8017B368 *)&D_801A7CC4).b; + D_8012698C = (*(SV4_8017B368 *)&D_801A7CC4).c; +} + extern void func_8012A018(s32 a, s32 b); diff --git a/src/ov_SC07_011/ov_SC07_011.c b/src/ov_SC07_011/ov_SC07_011.c index e5f2d3b97..ca6ac4de7 100644 --- a/src/ov_SC07_011/ov_SC07_011.c +++ b/src/ov_SC07_011/ov_SC07_011.c @@ -2620,11 +2620,267 @@ INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011", func_80135D20); INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011", func_80135EB0); -INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011", func_80136334); -INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011", func_801365B8); +s32 func_80136334(void *arg0, s32 arg1, s32 arg2) { + + extern u8 D_80126720[]; + extern Box_80133784 * D_8017EC10; + extern Box_80133784 * D_8017EC14; + extern s16 *D_8017EC18; + extern u8 D_8017EC1C; + extern u8 D_801152A8[]; + extern s16 D_801152AA; + extern s16 D_801152AC; + extern s16 D_80126722; + extern s16 D_80126724; + register s32 a1v __asm__("$11"); + register s32 a2v __asm__("$12"); + register s32 n __asm__("$5"); + register s16 *b4 __asm__("$7"); + s32 d; + s32 dx; + s32 denom; + s32 result; + s32 frame_pad[2]; + (void)&frame_pad; + __asm__("" : "=r"(a1v) : "0"(arg1)); + a2v = arg2; + + if (!(arg1 & 1)) { + dx = (s16) arg2 - (*(s16 **)&D_8017EC10)[2]; + d = dx; + denom = -(*(s16 **)&D_8017EC1C)[2]; + } else { + denom = (*(s16 **)&D_8017EC1C)[2]; + d = (*(s16 **)&D_8017EC10)[2] - (s16) arg2; + dx = -d; + } + n = -d; + { + register s16 *b8 __asm__("$6") = *(s16 **)&D_8017EC1C; + u16 *ac = *(u16 **)&D_8017EC10; + b4 = D_8017EC18; + b4[0] = ac[0] + n * b8[0] / denom; + b4[1] = ac[1] + n * b8[1] / denom; + b4[2] = ac[2] + dx; + } + + if (b4[0] < M2C_FIELD(arg0, s16 *, 4)) return 0; + if (M2C_FIELD(arg0, s16 *, 6) < b4[0]) return 0; + if (b4[1] < M2C_FIELD(arg0, s16 *, 8)) return 0; + if (M2C_FIELD(arg0, s16 *, 0xA) < b4[1]) return 0; + if (a1v & 0x8000) { + u16 *b0 = *(u16 **)&D_8017EC14; + b4[0] = b0[0]; + b4[1] = b0[1]; + } + D_801152AA = 0; + (*(s16 *)D_801152A8) = 0; + if (a1v & 1) { + D_8017EC18[2] = a2v + 2; + __asm__ __volatile__(""); + D_801152AC = 0xFFF; + } else { + D_801152AC = -0xFFF; + D_8017EC18[2] = a2v - 2; + } + __asm__ __volatile__("" :: "r"(a1v), "r"(a2v)); + (*(s16 *)D_80126720) = (M2C_FIELD(arg0, s16 *, 4) + M2C_FIELD(arg0, s16 *, 6)) >> 1; + D_80126722 = (M2C_FIELD(arg0, s16 *, 8) + M2C_FIELD(arg0, s16 *, 0xA)) >> 1; + result = 1; + D_80126724 = (M2C_FIELD(arg0, s16 *, 0xC) + M2C_FIELD(arg0, s16 *, 0xE)) >> 1; + return result; +} + + + +// @class: regalloc-order — F-band exemplar func_801365B8 (x134). Real-TU reconciled (rtu_match). +// D_8017EC10/B0/B8 file-scope `extern u8` holding pointers -> read via *(T**)&sym (§42c-2). +// D_8017EC18 file-scope `extern s16*` -> use directly. D_80126720 file-scope `extern u8[]` +// -> single store via *(s16*)D_80126720. D_801152A8/AA/AC, D_80126722/24 block-scope externs +// (siblings use block-scope; gcc-2.7.2 does not cross-conflict block-scope externs). +s32 func_801365B8(void *arg0, s32 arg1, s32 arg2) { + + extern u8 D_80126720[]; + extern Box_80133784 * D_8017EC10; + extern Box_80133784 * D_8017EC14; + extern s16 *D_8017EC18; + extern u8 D_8017EC1C; + extern u8 D_801152A8[]; + extern s16 D_801152AA; + extern s16 D_801152AC; + extern s16 D_80126722; + extern s16 D_80126724; + u16 *ac; + s16 *b8; + s16 *b4; + s16 temp_v0; + s16 temp_v1; + s32 var_a3; + s32 temp_a1; + s32 var_a1; + s32 var_v0; + s32 var_v1; + s32 a1c; + s32 a2c; + s32 cond; + register u32 zr __asm__("$0"); + + __asm__("addu %0,%1,$zero" : "=r"(a1c) : "r"(arg1)); + cond = arg1 & 1; + a2c = arg2 + zr; + if (!cond) { + var_v1 = (s16) arg2 - (*(s16 **)&D_8017EC10)[0]; + var_a1 = var_v1; + var_a3 = -(*(s16 **)&D_8017EC1C)[0]; + } else { + var_a3 = (*(s16 **)&D_8017EC1C)[0]; + var_v1 = (*(s16 **)&D_8017EC10)[0] - (s16) arg2; + var_a1 = -var_v1; + } + ac = *(u16 **)&D_8017EC10; + b4 = D_8017EC18; + b8 = *(s16 **)&D_8017EC1C; + b4[0] = ac[0] + var_a1; + temp_a1 = -var_v1; + b4[1] = ac[1] + (temp_a1 * b8[1]) / var_a3; + temp_v0 = ac[2] + (temp_a1 * b8[2]) / var_a3; + b4[2] = temp_v0; + var_v0 = 0; + if (temp_v0 < M2C_FIELD(arg0, s16 *, 0xC)) { + return var_v0; + } + if (M2C_FIELD(arg0, s16 *, 0xE) < temp_v0) { + return var_v0; + } + temp_v1 = b4[1]; + if (temp_v1 < M2C_FIELD(arg0, s16 *, 8)) { + return var_v0; + } + if (M2C_FIELD(arg0, s16 *, 0xA) < temp_v1) { + return var_v0; + } + __asm__("" :: "r"(a1c)); + __asm__("" :: "r"(a1c)); + if (a1c & 0x8000) { + b4[1] = (s16) (*(u16 **)&D_8017EC14)[1]; + b4[2] = (s16) (*(u16 **)&D_8017EC14)[2]; + } + D_801152AC = 0; + D_801152AA = 0; + if ((a1c & 1) != 0) { + *(s16 *)D_801152A8 = 0xFFF; + M2C_FIELD(D_8017EC18, s16 *, 0) = a2c + 2; + } else { + *(s16 *)D_801152A8 = -0xFFF; + M2C_FIELD(D_8017EC18, s16 *, 0) = a2c - 2; + } + *(s16 *)D_80126720 = (s16) ((s32) (M2C_FIELD(arg0, s16 *, 4) + M2C_FIELD(arg0, s16 *, 6)) >> 1); + D_80126722 = (s16) ((s32) (M2C_FIELD(arg0, s16 *, 8) + M2C_FIELD(arg0, s16 *, 0xA)) >> 1); + var_v0 = 1; + D_80126724 = (s16) ((s32) (M2C_FIELD(arg0, s16 *, 0xC) + M2C_FIELD(arg0, s16 *, 0xE)) >> 1); + return var_v0; +} + + + +// @class: pointer-type — pointer-vs-array reconcile for func_80136824 (ov_SC01_077_a) +// D_8017EC10/B0/B8 are file-scope `extern u8`, D_8017EC18 is `extern s32 []`; each HOLDS a +// pointer value that the target loads via lw then derefs. Read as pointer via *(T**)&sym. +// D_8017EC18 must be a SCALAR pointer (not s32[]) — as an array it decays and gcc CSEs the +// base address into a held reg (lui;addiu;lw 0(reg)) across the 3 reloads; as a scalar +// pointer it folds %lo (lui;lw %lo). Retype all 3 file-TU occurrences (byte-neutral: the +// siblings read it once via *(u16**)&sym == direct lw either way). + +s32 func_80136824(s32 arg0, s32 arg1, s32 arg2) { + + extern u8 D_80126720[]; + extern Box_80133784 * D_8017EC10; + extern Box_80133784 * D_8017EC14; + extern s16 *D_8017EC18; + extern u8 D_8017EC1C; + extern u8 D_801152A8[]; + extern s16 D_801152AA; + extern s16 D_801152AC; + extern s16 D_80126722; + extern s16 D_80126724; + + register u16 *ac __asm__("$4"); + register s16 *b8 __asm__("$6"); + register s16 *b4 __asm__("$9"); + register s32 r __asm__("$3"); + register s32 pos __asm__("$12"); + register s32 a1v __asm__("$5"); + s16 temp_v0; + s16 temp_v1; + s32 var_a3; + s16 var_v0_3; + s32 temp_a1; + s32 var_t0; + s32 var_v1; + s16 *b4b; + u16 *p; + + __asm__ ("" : "=r"(a1v) : "0"(arg1)); + pos = arg2; + if (!(a1v & 1)) { + var_t0 = (s16) arg2 - (*(s16 **)&D_8017EC10)[1]; + var_v1 = var_t0; + var_a3 = -(*(s16 **)&D_8017EC1C)[1]; + } else { + var_a3 = (*(s16 **)&D_8017EC1C)[1]; + var_v1 = (*(s16 **)&D_8017EC10)[1] - (s16) arg2; + var_t0 = -var_v1; + } + b8 = (*(s16 **)&D_8017EC1C); + ac = (*(u16 **)&D_8017EC10); + b4 = D_8017EC18; + temp_a1 = -var_v1; + r = (temp_a1 * b8[0]) / var_a3; + b4[0] = ac[0] + r; + b4[1] = ac[1] + var_t0; + r = (temp_a1 * b8[2]) / var_a3; + temp_v0 = ac[2] + r; + b4[2] = temp_v0; + temp_v1 = b4[0]; + if (temp_v1 < M2C_FIELD(((void *)arg0), s16 *, 4)) { + return 0; + } + if (M2C_FIELD(((void *)arg0), s16 *, 6) < temp_v1) { + return 0; + } + if (temp_v0 < M2C_FIELD(((void *)arg0), s16 *, 0xC)) { + return 0; + } + if (M2C_FIELD(((void *)arg0), s16 *, 0xE) < temp_v0) { + return 0; + } + if (arg1 & 0x8000) { + p = (*(u16 **)&D_8017EC14); + b4[0] = (s16) p[0]; + b4[2] = (s16) p[2]; + } + D_801152AC = 0; + (*(s16 *)D_801152A8) = 0; + if (arg1 & 1) { + b4b = D_8017EC18; + D_801152AA = 0xFFF; + __asm__ __volatile__(""); + var_v0_3 = pos + 2; + } else { + b4b = D_8017EC18; + D_801152AA = -0xFFF; + __asm__ __volatile__(""); + var_v0_3 = pos - 2; + } + b4b[1] = var_v0_3; + __asm__ __volatile__("" :: "r"(pos)); + (*(s16 *)D_80126720) = (s16) ((s32) (M2C_FIELD(((void *)arg0), s16 *, 4) + M2C_FIELD(((void *)arg0), s16 *, 6)) >> 1); + D_80126722 = (s16) ((s32) (M2C_FIELD(((void *)arg0), s16 *, 8) + M2C_FIELD(((void *)arg0), s16 *, 0xA)) >> 1); + D_80126724 = (s16) ((s32) (M2C_FIELD(((void *)arg0), s16 *, 0xC) + M2C_FIELD(((void *)arg0), s16 *, 0xE)) >> 1); + return 1; +} -INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011", func_80136824); // @class: schedule @@ -15293,7 +15549,54 @@ s32 func_8017B368(s32 param) } -INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011", func_8017B490); + + +s32 func_8017B490(s32 param) +{ + extern void func_8017BA3C(s32 param_1, s32 param_2); + extern void func_8012F214(s32 a0, s32 a1, s32 a2); + extern SV4_8017B368 D_8019030C; + extern SV4_8017B368 D_80190314; + extern s16 D_80190364; + extern s16 D_8019035C; + extern u16 D_80181FC0; + extern s16 D_801902EC; + extern s16 D_80190488; + extern s32 D_80126984; + extern s32 D_80126988; + extern s32 D_8012698C; + extern s32 D_80126990; + extern s32 D_80126994; + extern s32 D_80126998; + + SV4_8017B368 loc0; + SV4_8017B368 loc1; + u32 n = (u32)&D_8019030C; + + ((void (*)(void))func_8017BA3C)(); + + if (n >= 0xB) { + loc0 = *(SV4_8017B368 *)n; + loc1 = D_80190314; + } else { + s32 ax = (s32)&((Pair16 *)&D_80181FC0)[n].x; + s32 ay = (s32)&((Pair16 *)&D_80181FC0)[n].y; + func_8012F214(param, ax, (s32)&loc0); + func_8012F214(param, ay, (s32)&loc1); + } + + (*(SV4_8017B368 *)&D_80190364) = loc0; + (*(SV4_8017B368 *)&D_8019035C) = loc1; + D_80190488 = 1; + D_801902EC = 0x1E; + D_80126990 = (*(SV4_8017B368 *)&D_80190364).a; + D_80126994 = (*(SV4_8017B368 *)&D_80190364).b; + D_80126998 = (*(SV4_8017B368 *)&D_80190364).c; + D_80126984 = (*(SV4_8017B368 *)&D_8019035C).a; + D_80126988 = (*(SV4_8017B368 *)&D_8019035C).b; + D_8012698C = (*(SV4_8017B368 *)&D_8019035C).c; +} + extern void func_8012A018(s32 a, s32 b);