diff --git a/config/overlays.mk b/config/overlays.mk index b5c9869cd..35f7e75e0 100644 --- a/config/overlays.mk +++ b/config/overlays.mk @@ -129,7 +129,7 @@ ov_SC03_001_ELF := $(ov_SC03_001_OUT).elf ov_SC03_001_MAPFILE := $(ov_SC03_001_OUT).map ov_SC03_001_LD_SCRIPT := $(ov_SC03_001_OUT).ld ov_SC03_001_SPLAT_YAML := config/splat.ov_SC03_001.yaml -ov_SC03_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_001.o,ov_SC03_001_jr_8012ACE0.o,tail2.data.o,ov_SC03_001_jr_80135888.o,tail3.data.o,ov_SC03_001_jr_80135A4C.o,tail4.data.o,ov_SC03_001_jr_80135D20.o,tail5.data.o,ov_SC03_001_jr_801380E0.o,ov_SC03_001_o0c.o,tail6.data.o,ov_SC03_001_jr_8013F350.o,tail7.data.o,ov_SC03_001_jr_8013FFD8.o,tail8.data.o,ov_SC03_001_jr_80140608.o,tail9.data.o,ov_SC03_001_jr_8015444C.o,ov_SC03_001_jr_80154C24.o,ov_SC03_001_jr_801588CC.o,ov_SC03_001_jr_80159C84.o,tail10.data.o,ov_SC03_001_jr_8015A3C8.o,tail11.data.o,ov_SC03_001_jr_8015AE2C.o,tail12.data.o,ov_SC03_001_jr_8015C32C.o,tail13.data.o,ov_SC03_001_jr_8016AB6C.o,tail14.data.o,ov_SC03_001_jr_80171B4C.o,ov_SC03_001_jr_801734BC.o,tail15.data.o,ov_SC03_001_jr_801789AC.o,ov_SC03_001_jr_80178D40.o,tail16.data.o,ov_SC03_001_jr_8017A4AC.o,tail17.data.o,ov_SC03_001_jr_8017AE2C.o,tail18.data.o,ov_SC03_001_jr_80188830.o,tail19.data.o,ov_SC03_001_jr_80189030.o,tail20.data.o,ov_SC03_001_jr_8018A3A8.o,tail21.data.o,ov_SC03_001_jr_8018B8DC.o,tail22.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_001.o,ov_SC03_001_jr_8012ACE0.o,tail2.data.o,ov_SC03_001_jr_80135888.o,tail3.data.o,ov_SC03_001_jr_80135A4C.o,tail4.data.o,ov_SC03_001_jr_80135D20.o,tail5.data.o,ov_SC03_001_jr_801380E0.o,ov_SC03_001_o0c.o,tail6.data.o,ov_SC03_001_jr_8013F350.o,tail7.data.o,ov_SC03_001_jr_8013FFD8.o,tail8.data.o,ov_SC03_001_jr_80140608.o,tail9.data.o,ov_SC03_001_jr_8015444C.o,ov_SC03_001_jr_80154C24.o,ov_SC03_001_jr_801588CC.o,ov_SC03_001_jr_80159C84.o,tail10.data.o,ov_SC03_001_jr_8015A3C8.o,tail11.data.o,ov_SC03_001_jr_8015AE2C.o,tail12.data.o,ov_SC03_001_jr_8015C32C.o,tail13.data.o,ov_SC03_001_jr_8016AB6C.o,tail14.data.o,ov_SC03_001_jr_80171B4C.o,ov_SC03_001_jr_801734BC.o,tail15.data.o,ov_SC03_001_jr_801789AC.o,ov_SC03_001_jr_80178D40.o,tail16.data.o,ov_SC03_001_jr_8017A4AC.o,tail17.data.o,ov_SC03_001_jr_8017AE2C.o,tail18.data.o,ov_SC03_001_jr_80188830.o,tail19.data.o,ov_SC03_001_jr_80189030.o,tail20.data.o,ov_SC03_001_jr_8018A3A8.o,ov_SC03_001_jr_8018B8DC.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_001/ov_SC03_001.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_001/ov_SC03_001_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_001/ov_SC03_001_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 @@ -143,6 +143,7 @@ build/src/ov_SC03_001/ov_SC03_001_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_001/ov_SC03_001_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_001/ov_SC03_001_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 build/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 +build/src/ov_SC03_001/ov_SC03_001_jr_8018A3A8.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38 build/src/ov_SC03_001/ov_SC03_001_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118 ov_SC03_001_CHECK_SHA := config/check.ov_SC03_001.sha ov_SC03_001_SYMBOLS := config/symbols.ov_SC03_001.txt @@ -453,7 +454,7 @@ ov_SC04_019_ELF := $(ov_SC04_019_OUT).elf ov_SC04_019_MAPFILE := $(ov_SC04_019_OUT).map ov_SC04_019_LD_SCRIPT := $(ov_SC04_019_OUT).ld ov_SC04_019_SPLAT_YAML := config/splat.ov_SC04_019.yaml -ov_SC04_019_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_019.o,ov_SC04_019_jr_8012ACE0.o,tail2.data.o,ov_SC04_019_jr_80135888.o,tail3.data.o,ov_SC04_019_jr_80135A4C.o,tail4.data.o,ov_SC04_019_jr_80135D20.o,tail5.data.o,ov_SC04_019_jr_801380E0.o,ov_SC04_019_o0c.o,tail6.data.o,ov_SC04_019_jr_8013F350.o,tail7.data.o,ov_SC04_019_jr_8013FFD8.o,tail8.data.o,ov_SC04_019_jr_80140608.o,tail9.data.o,ov_SC04_019_jr_8015444C.o,ov_SC04_019_jr_80154C24.o,ov_SC04_019_jr_801588CC.o,ov_SC04_019_jr_80159C84.o,tail10.data.o,ov_SC04_019_jr_8015A3C8.o,tail11.data.o,ov_SC04_019_jr_8015AE2C.o,tail12.data.o,ov_SC04_019_jr_8015C32C.o,tail13.data.o,ov_SC04_019_jr_8016AB6C.o,tail14.data.o,ov_SC04_019_jr_80171B4C.o,ov_SC04_019_jr_801734BC.o,tail15.data.o,ov_SC04_019_jr_801789AC.o,ov_SC04_019_jr_80178D40.o,tail16.data.o,ov_SC04_019_jr_8017A4AC.o,tail17.data.o,ov_SC04_019_jr_8017AE2C.o,tail18.data.o,ov_SC04_019_jr_80185D70.o,tail19.data.o,ov_SC04_019_jr_801878E8.o,tail20.data.o,ov_SC04_019_jr_80188E1C.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC04_019_JTBL_INTERLEAVE := --order tail.data.o,ov_SC04_019.o,ov_SC04_019_jr_8012ACE0.o,tail2.data.o,ov_SC04_019_jr_80135888.o,tail3.data.o,ov_SC04_019_jr_80135A4C.o,tail4.data.o,ov_SC04_019_jr_80135D20.o,tail5.data.o,ov_SC04_019_jr_801380E0.o,ov_SC04_019_o0c.o,tail6.data.o,ov_SC04_019_jr_8013F350.o,tail7.data.o,ov_SC04_019_jr_8013FFD8.o,tail8.data.o,ov_SC04_019_jr_80140608.o,tail9.data.o,ov_SC04_019_jr_8015444C.o,ov_SC04_019_jr_80154C24.o,ov_SC04_019_jr_801588CC.o,ov_SC04_019_jr_80159C84.o,tail10.data.o,ov_SC04_019_jr_8015A3C8.o,tail11.data.o,ov_SC04_019_jr_8015AE2C.o,tail12.data.o,ov_SC04_019_jr_8015C32C.o,tail13.data.o,ov_SC04_019_jr_8016AB6C.o,tail14.data.o,ov_SC04_019_jr_80171B4C.o,ov_SC04_019_jr_801734BC.o,tail15.data.o,ov_SC04_019_jr_801789AC.o,ov_SC04_019_jr_80178D40.o,tail16.data.o,ov_SC04_019_jr_8017A4AC.o,tail17.data.o,ov_SC04_019_jr_8017AE2C.o,tail18.data.o,ov_SC04_019_jr_80185D70.o,tail19.data.o,ov_SC04_019_jr_801878E8.o,ov_SC04_019_jr_80188E1C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC04_019/ov_SC04_019.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC04_019/ov_SC04_019_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC04_019/ov_SC04_019_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 @@ -467,6 +468,7 @@ build/src/ov_SC04_019/ov_SC04_019_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_019/ov_SC04_019_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_019/ov_SC04_019_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 build/src/ov_SC04_019/ov_SC04_019_jr_8017AE2C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 +build/src/ov_SC04_019/ov_SC04_019_jr_801878E8.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38 build/src/ov_SC04_019/ov_SC04_019_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118 ov_SC04_019_CHECK_SHA := config/check.ov_SC04_019.sha ov_SC04_019_SYMBOLS := config/symbols.ov_SC04_019.txt @@ -2866,7 +2868,7 @@ ov_SC03_124_ELF := $(ov_SC03_124_OUT).elf ov_SC03_124_MAPFILE := $(ov_SC03_124_OUT).map ov_SC03_124_LD_SCRIPT := $(ov_SC03_124_OUT).ld ov_SC03_124_SPLAT_YAML := config/splat.ov_SC03_124.yaml -ov_SC03_124_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_124.o,ov_SC03_124_jr_8012ACE0.o,tail2.data.o,ov_SC03_124_jr_80135888.o,tail3.data.o,ov_SC03_124_jr_80135A4C.o,tail4.data.o,ov_SC03_124_jr_80135D20.o,tail5.data.o,ov_SC03_124_jr_801380E0.o,ov_SC03_124_o0c.o,tail6.data.o,ov_SC03_124_jr_8013F350.o,tail7.data.o,ov_SC03_124_jr_8013FFD8.o,tail8.data.o,ov_SC03_124_jr_80140608.o,tail9.data.o,ov_SC03_124_jr_8015444C.o,ov_SC03_124_jr_80154C24.o,ov_SC03_124_jr_801588CC.o,ov_SC03_124_jr_80159C84.o,tail10.data.o,ov_SC03_124_jr_8015A3C8.o,tail11.data.o,ov_SC03_124_jr_8015AE2C.o,tail12.data.o,ov_SC03_124_jr_8015C32C.o,tail13.data.o,ov_SC03_124_jr_8016AB6C.o,tail14.data.o,ov_SC03_124_jr_80171B4C.o,ov_SC03_124_jr_801734BC.o,tail15.data.o,ov_SC03_124_jr_801789AC.o,ov_SC03_124_jr_80178D40.o,tail16.data.o,ov_SC03_124_jr_8017A4AC.o,tail17.data.o,ov_SC03_124_jr_8017AE2C.o,tail18.data.o,ov_SC03_124_jr_80185498.o,tail19.data.o,ov_SC03_124_jr_80187010.o,tail20.data.o,ov_SC03_124_jr_80188544.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC03_124_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_124.o,ov_SC03_124_jr_8012ACE0.o,tail2.data.o,ov_SC03_124_jr_80135888.o,tail3.data.o,ov_SC03_124_jr_80135A4C.o,tail4.data.o,ov_SC03_124_jr_80135D20.o,tail5.data.o,ov_SC03_124_jr_801380E0.o,ov_SC03_124_o0c.o,tail6.data.o,ov_SC03_124_jr_8013F350.o,tail7.data.o,ov_SC03_124_jr_8013FFD8.o,tail8.data.o,ov_SC03_124_jr_80140608.o,tail9.data.o,ov_SC03_124_jr_8015444C.o,ov_SC03_124_jr_80154C24.o,ov_SC03_124_jr_801588CC.o,ov_SC03_124_jr_80159C84.o,tail10.data.o,ov_SC03_124_jr_8015A3C8.o,tail11.data.o,ov_SC03_124_jr_8015AE2C.o,tail12.data.o,ov_SC03_124_jr_8015C32C.o,tail13.data.o,ov_SC03_124_jr_8016AB6C.o,tail14.data.o,ov_SC03_124_jr_80171B4C.o,ov_SC03_124_jr_801734BC.o,tail15.data.o,ov_SC03_124_jr_801789AC.o,ov_SC03_124_jr_80178D40.o,tail16.data.o,ov_SC03_124_jr_8017A4AC.o,tail17.data.o,ov_SC03_124_jr_8017AE2C.o,tail18.data.o,ov_SC03_124_jr_80185498.o,tail19.data.o,ov_SC03_124_jr_80187010.o,ov_SC03_124_jr_80188544.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC03_124/ov_SC03_124.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC03_124/ov_SC03_124_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC03_124/ov_SC03_124_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 @@ -2880,6 +2882,7 @@ build/src/ov_SC03_124/ov_SC03_124_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_124/ov_SC03_124_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_124/ov_SC03_124_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 build/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 +build/src/ov_SC03_124/ov_SC03_124_jr_80187010.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38 build/src/ov_SC03_124/ov_SC03_124_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118 ov_SC03_124_CHECK_SHA := config/check.ov_SC03_124.sha ov_SC03_124_SYMBOLS := config/symbols.ov_SC03_124.txt @@ -3890,7 +3893,7 @@ ov_SC05_017_ELF := $(ov_SC05_017_OUT).elf ov_SC05_017_MAPFILE := $(ov_SC05_017_OUT).map ov_SC05_017_LD_SCRIPT := $(ov_SC05_017_OUT).ld ov_SC05_017_SPLAT_YAML := config/splat.ov_SC05_017.yaml -ov_SC05_017_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_017.o,ov_SC05_017_jr_8012ACE0.o,tail2.data.o,ov_SC05_017_jr_80135888.o,tail3.data.o,ov_SC05_017_jr_80135A4C.o,tail4.data.o,ov_SC05_017_jr_80135D20.o,tail5.data.o,ov_SC05_017_jr_801380E0.o,ov_SC05_017_o0c.o,tail6.data.o,ov_SC05_017_jr_8013F350.o,tail7.data.o,ov_SC05_017_jr_8013FFD8.o,tail8.data.o,ov_SC05_017_jr_80140608.o,tail9.data.o,ov_SC05_017_jr_8015444C.o,ov_SC05_017_jr_80154C24.o,ov_SC05_017_jr_801588CC.o,ov_SC05_017_jr_80159C84.o,tail10.data.o,ov_SC05_017_jr_8015A3C8.o,tail11.data.o,ov_SC05_017_jr_8015AE2C.o,tail12.data.o,ov_SC05_017_jr_8015C32C.o,tail13.data.o,ov_SC05_017_jr_8016AB6C.o,tail14.data.o,ov_SC05_017_jr_80171B4C.o,ov_SC05_017_jr_801734BC.o,tail15.data.o,ov_SC05_017_jr_801789AC.o,ov_SC05_017_jr_80178D40.o,tail16.data.o,ov_SC05_017_jr_8017A4AC.o,tail17.data.o,ov_SC05_017_jr_8017AE2C.o,tail18.data.o,ov_SC05_017_jr_80185A70.o,tail19.data.o,ov_SC05_017_jr_801875E8.o,tail20.data.o,ov_SC05_017_jr_80188B1C.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC05_017_JTBL_INTERLEAVE := --order tail.data.o,ov_SC05_017.o,ov_SC05_017_jr_8012ACE0.o,tail2.data.o,ov_SC05_017_jr_80135888.o,tail3.data.o,ov_SC05_017_jr_80135A4C.o,tail4.data.o,ov_SC05_017_jr_80135D20.o,tail5.data.o,ov_SC05_017_jr_801380E0.o,ov_SC05_017_o0c.o,tail6.data.o,ov_SC05_017_jr_8013F350.o,tail7.data.o,ov_SC05_017_jr_8013FFD8.o,tail8.data.o,ov_SC05_017_jr_80140608.o,tail9.data.o,ov_SC05_017_jr_8015444C.o,ov_SC05_017_jr_80154C24.o,ov_SC05_017_jr_801588CC.o,ov_SC05_017_jr_80159C84.o,tail10.data.o,ov_SC05_017_jr_8015A3C8.o,tail11.data.o,ov_SC05_017_jr_8015AE2C.o,tail12.data.o,ov_SC05_017_jr_8015C32C.o,tail13.data.o,ov_SC05_017_jr_8016AB6C.o,tail14.data.o,ov_SC05_017_jr_80171B4C.o,ov_SC05_017_jr_801734BC.o,tail15.data.o,ov_SC05_017_jr_801789AC.o,ov_SC05_017_jr_80178D40.o,tail16.data.o,ov_SC05_017_jr_8017A4AC.o,tail17.data.o,ov_SC05_017_jr_8017AE2C.o,tail18.data.o,ov_SC05_017_jr_80185A70.o,tail19.data.o,ov_SC05_017_jr_801875E8.o,ov_SC05_017_jr_80188B1C.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC05_017/ov_SC05_017.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC05_017/ov_SC05_017_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC05_017/ov_SC05_017_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 @@ -3904,6 +3907,7 @@ build/src/ov_SC05_017/ov_SC05_017_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_017/ov_SC05_017_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_017/ov_SC05_017_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 build/src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 +build/src/ov_SC05_017/ov_SC05_017_jr_801875E8.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38 build/src/ov_SC05_017/ov_SC05_017_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118 ov_SC05_017_CHECK_SHA := config/check.ov_SC05_017.sha ov_SC05_017_SYMBOLS := config/symbols.ov_SC05_017.txt diff --git a/config/splat.ov_SC03_001.yaml b/config/splat.ov_SC03_001.yaml index 3ec829e0b..b6eb85b5c 100644 --- a/config/splat.ov_SC03_001.yaml +++ b/config/splat.ov_SC03_001.yaml @@ -171,9 +171,8 @@ segments: - [0xc50a8, .rodata, ov_SC03_001_jr_80189030] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc50bc, data, tail20] - [0xc5130, .rodata, ov_SC03_001_jr_8018A3A8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc5168, data, tail21] - [0xc5188, .rodata, ov_SC03_001_jr_8018B8DC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc51a8, data, tail22] + - [0xc51a8, data, tail21] - [0xC730C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC730F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC03_124.yaml b/config/splat.ov_SC03_124.yaml index 6b271c09f..bb38e9117 100644 --- a/config/splat.ov_SC03_124.yaml +++ b/config/splat.ov_SC03_124.yaml @@ -168,9 +168,8 @@ segments: - [0xb7f68, .rodata, ov_SC03_124_jr_80185498] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7f84, data, tail19] - [0xb82ac, .rodata, ov_SC03_124_jr_80187010] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb82e4, data, tail20] - [0xb8304, .rodata, ov_SC03_124_jr_80188544] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8324, data, tail21] + - [0xb8324, data, tail20] - [0xBA48C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xBA48F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC04_019.yaml b/config/splat.ov_SC04_019.yaml index 35208469d..0280d437d 100644 --- a/config/splat.ov_SC04_019.yaml +++ b/config/splat.ov_SC04_019.yaml @@ -168,9 +168,8 @@ segments: - [0xbd4a8, .rodata, ov_SC04_019_jr_80185D70] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbd4c4, data, tail19] - [0xbd7ec, .rodata, ov_SC04_019_jr_801878E8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbd824, data, tail20] - [0xbd844, .rodata, ov_SC04_019_jr_80188E1C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbd864, data, tail21] + - [0xbd864, data, tail20] - [0xBF9CC, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xBF9CF] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC05_017.yaml b/config/splat.ov_SC05_017.yaml index 2e3173c92..062b46d7f 100644 --- a/config/splat.ov_SC05_017.yaml +++ b/config/splat.ov_SC05_017.yaml @@ -168,9 +168,8 @@ segments: - [0xc32fc, .rodata, ov_SC05_017_jr_80185A70] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc3318, data, tail19] - [0xc3640, .rodata, ov_SC05_017_jr_801875E8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3678, data, tail20] - [0xc3698, .rodata, ov_SC05_017_jr_80188B1C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc36b8, data, tail21] + - [0xc36b8, data, tail20] - [0xC582C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xC582F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/src/ov_SC03_001/ov_SC03_001_jr_8018A3A8.c b/src/ov_SC03_001/ov_SC03_001_jr_8018A3A8.c index 22a86498c..6c11c68e2 100644 --- a/src/ov_SC03_001/ov_SC03_001_jr_8018A3A8.c +++ b/src/ov_SC03_001/ov_SC03_001_jr_8018A3A8.c @@ -3948,4 +3948,136 @@ s32 *func_8018B478(s32 *ot, Panel_8017E978_8018B478 *w0, s16 idx) { } -INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8018A3A8", func_8018B644); + +/* func_8018B644 — "resolve one HUD sub-item's tile pointer", 166 ins, jtbl_801E597C + * (8 entries, minval 7 -> `addiu $a1,$a1,-7` + HImode re-extension, so the switch value is + * `(s16)arg1` with cases 7..14 — the same construction as the already-matched twin + * func_80188E1C in this overlay). Case bodies are emitted in SOURCE order, so the order here + * is 10/11/13, 12, 7/8, 14, default (block order after the jr: 80188C0C, 80188C5C, 80188CB8, + * 80188D10, 80188DC4). Case 9 is ABSENT: its jtbl slot (index 2) points at the default label. + * + * Structural sibling that fixed the whole engine idiom (already matched): + * src/ov_SC03_099/ov_SC03_099_jr_8013FFD8.c func_8013FFD8 + * `*arg2 = 0x808080; ret = 0; switch(...) … return ret;`, the `s16 v1 = (s16)arg1;` + * per-case truncation temp, `return 1` on the zero probe, `D_8010EDE8[v3 * 3]`, + * `*arg2 = 0x804040`. + * + * Four register/shape constraints read off the target: + * + * (a) the default arm's `< (mode == 5 ? 4 : 3)` must be a VALUE (`ok`), not a COND_EXPR in the + * `if`. do_jump's COND_EXPR case emits one conditional branch PER ARM (`bnez`+`beqz`, + * +4 ins); the target converges both `slti`s on a single `beqz`, which is the store-then- + * test form. `v1` must also be an s32 temp taken BEFORE the `mode == 5` test — a short + * local is re-extended inside each arm instead of being shared (+2 ins). The body then + * re-derives `(s16)arg3` (the ternary's label ends the cse block) and combine folds + * sra16+sll2 into the target's `sra $v0,$v0,14`. + * + * (b) `D_8010F468[(k + 1) * 2]` must go through the temp `e`. Written inline, fold + * distributes the +1 into the address (`sll $v0,$s0,3` + `lw $s0,8($at)`) and the + * function is one instruction short; a VAR_DECL leaf blocks the distribution and gives + * the target's `addiu $v0,$s0,1; sll $v0,$v0,3`. + * + * (c) `n` must be built IN PLACE (`n = A; n = n * B;`). As one expression the first `lbu` + * is a block-local quantity, local-alloc hands it $a0, and arg0's allocno then CONFLICTS + * with $a0 — so arg0 is copied out to $t1 and the target's `addu $t0,$a1,$zero` (the arg1 + * copy) never appears. In-place, arg0 keeps $a0 and the whole prologue falls into place. + * + * (d) RC-12 ($0-ADD OPAQUE COPY, docs/gcc-2.7.2-map/regalloc.md, and the same lever the + * matched func_801889B8 above needed). The target keeps arg1 in TWO registers: $a1 is + * consumed in place by the switch index (`addiu $a1,$a1,-7`) while the default arm reads + * the copy in $t0. A plain `mode = arg1;` is coalesced away and arg1 keeps $a1, pushing + * the switch index to $t0. `mode = arg1 + zr` is a (plus rA (reg 0)) — not a reg-reg set, + * so nothing merges it — and assembles to the byte-identical `addu $t0,$a1,$zero`. + * Finally `n = func_800291B4(c)` REUSES n as the second probe's temp: that 8th reference + * is what lifts n's allocno priority above the per-case `j` allocnos, so n gets $v1 and + * `j` gets $a1/$a0 instead of the other way round (the last 23-instruction residual). + */ + +s32 func_8018B644(void *arg0, s32 arg1, s32 arg2, s32 arg3, s32 *arg4) { + + extern s32 func_800291B4(s32 arg); + + extern u8 D_80115140[]; + extern u8 D_80115158[]; + extern u8 D_80115159[]; + extern u8 D_8018E5C0[]; + extern u8 D_801EF290[]; + extern u8 D_801EF298[]; + extern s32 D_8010EDE8[]; + extern s32 D_8010F468[]; + extern s32 D_801C12E8; + + register s32 zr __asm__("$0"); + s32 ret; + s32 n; + s32 mode; + + *arg4 = 0x808080; + n = D_80115159[(s16)arg2 * 2]; + n = n * D_80115158[(s16)arg2 * 2]; + ret = 0; + mode = arg1 + zr; + + switch ((s16)arg1) { /* jtbl_801E597C */ + case 10: + case 11: + case 13: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + ret = ((s32 *)arg0)[(s16)j]; + } + break; + } + + case 12: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + ret = ((s32 *)arg0)[D_801EF290[(s16)j]]; + } + break; + } + + case 7: + case 8: { + s16 v1 = (s16)arg3; + if (v1 < 0xC) { + s32 t = func_800291B4(D_8018E5C0[v1]) & 0xFF; + if (t == 0) { + return 1; + } + ret = D_8010EDE8[t * 3]; + } + break; + } + + case 14: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + s32 k = D_801EF298[(s16)j]; + s32 c = k + 0x63; + if (k < 0 || (func_800291B4(c) & 0x40) == 0) { + ret = D_801C12E8; + } else { + s32 e = k + 1; + ret = D_8010F468[e * 2]; + n = func_800291B4(c); + if (n & 0x20) { + *arg4 = 0x804040; + } + } + } + break; + } + + default: { + s32 v1 = (s16)arg3; + s32 ok = ((s16)mode == 5) ? (v1 < 4) : (v1 < 3); + if (ok) { + ret = ((s32 *)arg0)[(s16)arg3]; + } + break; + } + } + + return ret; +} diff --git a/src/ov_SC03_124/ov_SC03_124_jr_80187010.c b/src/ov_SC03_124/ov_SC03_124_jr_80187010.c index 5f0158a93..f6336460e 100644 --- a/src/ov_SC03_124/ov_SC03_124_jr_80187010.c +++ b/src/ov_SC03_124/ov_SC03_124_jr_80187010.c @@ -3631,4 +3631,136 @@ s32 *func_801880E0(s32 *ot, Panel_8017E978_801880E0 *w0, s16 idx) { } -INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_80187010", func_801882AC); + +/* func_801882AC — "resolve one HUD sub-item's tile pointer", 166 ins, jtbl_801E597C + * (8 entries, minval 7 -> `addiu $a1,$a1,-7` + HImode re-extension, so the switch value is + * `(s16)arg1` with cases 7..14 — the same construction as the already-matched twin + * func_80188E1C in this overlay). Case bodies are emitted in SOURCE order, so the order here + * is 10/11/13, 12, 7/8, 14, default (block order after the jr: 80188C0C, 80188C5C, 80188CB8, + * 80188D10, 80188DC4). Case 9 is ABSENT: its jtbl slot (index 2) points at the default label. + * + * Structural sibling that fixed the whole engine idiom (already matched): + * src/ov_SC03_099/ov_SC03_099_jr_8013FFD8.c func_8013FFD8 + * `*arg2 = 0x808080; ret = 0; switch(...) … return ret;`, the `s16 v1 = (s16)arg1;` + * per-case truncation temp, `return 1` on the zero probe, `D_8010EDE8[v3 * 3]`, + * `*arg2 = 0x804040`. + * + * Four register/shape constraints read off the target: + * + * (a) the default arm's `< (mode == 5 ? 4 : 3)` must be a VALUE (`ok`), not a COND_EXPR in the + * `if`. do_jump's COND_EXPR case emits one conditional branch PER ARM (`bnez`+`beqz`, + * +4 ins); the target converges both `slti`s on a single `beqz`, which is the store-then- + * test form. `v1` must also be an s32 temp taken BEFORE the `mode == 5` test — a short + * local is re-extended inside each arm instead of being shared (+2 ins). The body then + * re-derives `(s16)arg3` (the ternary's label ends the cse block) and combine folds + * sra16+sll2 into the target's `sra $v0,$v0,14`. + * + * (b) `D_8010F468[(k + 1) * 2]` must go through the temp `e`. Written inline, fold + * distributes the +1 into the address (`sll $v0,$s0,3` + `lw $s0,8($at)`) and the + * function is one instruction short; a VAR_DECL leaf blocks the distribution and gives + * the target's `addiu $v0,$s0,1; sll $v0,$v0,3`. + * + * (c) `n` must be built IN PLACE (`n = A; n = n * B;`). As one expression the first `lbu` + * is a block-local quantity, local-alloc hands it $a0, and arg0's allocno then CONFLICTS + * with $a0 — so arg0 is copied out to $t1 and the target's `addu $t0,$a1,$zero` (the arg1 + * copy) never appears. In-place, arg0 keeps $a0 and the whole prologue falls into place. + * + * (d) RC-12 ($0-ADD OPAQUE COPY, docs/gcc-2.7.2-map/regalloc.md, and the same lever the + * matched func_801889B8 above needed). The target keeps arg1 in TWO registers: $a1 is + * consumed in place by the switch index (`addiu $a1,$a1,-7`) while the default arm reads + * the copy in $t0. A plain `mode = arg1;` is coalesced away and arg1 keeps $a1, pushing + * the switch index to $t0. `mode = arg1 + zr` is a (plus rA (reg 0)) — not a reg-reg set, + * so nothing merges it — and assembles to the byte-identical `addu $t0,$a1,$zero`. + * Finally `n = func_800291B4(c)` REUSES n as the second probe's temp: that 8th reference + * is what lifts n's allocno priority above the per-case `j` allocnos, so n gets $v1 and + * `j` gets $a1/$a0 instead of the other way round (the last 23-instruction residual). + */ + +s32 func_801882AC(void *arg0, s32 arg1, s32 arg2, s32 arg3, s32 *arg4) { + + extern s32 func_800291B4(s32 arg); + + extern u8 D_80115140[]; + extern u8 D_80115158[]; + extern u8 D_80115159[]; + extern u8 D_8018BC64[]; + extern u8 D_801E2408[]; + extern u8 D_801E2410[]; + extern s32 D_8010EDE8[]; + extern s32 D_8010F468[]; + extern s32 D_801BC650; + + register s32 zr __asm__("$0"); + s32 ret; + s32 n; + s32 mode; + + *arg4 = 0x808080; + n = D_80115159[(s16)arg2 * 2]; + n = n * D_80115158[(s16)arg2 * 2]; + ret = 0; + mode = arg1 + zr; + + switch ((s16)arg1) { /* jtbl_801E597C */ + case 10: + case 11: + case 13: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + ret = ((s32 *)arg0)[(s16)j]; + } + break; + } + + case 12: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + ret = ((s32 *)arg0)[D_801E2408[(s16)j]]; + } + break; + } + + case 7: + case 8: { + s16 v1 = (s16)arg3; + if (v1 < 0xC) { + s32 t = func_800291B4(D_8018BC64[v1]) & 0xFF; + if (t == 0) { + return 1; + } + ret = D_8010EDE8[t * 3]; + } + break; + } + + case 14: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + s32 k = D_801E2410[(s16)j]; + s32 c = k + 0x63; + if (k < 0 || (func_800291B4(c) & 0x40) == 0) { + ret = D_801BC650; + } else { + s32 e = k + 1; + ret = D_8010F468[e * 2]; + n = func_800291B4(c); + if (n & 0x20) { + *arg4 = 0x804040; + } + } + } + break; + } + + default: { + s32 v1 = (s16)arg3; + s32 ok = ((s16)mode == 5) ? (v1 < 4) : (v1 < 3); + if (ok) { + ret = ((s32 *)arg0)[(s16)arg3]; + } + break; + } + } + + return ret; +} diff --git a/src/ov_SC04_019/ov_SC04_019_jr_801878E8.c b/src/ov_SC04_019/ov_SC04_019_jr_801878E8.c index 409302fa5..192273ddf 100644 --- a/src/ov_SC04_019/ov_SC04_019_jr_801878E8.c +++ b/src/ov_SC04_019/ov_SC04_019_jr_801878E8.c @@ -3646,4 +3646,136 @@ s32 *func_801889B8(s32 *ot, Panel_8017E978_801889B8 *w0, s16 idx) { } -INCLUDE_ASM("asm/ov_SC04_019/nonmatchings/ov_SC04_019_jr_801878E8", func_80188B84); + +/* func_80188B84 — "resolve one HUD sub-item's tile pointer", 166 ins, jtbl_801E597C + * (8 entries, minval 7 -> `addiu $a1,$a1,-7` + HImode re-extension, so the switch value is + * `(s16)arg1` with cases 7..14 — the same construction as the already-matched twin + * func_80188E1C in this overlay). Case bodies are emitted in SOURCE order, so the order here + * is 10/11/13, 12, 7/8, 14, default (block order after the jr: 80188C0C, 80188C5C, 80188CB8, + * 80188D10, 80188DC4). Case 9 is ABSENT: its jtbl slot (index 2) points at the default label. + * + * Structural sibling that fixed the whole engine idiom (already matched): + * src/ov_SC03_099/ov_SC03_099_jr_8013FFD8.c func_8013FFD8 + * `*arg2 = 0x808080; ret = 0; switch(...) … return ret;`, the `s16 v1 = (s16)arg1;` + * per-case truncation temp, `return 1` on the zero probe, `D_8010EDE8[v3 * 3]`, + * `*arg2 = 0x804040`. + * + * Four register/shape constraints read off the target: + * + * (a) the default arm's `< (mode == 5 ? 4 : 3)` must be a VALUE (`ok`), not a COND_EXPR in the + * `if`. do_jump's COND_EXPR case emits one conditional branch PER ARM (`bnez`+`beqz`, + * +4 ins); the target converges both `slti`s on a single `beqz`, which is the store-then- + * test form. `v1` must also be an s32 temp taken BEFORE the `mode == 5` test — a short + * local is re-extended inside each arm instead of being shared (+2 ins). The body then + * re-derives `(s16)arg3` (the ternary's label ends the cse block) and combine folds + * sra16+sll2 into the target's `sra $v0,$v0,14`. + * + * (b) `D_8010F468[(k + 1) * 2]` must go through the temp `e`. Written inline, fold + * distributes the +1 into the address (`sll $v0,$s0,3` + `lw $s0,8($at)`) and the + * function is one instruction short; a VAR_DECL leaf blocks the distribution and gives + * the target's `addiu $v0,$s0,1; sll $v0,$v0,3`. + * + * (c) `n` must be built IN PLACE (`n = A; n = n * B;`). As one expression the first `lbu` + * is a block-local quantity, local-alloc hands it $a0, and arg0's allocno then CONFLICTS + * with $a0 — so arg0 is copied out to $t1 and the target's `addu $t0,$a1,$zero` (the arg1 + * copy) never appears. In-place, arg0 keeps $a0 and the whole prologue falls into place. + * + * (d) RC-12 ($0-ADD OPAQUE COPY, docs/gcc-2.7.2-map/regalloc.md, and the same lever the + * matched func_801889B8 above needed). The target keeps arg1 in TWO registers: $a1 is + * consumed in place by the switch index (`addiu $a1,$a1,-7`) while the default arm reads + * the copy in $t0. A plain `mode = arg1;` is coalesced away and arg1 keeps $a1, pushing + * the switch index to $t0. `mode = arg1 + zr` is a (plus rA (reg 0)) — not a reg-reg set, + * so nothing merges it — and assembles to the byte-identical `addu $t0,$a1,$zero`. + * Finally `n = func_800291B4(c)` REUSES n as the second probe's temp: that 8th reference + * is what lifts n's allocno priority above the per-case `j` allocnos, so n gets $v1 and + * `j` gets $a1/$a0 instead of the other way round (the last 23-instruction residual). + */ + +s32 func_80188B84(void *arg0, s32 arg1, s32 arg2, s32 arg3, s32 *arg4) { + + extern s32 func_800291B4(s32 arg); + + extern u8 D_80115140[]; + extern u8 D_80115158[]; + extern u8 D_80115159[]; + extern u8 D_8018E2C8[]; + extern u8 D_801E77B0[]; + extern u8 D_801E77B8[]; + extern s32 D_8010EDE8[]; + extern s32 D_8010F468[]; + extern s32 D_801B8F08; + + register s32 zr __asm__("$0"); + s32 ret; + s32 n; + s32 mode; + + *arg4 = 0x808080; + n = D_80115159[(s16)arg2 * 2]; + n = n * D_80115158[(s16)arg2 * 2]; + ret = 0; + mode = arg1 + zr; + + switch ((s16)arg1) { /* jtbl_801E597C */ + case 10: + case 11: + case 13: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + ret = ((s32 *)arg0)[(s16)j]; + } + break; + } + + case 12: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + ret = ((s32 *)arg0)[D_801E77B0[(s16)j]]; + } + break; + } + + case 7: + case 8: { + s16 v1 = (s16)arg3; + if (v1 < 0xC) { + s32 t = func_800291B4(D_8018E2C8[v1]) & 0xFF; + if (t == 0) { + return 1; + } + ret = D_8010EDE8[t * 3]; + } + break; + } + + case 14: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + s32 k = D_801E77B8[(s16)j]; + s32 c = k + 0x63; + if (k < 0 || (func_800291B4(c) & 0x40) == 0) { + ret = D_801B8F08; + } else { + s32 e = k + 1; + ret = D_8010F468[e * 2]; + n = func_800291B4(c); + if (n & 0x20) { + *arg4 = 0x804040; + } + } + } + break; + } + + default: { + s32 v1 = (s16)arg3; + s32 ok = ((s16)mode == 5) ? (v1 < 4) : (v1 < 3); + if (ok) { + ret = ((s32 *)arg0)[(s16)arg3]; + } + break; + } + } + + return ret; +} diff --git a/src/ov_SC05_017/ov_SC05_017_jr_801875E8.c b/src/ov_SC05_017/ov_SC05_017_jr_801875E8.c index 70945f9c8..36540af8d 100644 --- a/src/ov_SC05_017/ov_SC05_017_jr_801875E8.c +++ b/src/ov_SC05_017/ov_SC05_017_jr_801875E8.c @@ -3629,4 +3629,136 @@ s32 *func_801886B8(s32 *ot, Panel_8017E978_801886B8 *w0, s16 idx) { } -INCLUDE_ASM("asm/ov_SC05_017/nonmatchings/ov_SC05_017_jr_801875E8", func_80188884); + +/* func_80188884 — "resolve one HUD sub-item's tile pointer", 166 ins, jtbl_801E597C + * (8 entries, minval 7 -> `addiu $a1,$a1,-7` + HImode re-extension, so the switch value is + * `(s16)arg1` with cases 7..14 — the same construction as the already-matched twin + * func_80188E1C in this overlay). Case bodies are emitted in SOURCE order, so the order here + * is 10/11/13, 12, 7/8, 14, default (block order after the jr: 80188C0C, 80188C5C, 80188CB8, + * 80188D10, 80188DC4). Case 9 is ABSENT: its jtbl slot (index 2) points at the default label. + * + * Structural sibling that fixed the whole engine idiom (already matched): + * src/ov_SC03_099/ov_SC03_099_jr_8013FFD8.c func_8013FFD8 + * `*arg2 = 0x808080; ret = 0; switch(...) … return ret;`, the `s16 v1 = (s16)arg1;` + * per-case truncation temp, `return 1` on the zero probe, `D_8010EDE8[v3 * 3]`, + * `*arg2 = 0x804040`. + * + * Four register/shape constraints read off the target: + * + * (a) the default arm's `< (mode == 5 ? 4 : 3)` must be a VALUE (`ok`), not a COND_EXPR in the + * `if`. do_jump's COND_EXPR case emits one conditional branch PER ARM (`bnez`+`beqz`, + * +4 ins); the target converges both `slti`s on a single `beqz`, which is the store-then- + * test form. `v1` must also be an s32 temp taken BEFORE the `mode == 5` test — a short + * local is re-extended inside each arm instead of being shared (+2 ins). The body then + * re-derives `(s16)arg3` (the ternary's label ends the cse block) and combine folds + * sra16+sll2 into the target's `sra $v0,$v0,14`. + * + * (b) `D_8010F468[(k + 1) * 2]` must go through the temp `e`. Written inline, fold + * distributes the +1 into the address (`sll $v0,$s0,3` + `lw $s0,8($at)`) and the + * function is one instruction short; a VAR_DECL leaf blocks the distribution and gives + * the target's `addiu $v0,$s0,1; sll $v0,$v0,3`. + * + * (c) `n` must be built IN PLACE (`n = A; n = n * B;`). As one expression the first `lbu` + * is a block-local quantity, local-alloc hands it $a0, and arg0's allocno then CONFLICTS + * with $a0 — so arg0 is copied out to $t1 and the target's `addu $t0,$a1,$zero` (the arg1 + * copy) never appears. In-place, arg0 keeps $a0 and the whole prologue falls into place. + * + * (d) RC-12 ($0-ADD OPAQUE COPY, docs/gcc-2.7.2-map/regalloc.md, and the same lever the + * matched func_801889B8 above needed). The target keeps arg1 in TWO registers: $a1 is + * consumed in place by the switch index (`addiu $a1,$a1,-7`) while the default arm reads + * the copy in $t0. A plain `mode = arg1;` is coalesced away and arg1 keeps $a1, pushing + * the switch index to $t0. `mode = arg1 + zr` is a (plus rA (reg 0)) — not a reg-reg set, + * so nothing merges it — and assembles to the byte-identical `addu $t0,$a1,$zero`. + * Finally `n = func_800291B4(c)` REUSES n as the second probe's temp: that 8th reference + * is what lifts n's allocno priority above the per-case `j` allocnos, so n gets $v1 and + * `j` gets $a1/$a0 instead of the other way round (the last 23-instruction residual). + */ + +s32 func_80188884(void *arg0, s32 arg1, s32 arg2, s32 arg3, s32 *arg4) { + + extern s32 func_800291B4(s32 arg); + + extern u8 D_80115140[]; + extern u8 D_80115158[]; + extern u8 D_80115159[]; + extern u8 D_8018E28C[]; + extern u8 D_801ED610[]; + extern u8 D_801ED618[]; + extern s32 D_8010EDE8[]; + extern s32 D_8010F468[]; + extern s32 D_801B8EC4; + + register s32 zr __asm__("$0"); + s32 ret; + s32 n; + s32 mode; + + *arg4 = 0x808080; + n = D_80115159[(s16)arg2 * 2]; + n = n * D_80115158[(s16)arg2 * 2]; + ret = 0; + mode = arg1 + zr; + + switch ((s16)arg1) { /* jtbl_801E597C */ + case 10: + case 11: + case 13: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + ret = ((s32 *)arg0)[(s16)j]; + } + break; + } + + case 12: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + ret = ((s32 *)arg0)[D_801ED610[(s16)j]]; + } + break; + } + + case 7: + case 8: { + s16 v1 = (s16)arg3; + if (v1 < 0xC) { + s32 t = func_800291B4(D_8018E28C[v1]) & 0xFF; + if (t == 0) { + return 1; + } + ret = D_8010EDE8[t * 3]; + } + break; + } + + case 14: { + s32 j = arg3 + D_80115140[(s16)arg2]; + if ((s16)arg3 < 6 && (s16)j < (s16)n) { + s32 k = D_801ED618[(s16)j]; + s32 c = k + 0x63; + if (k < 0 || (func_800291B4(c) & 0x40) == 0) { + ret = D_801B8EC4; + } else { + s32 e = k + 1; + ret = D_8010F468[e * 2]; + n = func_800291B4(c); + if (n & 0x20) { + *arg4 = 0x804040; + } + } + } + break; + } + + default: { + s32 v1 = (s16)arg3; + s32 ok = ((s16)mode == 5) ? (v1 < 4) : (v1 < 3); + if (ok) { + ret = ((s32 *)arg0)[(s16)arg3]; + } + break; + } + } + + return ret; +}