diff --git a/config/overlays.mk b/config/overlays.mk
index ea85612cd0..e7bb245708 100644
--- a/config/overlays.mk
+++ b/config/overlays.mk
@@ -2910,7 +2910,7 @@ ov_SC03_124_ELF        := $(ov_SC03_124_OUT).elf
 ov_SC03_124_MAPFILE    := $(ov_SC03_124_OUT).map
 ov_SC03_124_LD_SCRIPT  := $(ov_SC03_124_OUT).ld
 ov_SC03_124_SPLAT_YAML := config/splat.ov_SC03_124.yaml
-ov_SC03_124_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_124.o,ov_SC03_124_jr_8012ACE0.o,tail2.data.o,ov_SC03_124_jr_80135888.o,tail3.data.o,ov_SC03_124_jr_80135A4C.o,tail4.data.o,ov_SC03_124_jr_80135D20.o,tail5.data.o,ov_SC03_124_jr_801380E0.o,ov_SC03_124_o0c.o,tail6.data.o,ov_SC03_124_jr_8013F350.o,tail7.data.o,ov_SC03_124_jr_8013FFD8.o,tail8.data.o,ov_SC03_124_jr_80140608.o,tail9.data.o,ov_SC03_124_jr_8015444C.o,ov_SC03_124_jr_80154C24.o,ov_SC03_124_jr_801588CC.o,ov_SC03_124_jr_80159C84.o,tail10.data.o,ov_SC03_124_jr_8015A3C8.o,tail11.data.o,ov_SC03_124_jr_8015AE2C.o,tail12.data.o,ov_SC03_124_jr_8015C32C.o,tail13.data.o,ov_SC03_124_jr_8016AB6C.o,tail14.data.o,ov_SC03_124_jr_80171B4C.o,ov_SC03_124_jr_801734BC.o,tail15.data.o,ov_SC03_124_jr_801789AC.o,ov_SC03_124_jr_80178D40.o,tail16.data.o,ov_SC03_124_jr_8017A4AC.o,tail17.data.o,ov_SC03_124_jr_8017AE2C.o,tail18.data.o,ov_SC03_124_jr_80181B44.o,ov_SC03_124_jr_80185498.o,tail19.data.o,ov_SC03_124_jr_80185C98.o,tail20.data.o,ov_SC03_124_jr_80187010.o,ov_SC03_124_jr_80188544.o,tail21.data.o,trailing.o  # Phase-26 §8 jtbl-rodata carve
+ov_SC03_124_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_124.o,ov_SC03_124_jr_8012ACE0.o,tail2.data.o,ov_SC03_124_jr_80135888.o,tail3.data.o,ov_SC03_124_jr_80135A4C.o,tail4.data.o,ov_SC03_124_jr_80135D20.o,tail5.data.o,ov_SC03_124_jr_801380E0.o,ov_SC03_124_o0c.o,tail6.data.o,ov_SC03_124_jr_8013F350.o,tail7.data.o,ov_SC03_124_jr_8013FFD8.o,tail8.data.o,ov_SC03_124_jr_80140608.o,tail9.data.o,ov_SC03_124_jr_8015444C.o,ov_SC03_124_jr_80154C24.o,ov_SC03_124_jr_801588CC.o,ov_SC03_124_jr_80159C84.o,tail10.data.o,ov_SC03_124_jr_8015A3C8.o,tail11.data.o,ov_SC03_124_jr_8015AE2C.o,tail12.data.o,ov_SC03_124_jr_8015C32C.o,tail13.data.o,ov_SC03_124_jr_8016AB6C.o,tail14.data.o,ov_SC03_124_jr_80171B4C.o,ov_SC03_124_jr_801734BC.o,tail15.data.o,ov_SC03_124_jr_801789AC.o,ov_SC03_124_jr_80178D40.o,tail16.data.o,ov_SC03_124_jr_8017A4AC.o,tail17.data.o,ov_SC03_124_jr_8017AE2C.o,ov_SC03_124_jr_80181B44.o,ov_SC03_124_jr_80185498.o,tail18.data.o,ov_SC03_124_jr_80185C98.o,tail19.data.o,ov_SC03_124_jr_80187010.o,ov_SC03_124_jr_80188544.o,tail20.data.o,trailing.o  # Phase-26 §8 jtbl-rodata carve
 build/src/ov_SC03_124/ov_SC03_124.o: JTBL_PADS := 0,0  # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
 build/src/ov_SC03_124/ov_SC03_124_jr_8012ACE0.o: JTBL_PADS := 0,0,0  # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0
 build/src/ov_SC03_124/ov_SC03_124_jr_80135D20.o: JTBL_PADS := 0,4  # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
@@ -2923,7 +2923,7 @@ build/src/ov_SC03_124/ov_SC03_124_jr_80159C84.o: JTBL_PADS := 0,4  # §8e pads (
 build/src/ov_SC03_124/ov_SC03_124_jr_8015AE2C.o: JTBL_PADS := 0,4  # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
 build/src/ov_SC03_124/ov_SC03_124_jr_8016AB6C.o: JTBL_PADS := 0,0  # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
 build/src/ov_SC03_124/ov_SC03_124_jr_80178D40.o: JTBL_PADS := 0,0  # §8e pads (jtbl_carve.py) tables=+0x0,+0x178
-build/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.o: JTBL_PADS := 0,0  # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
+build/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.o: JTBL_PADS := 0,0,0,0  # §8e pads (jtbl_carve.py) tables=+0x0,+0x14,+0x34,+0x48
 build/src/ov_SC03_124/ov_SC03_124_jr_80187010.o: JTBL_PADS := 0,0  # §8e pads (jtbl_carve.py) tables=+0x0,+0x38
 build/src/ov_SC03_124/ov_SC03_124_o0c.o: JTBL_PADS := 0,4,4,4  # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118
 ov_SC03_124_CHECK_SHA  := config/check.ov_SC03_124.sha
diff --git a/config/splat.ov_SC03_124.yaml b/config/splat.ov_SC03_124.yaml
index 00836c5775..324ff8e208 100644
--- a/config/splat.ov_SC03_124.yaml
+++ b/config/splat.ov_SC03_124.yaml
@@ -166,15 +166,14 @@ segments:
       - [0xb7e64, .rodata, ov_SC03_124_jr_8017A4AC]  # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
       - [0xb7ef0, data, tail17]
       - [0xb7ef4, .rodata, ov_SC03_124_jr_8017AE2C]  # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
-      - [0xb7f28, data, tail18]
       - [0xb7f50, .rodata, ov_SC03_124_jr_80181B44]  # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
       - [0xb7f68, .rodata, ov_SC03_124_jr_80185498]  # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
-      - [0xb7f84, data, tail19]
+      - [0xb7f84, data, tail18]
       - [0xb8224, .rodata, ov_SC03_124_jr_80185C98]  # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
-      - [0xb8238, data, tail20]
+      - [0xb8238, data, tail19]
       - [0xb82ac, .rodata, ov_SC03_124_jr_80187010]  # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
       - [0xb8304, .rodata, ov_SC03_124_jr_80188544]  # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
-      - [0xb8360, data, tail21]
+      - [0xb8360, data, tail20]
       - [0xBA48C, bin, trailing]    # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
   - [0xBA48F]   # EOF marker = the 0.4.dec byte length
 # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes
diff --git a/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c b/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c
index 54c9fa48b5..6421803e69 100644
--- a/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c
+++ b/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c
@@ -6028,7 +6028,65 @@ void func_8018004C(s32 a0) {
 }
 
 
-INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_8017AE2C", func_8018009C);
+extern s32 D_801BEAF8;
+extern s32 D_801D3BC4;
+extern void func_8012A828(s32, s32);
+extern s32 func_8012B608(s32, s32, s32);
+
+void func_8018009C(s32 param_1)
+{
+    s32 v0;
+    s32 a1;
+    s32 t0;
+    s32 t1;
+    s32 r;
+
+    switch ((s16)(*(u16 *)(param_1 + 0xFC) - 1)) {
+    case 1:
+        if (*(s32 *)(param_1 + 0x90) != (s32)&D_801D3BC4) {
+            func_8012A828(param_1, (s32)&D_801D3BC4);
+        }
+        v0 = *(s32 *)(param_1 + 0x20);
+        __asm__ __volatile__(""); /* §5a cross-jump barrier, placed between the two tail
+                                      stores (not immediately before the jump) so reorg can
+                                      still fill the branch delay slot with `a1 = 0xC00`;
+                                      keeps this arm's tail distinct from case 0's identical
+                                      one so gcc does not fold the two duplicate tails */
+        a1 = 0xC00;
+        goto common;
+    case 0:
+        if (*(s32 *)(param_1 + 0x90) != (s32)&D_801BEAF8) {
+            func_8012A828(param_1, (s32)&D_801BEAF8);
+        }
+        v0 = *(s32 *)(param_1 + 0x20);
+        a1 = 0xC00;
+        goto common;
+    case 3:
+        t0 = *(s32 *)(param_1 + 0x90);
+        t1 = (s32)&D_801D3BC4;
+        goto LAB_80180154;
+    case 2:
+        t0 = *(s32 *)(param_1 + 0x90);
+        t1 = (s32)&D_801BEAF8;
+    LAB_80180154:
+        if (t0 != t1) {
+            func_8012A828(param_1, t1);
+        }
+        v0 = *(s32 *)(param_1 + 0x20);
+        a1 = 0xE00;
+    common:
+        r = func_8012B608((s32)*(s16 *)(v0 + 0x12), a1, 8);
+        *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) =
+            *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) + r;
+        return;
+    case 4:
+        func_801801B0(param_1);
+        return;
+    default:
+        return;
+    }
+}
+
 
 extern short D_801BEA50;
 extern void func_8012A828(s32, s32);
@@ -6733,7 +6791,84 @@ s32 func_8018107C()
 }
 
 
-INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_jr_8017AE2C", func_801810E4);
+void func_801810E4(void *a0)
+{
+    extern s32 func_801846CC(s32 a0);
+    extern void func_801845FC(s32, s32, s32, s32);
+    extern s32 func_801842D4(s32 a0, s32 a1);
+    extern void func_8012A828(s32, s32);
+    extern s32 func_8012BEE8(s32 a0);
+    extern s32 func_8012C588(s32 a0, s32 a1);
+    extern void func_8012E8A8(u8 *a0);
+    extern void func_8012C218(void *a0);
+    extern s32 func_80132EF4(s32 a0, s32 a1);
+    extern u8 D_80190020;
+    extern s32 D_80190024[];
+    extern s16 D_8018FF68;
+    extern s16 D_8018FEE4;
+    extern s16 D_8018FEE8;
+    extern s32 D_801E1A24;
+
+    s32 i;
+    s32 t;
+    s32 t2;
+    s32 a3v;
+
+    switch (*(u16 *)((s32)a0 + 0x34)) {
+    case 0:
+        if (func_801846CC((s32)a0) != 0) {
+            a3v = D_80190020;
+            *(s16 *)((s32)a0 + 0x34) = 1;
+            func_801845FC((s32)a0, D_80190024[*(s16 *)((s32)a0 + 0x70)], 0, a3v);
+        }
+        if (func_801842D4(7, 0x17) != 0) {
+            *(s16 *)((s32)a0 + 0x34) = 2;
+        }
+        break;
+    case 1:
+        if (func_801846CC((s32)a0) != 0) {
+            a3v = D_80190020;
+            *(s16 *)((s32)a0 + 0x34) = 0;
+            func_801845FC((s32)a0, D_80190024[*(s16 *)((s32)a0 + 0x70)], 1, a3v);
+        }
+        if (func_801842D4(7, 0x17) != 0) {
+            *(s16 *)((s32)a0 + 0x34) = 2;
+        }
+        break;
+    case 2:
+        *(s16 *)((s32)a0 + 0x34) = 3;
+        func_8012A828((s32)a0, (s32)&D_8018FF68);
+        *(s32 *)((s32)a0 + 0x1C) = 0x14;
+        break;
+    case 3:
+        if (func_8012BEE8((s32)a0) != 0) {
+            if (D_8018FEE8 + 4 >= D_801E1A24) {
+                t2 = D_801E1A24 + 2;
+                D_801E1A24 = t2 + D_8018FEE8;
+                for (i = 0; i < D_8018FEE4; i++) {
+                    func_8012C588(0x25F, (s32)a0);
+                }
+                func_8012E8A8((u8 *)a0);
+                *(s32 *)((s32)a0 + 0x1C) = 0xA;
+                *(u16 *)((s32)a0 + 0x34) = *(u16 *)((s32)a0 + 0x34) + 1;
+            }
+        }
+        break;
+    case 4:
+        if ((*(s32 *)((s32)a0 + 0x1C) & 1) == 0) {
+            t = func_80132EF4((s32)a0, 0x22);
+            if (t != 0) {
+                *(s16 *)(t + 0x34) = 0x5001;
+                *(s32 *)(t + 0x14) = 0xFFFA0000;
+            }
+        }
+        if (func_8012BEE8((s32)a0) != 0) {
+            func_8012C218(a0);
+        }
+        break;
+    }
+}
+
 
 
 extern void (*D_8019003C[])(void);