From c824c19a3dd1f76c0d75f9f8ffbeb7e2965fb956 Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Tue, 11 Aug 2026 18:35:20 -0600 Subject: [PATCH] feat(phase-30 S48-T6): propagate func_80185F58 to its zero-crack siblings --- config/overlays.mk | 17 ++- config/splat.ov_SC06_020.yaml | 3 +- config/splat.ov_SC06_022.yaml | 3 +- config/splat.ov_SC06_024.yaml | 3 +- config/splat.ov_SC06_032.yaml | 7 +- config/splat.ov_SC06_033.yaml | 7 +- src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c | 172 +++++++++++++++++++++- src/ov_SC06_022/ov_SC06_022_jr_80182D08.c | 172 +++++++++++++++++++++- src/ov_SC06_024/ov_SC06_024_jr_801851E0.c | 172 +++++++++++++++++++++- src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c | 172 +++++++++++++++++++++- src/ov_SC06_033/ov_SC06_033_jr_801836FC.c | 172 +++++++++++++++++++++- 11 files changed, 874 insertions(+), 26 deletions(-) diff --git a/config/overlays.mk b/config/overlays.mk index bb30d9651..4552abce9 100644 --- a/config/overlays.mk +++ b/config/overlays.mk @@ -4312,7 +4312,7 @@ ov_SC06_020_ELF := $(ov_SC06_020_OUT).elf ov_SC06_020_MAPFILE := $(ov_SC06_020_OUT).map ov_SC06_020_LD_SCRIPT := $(ov_SC06_020_OUT).ld ov_SC06_020_SPLAT_YAML := config/splat.ov_SC06_020.yaml -ov_SC06_020_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_020.o,ov_SC06_020_jr_8012ACE0.o,tail2.data.o,ov_SC06_020_jr_80135888.o,tail3.data.o,ov_SC06_020_jr_80135A4C.o,tail4.data.o,ov_SC06_020_jr_80135D20.o,tail5.data.o,ov_SC06_020_jr_801380E0.o,ov_SC06_020_o0c.o,tail6.data.o,ov_SC06_020_jr_8013F350.o,tail7.data.o,ov_SC06_020_jr_8013FFD8.o,tail8.data.o,ov_SC06_020_jr_80140608.o,tail9.data.o,ov_SC06_020_jr_8015444C.o,ov_SC06_020_jr_80154C24.o,ov_SC06_020_jr_801588CC.o,ov_SC06_020_jr_80159C84.o,tail10.data.o,ov_SC06_020_jr_8015A3C8.o,tail11.data.o,ov_SC06_020_jr_8015AE2C.o,tail12.data.o,ov_SC06_020_jr_8015C32C.o,tail13.data.o,ov_SC06_020_jr_8016AB6C.o,tail14.data.o,ov_SC06_020_jr_80171B4C.o,ov_SC06_020_jr_801734BC.o,tail15.data.o,ov_SC06_020_jr_801789AC.o,ov_SC06_020_jr_80178D40.o,tail16.data.o,ov_SC06_020_jr_8017A4AC.o,tail17.data.o,ov_SC06_020_jr_8017AE2C.o,ov_SC06_020_jr_8017C24C.o,tail18.data.o,ov_SC06_020_jr_801803E0.o,ov_SC06_020_jr_80180B04.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_020_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_020.o,ov_SC06_020_jr_8012ACE0.o,tail2.data.o,ov_SC06_020_jr_80135888.o,tail3.data.o,ov_SC06_020_jr_80135A4C.o,tail4.data.o,ov_SC06_020_jr_80135D20.o,tail5.data.o,ov_SC06_020_jr_801380E0.o,ov_SC06_020_o0c.o,tail6.data.o,ov_SC06_020_jr_8013F350.o,tail7.data.o,ov_SC06_020_jr_8013FFD8.o,tail8.data.o,ov_SC06_020_jr_80140608.o,tail9.data.o,ov_SC06_020_jr_8015444C.o,ov_SC06_020_jr_80154C24.o,ov_SC06_020_jr_801588CC.o,ov_SC06_020_jr_80159C84.o,tail10.data.o,ov_SC06_020_jr_8015A3C8.o,tail11.data.o,ov_SC06_020_jr_8015AE2C.o,tail12.data.o,ov_SC06_020_jr_8015C32C.o,tail13.data.o,ov_SC06_020_jr_8016AB6C.o,tail14.data.o,ov_SC06_020_jr_80171B4C.o,ov_SC06_020_jr_801734BC.o,tail15.data.o,ov_SC06_020_jr_801789AC.o,ov_SC06_020_jr_80178D40.o,tail16.data.o,ov_SC06_020_jr_8017A4AC.o,tail17.data.o,ov_SC06_020_jr_8017AE2C.o,ov_SC06_020_jr_8017C24C.o,ov_SC06_020_jr_801803E0.o,ov_SC06_020_jr_80180B04.o,tail18.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_020/ov_SC06_020.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_020/ov_SC06_020_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_020/ov_SC06_020_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 @@ -4325,7 +4325,7 @@ build/src/ov_SC06_020/ov_SC06_020_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_020/ov_SC06_020_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_020/ov_SC06_020_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_020/ov_SC06_020_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 -build/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.o: JTBL_PADS := 0,0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38 build/src/ov_SC06_020/ov_SC06_020_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118 ov_SC06_020_CHECK_SHA := config/check.ov_SC06_020.sha ov_SC06_020_SYMBOLS := config/symbols.ov_SC06_020.txt @@ -4348,7 +4348,7 @@ ov_SC06_022_ELF := $(ov_SC06_022_OUT).elf ov_SC06_022_MAPFILE := $(ov_SC06_022_OUT).map ov_SC06_022_LD_SCRIPT := $(ov_SC06_022_OUT).ld ov_SC06_022_SPLAT_YAML := config/splat.ov_SC06_022.yaml -ov_SC06_022_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_022.o,ov_SC06_022_jr_8012ACE0.o,tail2.data.o,ov_SC06_022_jr_80135888.o,tail3.data.o,ov_SC06_022_jr_80135A4C.o,tail4.data.o,ov_SC06_022_jr_80135D20.o,tail5.data.o,ov_SC06_022_jr_801380E0.o,ov_SC06_022_o0c.o,tail6.data.o,ov_SC06_022_jr_8013F350.o,tail7.data.o,ov_SC06_022_jr_8013FFD8.o,tail8.data.o,ov_SC06_022_jr_80140608.o,tail9.data.o,ov_SC06_022_jr_8015444C.o,ov_SC06_022_jr_80154C24.o,ov_SC06_022_jr_801588CC.o,ov_SC06_022_jr_80159C84.o,tail10.data.o,ov_SC06_022_jr_8015A3C8.o,tail11.data.o,ov_SC06_022_jr_8015AE2C.o,tail12.data.o,ov_SC06_022_jr_8015C32C.o,tail13.data.o,ov_SC06_022_jr_8016AB6C.o,tail14.data.o,ov_SC06_022_jr_80171B4C.o,ov_SC06_022_jr_801734BC.o,tail15.data.o,ov_SC06_022_jr_801789AC.o,ov_SC06_022_jr_80178D40.o,tail16.data.o,ov_SC06_022_jr_8017A4AC.o,tail17.data.o,ov_SC06_022_jr_8017AE2C.o,ov_SC06_022_jr_8017BEBC.o,tail18.data.o,ov_SC06_022_jr_80182D08.o,tail19.data.o,ov_SC06_022_jr_80184304.o,ov_SC06_022_jr_80184A28.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_022_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_022.o,ov_SC06_022_jr_8012ACE0.o,tail2.data.o,ov_SC06_022_jr_80135888.o,tail3.data.o,ov_SC06_022_jr_80135A4C.o,tail4.data.o,ov_SC06_022_jr_80135D20.o,tail5.data.o,ov_SC06_022_jr_801380E0.o,ov_SC06_022_o0c.o,tail6.data.o,ov_SC06_022_jr_8013F350.o,tail7.data.o,ov_SC06_022_jr_8013FFD8.o,tail8.data.o,ov_SC06_022_jr_80140608.o,tail9.data.o,ov_SC06_022_jr_8015444C.o,ov_SC06_022_jr_80154C24.o,ov_SC06_022_jr_801588CC.o,ov_SC06_022_jr_80159C84.o,tail10.data.o,ov_SC06_022_jr_8015A3C8.o,tail11.data.o,ov_SC06_022_jr_8015AE2C.o,tail12.data.o,ov_SC06_022_jr_8015C32C.o,tail13.data.o,ov_SC06_022_jr_8016AB6C.o,tail14.data.o,ov_SC06_022_jr_80171B4C.o,ov_SC06_022_jr_801734BC.o,tail15.data.o,ov_SC06_022_jr_801789AC.o,ov_SC06_022_jr_80178D40.o,tail16.data.o,ov_SC06_022_jr_8017A4AC.o,tail17.data.o,ov_SC06_022_jr_8017AE2C.o,ov_SC06_022_jr_8017BEBC.o,tail18.data.o,ov_SC06_022_jr_80182D08.o,ov_SC06_022_jr_80184304.o,ov_SC06_022_jr_80184A28.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_022/ov_SC06_022.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_022/ov_SC06_022_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_022/ov_SC06_022_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 @@ -4361,6 +4361,7 @@ build/src/ov_SC06_022/ov_SC06_022_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_022/ov_SC06_022_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_022/ov_SC06_022_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_022/ov_SC06_022_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_022/ov_SC06_022_jr_80182D08.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_022/ov_SC06_022_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118 ov_SC06_022_CHECK_SHA := config/check.ov_SC06_022.sha ov_SC06_022_SYMBOLS := config/symbols.ov_SC06_022.txt @@ -4383,7 +4384,7 @@ ov_SC06_024_ELF := $(ov_SC06_024_OUT).elf ov_SC06_024_MAPFILE := $(ov_SC06_024_OUT).map ov_SC06_024_LD_SCRIPT := $(ov_SC06_024_OUT).ld ov_SC06_024_SPLAT_YAML := config/splat.ov_SC06_024.yaml -ov_SC06_024_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_024.o,ov_SC06_024_jr_8012ACE0.o,tail2.data.o,ov_SC06_024_jr_80135888.o,tail3.data.o,ov_SC06_024_jr_80135A4C.o,tail4.data.o,ov_SC06_024_jr_80135D20.o,tail5.data.o,ov_SC06_024_jr_801380E0.o,ov_SC06_024_o0c.o,tail6.data.o,ov_SC06_024_jr_8013F350.o,tail7.data.o,ov_SC06_024_jr_8013FFD8.o,tail8.data.o,ov_SC06_024_jr_80140608.o,tail9.data.o,ov_SC06_024_jr_8015444C.o,ov_SC06_024_jr_80154C24.o,ov_SC06_024_jr_801588CC.o,ov_SC06_024_jr_80159C84.o,tail10.data.o,ov_SC06_024_jr_8015A3C8.o,tail11.data.o,ov_SC06_024_jr_8015AE2C.o,tail12.data.o,ov_SC06_024_jr_8015C32C.o,tail13.data.o,ov_SC06_024_jr_8016AB6C.o,tail14.data.o,ov_SC06_024_jr_80171B4C.o,ov_SC06_024_jr_801734BC.o,tail15.data.o,ov_SC06_024_jr_801789AC.o,ov_SC06_024_jr_80178D40.o,tail16.data.o,ov_SC06_024_jr_8017A4AC.o,tail17.data.o,ov_SC06_024_jr_8017AE2C.o,ov_SC06_024_jr_8017BEBC.o,tail18.data.o,ov_SC06_024_jr_801851E0.o,tail19.data.o,ov_SC06_024_jr_801867DC.o,ov_SC06_024_jr_80186F00.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_024_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_024.o,ov_SC06_024_jr_8012ACE0.o,tail2.data.o,ov_SC06_024_jr_80135888.o,tail3.data.o,ov_SC06_024_jr_80135A4C.o,tail4.data.o,ov_SC06_024_jr_80135D20.o,tail5.data.o,ov_SC06_024_jr_801380E0.o,ov_SC06_024_o0c.o,tail6.data.o,ov_SC06_024_jr_8013F350.o,tail7.data.o,ov_SC06_024_jr_8013FFD8.o,tail8.data.o,ov_SC06_024_jr_80140608.o,tail9.data.o,ov_SC06_024_jr_8015444C.o,ov_SC06_024_jr_80154C24.o,ov_SC06_024_jr_801588CC.o,ov_SC06_024_jr_80159C84.o,tail10.data.o,ov_SC06_024_jr_8015A3C8.o,tail11.data.o,ov_SC06_024_jr_8015AE2C.o,tail12.data.o,ov_SC06_024_jr_8015C32C.o,tail13.data.o,ov_SC06_024_jr_8016AB6C.o,tail14.data.o,ov_SC06_024_jr_80171B4C.o,ov_SC06_024_jr_801734BC.o,tail15.data.o,ov_SC06_024_jr_801789AC.o,ov_SC06_024_jr_80178D40.o,tail16.data.o,ov_SC06_024_jr_8017A4AC.o,tail17.data.o,ov_SC06_024_jr_8017AE2C.o,ov_SC06_024_jr_8017BEBC.o,tail18.data.o,ov_SC06_024_jr_801851E0.o,ov_SC06_024_jr_801867DC.o,ov_SC06_024_jr_80186F00.o,tail19.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_024/ov_SC06_024.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_024/ov_SC06_024_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_024/ov_SC06_024_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 @@ -4396,6 +4397,7 @@ build/src/ov_SC06_024/ov_SC06_024_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_024/ov_SC06_024_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_024/ov_SC06_024_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_024/ov_SC06_024_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_024/ov_SC06_024_jr_801851E0.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_024/ov_SC06_024_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118 ov_SC06_024_CHECK_SHA := config/check.ov_SC06_024.sha ov_SC06_024_SYMBOLS := config/symbols.ov_SC06_024.txt @@ -4559,7 +4561,7 @@ ov_SC06_032_ELF := $(ov_SC06_032_OUT).elf ov_SC06_032_MAPFILE := $(ov_SC06_032_OUT).map ov_SC06_032_LD_SCRIPT := $(ov_SC06_032_OUT).ld ov_SC06_032_SPLAT_YAML := config/splat.ov_SC06_032.yaml -ov_SC06_032_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_032.o,ov_SC06_032_jr_8012ACE0.o,tail2.data.o,ov_SC06_032_jr_80135888.o,tail3.data.o,ov_SC06_032_jr_80135A4C.o,tail4.data.o,ov_SC06_032_jr_80135D20.o,tail5.data.o,ov_SC06_032_jr_801380E0.o,ov_SC06_032_o0c.o,tail6.data.o,ov_SC06_032_jr_8013F350.o,tail7.data.o,ov_SC06_032_jr_8013FFD8.o,tail8.data.o,ov_SC06_032_jr_80140608.o,tail9.data.o,ov_SC06_032_jr_8015444C.o,ov_SC06_032_jr_80154C24.o,ov_SC06_032_jr_801588CC.o,ov_SC06_032_jr_80159C84.o,tail10.data.o,ov_SC06_032_jr_8015A3C8.o,tail11.data.o,ov_SC06_032_jr_8015AE2C.o,tail12.data.o,ov_SC06_032_jr_8015C32C.o,tail13.data.o,ov_SC06_032_jr_8016AB6C.o,tail14.data.o,ov_SC06_032_jr_80171B4C.o,ov_SC06_032_jr_801734BC.o,tail15.data.o,ov_SC06_032_jr_801789AC.o,ov_SC06_032_jr_80178D40.o,tail16.data.o,ov_SC06_032_jr_8017A4AC.o,tail17.data.o,ov_SC06_032_jr_8017AE2C.o,ov_SC06_032_jr_8017C24C.o,tail18.data.o,ov_SC06_032_jr_80181014.o,tail19.data.o,ov_SC06_032_jr_801902EC.o,tail20.data.o,ov_SC06_032_jr_801919A0.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_032_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_032.o,ov_SC06_032_jr_8012ACE0.o,tail2.data.o,ov_SC06_032_jr_80135888.o,tail3.data.o,ov_SC06_032_jr_80135A4C.o,tail4.data.o,ov_SC06_032_jr_80135D20.o,tail5.data.o,ov_SC06_032_jr_801380E0.o,ov_SC06_032_o0c.o,tail6.data.o,ov_SC06_032_jr_8013F350.o,tail7.data.o,ov_SC06_032_jr_8013FFD8.o,tail8.data.o,ov_SC06_032_jr_80140608.o,tail9.data.o,ov_SC06_032_jr_8015444C.o,ov_SC06_032_jr_80154C24.o,ov_SC06_032_jr_801588CC.o,ov_SC06_032_jr_80159C84.o,tail10.data.o,ov_SC06_032_jr_8015A3C8.o,tail11.data.o,ov_SC06_032_jr_8015AE2C.o,tail12.data.o,ov_SC06_032_jr_8015C32C.o,tail13.data.o,ov_SC06_032_jr_8016AB6C.o,tail14.data.o,ov_SC06_032_jr_80171B4C.o,ov_SC06_032_jr_801734BC.o,tail15.data.o,ov_SC06_032_jr_801789AC.o,ov_SC06_032_jr_80178D40.o,tail16.data.o,ov_SC06_032_jr_8017A4AC.o,tail17.data.o,ov_SC06_032_jr_8017AE2C.o,ov_SC06_032_jr_8017C24C.o,ov_SC06_032_jr_80181014.o,tail18.data.o,ov_SC06_032_jr_801902EC.o,tail19.data.o,ov_SC06_032_jr_801919A0.o,tail20.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_032/ov_SC06_032.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_032/ov_SC06_032_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_032/ov_SC06_032_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 @@ -4572,7 +4574,7 @@ build/src/ov_SC06_032/ov_SC06_032_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_032/ov_SC06_032_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_032/ov_SC06_032_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_032/ov_SC06_032_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 -build/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.o: JTBL_PADS := 0,0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20,+0x38 build/src/ov_SC06_032/ov_SC06_032_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118 ov_SC06_032_CHECK_SHA := config/check.ov_SC06_032.sha ov_SC06_032_SYMBOLS := config/symbols.ov_SC06_032.txt @@ -4595,7 +4597,7 @@ ov_SC06_033_ELF := $(ov_SC06_033_OUT).elf ov_SC06_033_MAPFILE := $(ov_SC06_033_OUT).map ov_SC06_033_LD_SCRIPT := $(ov_SC06_033_OUT).ld ov_SC06_033_SPLAT_YAML := config/splat.ov_SC06_033.yaml -ov_SC06_033_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_033.o,ov_SC06_033_jr_8012ACE0.o,tail2.data.o,ov_SC06_033_jr_80135888.o,tail3.data.o,ov_SC06_033_jr_80135A4C.o,tail4.data.o,ov_SC06_033_jr_80135D20.o,tail5.data.o,ov_SC06_033_jr_801380E0.o,ov_SC06_033_o0c.o,tail6.data.o,ov_SC06_033_jr_8013F350.o,tail7.data.o,ov_SC06_033_jr_8013FFD8.o,tail8.data.o,ov_SC06_033_jr_80140608.o,tail9.data.o,ov_SC06_033_jr_8015444C.o,ov_SC06_033_jr_80154C24.o,ov_SC06_033_jr_801588CC.o,ov_SC06_033_jr_80159C84.o,tail10.data.o,ov_SC06_033_jr_8015A3C8.o,tail11.data.o,ov_SC06_033_jr_8015AE2C.o,tail12.data.o,ov_SC06_033_jr_8015C32C.o,tail13.data.o,ov_SC06_033_jr_8016AB6C.o,tail14.data.o,ov_SC06_033_jr_80171B4C.o,ov_SC06_033_jr_801734BC.o,tail15.data.o,ov_SC06_033_jr_801789AC.o,ov_SC06_033_jr_80178D40.o,tail16.data.o,ov_SC06_033_jr_8017A4AC.o,tail17.data.o,ov_SC06_033_jr_8017AE2C.o,ov_SC06_033_jr_8017C24C.o,tail18.data.o,ov_SC06_033_jr_801836FC.o,tail19.data.o,ov_SC06_033_jr_80184CF8.o,tail20.data.o,ov_SC06_033_jr_8018C2D8.o,tail21.data.o,ov_SC06_033_jr_8018D98C.o,tail22.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve +ov_SC06_033_JTBL_INTERLEAVE := --order tail.data.o,ov_SC06_033.o,ov_SC06_033_jr_8012ACE0.o,tail2.data.o,ov_SC06_033_jr_80135888.o,tail3.data.o,ov_SC06_033_jr_80135A4C.o,tail4.data.o,ov_SC06_033_jr_80135D20.o,tail5.data.o,ov_SC06_033_jr_801380E0.o,ov_SC06_033_o0c.o,tail6.data.o,ov_SC06_033_jr_8013F350.o,tail7.data.o,ov_SC06_033_jr_8013FFD8.o,tail8.data.o,ov_SC06_033_jr_80140608.o,tail9.data.o,ov_SC06_033_jr_8015444C.o,ov_SC06_033_jr_80154C24.o,ov_SC06_033_jr_801588CC.o,ov_SC06_033_jr_80159C84.o,tail10.data.o,ov_SC06_033_jr_8015A3C8.o,tail11.data.o,ov_SC06_033_jr_8015AE2C.o,tail12.data.o,ov_SC06_033_jr_8015C32C.o,tail13.data.o,ov_SC06_033_jr_8016AB6C.o,tail14.data.o,ov_SC06_033_jr_80171B4C.o,ov_SC06_033_jr_801734BC.o,tail15.data.o,ov_SC06_033_jr_801789AC.o,ov_SC06_033_jr_80178D40.o,tail16.data.o,ov_SC06_033_jr_8017A4AC.o,tail17.data.o,ov_SC06_033_jr_8017AE2C.o,ov_SC06_033_jr_8017C24C.o,tail18.data.o,ov_SC06_033_jr_801836FC.o,ov_SC06_033_jr_80184CF8.o,tail19.data.o,ov_SC06_033_jr_8018C2D8.o,tail20.data.o,ov_SC06_033_jr_8018D98C.o,tail21.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve build/src/ov_SC06_033/ov_SC06_033.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14 build/src/ov_SC06_033/ov_SC06_033_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0 build/src/ov_SC06_033/ov_SC06_033_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 @@ -4608,6 +4610,7 @@ build/src/ov_SC06_033/ov_SC06_033_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_033/ov_SC06_033_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_033/ov_SC06_033_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_033/ov_SC06_033_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_033/ov_SC06_033_jr_801836FC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC06_033/ov_SC06_033_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118 ov_SC06_033_CHECK_SHA := config/check.ov_SC06_033.sha ov_SC06_033_SYMBOLS := config/symbols.ov_SC06_033.txt diff --git a/config/splat.ov_SC06_020.yaml b/config/splat.ov_SC06_020.yaml index 19bd0efed..9233c2854 100644 --- a/config/splat.ov_SC06_020.yaml +++ b/config/splat.ov_SC06_020.yaml @@ -165,10 +165,9 @@ segments: - [0x91138, data, tail17] - [0x9113c, .rodata, ov_SC06_020_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x91150, .rodata, ov_SC06_020_jr_8017C24C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x91184, data, tail18] - [0x91250, .rodata, ov_SC06_020_jr_801803E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x91268, .rodata, ov_SC06_020_jr_80180B04] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9127c, data, tail19] + - [0x9127c, data, tail18] - [0x92894, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0x92897] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_022.yaml b/config/splat.ov_SC06_022.yaml index 1eaeb3dbe..2b088d13d 100644 --- a/config/splat.ov_SC06_022.yaml +++ b/config/splat.ov_SC06_022.yaml @@ -168,10 +168,9 @@ segments: - [0xb8960, .rodata, ov_SC06_022_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb8980, data, tail18] - [0xb89d4, .rodata, ov_SC06_022_jr_80182D08] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb89e8, data, tail19] - [0xb8ab4, .rodata, ov_SC06_022_jr_80184304] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb8acc, .rodata, ov_SC06_022_jr_80184A28] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb8ae0, data, tail20] + - [0xb8ae0, data, tail19] - [0xBA114, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xBA117] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_024.yaml b/config/splat.ov_SC06_024.yaml index 328f0fb8a..d4324b566 100644 --- a/config/splat.ov_SC06_024.yaml +++ b/config/splat.ov_SC06_024.yaml @@ -168,10 +168,9 @@ segments: - [0xb7aa4, .rodata, ov_SC06_024_jr_8017BEBC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7ac4, data, tail18] - [0xb7b58, .rodata, ov_SC06_024_jr_801851E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7b6c, data, tail19] - [0xb7c38, .rodata, ov_SC06_024_jr_801867DC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7c50, .rodata, ov_SC06_024_jr_80186F00] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7c64, data, tail20] + - [0xb7c64, data, tail19] - [0xB980C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xB980F] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_032.yaml b/config/splat.ov_SC06_032.yaml index 424287f37..a8f269aaf 100644 --- a/config/splat.ov_SC06_032.yaml +++ b/config/splat.ov_SC06_032.yaml @@ -166,13 +166,12 @@ segments: - [0xa6e24, data, tail17] - [0xa6e28, .rodata, ov_SC06_032_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6e3c, .rodata, ov_SC06_032_jr_8017C24C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6e70, data, tail18] - [0xa6f3c, .rodata, ov_SC06_032_jr_80181014] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6f54, data, tail19] + - [0xa6f54, data, tail18] - [0xa6fc8, .rodata, ov_SC06_032_jr_801902EC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6ff0, data, tail20] + - [0xa6ff0, data, tail19] - [0xa7020, .rodata, ov_SC06_032_jr_801919A0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa7050, data, tail21] + - [0xa7050, data, tail20] - [0xA9014, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA9017] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/config/splat.ov_SC06_033.yaml b/config/splat.ov_SC06_033.yaml index 0ea008226..ac317f093 100644 --- a/config/splat.ov_SC06_033.yaml +++ b/config/splat.ov_SC06_033.yaml @@ -169,13 +169,12 @@ segments: - [0xa6ef0, .rodata, ov_SC06_033_jr_8017C24C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6f10, data, tail18] - [0xa6f24, .rodata, ov_SC06_033_jr_801836FC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6f38, data, tail19] - [0xa7004, .rodata, ov_SC06_033_jr_80184CF8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa701c, data, tail20] + - [0xa701c, data, tail19] - [0xa7084, .rodata, ov_SC06_033_jr_8018C2D8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa70ac, data, tail21] + - [0xa70ac, data, tail20] - [0xa70dc, .rodata, ov_SC06_033_jr_8018D98C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa710c, data, tail22] + - [0xa710c, data, tail21] - [0xA8E94, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word) - [0xA8E97] # EOF marker = the 0.4.dec byte length # @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes diff --git a/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c b/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c index c77e9a1fe..116ccce82 100644 --- a/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c +++ b/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c @@ -4204,4 +4204,174 @@ extern void func_801811A8(void); INCLUDE_ASM("asm/ov_SC06_020/nonmatchings/ov_SC06_020_jr_8017C24C", func_8017FF48); -INCLUDE_ASM("asm/ov_SC06_020/nonmatchings/ov_SC06_020_jr_8017C24C", func_801800C8); + +/* func_801800C8 (ov_SC06_018_jr_8017C24C) — MATCH 198/198, relocation-masked. + * @class: regalloc-copy + schedule + * @stuck: none. Three load-bearing idioms: + * 1. ONE shared scratch `t` for all three `sll 16` compares. Three separate temps let + * local-alloc TIE the short temp to `iVar1` (no `addu $s1,$v0,$zero` at all, 197 ins); + * the shared `t` conflicts with `iVar1` so the copy survives. + * 2. `t = t << 16; if (t <= 0)` instead of `if ((s16)t <= 0)` at the FIRST site only. + * With the natural cast the shift lands in a fresh pseudo, so local-alloc's + * `optimize_reg_copy_1` (local-alloc.c:700, called at :1007 — MIPS never defines + * SMALL_REGISTER_CLASSES so pins cannot block it) finds `t` dying there and rewrites the + * use to the copy's destination -> `sll $v0,$s1,16`. Shifting IN PLACE makes the insn + * SET `t`, which trips the `reg_set_p (src, p)` break in the forward scan (and flow emits + * no REG_DEAD when a reg is set in the insn that last uses it, cookbook §45 Lever B) + * -> the scan aborts, the use stays on `$v0`: `sll $v0,$v0,16`. Cookbook §25 triage tell. + * Sites 2 and 3 (0xFE / 0x76) have no copy insn, so `(s16)t <= 0` is correct there. + * 3. case 8 assigns `ptr` AFTER the func_8012A828 call. Assigning it first gives the + * `la $s1,D_8019E9FC` a low enough LUID to win the `lhu 0x70` load-delay slot, which + * eats the target's `nop` (-1 ins). $s1 is callee-saved, so sched1 still hoists the + * `la` back above the call — just not into the delay slot. + * Also: `D_8019E994 + 8` (not a separate D_801B516C symbol) is what produces the CSE'd + * `addiu $a1,$s2,0x8` off the $s2 base; two symbols would emit a second lui/addiu pair. + * The `| 0x40000000 | 0x20000000` must stay as TWO ors — gcc-2.7.2 fold has no associate + * step for BIT_IOR_EXPR, and a folded `| 0x60000000` emits only one lui/or. + */ + +extern u8 D_8019E994[]; +extern u8 D_8019E8B4[]; +extern u8 D_801A4EAC; +extern u8 D_8019EA1C[]; +extern u8 D_8019E9FC[]; +extern u8 D_8019EA0C[]; +extern u8 D_8019E9EC[]; +extern u8 D_801B6598[]; +extern void *D_8019EB7C[]; + +extern void func_8012E9C0(s32 a0); +extern void func_8012B23C(s32 a0); +extern void func_8012F214(s32, s32, s32); +extern s32 func_801833F4(void *a0, s32 a1, s32 a2); +extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6); +extern void func_801834F0(s32 a0, void *a1, void *a2, s32 a3); +extern void func_8018348C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5); +extern void func_8001C924(s32 a0, void *a1); +extern void func_8012B14C(s32 a0, s32 a1); /* TU-canonical: matches the decl at ov_SC06_018_jr_8017C24C.c:7883 */ +extern void func_8002A520(s32 a0); +extern void func_8002A790(s32 a0); +extern void func_80131E00(s32 a0, s32 a1); +extern void func_8012B2CC(s32 a0); +extern void func_80183FD0(s32 a0, s32 a1); +extern void func_8012A828(s32 a0, void *a1); +extern void func_80181654(s32 a0, s32 a1); + +void func_801800C8(s32 p) { + s32 buf20[2]; + s32 iVar1; + s32 iVar2; + s32 t; + void *ptr; + + func_8012E9C0(p); + *(s32 *)(p + 0x1C) = 0; + *(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE; + func_8012B23C(p); + + t = (*(s16 *)(p + 0x60) * *(s16 *)(*(s32 *)(p + 0x78) + 0x30)) >> 12; + iVar1 = t; + t = t << 16; + if (t <= 0) { + iVar1 = 1; + } + + if (*(u32 *)(p + 0xE0) & 1) { + ((void (*)(s32, void *, void *))func_8012F214)(p, D_8019E994, buf20); + if (func_801833F4(buf20, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x400) != 0) { + func_80146A6C(6, (void *)p, *(s16 *)(p + 0x7C), *(s16 *)(p + 0x7E), + *(s16 *)(p + 0x80), 0, 0); + t = *(u16 *)(p + 0xFE) - iVar1; + *(s16 *)(p + 0xFE) = t; + if ((s16)t <= 0) { + func_801834F0(p, D_8019E994 + 8, buf20, 0xC); + func_8018348C(p, buf20, 0x27F, 0, 0, 0); + *(s32 *)(p + 0x58) = (s32)D_8019E8B4 | 0x40000000 | 0x20000000; + *(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) & 0xFFFFFFFE; + func_8001C924(*(s32 *)(p + 0x20), &D_801A4EAC); + } + func_8012B14C(p, (s32)D_8019EA1C); + *(s16 *)(p + 0x34) = 3; + return; + } + } + + if (*(u16 *)(p + 0x5E) != 0x1D) { + if (*(u8 *)(p + 0xC8) != 0) { + func_8002A520(p); + } + if (*(u8 *)(p + 0xC9) != 0) { + func_8002A790(p); + } + } + + t = *(u16 *)(p + 0x76) - iVar1; + *(s16 *)(p + 0x76) = t; + if ((s16)t <= 0) { + func_80131E00(p, 0xC); + return; + } + + *(s16 *)(p + 0x98) = 0; + *(u16 *)(*(s32 *)(p + 0x20) + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF; + iVar2 = *(s32 *)(p + 0x20); + *(s16 *)(iVar2 + 0x14) = 0; + *(s16 *)(iVar2 + 0x10) = 0; + func_8012B2CC(p); + func_80183FD0(p, 0x9B7); + + switch (*(u16 *)(p + 0x5E)) { + case 1: + case 2: + case 3: + case 4: + case 6: + case 7: + case 0xB: + case 0xC: + case 0x10: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1A: + case 0x23: + case 0x24: + case 0x25: + case 0x28: + case 0x2B: + case 0x2C: + case 0x2D: + case 0x2E: + case 0x2F: + case 0x30: + case 0x31: + case 0x32: + *(s16 *)(p + 0x34) = 4; + func_8012A828(p, D_8019EB7C[*(u16 *)(p + 0x70) & 0xF]); + return; + case 8: + func_8012A828(p, D_8019EB7C[*(u16 *)(p + 0x70) & 0xF]); + ptr = D_8019E9FC; + break; + case 5: + case 0x1D: + case 0x20: + case 0x26: + case 0x2A: + ptr = D_8019EA0C; + func_8012A828(p, D_801B6598); + *(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) | 8; + *(u16 *)(p + 0xAE) = *(u16 *)(p + 0xAE) | 1; + func_80181654(p, -0x8000); + break; + default: + ptr = D_8019E9EC; + break; + } + func_8012B14C(p, (s32)ptr); + *(s16 *)(p + 0x34) = 0; +} diff --git a/src/ov_SC06_022/ov_SC06_022_jr_80182D08.c b/src/ov_SC06_022/ov_SC06_022_jr_80182D08.c index 621266f0e..fb78503fe 100644 --- a/src/ov_SC06_022/ov_SC06_022_jr_80182D08.c +++ b/src/ov_SC06_022/ov_SC06_022_jr_80182D08.c @@ -3259,4 +3259,174 @@ extern void func_801850CC(void); INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_80182D08", func_80183E6C); -INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_80182D08", func_80183FEC); + +/* func_80183FEC (ov_SC06_018_jr_8017C24C) — MATCH 198/198, relocation-masked. + * @class: regalloc-copy + schedule + * @stuck: none. Three load-bearing idioms: + * 1. ONE shared scratch `t` for all three `sll 16` compares. Three separate temps let + * local-alloc TIE the short temp to `iVar1` (no `addu $s1,$v0,$zero` at all, 197 ins); + * the shared `t` conflicts with `iVar1` so the copy survives. + * 2. `t = t << 16; if (t <= 0)` instead of `if ((s16)t <= 0)` at the FIRST site only. + * With the natural cast the shift lands in a fresh pseudo, so local-alloc's + * `optimize_reg_copy_1` (local-alloc.c:700, called at :1007 — MIPS never defines + * SMALL_REGISTER_CLASSES so pins cannot block it) finds `t` dying there and rewrites the + * use to the copy's destination -> `sll $v0,$s1,16`. Shifting IN PLACE makes the insn + * SET `t`, which trips the `reg_set_p (src, p)` break in the forward scan (and flow emits + * no REG_DEAD when a reg is set in the insn that last uses it, cookbook §45 Lever B) + * -> the scan aborts, the use stays on `$v0`: `sll $v0,$v0,16`. Cookbook §25 triage tell. + * Sites 2 and 3 (0xFE / 0x76) have no copy insn, so `(s16)t <= 0` is correct there. + * 3. case 8 assigns `ptr` AFTER the func_8012A828 call. Assigning it first gives the + * `la $s1,D_801BD124` a low enough LUID to win the `lhu 0x70` load-delay slot, which + * eats the target's `nop` (-1 ins). $s1 is callee-saved, so sched1 still hoists the + * `la` back above the call — just not into the delay slot. + * Also: `D_801BD0BC + 8` (not a separate D_801B516C symbol) is what produces the CSE'd + * `addiu $a1,$s2,0x8` off the $s2 base; two symbols would emit a second lui/addiu pair. + * The `| 0x40000000 | 0x20000000` must stay as TWO ors — gcc-2.7.2 fold has no associate + * step for BIT_IOR_EXPR, and a folded `| 0x60000000` emits only one lui/or. + */ + +extern u8 D_801BD0BC[]; +extern u8 D_801BCFDC[]; +extern u8 D_801C35D4; +extern u8 D_801BD144[]; +extern u8 D_801BD124[]; +extern u8 D_801BD134[]; +extern u8 D_801BD114[]; +extern u8 D_801D4CC0[]; +extern void *D_801BD2A4[]; + +extern void func_8012E9C0(s32 a0); +extern void func_8012B23C(s32 a0); +extern void func_8012F214(s32, s32, s32); +extern s32 func_80187318(void *a0, s32 a1, s32 a2); +extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6); +extern void func_80187414(s32 a0, void *a1, void *a2, s32 a3); +extern void func_801873B0(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5); +extern void func_8001C924(s32 a0, void *a1); +extern void func_8012B14C(s32 a0, s32 a1); /* TU-canonical: matches the decl at ov_SC06_018_jr_8017C24C.c:7883 */ +extern void func_8002A520(s32 a0); +extern void func_8002A790(s32 a0); +extern void func_80131E00(s32 a0, s32 a1); +extern void func_8012B2CC(s32 a0); +extern void func_80187EF4(s32 a0, s32 a1); +extern void func_8012A828(s32 a0, void *a1); +extern void func_80185578(s32 a0, s32 a1); + +void func_80183FEC(s32 p) { + s32 buf20[2]; + s32 iVar1; + s32 iVar2; + s32 t; + void *ptr; + + func_8012E9C0(p); + *(s32 *)(p + 0x1C) = 0; + *(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE; + func_8012B23C(p); + + t = (*(s16 *)(p + 0x60) * *(s16 *)(*(s32 *)(p + 0x78) + 0x30)) >> 12; + iVar1 = t; + t = t << 16; + if (t <= 0) { + iVar1 = 1; + } + + if (*(u32 *)(p + 0xE0) & 1) { + ((void (*)(s32, void *, void *))func_8012F214)(p, D_801BD0BC, buf20); + if (func_80187318(buf20, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x400) != 0) { + func_80146A6C(6, (void *)p, *(s16 *)(p + 0x7C), *(s16 *)(p + 0x7E), + *(s16 *)(p + 0x80), 0, 0); + t = *(u16 *)(p + 0xFE) - iVar1; + *(s16 *)(p + 0xFE) = t; + if ((s16)t <= 0) { + func_80187414(p, D_801BD0BC + 8, buf20, 0xC); + func_801873B0(p, buf20, 0x27F, 0, 0, 0); + *(s32 *)(p + 0x58) = (s32)D_801BCFDC | 0x40000000 | 0x20000000; + *(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) & 0xFFFFFFFE; + func_8001C924(*(s32 *)(p + 0x20), &D_801C35D4); + } + func_8012B14C(p, (s32)D_801BD144); + *(s16 *)(p + 0x34) = 3; + return; + } + } + + if (*(u16 *)(p + 0x5E) != 0x1D) { + if (*(u8 *)(p + 0xC8) != 0) { + func_8002A520(p); + } + if (*(u8 *)(p + 0xC9) != 0) { + func_8002A790(p); + } + } + + t = *(u16 *)(p + 0x76) - iVar1; + *(s16 *)(p + 0x76) = t; + if ((s16)t <= 0) { + func_80131E00(p, 0xC); + return; + } + + *(s16 *)(p + 0x98) = 0; + *(u16 *)(*(s32 *)(p + 0x20) + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF; + iVar2 = *(s32 *)(p + 0x20); + *(s16 *)(iVar2 + 0x14) = 0; + *(s16 *)(iVar2 + 0x10) = 0; + func_8012B2CC(p); + func_80187EF4(p, 0x9B7); + + switch (*(u16 *)(p + 0x5E)) { + case 1: + case 2: + case 3: + case 4: + case 6: + case 7: + case 0xB: + case 0xC: + case 0x10: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1A: + case 0x23: + case 0x24: + case 0x25: + case 0x28: + case 0x2B: + case 0x2C: + case 0x2D: + case 0x2E: + case 0x2F: + case 0x30: + case 0x31: + case 0x32: + *(s16 *)(p + 0x34) = 4; + func_8012A828(p, D_801BD2A4[*(u16 *)(p + 0x70) & 0xF]); + return; + case 8: + func_8012A828(p, D_801BD2A4[*(u16 *)(p + 0x70) & 0xF]); + ptr = D_801BD124; + break; + case 5: + case 0x1D: + case 0x20: + case 0x26: + case 0x2A: + ptr = D_801BD134; + func_8012A828(p, D_801D4CC0); + *(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) | 8; + *(u16 *)(p + 0xAE) = *(u16 *)(p + 0xAE) | 1; + func_80185578(p, -0x8000); + break; + default: + ptr = D_801BD114; + break; + } + func_8012B14C(p, (s32)ptr); + *(s16 *)(p + 0x34) = 0; +} diff --git a/src/ov_SC06_024/ov_SC06_024_jr_801851E0.c b/src/ov_SC06_024/ov_SC06_024_jr_801851E0.c index 000137683..3ae97af58 100644 --- a/src/ov_SC06_024/ov_SC06_024_jr_801851E0.c +++ b/src/ov_SC06_024/ov_SC06_024_jr_801851E0.c @@ -3203,4 +3203,174 @@ extern void func_801875A4(void); INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_801851E0", func_80186344); -INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_801851E0", func_801864C4); + +/* func_801864C4 (ov_SC06_018_jr_8017C24C) — MATCH 198/198, relocation-masked. + * @class: regalloc-copy + schedule + * @stuck: none. Three load-bearing idioms: + * 1. ONE shared scratch `t` for all three `sll 16` compares. Three separate temps let + * local-alloc TIE the short temp to `iVar1` (no `addu $s1,$v0,$zero` at all, 197 ins); + * the shared `t` conflicts with `iVar1` so the copy survives. + * 2. `t = t << 16; if (t <= 0)` instead of `if ((s16)t <= 0)` at the FIRST site only. + * With the natural cast the shift lands in a fresh pseudo, so local-alloc's + * `optimize_reg_copy_1` (local-alloc.c:700, called at :1007 — MIPS never defines + * SMALL_REGISTER_CLASSES so pins cannot block it) finds `t` dying there and rewrites the + * use to the copy's destination -> `sll $v0,$s1,16`. Shifting IN PLACE makes the insn + * SET `t`, which trips the `reg_set_p (src, p)` break in the forward scan (and flow emits + * no REG_DEAD when a reg is set in the insn that last uses it, cookbook §45 Lever B) + * -> the scan aborts, the use stays on `$v0`: `sll $v0,$v0,16`. Cookbook §25 triage tell. + * Sites 2 and 3 (0xFE / 0x76) have no copy insn, so `(s16)t <= 0` is correct there. + * 3. case 8 assigns `ptr` AFTER the func_8012A828 call. Assigning it first gives the + * `la $s1,D_801BC268` a low enough LUID to win the `lhu 0x70` load-delay slot, which + * eats the target's `nop` (-1 ins). $s1 is callee-saved, so sched1 still hoists the + * `la` back above the call — just not into the delay slot. + * Also: `D_801BC200 + 8` (not a separate D_801B516C symbol) is what produces the CSE'd + * `addiu $a1,$s2,0x8` off the $s2 base; two symbols would emit a second lui/addiu pair. + * The `| 0x40000000 | 0x20000000` must stay as TWO ors — gcc-2.7.2 fold has no associate + * step for BIT_IOR_EXPR, and a folded `| 0x60000000` emits only one lui/or. + */ + +extern u8 D_801BC200[]; +extern u8 D_801BC120[]; +extern u8 D_801C2718; +extern u8 D_801BC288[]; +extern u8 D_801BC268[]; +extern u8 D_801BC278[]; +extern u8 D_801BC258[]; +extern u8 D_801D3E04[]; +extern void *D_801BC3E8[]; + +extern void func_8012E9C0(s32 a0); +extern void func_8012B23C(s32 a0); +extern void func_8012F214(s32, s32, s32); +extern s32 func_801897F0(void *a0, s32 a1, s32 a2); +extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6); +extern void func_801898EC(s32 a0, void *a1, void *a2, s32 a3); +extern void func_80189888(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5); +extern void func_8001C924(s32 a0, void *a1); +extern void func_8012B14C(s32 a0, s32 a1); /* TU-canonical: matches the decl at ov_SC06_018_jr_8017C24C.c:7883 */ +extern void func_8002A520(s32 a0); +extern void func_8002A790(s32 a0); +extern void func_80131E00(s32 a0, s32 a1); +extern void func_8012B2CC(s32 a0); +extern void func_8018A3CC(s32 a0, s32 a1); +extern void func_8012A828(s32 a0, void *a1); +extern void func_80187A50(s32 a0, s32 a1); + +void func_801864C4(s32 p) { + s32 buf20[2]; + s32 iVar1; + s32 iVar2; + s32 t; + void *ptr; + + func_8012E9C0(p); + *(s32 *)(p + 0x1C) = 0; + *(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE; + func_8012B23C(p); + + t = (*(s16 *)(p + 0x60) * *(s16 *)(*(s32 *)(p + 0x78) + 0x30)) >> 12; + iVar1 = t; + t = t << 16; + if (t <= 0) { + iVar1 = 1; + } + + if (*(u32 *)(p + 0xE0) & 1) { + ((void (*)(s32, void *, void *))func_8012F214)(p, D_801BC200, buf20); + if (func_801897F0(buf20, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x400) != 0) { + func_80146A6C(6, (void *)p, *(s16 *)(p + 0x7C), *(s16 *)(p + 0x7E), + *(s16 *)(p + 0x80), 0, 0); + t = *(u16 *)(p + 0xFE) - iVar1; + *(s16 *)(p + 0xFE) = t; + if ((s16)t <= 0) { + func_801898EC(p, D_801BC200 + 8, buf20, 0xC); + func_80189888(p, buf20, 0x27F, 0, 0, 0); + *(s32 *)(p + 0x58) = (s32)D_801BC120 | 0x40000000 | 0x20000000; + *(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) & 0xFFFFFFFE; + func_8001C924(*(s32 *)(p + 0x20), &D_801C2718); + } + func_8012B14C(p, (s32)D_801BC288); + *(s16 *)(p + 0x34) = 3; + return; + } + } + + if (*(u16 *)(p + 0x5E) != 0x1D) { + if (*(u8 *)(p + 0xC8) != 0) { + func_8002A520(p); + } + if (*(u8 *)(p + 0xC9) != 0) { + func_8002A790(p); + } + } + + t = *(u16 *)(p + 0x76) - iVar1; + *(s16 *)(p + 0x76) = t; + if ((s16)t <= 0) { + func_80131E00(p, 0xC); + return; + } + + *(s16 *)(p + 0x98) = 0; + *(u16 *)(*(s32 *)(p + 0x20) + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF; + iVar2 = *(s32 *)(p + 0x20); + *(s16 *)(iVar2 + 0x14) = 0; + *(s16 *)(iVar2 + 0x10) = 0; + func_8012B2CC(p); + func_8018A3CC(p, 0x9B7); + + switch (*(u16 *)(p + 0x5E)) { + case 1: + case 2: + case 3: + case 4: + case 6: + case 7: + case 0xB: + case 0xC: + case 0x10: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1A: + case 0x23: + case 0x24: + case 0x25: + case 0x28: + case 0x2B: + case 0x2C: + case 0x2D: + case 0x2E: + case 0x2F: + case 0x30: + case 0x31: + case 0x32: + *(s16 *)(p + 0x34) = 4; + func_8012A828(p, D_801BC3E8[*(u16 *)(p + 0x70) & 0xF]); + return; + case 8: + func_8012A828(p, D_801BC3E8[*(u16 *)(p + 0x70) & 0xF]); + ptr = D_801BC268; + break; + case 5: + case 0x1D: + case 0x20: + case 0x26: + case 0x2A: + ptr = D_801BC278; + func_8012A828(p, D_801D3E04); + *(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) | 8; + *(u16 *)(p + 0xAE) = *(u16 *)(p + 0xAE) | 1; + func_80187A50(p, -0x8000); + break; + default: + ptr = D_801BC258; + break; + } + func_8012B14C(p, (s32)ptr); + *(s16 *)(p + 0x34) = 0; +} diff --git a/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c b/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c index 78543443b..ec867263a 100644 --- a/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c +++ b/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c @@ -4629,4 +4629,174 @@ extern void func_80181DDC(void); INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_80180B7C); -INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_80180CFC); + +/* func_80180CFC (ov_SC06_018_jr_8017C24C) — MATCH 198/198, relocation-masked. + * @class: regalloc-copy + schedule + * @stuck: none. Three load-bearing idioms: + * 1. ONE shared scratch `t` for all three `sll 16` compares. Three separate temps let + * local-alloc TIE the short temp to `iVar1` (no `addu $s1,$v0,$zero` at all, 197 ins); + * the shared `t` conflicts with `iVar1` so the copy survives. + * 2. `t = t << 16; if (t <= 0)` instead of `if ((s16)t <= 0)` at the FIRST site only. + * With the natural cast the shift lands in a fresh pseudo, so local-alloc's + * `optimize_reg_copy_1` (local-alloc.c:700, called at :1007 — MIPS never defines + * SMALL_REGISTER_CLASSES so pins cannot block it) finds `t` dying there and rewrites the + * use to the copy's destination -> `sll $v0,$s1,16`. Shifting IN PLACE makes the insn + * SET `t`, which trips the `reg_set_p (src, p)` break in the forward scan (and flow emits + * no REG_DEAD when a reg is set in the insn that last uses it, cookbook §45 Lever B) + * -> the scan aborts, the use stays on `$v0`: `sll $v0,$v0,16`. Cookbook §25 triage tell. + * Sites 2 and 3 (0xFE / 0x76) have no copy insn, so `(s16)t <= 0` is correct there. + * 3. case 8 assigns `ptr` AFTER the func_8012A828 call. Assigning it first gives the + * `la $s1,D_801A665C` a low enough LUID to win the `lhu 0x70` load-delay slot, which + * eats the target's `nop` (-1 ins). $s1 is callee-saved, so sched1 still hoists the + * `la` back above the call — just not into the delay slot. + * Also: `D_801A65F4 + 8` (not a separate D_801B516C symbol) is what produces the CSE'd + * `addiu $a1,$s2,0x8` off the $s2 base; two symbols would emit a second lui/addiu pair. + * The `| 0x40000000 | 0x20000000` must stay as TWO ors — gcc-2.7.2 fold has no associate + * step for BIT_IOR_EXPR, and a folded `| 0x60000000` emits only one lui/or. + */ + +extern u8 D_801A65F4[]; +extern u8 D_801A6514[]; +extern u8 D_801ACB0C; +extern u8 D_801A667C[]; +extern u8 D_801A665C[]; +extern u8 D_801A666C[]; +extern u8 D_801A664C[]; +extern u8 D_801BE1F8[]; +extern void *D_801A67DC[]; + +extern void func_8012E9C0(s32 a0); +extern void func_8012B23C(s32 a0); +extern void func_8012F214(s32, s32, s32); +extern s32 func_80184028(void *a0, s32 a1, s32 a2); +extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6); +extern void func_80184124(s32 a0, void *a1, void *a2, s32 a3); +extern void func_801840C0(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5); +extern void func_8001C924(s32 a0, void *a1); +extern void func_8012B14C(s32 a0, s32 a1); /* TU-canonical: matches the decl at ov_SC06_018_jr_8017C24C.c:7883 */ +extern void func_8002A520(s32 a0); +extern void func_8002A790(s32 a0); +extern void func_80131E00(s32 a0, s32 a1); +extern void func_8012B2CC(s32 a0); +extern void func_80184C04(s32 a0, s32 a1); +extern void func_8012A828(s32 a0, void *a1); +extern void func_80182288(s32 a0, s32 a1); + +void func_80180CFC(s32 p) { + s32 buf20[2]; + s32 iVar1; + s32 iVar2; + s32 t; + void *ptr; + + func_8012E9C0(p); + *(s32 *)(p + 0x1C) = 0; + *(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE; + func_8012B23C(p); + + t = (*(s16 *)(p + 0x60) * *(s16 *)(*(s32 *)(p + 0x78) + 0x30)) >> 12; + iVar1 = t; + t = t << 16; + if (t <= 0) { + iVar1 = 1; + } + + if (*(u32 *)(p + 0xE0) & 1) { + ((void (*)(s32, void *, void *))func_8012F214)(p, D_801A65F4, buf20); + if (func_80184028(buf20, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x400) != 0) { + func_80146A6C(6, (void *)p, *(s16 *)(p + 0x7C), *(s16 *)(p + 0x7E), + *(s16 *)(p + 0x80), 0, 0); + t = *(u16 *)(p + 0xFE) - iVar1; + *(s16 *)(p + 0xFE) = t; + if ((s16)t <= 0) { + func_80184124(p, D_801A65F4 + 8, buf20, 0xC); + func_801840C0(p, buf20, 0x27F, 0, 0, 0); + *(s32 *)(p + 0x58) = (s32)D_801A6514 | 0x40000000 | 0x20000000; + *(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) & 0xFFFFFFFE; + func_8001C924(*(s32 *)(p + 0x20), &D_801ACB0C); + } + func_8012B14C(p, (s32)D_801A667C); + *(s16 *)(p + 0x34) = 3; + return; + } + } + + if (*(u16 *)(p + 0x5E) != 0x1D) { + if (*(u8 *)(p + 0xC8) != 0) { + func_8002A520(p); + } + if (*(u8 *)(p + 0xC9) != 0) { + func_8002A790(p); + } + } + + t = *(u16 *)(p + 0x76) - iVar1; + *(s16 *)(p + 0x76) = t; + if ((s16)t <= 0) { + func_80131E00(p, 0xC); + return; + } + + *(s16 *)(p + 0x98) = 0; + *(u16 *)(*(s32 *)(p + 0x20) + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF; + iVar2 = *(s32 *)(p + 0x20); + *(s16 *)(iVar2 + 0x14) = 0; + *(s16 *)(iVar2 + 0x10) = 0; + func_8012B2CC(p); + func_80184C04(p, 0x9B7); + + switch (*(u16 *)(p + 0x5E)) { + case 1: + case 2: + case 3: + case 4: + case 6: + case 7: + case 0xB: + case 0xC: + case 0x10: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1A: + case 0x23: + case 0x24: + case 0x25: + case 0x28: + case 0x2B: + case 0x2C: + case 0x2D: + case 0x2E: + case 0x2F: + case 0x30: + case 0x31: + case 0x32: + *(s16 *)(p + 0x34) = 4; + func_8012A828(p, D_801A67DC[*(u16 *)(p + 0x70) & 0xF]); + return; + case 8: + func_8012A828(p, D_801A67DC[*(u16 *)(p + 0x70) & 0xF]); + ptr = D_801A665C; + break; + case 5: + case 0x1D: + case 0x20: + case 0x26: + case 0x2A: + ptr = D_801A666C; + func_8012A828(p, D_801BE1F8); + *(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) | 8; + *(u16 *)(p + 0xAE) = *(u16 *)(p + 0xAE) | 1; + func_80182288(p, -0x8000); + break; + default: + ptr = D_801A664C; + break; + } + func_8012B14C(p, (s32)ptr); + *(s16 *)(p + 0x34) = 0; +} diff --git a/src/ov_SC06_033/ov_SC06_033_jr_801836FC.c b/src/ov_SC06_033/ov_SC06_033_jr_801836FC.c index 471a649e9..d985d3650 100644 --- a/src/ov_SC06_033/ov_SC06_033_jr_801836FC.c +++ b/src/ov_SC06_033/ov_SC06_033_jr_801836FC.c @@ -3327,4 +3327,174 @@ extern void func_80185AC0(void); INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_801836FC", func_80184860); -INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_801836FC", func_801849E0); + +/* func_801849E0 (ov_SC06_018_jr_8017C24C) — MATCH 198/198, relocation-masked. + * @class: regalloc-copy + schedule + * @stuck: none. Three load-bearing idioms: + * 1. ONE shared scratch `t` for all three `sll 16` compares. Three separate temps let + * local-alloc TIE the short temp to `iVar1` (no `addu $s1,$v0,$zero` at all, 197 ins); + * the shared `t` conflicts with `iVar1` so the copy survives. + * 2. `t = t << 16; if (t <= 0)` instead of `if ((s16)t <= 0)` at the FIRST site only. + * With the natural cast the shift lands in a fresh pseudo, so local-alloc's + * `optimize_reg_copy_1` (local-alloc.c:700, called at :1007 — MIPS never defines + * SMALL_REGISTER_CLASSES so pins cannot block it) finds `t` dying there and rewrites the + * use to the copy's destination -> `sll $v0,$s1,16`. Shifting IN PLACE makes the insn + * SET `t`, which trips the `reg_set_p (src, p)` break in the forward scan (and flow emits + * no REG_DEAD when a reg is set in the insn that last uses it, cookbook §45 Lever B) + * -> the scan aborts, the use stays on `$v0`: `sll $v0,$v0,16`. Cookbook §25 triage tell. + * Sites 2 and 3 (0xFE / 0x76) have no copy insn, so `(s16)t <= 0` is correct there. + * 3. case 8 assigns `ptr` AFTER the func_8012A828 call. Assigning it first gives the + * `la $s1,D_801AF9F0` a low enough LUID to win the `lhu 0x70` load-delay slot, which + * eats the target's `nop` (-1 ins). $s1 is callee-saved, so sched1 still hoists the + * `la` back above the call — just not into the delay slot. + * Also: `D_801AF988 + 8` (not a separate D_801B516C symbol) is what produces the CSE'd + * `addiu $a1,$s2,0x8` off the $s2 base; two symbols would emit a second lui/addiu pair. + * The `| 0x40000000 | 0x20000000` must stay as TWO ors — gcc-2.7.2 fold has no associate + * step for BIT_IOR_EXPR, and a folded `| 0x60000000` emits only one lui/or. + */ + +extern u8 D_801AF988[]; +extern u8 D_801AF8A8[]; +extern u8 D_801B5EA0; +extern u8 D_801AFA10[]; +extern u8 D_801AF9F0[]; +extern u8 D_801AFA00[]; +extern u8 D_801AF9E0[]; +extern u8 D_801C758C[]; +extern void *D_801AFB70[]; + +extern void func_8012E9C0(s32 a0); +extern void func_8012B23C(s32 a0); +extern void func_8012F214(s32, s32, s32); +extern s32 func_80187D0C(void *a0, s32 a1, s32 a2); +extern s32 func_80146A6C(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5, s32 a6); +extern void func_80187E08(s32 a0, void *a1, void *a2, s32 a3); +extern void func_80187DA4(s32 a0, void *a1, s32 a2, s32 a3, s32 a4, s32 a5); +extern void func_8001C924(s32 a0, void *a1); +extern void func_8012B14C(s32 a0, s32 a1); /* TU-canonical: matches the decl at ov_SC06_018_jr_8017C24C.c:7883 */ +extern void func_8002A520(s32 a0); +extern void func_8002A790(s32 a0); +extern void func_80131E00(s32 a0, s32 a1); +extern void func_8012B2CC(s32 a0); +extern void func_801888E8(s32 a0, s32 a1); +extern void func_8012A828(s32 a0, void *a1); +extern void func_80185F6C(s32 a0, s32 a1); + +void func_801849E0(s32 p) { + s32 buf20[2]; + s32 iVar1; + s32 iVar2; + s32 t; + void *ptr; + + func_8012E9C0(p); + *(s32 *)(p + 0x1C) = 0; + *(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE; + func_8012B23C(p); + + t = (*(s16 *)(p + 0x60) * *(s16 *)(*(s32 *)(p + 0x78) + 0x30)) >> 12; + iVar1 = t; + t = t << 16; + if (t <= 0) { + iVar1 = 1; + } + + if (*(u32 *)(p + 0xE0) & 1) { + ((void (*)(s32, void *, void *))func_8012F214)(p, D_801AF988, buf20); + if (func_80187D0C(buf20, *(s16 *)(*(s32 *)(p + 0x20) + 0x12), 0x400) != 0) { + func_80146A6C(6, (void *)p, *(s16 *)(p + 0x7C), *(s16 *)(p + 0x7E), + *(s16 *)(p + 0x80), 0, 0); + t = *(u16 *)(p + 0xFE) - iVar1; + *(s16 *)(p + 0xFE) = t; + if ((s16)t <= 0) { + func_80187E08(p, D_801AF988 + 8, buf20, 0xC); + func_80187DA4(p, buf20, 0x27F, 0, 0, 0); + *(s32 *)(p + 0x58) = (s32)D_801AF8A8 | 0x40000000 | 0x20000000; + *(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) & 0xFFFFFFFE; + func_8001C924(*(s32 *)(p + 0x20), &D_801B5EA0); + } + func_8012B14C(p, (s32)D_801AFA10); + *(s16 *)(p + 0x34) = 3; + return; + } + } + + if (*(u16 *)(p + 0x5E) != 0x1D) { + if (*(u8 *)(p + 0xC8) != 0) { + func_8002A520(p); + } + if (*(u8 *)(p + 0xC9) != 0) { + func_8002A790(p); + } + } + + t = *(u16 *)(p + 0x76) - iVar1; + *(s16 *)(p + 0x76) = t; + if ((s16)t <= 0) { + func_80131E00(p, 0xC); + return; + } + + *(s16 *)(p + 0x98) = 0; + *(u16 *)(*(s32 *)(p + 0x20) + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF; + iVar2 = *(s32 *)(p + 0x20); + *(s16 *)(iVar2 + 0x14) = 0; + *(s16 *)(iVar2 + 0x10) = 0; + func_8012B2CC(p); + func_801888E8(p, 0x9B7); + + switch (*(u16 *)(p + 0x5E)) { + case 1: + case 2: + case 3: + case 4: + case 6: + case 7: + case 0xB: + case 0xC: + case 0x10: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1A: + case 0x23: + case 0x24: + case 0x25: + case 0x28: + case 0x2B: + case 0x2C: + case 0x2D: + case 0x2E: + case 0x2F: + case 0x30: + case 0x31: + case 0x32: + *(s16 *)(p + 0x34) = 4; + func_8012A828(p, D_801AFB70[*(u16 *)(p + 0x70) & 0xF]); + return; + case 8: + func_8012A828(p, D_801AFB70[*(u16 *)(p + 0x70) & 0xF]); + ptr = D_801AF9F0; + break; + case 5: + case 0x1D: + case 0x20: + case 0x26: + case 0x2A: + ptr = D_801AFA00; + func_8012A828(p, D_801C758C); + *(u32 *)(p + 0xE0) = *(u32 *)(p + 0xE0) | 8; + *(u16 *)(p + 0xAE) = *(u16 *)(p + 0xAE) | 1; + func_80185F6C(p, -0x8000); + break; + default: + ptr = D_801AF9E0; + break; + } + func_8012B14C(p, (s32)ptr); + *(s16 *)(p + 0x34) = 0; +}