From d1a1d756e0218a95fa92d4aa5e4f6692f62d705b Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Thu, 23 Jul 2026 21:35:07 -0600 Subject: [PATCH] =?UTF-8?q?fix(phase-29):=20PsyQ=20MATRIX=20name=20hazard?= =?UTF-8?q?=20=E2=80=94=20the=20true=2032B=20layout=20now=20owns=20the=20c?= =?UTF-8?q?anonical=20name=20(R22=20140/140)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Oracle (G1, Ghidra types get, /LIBGTE.H, psyq400.gdt): MATRIX = 32 bytes (short m[3][3] @+0x00, long t[3] @+0x14, 2B pad after m); SVECTOR = 8B; VECTOR = 16B (long vx,vy,vz,pad). - HAZARD CONFIRMED: the fleet-wide name `MATRIX` held {s32 m[3][3]; s32 t[3]} = 48 BYTES, not a PsyQ type at all, while THREE other names (MATRIX_c1, MATRIX_c2, MATRIX2) held the true 32B layout. The canonical name carried an invention; any future reader assuming PsyQ semantics would be misled. - FIXED by pure consistent rename across 205 files: 48B invention -> MATRIX_L48 (KEPT — ~131 files are byte-correct against it, and "fixing" it to 32B would change sizeof/array stride hence codegen); the true 32B layout now owns MATRIX. R22 clean-fleet 140/140 BYTE-IDENTICAL. - VECTOR left UNCHANGED on purpose: ours is 12B vs PsyQ 16B (missing trailing pad). I first called it dead — wrong, it has 1 live use (engine_core.h gte_ldlv0((VECTOR*)sp)). Offsets already agree so a fix is likely byte-neutral, but it is a LAYOUT change and bundling it with a rename would make an R22 failure ambiguous. Own R22-gated commit, later. - engine_types.h gains an oracle-sourced GROUND-TRUTH block: real PsyQ layouts, which of our names are true vs invented, why MATRIX_L48 must not be "corrected", and the draft-time rule (address-suffix anything you invent — 7 of the 8 collisions this fleet accumulated were bare generic names). - SCOPE HELD: renamed + documented; did NOT force existing code onto real PsyQ definitions. --- phase-ends/CURRENT_PHASE.md | 22 +++++++++++++++++ src/ov_SC01_000/ov_SC01_000_jr_8017AE2C.c | 6 ++--- src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c | 4 +-- src/ov_SC01_001/ov_SC01_001_jr_8017AE2C.c | 6 ++--- src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c | 4 +-- src/ov_SC01_004/ov_SC01_004_jr_8017AE2C.c | 6 ++--- src/ov_SC01_005/ov_SC01_005_jr_8017AE2C.c | 6 ++--- src/ov_SC01_006/ov_SC01_006_jr_8017AE2C.c | 6 ++--- src/ov_SC01_008/ov_SC01_008_jr_8017AE2C.c | 6 ++--- src/ov_SC01_009/ov_SC01_009_jr_8017AE2C.c | 6 ++--- src/ov_SC01_074/ov_SC01_074_jr_8017AE2C.c | 6 ++--- src/ov_SC01_074/ov_SC01_074_jr_8017BE9C.c | 4 +-- src/ov_SC01_080/ov_SC01_080_jr_8017AE2C.c | 6 ++--- src/ov_SC01_084/ov_SC01_084_jr_8017AE2C.c | 6 ++--- src/ov_SC02_000/ov_SC02_000_jr_8017AE2C.c | 6 ++--- src/ov_SC02_003/ov_SC02_003_jr_8017AE2C.c | 6 ++--- src/ov_SC02_004/ov_SC02_004_jr_8017AE2C.c | 6 ++--- src/ov_SC02_005/ov_SC02_005_jr_8017AE2C.c | 6 ++--- src/ov_SC02_011/ov_SC02_011_jr_8017AE2C.c | 6 ++--- src/ov_SC02_015/ov_SC02_015_jr_8017AE2C.c | 6 ++--- src/ov_SC02_016/ov_SC02_016_jr_8017AE2C.c | 6 ++--- src/ov_SC02_016/ov_SC02_016_jr_8017DC70.c | 4 +-- src/ov_SC02_017/ov_SC02_017_jr_8017AE2C.c | 6 ++--- src/ov_SC02_021/ov_SC02_021_jr_8017AE2C.c | 6 ++--- src/ov_SC02_026/ov_SC02_026_jr_8017AE2C.c | 6 ++--- src/ov_SC02_026/ov_SC02_026_jr_8017C180.c | 4 +-- src/ov_SC02_027/ov_SC02_027_jr_8017AE2C.c | 6 ++--- src/ov_SC02_027/ov_SC02_027_jr_8017D898.c | 4 +-- src/ov_SC02_028/ov_SC02_028_jr_8017AE2C.c | 6 ++--- src/ov_SC02_028/ov_SC02_028_jr_8017D898.c | 4 +-- src/ov_SC02_031/ov_SC02_031_jr_8017AE2C.c | 6 ++--- src/ov_SC02_035/ov_SC02_035_jr_8017AE2C.c | 6 ++--- src/ov_SC02_035/ov_SC02_035_jr_8017BEBC.c | 4 +-- src/ov_SC02_039/ov_SC02_039_jr_8017AE2C.c | 6 ++--- src/ov_SC02_041/ov_SC02_041_jr_8017AE2C.c | 6 ++--- src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c | 4 +-- src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c | 6 ++--- src/ov_SC03_002/ov_SC03_002_jr_8017AE2C.c | 6 ++--- src/ov_SC03_003/ov_SC03_003_jr_8017AE2C.c | 6 ++--- src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c | 6 ++--- src/ov_SC03_007/ov_SC03_007_jr_8017AE2C.c | 6 ++--- src/ov_SC03_010/ov_SC03_010_jr_8017AE2C.c | 6 ++--- src/ov_SC03_011/ov_SC03_011_jr_8017AE2C.c | 6 ++--- src/ov_SC03_012/ov_SC03_012_jr_8017AE2C.c | 6 ++--- src/ov_SC03_013/ov_SC03_013_jr_8017AE2C.c | 6 ++--- src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.c | 6 ++--- src/ov_SC03_014/ov_SC03_014_jr_8017EB7C.c | 4 +-- src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.c | 6 ++--- src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.c | 4 +-- src/ov_SC03_023/ov_SC03_023_jr_8017AE2C.c | 6 ++--- src/ov_SC03_024/ov_SC03_024_jr_8017AE2C.c | 6 ++--- src/ov_SC03_024/ov_SC03_024_jr_8017DF84.c | 4 +-- src/ov_SC03_028/ov_SC03_028_jr_8017AE2C.c | 10 ++++---- src/ov_SC03_029/ov_SC03_029_jr_8017AE2C.c | 6 ++--- src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c | 6 ++--- src/ov_SC03_031/ov_SC03_031_jr_8017AE2C.c | 6 ++--- src/ov_SC03_089/ov_SC03_089_jr_8017AE2C.c | 6 ++--- src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c | 4 +-- src/ov_SC03_090/ov_SC03_090_jr_8017AE2C.c | 6 ++--- src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c | 4 +-- src/ov_SC03_091/ov_SC03_091_jr_8017AE2C.c | 6 ++--- src/ov_SC03_091/ov_SC03_091_jr_80182268.c | 4 +-- src/ov_SC03_092/ov_SC03_092_jr_8017AE2C.c | 6 ++--- src/ov_SC03_093/ov_SC03_093_jr_8017AE2C.c | 6 ++--- src/ov_SC03_093/ov_SC03_093_jr_8017D898.c | 4 +-- src/ov_SC03_094/ov_SC03_094_jr_8017AE2C.c | 6 ++--- src/ov_SC03_094/ov_SC03_094_jr_8017BEBC.c | 4 +-- src/ov_SC03_095/ov_SC03_095_jr_8017AE2C.c | 6 ++--- src/ov_SC03_095/ov_SC03_095_jr_8017BEBC.c | 4 +-- src/ov_SC03_096/ov_SC03_096_jr_8017AE2C.c | 6 ++--- src/ov_SC03_096/ov_SC03_096_jr_8017BEBC.c | 4 +-- src/ov_SC03_097/ov_SC03_097_jr_8017AE2C.c | 6 ++--- src/ov_SC03_097/ov_SC03_097_jr_8017D898.c | 4 +-- src/ov_SC03_098/ov_SC03_098_jr_8017AE2C.c | 6 ++--- src/ov_SC03_098/ov_SC03_098_jr_8017D898.c | 4 +-- src/ov_SC03_099/ov_SC03_099_jr_8017AE2C.c | 6 ++--- src/ov_SC03_099/ov_SC03_099_jr_8017BEBC.c | 4 +-- src/ov_SC03_100/ov_SC03_100_jr_8017AE2C.c | 6 ++--- src/ov_SC03_100/ov_SC03_100_jr_8017D898.c | 4 +-- src/ov_SC03_101/ov_SC03_101_jr_8017AE2C.c | 6 ++--- src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c | 4 +-- src/ov_SC03_102/ov_SC03_102_jr_8017AE2C.c | 6 ++--- src/ov_SC03_102/ov_SC03_102_jr_8017BEBC.c | 4 +-- src/ov_SC03_103/ov_SC03_103_jr_8017AE2C.c | 6 ++--- src/ov_SC03_103/ov_SC03_103_jr_8017C294.c | 4 +-- src/ov_SC03_104/ov_SC03_104_jr_8017AE2C.c | 6 ++--- src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c | 4 +-- src/ov_SC03_105/ov_SC03_105_jr_8017AE2C.c | 6 ++--- src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.c | 4 +-- src/ov_SC03_108/ov_SC03_108_jr_8017AE2C.c | 6 ++--- src/ov_SC03_109/ov_SC03_109_jr_8017AE2C.c | 6 ++--- src/ov_SC03_109/ov_SC03_109_jr_8017C180.c | 4 +-- src/ov_SC03_110/ov_SC03_110_jr_8017AE2C.c | 6 ++--- src/ov_SC03_110/ov_SC03_110_jr_8017D898.c | 4 +-- src/ov_SC03_111/ov_SC03_111_jr_8017AE2C.c | 6 ++--- src/ov_SC03_112/ov_SC03_112_jr_8017AE2C.c | 6 ++--- src/ov_SC03_113/ov_SC03_113_jr_8017AE2C.c | 6 ++--- src/ov_SC03_113/ov_SC03_113_jr_8017C294.c | 4 +-- src/ov_SC03_114/ov_SC03_114_jr_8017AE2C.c | 6 ++--- src/ov_SC03_115/ov_SC03_115_jr_8017AE2C.c | 6 ++--- src/ov_SC03_115/ov_SC03_115_jr_8017BEBC.c | 4 +-- src/ov_SC03_116/ov_SC03_116_jr_8017AE2C.c | 10 ++++---- src/ov_SC03_117/ov_SC03_117_jr_8017AE2C.c | 6 ++--- src/ov_SC03_117/ov_SC03_117_jr_8017BEBC.c | 4 +-- src/ov_SC03_118/ov_SC03_118_jr_8017AE2C.c | 6 ++--- src/ov_SC03_119/ov_SC03_119_jr_8017AE2C.c | 6 ++--- src/ov_SC03_121/ov_SC03_121_jr_8017AE2C.c | 6 ++--- src/ov_SC03_121/ov_SC03_121_jr_8017BEBC.c | 4 +-- src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c | 6 ++--- src/ov_SC03_125/ov_SC03_125_jr_8017AE2C.c | 6 ++--- src/ov_SC03_126/ov_SC03_126_jr_8017AE2C.c | 6 ++--- src/ov_SC04_000/ov_SC04_000_jr_8017AE2C.c | 6 ++--- src/ov_SC04_002/ov_SC04_002_jr_8017AE2C.c | 6 ++--- src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c | 4 +-- src/ov_SC04_003/ov_SC04_003_jr_8017AE2C.c | 6 ++--- src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c | 4 +-- src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c | 10 ++++---- src/ov_SC04_005/ov_SC04_005_jr_8017AE2C.c | 6 ++--- src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c | 4 +-- src/ov_SC04_006/ov_SC04_006_jr_8017AE2C.c | 6 ++--- src/ov_SC04_007/ov_SC04_007_jr_8017AE2C.c | 6 ++--- src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c | 4 +-- src/ov_SC04_008/ov_SC04_008_jr_8017AE2C.c | 10 ++++---- src/ov_SC04_009/ov_SC04_009_jr_8017AE2C.c | 6 ++--- src/ov_SC04_009/ov_SC04_009_jr_8017BEBC.c | 4 +-- src/ov_SC04_010/ov_SC04_010_jr_8017AE2C.c | 6 ++--- src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.c | 6 ++--- src/ov_SC04_012/ov_SC04_012_jr_8017AE2C.c | 10 ++++---- src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c | 6 ++--- src/ov_SC04_016/ov_SC04_016_jr_8017AE2C.c | 6 ++--- src/ov_SC04_018/ov_SC04_018_jr_8017AE2C.c | 6 ++--- src/ov_SC04_019/ov_SC04_019_jr_8017AE2C.c | 6 ++--- src/ov_SC04_020/ov_SC04_020_jr_8017AE2C.c | 6 ++--- src/ov_SC04_021/ov_SC04_021_jr_8017AE2C.c | 6 ++--- src/ov_SC05_000/ov_SC05_000_jr_8017AE2C.c | 6 ++--- src/ov_SC05_000/ov_SC05_000_jr_8017BEBC.c | 4 +-- src/ov_SC05_001/ov_SC05_001_jr_8017AE2C.c | 6 ++--- src/ov_SC05_002/ov_SC05_002_jr_8017AE2C.c | 6 ++--- src/ov_SC05_002/ov_SC05_002_jr_8017BEBC.c | 4 +-- src/ov_SC05_003/ov_SC05_003_jr_8017AE2C.c | 6 ++--- src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c | 4 +-- src/ov_SC05_004/ov_SC05_004_jr_8017AE2C.c | 6 ++--- src/ov_SC05_004/ov_SC05_004_jr_8017BEBC.c | 4 +-- src/ov_SC05_005/ov_SC05_005_jr_8017AE2C.c | 6 ++--- src/ov_SC05_006/ov_SC05_006_jr_8017AE2C.c | 6 ++--- src/ov_SC05_006/ov_SC05_006_jr_8017BEBC.c | 4 +-- src/ov_SC05_007/ov_SC05_007_jr_8017AE2C.c | 6 ++--- src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c | 4 +-- src/ov_SC05_008/ov_SC05_008_jr_8017AE2C.c | 10 ++++---- src/ov_SC05_009/ov_SC05_009_jr_8017AE2C.c | 6 ++--- src/ov_SC05_009/ov_SC05_009_jr_8017BEBC.c | 4 +-- src/ov_SC05_010/ov_SC05_010_jr_8017AE2C.c | 6 ++--- src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.c | 4 +-- src/ov_SC05_011/ov_SC05_011_jr_8017AE2C.c | 6 ++--- src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.c | 6 ++--- src/ov_SC05_018/ov_SC05_018_jr_8017AE2C.c | 6 ++--- src/ov_SC05_019/ov_SC05_019_jr_8017AE2C.c | 6 ++--- src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c | 6 ++--- src/ov_SC06_006/ov_SC06_006_jr_8017AE2C.c | 6 ++--- src/ov_SC06_008/ov_SC06_008_jr_8017AE2C.c | 6 ++--- src/ov_SC06_008/ov_SC06_008_jr_8017C294.c | 4 +-- src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c | 10 ++++---- src/ov_SC06_011/ov_SC06_011_jr_8017AE2C.c | 6 ++--- src/ov_SC06_011/ov_SC06_011_jr_8017BEBC.c | 4 +-- src/ov_SC06_013/ov_SC06_013_jr_8017AE2C.c | 6 ++--- src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c | 4 +-- src/ov_SC06_014/ov_SC06_014_jr_8017AE2C.c | 6 ++--- src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c | 4 +-- src/ov_SC06_015/ov_SC06_015_jr_8017AE2C.c | 6 ++--- src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c | 4 +-- src/ov_SC06_016/ov_SC06_016_jr_8017AE2C.c | 6 ++--- src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c | 4 +-- src/ov_SC06_018/ov_SC06_018_jr_801734BC.c | 2 +- src/ov_SC06_018/ov_SC06_018_jr_8017AE2C.c | 6 ++--- src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c | 4 +-- src/ov_SC06_020/ov_SC06_020_jr_8017AE2C.c | 6 ++--- src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c | 4 +-- src/ov_SC06_022/ov_SC06_022_jr_8017AE2C.c | 6 ++--- src/ov_SC06_022/ov_SC06_022_jr_8017BEBC.c | 4 +-- src/ov_SC06_024/ov_SC06_024_jr_8017AE2C.c | 6 ++--- src/ov_SC06_024/ov_SC06_024_jr_8017BEBC.c | 4 +-- src/ov_SC06_025/ov_SC06_025_jr_8017AE2C.c | 6 ++--- src/ov_SC06_025/ov_SC06_025_jr_8017BEBC.c | 4 +-- src/ov_SC06_027/ov_SC06_027_jr_8017AE2C.c | 6 ++--- src/ov_SC06_029/ov_SC06_029_jr_8017AE2C.c | 6 ++--- src/ov_SC06_030/ov_SC06_030_jr_8017AE2C.c | 6 ++--- src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.c | 4 +-- src/ov_SC06_032/ov_SC06_032_jr_8017AE2C.c | 6 ++--- src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c | 4 +-- src/ov_SC06_033/ov_SC06_033_jr_8017AE2C.c | 6 ++--- src/ov_SC06_033/ov_SC06_033_jr_8017C24C.c | 4 +-- src/ov_SC07_000/ov_SC07_000_jr_8017AE2C.c | 6 ++--- src/ov_SC07_000/ov_SC07_000_jr_8017BEBC.c | 4 +-- src/ov_SC07_001/ov_SC07_001_jr_8017AE2C.c | 6 ++--- src/ov_SC07_002/ov_SC07_002_jr_8017AE2C.c | 6 ++--- src/ov_SC07_006/ov_SC07_006_jr_8017AE2C.c | 2 +- src/ov_SC07_007/ov_SC07_007_jr_8017AE2C.c | 2 +- src/ov_SC07_008/ov_SC07_008_jr_8017AE2C.c | 6 ++--- src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c | 4 +-- src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c | 6 ++--- src/ov_SC07_010/ov_SC07_010_jr_8015C32C.c | 8 +++--- src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c | 6 ++--- src/ov_SC07_011/ov_SC07_011_jr_8017AE2C.c | 2 +- src/shared/engine_core.h | 18 +++++++------- src/shared/engine_types.h | 30 +++++++++++++++++++++-- 205 files changed, 609 insertions(+), 561 deletions(-) diff --git a/phase-ends/CURRENT_PHASE.md b/phase-ends/CURRENT_PHASE.md index dedbf6a566..85f91370ca 100644 --- a/phase-ends/CURRENT_PHASE.md +++ b/phase-ends/CURRENT_PHASE.md @@ -1931,3 +1931,25 @@ conditional) · main-EXE/B9 + GLM/B6 + resident's 14 walls (P30) · behemoths B7 > FAILED); read the GATE's own output, never the wrapper's exit code (`| tail` masked a 103/140 failure as > "exit 0"; a session fork later reported a GREEN run as "exit -1"); R14 applies to my own 3-line scripts — > two produced false evidence before any project tool did. + +- **✅ 2026-07-23 (SESSION-14 cont.) — PsyQ primitive-type CORRECTNESS: the `MATRIX` name hazard fixed.** + **Oracle-sourced (G1, Ghidra `types get`, /LIBGTE.H, psyq400.gdt):** `MATRIX` = **32B** (`short m[3][3]` + @+0x00, `long t[3]` @**+0x14** — 2B pad after m) · `SVECTOR` = 8B · `VECTOR` = **16B** (`long vx,vy,vz,pad`). + **THE HAZARD, CONFIRMED AND FIXED:** the fleet-wide name `MATRIX` held `{s32 m[3][3]; s32 t[3]}` = **48B, + NOT a PsyQ type**, while THREE other names (`MATRIX_c1`, `MATRIX_c2`, `MATRIX2`) held the true 32B layout. + Swapped by pure consistent rename across **205 files**: the 48B invention → **`MATRIX_L48`** (kept — ~131 + files are byte-correct against it; "fixing" it to 32B would change sizeof/stride and therefore codegen), + and the true layout now owns **`MATRIX`**. **R22 clean-fleet 140/140 byte-identical.** + **`VECTOR` left UNCHANGED deliberately:** ours is 12B vs PsyQ's 16B (missing the trailing `pad`), and I + first called it dead — **WRONG, it has 1 live use** (`engine_core.h` `gte_ldlv0((VECTOR*)sp)`). vx/vy/vz + offsets already agree so a fix is likely byte-neutral, but it is a LAYOUT change and must not be bundled + with a rename (an R22 failure would then be ambiguous about which caused it). Own commit, later. + **`engine_types.h` now carries an oracle-sourced GROUND-TRUTH block** documenting the real layouts, which + of our names are true vs invented, and the draft-time rule (address-suffix anything you invent — 7 of the + 8 collisions were bare generic names). SCOPE HELD: renamed + documented; did NOT force code onto real + PsyQ definitions. + **⚠️ EXIT-CODE TRAP, THIRD VARIANT TODAY:** this R22 was reported by the harness as **"failed, exit 1"** — + the exit came from my own trailing `grep -c '^\[FAIL\]'`, which returns 1 when it matches NOTHING. The + failure signal WAS the success. Today the wrapper status has been wrong three separate ways: `| tail` + masked a real 103/140 failure as exit 0; a session fork reported a green run as exit -1; and now + grep-no-match reported a green run as exit 1. **Read the gate's own output. Never the wrapper's status.** diff --git a/src/ov_SC01_000/ov_SC01_000_jr_8017AE2C.c b/src/ov_SC01_000/ov_SC01_000_jr_8017AE2C.c index 51d221190b..a3150141c2 100644 --- a/src/ov_SC01_000/ov_SC01_000_jr_8017AE2C.c +++ b/src/ov_SC01_000/ov_SC01_000_jr_8017AE2C.c @@ -3078,7 +3078,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A5694; extern SV4 D_801A569C; @@ -3086,7 +3086,7 @@ extern SV4 D_801A569C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A569C) */ @@ -3124,7 +3124,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A569C)) */ diff --git a/src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c b/src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c index d62b158cc3..cb480ba796 100644 --- a/src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c +++ b/src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c @@ -3235,7 +3235,7 @@ INCLUDE_ASM("asm/ov_SC01_000/nonmatchings/ov_SC01_000_jr_8017BEBC", func_8017D1F // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3248,7 +3248,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D290(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC01_001/ov_SC01_001_jr_8017AE2C.c b/src/ov_SC01_001/ov_SC01_001_jr_8017AE2C.c index 2170d8bbc4..fdda7505ee 100644 --- a/src/ov_SC01_001/ov_SC01_001_jr_8017AE2C.c +++ b/src/ov_SC01_001/ov_SC01_001_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801ED924; extern SV4 D_801ED92C; @@ -3084,7 +3084,7 @@ extern SV4 D_801ED92C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801ED92C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801ED92C)) */ diff --git a/src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c b/src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c index 88a99905b8..13ea60b5f1 100644 --- a/src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c +++ b/src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c @@ -3215,7 +3215,7 @@ INCLUDE_ASM("asm/ov_SC01_001/nonmatchings/ov_SC01_001_jr_8017BEBC", func_8017D09 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3228,7 +3228,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D13C(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC01_004/ov_SC01_004_jr_8017AE2C.c b/src/ov_SC01_004/ov_SC01_004_jr_8017AE2C.c index f20a53d10c..341b03410b 100644 --- a/src/ov_SC01_004/ov_SC01_004_jr_8017AE2C.c +++ b/src/ov_SC01_004/ov_SC01_004_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019008C; extern SV4 D_80190094; @@ -3084,7 +3084,7 @@ extern SV4 D_80190094; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80190094) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80190094)) */ diff --git a/src/ov_SC01_005/ov_SC01_005_jr_8017AE2C.c b/src/ov_SC01_005/ov_SC01_005_jr_8017AE2C.c index 40c9241dab..a001c08c27 100644 --- a/src/ov_SC01_005/ov_SC01_005_jr_8017AE2C.c +++ b/src/ov_SC01_005/ov_SC01_005_jr_8017AE2C.c @@ -3077,7 +3077,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801CD7EC; extern SV4 D_801CD7F4; @@ -3085,7 +3085,7 @@ extern SV4 D_801CD7F4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CD7F4) */ @@ -3123,7 +3123,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CD7F4)) */ diff --git a/src/ov_SC01_006/ov_SC01_006_jr_8017AE2C.c b/src/ov_SC01_006/ov_SC01_006_jr_8017AE2C.c index f8c7ce9b38..f79e03728b 100644 --- a/src/ov_SC01_006/ov_SC01_006_jr_8017AE2C.c +++ b/src/ov_SC01_006/ov_SC01_006_jr_8017AE2C.c @@ -3077,7 +3077,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801CD7EC; extern SV4 D_801CD7F4; @@ -3085,7 +3085,7 @@ extern SV4 D_801CD7F4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CD7F4) */ @@ -3123,7 +3123,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CD7F4)) */ diff --git a/src/ov_SC01_008/ov_SC01_008_jr_8017AE2C.c b/src/ov_SC01_008/ov_SC01_008_jr_8017AE2C.c index 492c6853b1..2958cc996b 100644 --- a/src/ov_SC01_008/ov_SC01_008_jr_8017AE2C.c +++ b/src/ov_SC01_008/ov_SC01_008_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A329C; extern SV4 D_801A32A4; @@ -3084,7 +3084,7 @@ extern SV4 D_801A32A4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A32A4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A32A4)) */ diff --git a/src/ov_SC01_009/ov_SC01_009_jr_8017AE2C.c b/src/ov_SC01_009/ov_SC01_009_jr_8017AE2C.c index b0f4df11f0..e9d6759a65 100644 --- a/src/ov_SC01_009/ov_SC01_009_jr_8017AE2C.c +++ b/src/ov_SC01_009/ov_SC01_009_jr_8017AE2C.c @@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801F30FC; extern SV4 D_801F3104; @@ -3078,7 +3078,7 @@ extern SV4 D_801F3104; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801F3104) */ @@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801F3104)) */ diff --git a/src/ov_SC01_074/ov_SC01_074_jr_8017AE2C.c b/src/ov_SC01_074/ov_SC01_074_jr_8017AE2C.c index 46c0b70a9b..615aaefb94 100644 --- a/src/ov_SC01_074/ov_SC01_074_jr_8017AE2C.c +++ b/src/ov_SC01_074/ov_SC01_074_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019BB7C; extern SV4 D_8019BB84; @@ -3084,7 +3084,7 @@ extern SV4 D_8019BB84; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019BB84) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019BB84)) */ diff --git a/src/ov_SC01_074/ov_SC01_074_jr_8017BE9C.c b/src/ov_SC01_074/ov_SC01_074_jr_8017BE9C.c index 1d62bd982a..4eef54db84 100644 --- a/src/ov_SC01_074/ov_SC01_074_jr_8017BE9C.c +++ b/src/ov_SC01_074/ov_SC01_074_jr_8017BE9C.c @@ -3344,7 +3344,7 @@ INCLUDE_ASM("asm/ov_SC01_074/nonmatchings/ov_SC01_074_jr_8017BE9C", func_8017DE0 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3357,7 +3357,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017DE88(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC01_080/ov_SC01_080_jr_8017AE2C.c b/src/ov_SC01_080/ov_SC01_080_jr_8017AE2C.c index 79491f3d7f..386ec453d4 100644 --- a/src/ov_SC01_080/ov_SC01_080_jr_8017AE2C.c +++ b/src/ov_SC01_080/ov_SC01_080_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C59AC; extern SV4 D_801C59B4; @@ -3084,7 +3084,7 @@ extern SV4 D_801C59B4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C59B4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C59B4)) */ diff --git a/src/ov_SC01_084/ov_SC01_084_jr_8017AE2C.c b/src/ov_SC01_084/ov_SC01_084_jr_8017AE2C.c index 8c9fcf0861..e016a2365d 100644 --- a/src/ov_SC01_084/ov_SC01_084_jr_8017AE2C.c +++ b/src/ov_SC01_084/ov_SC01_084_jr_8017AE2C.c @@ -3084,7 +3084,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C7454; extern SV4 D_801C745C; @@ -3092,7 +3092,7 @@ extern SV4 D_801C745C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C745C) */ @@ -3130,7 +3130,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C745C)) */ diff --git a/src/ov_SC02_000/ov_SC02_000_jr_8017AE2C.c b/src/ov_SC02_000/ov_SC02_000_jr_8017AE2C.c index 30e80f6377..e792e00957 100644 --- a/src/ov_SC02_000/ov_SC02_000_jr_8017AE2C.c +++ b/src/ov_SC02_000/ov_SC02_000_jr_8017AE2C.c @@ -3074,7 +3074,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E7F84; extern SV4 D_801E7F8C; @@ -3082,7 +3082,7 @@ extern SV4 D_801E7F8C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E7F8C) */ @@ -3120,7 +3120,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E7F8C)) */ diff --git a/src/ov_SC02_003/ov_SC02_003_jr_8017AE2C.c b/src/ov_SC02_003/ov_SC02_003_jr_8017AE2C.c index 2d68e79fea..b2f9ed5c8d 100644 --- a/src/ov_SC02_003/ov_SC02_003_jr_8017AE2C.c +++ b/src/ov_SC02_003/ov_SC02_003_jr_8017AE2C.c @@ -3074,7 +3074,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E7F84; extern SV4 D_801E7F8C; @@ -3082,7 +3082,7 @@ extern SV4 D_801E7F8C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E7F8C) */ @@ -3120,7 +3120,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E7F8C)) */ diff --git a/src/ov_SC02_004/ov_SC02_004_jr_8017AE2C.c b/src/ov_SC02_004/ov_SC02_004_jr_8017AE2C.c index 19c87dbae5..85848361e4 100644 --- a/src/ov_SC02_004/ov_SC02_004_jr_8017AE2C.c +++ b/src/ov_SC02_004/ov_SC02_004_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801961D4; extern SV4 D_801961DC; @@ -3084,7 +3084,7 @@ extern SV4 D_801961DC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801961DC) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801961DC)) */ diff --git a/src/ov_SC02_005/ov_SC02_005_jr_8017AE2C.c b/src/ov_SC02_005/ov_SC02_005_jr_8017AE2C.c index 047d3eb283..b7b5a457c2 100644 --- a/src/ov_SC02_005/ov_SC02_005_jr_8017AE2C.c +++ b/src/ov_SC02_005/ov_SC02_005_jr_8017AE2C.c @@ -3078,7 +3078,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E424C; extern SV4 D_801E4254; @@ -3086,7 +3086,7 @@ extern SV4 D_801E4254; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E4254) */ @@ -3124,7 +3124,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E4254)) */ diff --git a/src/ov_SC02_011/ov_SC02_011_jr_8017AE2C.c b/src/ov_SC02_011/ov_SC02_011_jr_8017AE2C.c index 717eeb4902..a68c9bde50 100644 --- a/src/ov_SC02_011/ov_SC02_011_jr_8017AE2C.c +++ b/src/ov_SC02_011/ov_SC02_011_jr_8017AE2C.c @@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801EB12C; extern SV4 D_801EB134; @@ -3078,7 +3078,7 @@ extern SV4 D_801EB134; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EB134) */ @@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EB134)) */ diff --git a/src/ov_SC02_015/ov_SC02_015_jr_8017AE2C.c b/src/ov_SC02_015/ov_SC02_015_jr_8017AE2C.c index 282407d9d2..08deab9e1f 100644 --- a/src/ov_SC02_015/ov_SC02_015_jr_8017AE2C.c +++ b/src/ov_SC02_015/ov_SC02_015_jr_8017AE2C.c @@ -3074,7 +3074,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801902AC; extern SV4 D_801902B4; @@ -3082,7 +3082,7 @@ extern SV4 D_801902B4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801902B4) */ @@ -3120,7 +3120,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801902B4)) */ diff --git a/src/ov_SC02_016/ov_SC02_016_jr_8017AE2C.c b/src/ov_SC02_016/ov_SC02_016_jr_8017AE2C.c index 68db8a6a4c..2c39bf4f36 100644 --- a/src/ov_SC02_016/ov_SC02_016_jr_8017AE2C.c +++ b/src/ov_SC02_016/ov_SC02_016_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B3EC4; extern SV4 D_801B3ECC; @@ -3084,7 +3084,7 @@ extern SV4 D_801B3ECC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B3ECC) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B3ECC)) */ diff --git a/src/ov_SC02_016/ov_SC02_016_jr_8017DC70.c b/src/ov_SC02_016/ov_SC02_016_jr_8017DC70.c index 71001cb7d1..bf90e930a0 100644 --- a/src/ov_SC02_016/ov_SC02_016_jr_8017DC70.c +++ b/src/ov_SC02_016/ov_SC02_016_jr_8017DC70.c @@ -3245,7 +3245,7 @@ INCLUDE_ASM("asm/ov_SC02_016/nonmatchings/ov_SC02_016_jr_8017DC70", func_8017EE6 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3258,7 +3258,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017EF84(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC02_017/ov_SC02_017_jr_8017AE2C.c b/src/ov_SC02_017/ov_SC02_017_jr_8017AE2C.c index f6ae73cde3..663e1b35c9 100644 --- a/src/ov_SC02_017/ov_SC02_017_jr_8017AE2C.c +++ b/src/ov_SC02_017/ov_SC02_017_jr_8017AE2C.c @@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801EF6EC; extern SV4 D_801EF6F4; @@ -3078,7 +3078,7 @@ extern SV4 D_801EF6F4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EF6F4) */ @@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EF6F4)) */ diff --git a/src/ov_SC02_021/ov_SC02_021_jr_8017AE2C.c b/src/ov_SC02_021/ov_SC02_021_jr_8017AE2C.c index 711fcc84cc..b459a58675 100644 --- a/src/ov_SC02_021/ov_SC02_021_jr_8017AE2C.c +++ b/src/ov_SC02_021/ov_SC02_021_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_80192C5C; extern SV4 D_80192C64; @@ -3084,7 +3084,7 @@ extern SV4 D_80192C64; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80192C64) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80192C64)) */ diff --git a/src/ov_SC02_026/ov_SC02_026_jr_8017AE2C.c b/src/ov_SC02_026/ov_SC02_026_jr_8017AE2C.c index e52750bd18..8d0f5438eb 100644 --- a/src/ov_SC02_026/ov_SC02_026_jr_8017AE2C.c +++ b/src/ov_SC02_026/ov_SC02_026_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D009C; extern SV4 D_801D00A4; @@ -3084,7 +3084,7 @@ extern SV4 D_801D00A4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D00A4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D00A4)) */ diff --git a/src/ov_SC02_026/ov_SC02_026_jr_8017C180.c b/src/ov_SC02_026/ov_SC02_026_jr_8017C180.c index b252c1e003..e454309ea3 100644 --- a/src/ov_SC02_026/ov_SC02_026_jr_8017C180.c +++ b/src/ov_SC02_026/ov_SC02_026_jr_8017C180.c @@ -3260,7 +3260,7 @@ INCLUDE_ASM("asm/ov_SC02_026/nonmatchings/ov_SC02_026_jr_8017C180", func_8017D6D // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3273,7 +3273,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D780(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC02_027/ov_SC02_027_jr_8017AE2C.c b/src/ov_SC02_027/ov_SC02_027_jr_8017AE2C.c index 09fd8bec15..c3c7723910 100644 --- a/src/ov_SC02_027/ov_SC02_027_jr_8017AE2C.c +++ b/src/ov_SC02_027/ov_SC02_027_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D9E0C; extern SV4 D_801D9E14; @@ -3084,7 +3084,7 @@ extern SV4 D_801D9E14; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D9E14) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D9E14)) */ diff --git a/src/ov_SC02_027/ov_SC02_027_jr_8017D898.c b/src/ov_SC02_027/ov_SC02_027_jr_8017D898.c index 2d91dffd21..9ae13b3bf3 100644 --- a/src/ov_SC02_027/ov_SC02_027_jr_8017D898.c +++ b/src/ov_SC02_027/ov_SC02_027_jr_8017D898.c @@ -3313,7 +3313,7 @@ INCLUDE_ASM("asm/ov_SC02_027/nonmatchings/ov_SC02_027_jr_8017D898", func_8017F85 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3326,7 +3326,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017F918(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC02_028/ov_SC02_028_jr_8017AE2C.c b/src/ov_SC02_028/ov_SC02_028_jr_8017AE2C.c index 9784276d7f..ddeae2802f 100644 --- a/src/ov_SC02_028/ov_SC02_028_jr_8017AE2C.c +++ b/src/ov_SC02_028/ov_SC02_028_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D2DAC; extern SV4 D_801D2DB4; @@ -3084,7 +3084,7 @@ extern SV4 D_801D2DB4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D2DB4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D2DB4)) */ diff --git a/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c b/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c index c93669b7f8..8e2a4bb2fb 100644 --- a/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c +++ b/src/ov_SC02_028/ov_SC02_028_jr_8017D898.c @@ -3369,7 +3369,7 @@ INCLUDE_ASM("asm/ov_SC02_028/nonmatchings/ov_SC02_028_jr_8017D898", func_8017F8F // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3382,7 +3382,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017F9AC(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC02_031/ov_SC02_031_jr_8017AE2C.c b/src/ov_SC02_031/ov_SC02_031_jr_8017AE2C.c index 5d9639596a..c816c9c305 100644 --- a/src/ov_SC02_031/ov_SC02_031_jr_8017AE2C.c +++ b/src/ov_SC02_031/ov_SC02_031_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B7524; extern SV4 D_801B752C; @@ -3084,7 +3084,7 @@ extern SV4 D_801B752C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B752C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B752C)) */ diff --git a/src/ov_SC02_035/ov_SC02_035_jr_8017AE2C.c b/src/ov_SC02_035/ov_SC02_035_jr_8017AE2C.c index 3b9c0f47fb..27076fb82e 100644 --- a/src/ov_SC02_035/ov_SC02_035_jr_8017AE2C.c +++ b/src/ov_SC02_035/ov_SC02_035_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801BE854; extern SV4 D_801BE85C; @@ -3084,7 +3084,7 @@ extern SV4 D_801BE85C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801BE85C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801BE85C)) */ diff --git a/src/ov_SC02_035/ov_SC02_035_jr_8017BEBC.c b/src/ov_SC02_035/ov_SC02_035_jr_8017BEBC.c index e2e6414d79..b9804f0465 100644 --- a/src/ov_SC02_035/ov_SC02_035_jr_8017BEBC.c +++ b/src/ov_SC02_035/ov_SC02_035_jr_8017BEBC.c @@ -3246,7 +3246,7 @@ INCLUDE_ASM("asm/ov_SC02_035/nonmatchings/ov_SC02_035_jr_8017BEBC", func_8017D13 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3259,7 +3259,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D1D0(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC02_039/ov_SC02_039_jr_8017AE2C.c b/src/ov_SC02_039/ov_SC02_039_jr_8017AE2C.c index e9e721c425..7ddcee9e52 100644 --- a/src/ov_SC02_039/ov_SC02_039_jr_8017AE2C.c +++ b/src/ov_SC02_039/ov_SC02_039_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A0C04; extern SV4 D_801A0C0C; @@ -3084,7 +3084,7 @@ extern SV4 D_801A0C0C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A0C0C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A0C0C)) */ diff --git a/src/ov_SC02_041/ov_SC02_041_jr_8017AE2C.c b/src/ov_SC02_041/ov_SC02_041_jr_8017AE2C.c index c5c130841f..6f98c742ba 100644 --- a/src/ov_SC02_041/ov_SC02_041_jr_8017AE2C.c +++ b/src/ov_SC02_041/ov_SC02_041_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B8F7C; extern SV4 D_801B8F84; @@ -3084,7 +3084,7 @@ extern SV4 D_801B8F84; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B8F84) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B8F84)) */ diff --git a/src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c b/src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c index 26e9920368..6f8a5c0c9c 100644 --- a/src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c +++ b/src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c @@ -3348,7 +3348,7 @@ INCLUDE_ASM("asm/ov_SC02_041/nonmatchings/ov_SC02_041_jr_8017BEBC", func_8017E37 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3361,7 +3361,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017E414(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c b/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c index b82e4fab2d..b6ef48d1b8 100644 --- a/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c +++ b/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c @@ -3074,7 +3074,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801EE5FC; extern SV4 D_801EE604; @@ -3082,7 +3082,7 @@ extern SV4 D_801EE604; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EE604) */ @@ -3120,7 +3120,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EE604)) */ diff --git a/src/ov_SC03_002/ov_SC03_002_jr_8017AE2C.c b/src/ov_SC03_002/ov_SC03_002_jr_8017AE2C.c index bbed207563..13c88ff1bc 100644 --- a/src/ov_SC03_002/ov_SC03_002_jr_8017AE2C.c +++ b/src/ov_SC03_002/ov_SC03_002_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801CB67C; extern SV4 D_801CB684; @@ -3084,7 +3084,7 @@ extern SV4 D_801CB684; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CB684) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CB684)) */ diff --git a/src/ov_SC03_003/ov_SC03_003_jr_8017AE2C.c b/src/ov_SC03_003/ov_SC03_003_jr_8017AE2C.c index 8b7ef7aebb..aef6586ad4 100644 --- a/src/ov_SC03_003/ov_SC03_003_jr_8017AE2C.c +++ b/src/ov_SC03_003/ov_SC03_003_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8018F984; extern SV4 D_8018F98C; @@ -3084,7 +3084,7 @@ extern SV4 D_8018F98C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8018F98C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8018F98C)) */ diff --git a/src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c b/src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c index 218e62a3a6..4c5f6958c9 100644 --- a/src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c +++ b/src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c @@ -3071,7 +3071,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801F72FC; extern SV4 D_801F7304; @@ -3079,7 +3079,7 @@ extern SV4 D_801F7304; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801F7304) */ @@ -3117,7 +3117,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801F7304)) */ diff --git a/src/ov_SC03_007/ov_SC03_007_jr_8017AE2C.c b/src/ov_SC03_007/ov_SC03_007_jr_8017AE2C.c index 0f2531e72e..fe990df615 100644 --- a/src/ov_SC03_007/ov_SC03_007_jr_8017AE2C.c +++ b/src/ov_SC03_007/ov_SC03_007_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E9C54; extern SV4 D_801E9C5C; @@ -3084,7 +3084,7 @@ extern SV4 D_801E9C5C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E9C5C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E9C5C)) */ diff --git a/src/ov_SC03_010/ov_SC03_010_jr_8017AE2C.c b/src/ov_SC03_010/ov_SC03_010_jr_8017AE2C.c index d0a94c0649..017291a63a 100644 --- a/src/ov_SC03_010/ov_SC03_010_jr_8017AE2C.c +++ b/src/ov_SC03_010/ov_SC03_010_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019FEB4; extern SV4 D_8019FEBC; @@ -3084,7 +3084,7 @@ extern SV4 D_8019FEBC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019FEBC) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019FEBC)) */ diff --git a/src/ov_SC03_011/ov_SC03_011_jr_8017AE2C.c b/src/ov_SC03_011/ov_SC03_011_jr_8017AE2C.c index 4a2dfa7158..8374ef76a2 100644 --- a/src/ov_SC03_011/ov_SC03_011_jr_8017AE2C.c +++ b/src/ov_SC03_011/ov_SC03_011_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A214C; extern SV4 D_801A2154; @@ -3084,7 +3084,7 @@ extern SV4 D_801A2154; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A2154) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A2154)) */ diff --git a/src/ov_SC03_012/ov_SC03_012_jr_8017AE2C.c b/src/ov_SC03_012/ov_SC03_012_jr_8017AE2C.c index febf37be95..8b28ecc6cb 100644 --- a/src/ov_SC03_012/ov_SC03_012_jr_8017AE2C.c +++ b/src/ov_SC03_012/ov_SC03_012_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_80194F6C; extern SV4 D_80194F74; @@ -3084,7 +3084,7 @@ extern SV4 D_80194F74; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80194F74) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80194F74)) */ diff --git a/src/ov_SC03_013/ov_SC03_013_jr_8017AE2C.c b/src/ov_SC03_013/ov_SC03_013_jr_8017AE2C.c index 3783cc312b..1df5980d5d 100644 --- a/src/ov_SC03_013/ov_SC03_013_jr_8017AE2C.c +++ b/src/ov_SC03_013/ov_SC03_013_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801AD23C; extern SV4 D_801AD244; @@ -3084,7 +3084,7 @@ extern SV4 D_801AD244; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801AD244) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801AD244)) */ diff --git a/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.c b/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.c index 6b5fcd86a7..349349326f 100644 --- a/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.c +++ b/src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.c @@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801EA7BC; extern SV4 D_801EA7C4; @@ -3078,7 +3078,7 @@ extern SV4 D_801EA7C4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EA7C4) */ @@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EA7C4)) */ diff --git a/src/ov_SC03_014/ov_SC03_014_jr_8017EB7C.c b/src/ov_SC03_014/ov_SC03_014_jr_8017EB7C.c index 38da9d8808..1d966f9bef 100644 --- a/src/ov_SC03_014/ov_SC03_014_jr_8017EB7C.c +++ b/src/ov_SC03_014/ov_SC03_014_jr_8017EB7C.c @@ -3574,7 +3574,7 @@ INCLUDE_ASM("asm/ov_SC03_014/nonmatchings/ov_SC03_014_jr_8017EB7C", func_80183A5 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3587,7 +3587,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_80183B58(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.c b/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.c index 98f6a5db5a..224eb7a914 100644 --- a/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.c +++ b/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.c @@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801EA7BC; extern SV4 D_801EA7C4; @@ -3078,7 +3078,7 @@ extern SV4 D_801EA7C4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EA7C4) */ @@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EA7C4)) */ diff --git a/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.c b/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.c index cb4396b4b2..f99bb73cfd 100644 --- a/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.c +++ b/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.c @@ -3555,7 +3555,7 @@ INCLUDE_ASM("asm/ov_SC03_015/nonmatchings/ov_SC03_015_jr_8017EB7C", func_80183A5 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3568,7 +3568,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_80183B58(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_023/ov_SC03_023_jr_8017AE2C.c b/src/ov_SC03_023/ov_SC03_023_jr_8017AE2C.c index a406f61a23..6f94ad422c 100644 --- a/src/ov_SC03_023/ov_SC03_023_jr_8017AE2C.c +++ b/src/ov_SC03_023/ov_SC03_023_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_80198B94; extern SV4 D_80198B9C; @@ -3084,7 +3084,7 @@ extern SV4 D_80198B9C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80198B9C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80198B9C)) */ diff --git a/src/ov_SC03_024/ov_SC03_024_jr_8017AE2C.c b/src/ov_SC03_024/ov_SC03_024_jr_8017AE2C.c index ae20bc5be4..20b21676dc 100644 --- a/src/ov_SC03_024/ov_SC03_024_jr_8017AE2C.c +++ b/src/ov_SC03_024/ov_SC03_024_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C112C; extern SV4 D_801C1134; @@ -3084,7 +3084,7 @@ extern SV4 D_801C1134; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C1134) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C1134)) */ diff --git a/src/ov_SC03_024/ov_SC03_024_jr_8017DF84.c b/src/ov_SC03_024/ov_SC03_024_jr_8017DF84.c index 4e3a2b5ea8..c06ebe5716 100644 --- a/src/ov_SC03_024/ov_SC03_024_jr_8017DF84.c +++ b/src/ov_SC03_024/ov_SC03_024_jr_8017DF84.c @@ -3433,7 +3433,7 @@ INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_8017DF84", func_80180E6 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3446,7 +3446,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_80180EA8(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_028/ov_SC03_028_jr_8017AE2C.c b/src/ov_SC03_028/ov_SC03_028_jr_8017AE2C.c index 8eff6e6ecf..9d892c911e 100644 --- a/src/ov_SC03_028/ov_SC03_028_jr_8017AE2C.c +++ b/src/ov_SC03_028/ov_SC03_028_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX_c1: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801EB464; extern SV4 D_801EB46C; @@ -3084,7 +3084,7 @@ extern SV4 D_801EB46C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EB46C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EB46C)) */ @@ -3571,7 +3571,7 @@ INCLUDE_ASM("asm/ov_SC03_028/nonmatchings/ov_SC03_028_jr_8017AE2C", func_8017FE1 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3584,7 +3584,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017FF68(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_029/ov_SC03_029_jr_8017AE2C.c b/src/ov_SC03_029/ov_SC03_029_jr_8017AE2C.c index 66765bc531..fb241dbb55 100644 --- a/src/ov_SC03_029/ov_SC03_029_jr_8017AE2C.c +++ b/src/ov_SC03_029/ov_SC03_029_jr_8017AE2C.c @@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D943C; extern SV4 D_801D9444; @@ -3078,7 +3078,7 @@ extern SV4 D_801D9444; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D9444) */ @@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D9444)) */ diff --git a/src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c b/src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c index 28a809b9d5..f04ea2050b 100644 --- a/src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c +++ b/src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E1A34; extern SV4 D_801E1A3C; @@ -3084,7 +3084,7 @@ extern SV4 D_801E1A3C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E1A3C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E1A3C)) */ diff --git a/src/ov_SC03_031/ov_SC03_031_jr_8017AE2C.c b/src/ov_SC03_031/ov_SC03_031_jr_8017AE2C.c index c7345cf8f5..7c34055e78 100644 --- a/src/ov_SC03_031/ov_SC03_031_jr_8017AE2C.c +++ b/src/ov_SC03_031/ov_SC03_031_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C5E34; extern SV4 D_801C5E3C; @@ -3084,7 +3084,7 @@ extern SV4 D_801C5E3C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C5E3C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C5E3C)) */ diff --git a/src/ov_SC03_089/ov_SC03_089_jr_8017AE2C.c b/src/ov_SC03_089/ov_SC03_089_jr_8017AE2C.c index 2373ab83ba..198995f6e9 100644 --- a/src/ov_SC03_089/ov_SC03_089_jr_8017AE2C.c +++ b/src/ov_SC03_089/ov_SC03_089_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C66EC; extern SV4 D_801C66F4; @@ -3084,7 +3084,7 @@ extern SV4 D_801C66F4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C66F4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C66F4)) */ diff --git a/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c b/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c index 68197e1f75..dd10d9a2ad 100644 --- a/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c +++ b/src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c @@ -3380,7 +3380,7 @@ INCLUDE_ASM("asm/ov_SC03_089/nonmatchings/ov_SC03_089_jr_8017CA80", func_80181B1 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3393,7 +3393,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_80181BCC(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_090/ov_SC03_090_jr_8017AE2C.c b/src/ov_SC03_090/ov_SC03_090_jr_8017AE2C.c index a89a486697..7a99f50b15 100644 --- a/src/ov_SC03_090/ov_SC03_090_jr_8017AE2C.c +++ b/src/ov_SC03_090/ov_SC03_090_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801CBB54; extern SV4 D_801CBB5C; @@ -3084,7 +3084,7 @@ extern SV4 D_801CBB5C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CBB5C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CBB5C)) */ diff --git a/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c b/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c index 51ae4e2116..95e11a2ace 100644 --- a/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c +++ b/src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c @@ -3380,7 +3380,7 @@ INCLUDE_ASM("asm/ov_SC03_090/nonmatchings/ov_SC03_090_jr_8017CA80", func_80181C8 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3393,7 +3393,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_80181D30(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_091/ov_SC03_091_jr_8017AE2C.c b/src/ov_SC03_091/ov_SC03_091_jr_8017AE2C.c index 57ae1d87d9..2385bb6e3b 100644 --- a/src/ov_SC03_091/ov_SC03_091_jr_8017AE2C.c +++ b/src/ov_SC03_091/ov_SC03_091_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D2224; extern SV4 D_801D222C; @@ -3084,7 +3084,7 @@ extern SV4 D_801D222C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D222C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D222C)) */ diff --git a/src/ov_SC03_091/ov_SC03_091_jr_80182268.c b/src/ov_SC03_091/ov_SC03_091_jr_80182268.c index 1a2c64a441..8254b3ae15 100644 --- a/src/ov_SC03_091/ov_SC03_091_jr_80182268.c +++ b/src/ov_SC03_091/ov_SC03_091_jr_80182268.c @@ -2758,7 +2758,7 @@ INCLUDE_ASM("asm/ov_SC03_091/nonmatchings/ov_SC03_091_jr_80182268", func_80182A9 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -2771,7 +2771,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_80182B48(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_092/ov_SC03_092_jr_8017AE2C.c b/src/ov_SC03_092/ov_SC03_092_jr_8017AE2C.c index 0f47c4ed12..a698f3d668 100644 --- a/src/ov_SC03_092/ov_SC03_092_jr_8017AE2C.c +++ b/src/ov_SC03_092/ov_SC03_092_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B2DEC; extern SV4 D_801B2DF4; @@ -3084,7 +3084,7 @@ extern SV4 D_801B2DF4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B2DF4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B2DF4)) */ diff --git a/src/ov_SC03_093/ov_SC03_093_jr_8017AE2C.c b/src/ov_SC03_093/ov_SC03_093_jr_8017AE2C.c index 8b82bd66d7..f0b1765626 100644 --- a/src/ov_SC03_093/ov_SC03_093_jr_8017AE2C.c +++ b/src/ov_SC03_093/ov_SC03_093_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801CC25C; extern SV4 D_801CC264; @@ -3084,7 +3084,7 @@ extern SV4 D_801CC264; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CC264) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CC264)) */ diff --git a/src/ov_SC03_093/ov_SC03_093_jr_8017D898.c b/src/ov_SC03_093/ov_SC03_093_jr_8017D898.c index ea5684109a..1a660bbb78 100644 --- a/src/ov_SC03_093/ov_SC03_093_jr_8017D898.c +++ b/src/ov_SC03_093/ov_SC03_093_jr_8017D898.c @@ -3276,7 +3276,7 @@ INCLUDE_ASM("asm/ov_SC03_093/nonmatchings/ov_SC03_093_jr_8017D898", func_8017EE3 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3289,7 +3289,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017EF20(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_094/ov_SC03_094_jr_8017AE2C.c b/src/ov_SC03_094/ov_SC03_094_jr_8017AE2C.c index e12974c1a3..4bb4c1136f 100644 --- a/src/ov_SC03_094/ov_SC03_094_jr_8017AE2C.c +++ b/src/ov_SC03_094/ov_SC03_094_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D309C; extern SV4 D_801D30A4; @@ -3084,7 +3084,7 @@ extern SV4 D_801D30A4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D30A4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D30A4)) */ diff --git a/src/ov_SC03_094/ov_SC03_094_jr_8017BEBC.c b/src/ov_SC03_094/ov_SC03_094_jr_8017BEBC.c index 1007d60a9f..6a0e774289 100644 --- a/src/ov_SC03_094/ov_SC03_094_jr_8017BEBC.c +++ b/src/ov_SC03_094/ov_SC03_094_jr_8017BEBC.c @@ -3264,7 +3264,7 @@ INCLUDE_ASM("asm/ov_SC03_094/nonmatchings/ov_SC03_094_jr_8017BEBC", func_8017D63 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3277,7 +3277,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D6D0(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_095/ov_SC03_095_jr_8017AE2C.c b/src/ov_SC03_095/ov_SC03_095_jr_8017AE2C.c index c6235063f6..3deeac3e6d 100644 --- a/src/ov_SC03_095/ov_SC03_095_jr_8017AE2C.c +++ b/src/ov_SC03_095/ov_SC03_095_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019BC94; extern SV4 D_8019BC9C; @@ -3084,7 +3084,7 @@ extern SV4 D_8019BC9C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019BC9C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019BC9C)) */ diff --git a/src/ov_SC03_095/ov_SC03_095_jr_8017BEBC.c b/src/ov_SC03_095/ov_SC03_095_jr_8017BEBC.c index 56f9efe5aa..cb9a92c68f 100644 --- a/src/ov_SC03_095/ov_SC03_095_jr_8017BEBC.c +++ b/src/ov_SC03_095/ov_SC03_095_jr_8017BEBC.c @@ -3252,7 +3252,7 @@ INCLUDE_ASM("asm/ov_SC03_095/nonmatchings/ov_SC03_095_jr_8017BEBC", func_8017D2A // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3265,7 +3265,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D390(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_096/ov_SC03_096_jr_8017AE2C.c b/src/ov_SC03_096/ov_SC03_096_jr_8017AE2C.c index a9a8a457d2..00e478eb1b 100644 --- a/src/ov_SC03_096/ov_SC03_096_jr_8017AE2C.c +++ b/src/ov_SC03_096/ov_SC03_096_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019A74C; extern SV4 D_8019A754; @@ -3084,7 +3084,7 @@ extern SV4 D_8019A754; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019A754) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019A754)) */ diff --git a/src/ov_SC03_096/ov_SC03_096_jr_8017BEBC.c b/src/ov_SC03_096/ov_SC03_096_jr_8017BEBC.c index df85afaa97..9b85043629 100644 --- a/src/ov_SC03_096/ov_SC03_096_jr_8017BEBC.c +++ b/src/ov_SC03_096/ov_SC03_096_jr_8017BEBC.c @@ -3246,7 +3246,7 @@ INCLUDE_ASM("asm/ov_SC03_096/nonmatchings/ov_SC03_096_jr_8017BEBC", func_8017D13 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3259,7 +3259,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D238(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_097/ov_SC03_097_jr_8017AE2C.c b/src/ov_SC03_097/ov_SC03_097_jr_8017AE2C.c index 5746d2b571..9df6fe9a71 100644 --- a/src/ov_SC03_097/ov_SC03_097_jr_8017AE2C.c +++ b/src/ov_SC03_097/ov_SC03_097_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801AA7D4; extern SV4 D_801AA7DC; @@ -3084,7 +3084,7 @@ extern SV4 D_801AA7DC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801AA7DC) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801AA7DC)) */ diff --git a/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c b/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c index 8182768ba5..548dfd4f18 100644 --- a/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c +++ b/src/ov_SC03_097/ov_SC03_097_jr_8017D898.c @@ -3379,7 +3379,7 @@ INCLUDE_ASM("asm/ov_SC03_097/nonmatchings/ov_SC03_097_jr_8017D898", func_8017F48 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3392,7 +3392,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017F53C(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_098/ov_SC03_098_jr_8017AE2C.c b/src/ov_SC03_098/ov_SC03_098_jr_8017AE2C.c index 55ffe24cb1..1f38898764 100644 --- a/src/ov_SC03_098/ov_SC03_098_jr_8017AE2C.c +++ b/src/ov_SC03_098/ov_SC03_098_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C5444; extern SV4 D_801C544C; @@ -3084,7 +3084,7 @@ extern SV4 D_801C544C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C544C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C544C)) */ diff --git a/src/ov_SC03_098/ov_SC03_098_jr_8017D898.c b/src/ov_SC03_098/ov_SC03_098_jr_8017D898.c index a47c5d042d..8e5cb79362 100644 --- a/src/ov_SC03_098/ov_SC03_098_jr_8017D898.c +++ b/src/ov_SC03_098/ov_SC03_098_jr_8017D898.c @@ -3270,7 +3270,7 @@ INCLUDE_ASM("asm/ov_SC03_098/nonmatchings/ov_SC03_098_jr_8017D898", func_8017ECC // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3283,7 +3283,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017ED60(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_099/ov_SC03_099_jr_8017AE2C.c b/src/ov_SC03_099/ov_SC03_099_jr_8017AE2C.c index 6daf2dff3c..6dc8ec9e6b 100644 --- a/src/ov_SC03_099/ov_SC03_099_jr_8017AE2C.c +++ b/src/ov_SC03_099/ov_SC03_099_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801BF114; extern SV4 D_801BF11C; @@ -3084,7 +3084,7 @@ extern SV4 D_801BF11C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801BF11C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801BF11C)) */ diff --git a/src/ov_SC03_099/ov_SC03_099_jr_8017BEBC.c b/src/ov_SC03_099/ov_SC03_099_jr_8017BEBC.c index 2c0634ac1b..843f986023 100644 --- a/src/ov_SC03_099/ov_SC03_099_jr_8017BEBC.c +++ b/src/ov_SC03_099/ov_SC03_099_jr_8017BEBC.c @@ -3252,7 +3252,7 @@ INCLUDE_ASM("asm/ov_SC03_099/nonmatchings/ov_SC03_099_jr_8017BEBC", func_8017D2A // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3265,7 +3265,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D364(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_100/ov_SC03_100_jr_8017AE2C.c b/src/ov_SC03_100/ov_SC03_100_jr_8017AE2C.c index fdcc8b842e..3142cbe5fd 100644 --- a/src/ov_SC03_100/ov_SC03_100_jr_8017AE2C.c +++ b/src/ov_SC03_100/ov_SC03_100_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C839C; extern SV4 D_801C83A4; @@ -3084,7 +3084,7 @@ extern SV4 D_801C83A4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C83A4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C83A4)) */ diff --git a/src/ov_SC03_100/ov_SC03_100_jr_8017D898.c b/src/ov_SC03_100/ov_SC03_100_jr_8017D898.c index 635d920f34..d4c690d079 100644 --- a/src/ov_SC03_100/ov_SC03_100_jr_8017D898.c +++ b/src/ov_SC03_100/ov_SC03_100_jr_8017D898.c @@ -3260,7 +3260,7 @@ INCLUDE_ASM("asm/ov_SC03_100/nonmatchings/ov_SC03_100_jr_8017D898", func_8017EC8 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3273,7 +3273,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017ED90(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_101/ov_SC03_101_jr_8017AE2C.c b/src/ov_SC03_101/ov_SC03_101_jr_8017AE2C.c index 52115837f5..9380bf0559 100644 --- a/src/ov_SC03_101/ov_SC03_101_jr_8017AE2C.c +++ b/src/ov_SC03_101/ov_SC03_101_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019DC64; extern SV4 D_8019DC6C; @@ -3084,7 +3084,7 @@ extern SV4 D_8019DC6C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019DC6C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019DC6C)) */ diff --git a/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c b/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c index c0e6974bac..9c580e03f3 100644 --- a/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c +++ b/src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c @@ -3303,7 +3303,7 @@ INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_8017E0B // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3316,7 +3316,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017E174(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_102/ov_SC03_102_jr_8017AE2C.c b/src/ov_SC03_102/ov_SC03_102_jr_8017AE2C.c index dfd95e06bb..5b75107621 100644 --- a/src/ov_SC03_102/ov_SC03_102_jr_8017AE2C.c +++ b/src/ov_SC03_102/ov_SC03_102_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B98DC; extern SV4 D_801B98E4; @@ -3084,7 +3084,7 @@ extern SV4 D_801B98E4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B98E4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B98E4)) */ diff --git a/src/ov_SC03_102/ov_SC03_102_jr_8017BEBC.c b/src/ov_SC03_102/ov_SC03_102_jr_8017BEBC.c index 3da051a52f..b3331e0d4c 100644 --- a/src/ov_SC03_102/ov_SC03_102_jr_8017BEBC.c +++ b/src/ov_SC03_102/ov_SC03_102_jr_8017BEBC.c @@ -3260,7 +3260,7 @@ INCLUDE_ASM("asm/ov_SC03_102/nonmatchings/ov_SC03_102_jr_8017BEBC", func_8018055 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3273,7 +3273,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_80180628(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_103/ov_SC03_103_jr_8017AE2C.c b/src/ov_SC03_103/ov_SC03_103_jr_8017AE2C.c index be15113c72..a47eba34f2 100644 --- a/src/ov_SC03_103/ov_SC03_103_jr_8017AE2C.c +++ b/src/ov_SC03_103/ov_SC03_103_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C4A94; extern SV4 D_801C4A9C; @@ -3084,7 +3084,7 @@ extern SV4 D_801C4A9C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C4A9C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C4A9C)) */ diff --git a/src/ov_SC03_103/ov_SC03_103_jr_8017C294.c b/src/ov_SC03_103/ov_SC03_103_jr_8017C294.c index 46201050dc..bb3514d6cc 100644 --- a/src/ov_SC03_103/ov_SC03_103_jr_8017C294.c +++ b/src/ov_SC03_103/ov_SC03_103_jr_8017C294.c @@ -3274,7 +3274,7 @@ INCLUDE_ASM("asm/ov_SC03_103/nonmatchings/ov_SC03_103_jr_8017C294", func_8017E36 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3287,7 +3287,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017E40C(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_104/ov_SC03_104_jr_8017AE2C.c b/src/ov_SC03_104/ov_SC03_104_jr_8017AE2C.c index 2af4e2b486..d3026fe644 100644 --- a/src/ov_SC03_104/ov_SC03_104_jr_8017AE2C.c +++ b/src/ov_SC03_104/ov_SC03_104_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C002C; extern SV4 D_801C0034; @@ -3084,7 +3084,7 @@ extern SV4 D_801C0034; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C0034) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C0034)) */ diff --git a/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c b/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c index 851f3385c7..173f5b9708 100644 --- a/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c +++ b/src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c @@ -3320,7 +3320,7 @@ INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_8018152 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3333,7 +3333,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_801815DC(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_105/ov_SC03_105_jr_8017AE2C.c b/src/ov_SC03_105/ov_SC03_105_jr_8017AE2C.c index d270dd2f3a..56739f66ee 100644 --- a/src/ov_SC03_105/ov_SC03_105_jr_8017AE2C.c +++ b/src/ov_SC03_105/ov_SC03_105_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B95BC; extern SV4 D_801B95C4; @@ -3084,7 +3084,7 @@ extern SV4 D_801B95C4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B95C4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B95C4)) */ diff --git a/src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.c b/src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.c index 4a2a05e07c..45af2f9757 100644 --- a/src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.c +++ b/src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.c @@ -3254,7 +3254,7 @@ INCLUDE_ASM("asm/ov_SC03_105/nonmatchings/ov_SC03_105_jr_8017C8D0", func_8017E18 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3267,7 +3267,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017E33C(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_108/ov_SC03_108_jr_8017AE2C.c b/src/ov_SC03_108/ov_SC03_108_jr_8017AE2C.c index 8242db0e81..f445dde9fc 100644 --- a/src/ov_SC03_108/ov_SC03_108_jr_8017AE2C.c +++ b/src/ov_SC03_108/ov_SC03_108_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A18AC; extern SV4 D_801A18B4; @@ -3084,7 +3084,7 @@ extern SV4 D_801A18B4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A18B4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A18B4)) */ diff --git a/src/ov_SC03_109/ov_SC03_109_jr_8017AE2C.c b/src/ov_SC03_109/ov_SC03_109_jr_8017AE2C.c index 013b25fbaf..08243fb8e8 100644 --- a/src/ov_SC03_109/ov_SC03_109_jr_8017AE2C.c +++ b/src/ov_SC03_109/ov_SC03_109_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019A2BC; extern SV4 D_8019A2C4; @@ -3084,7 +3084,7 @@ extern SV4 D_8019A2C4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019A2C4) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019A2C4)) */ diff --git a/src/ov_SC03_109/ov_SC03_109_jr_8017C180.c b/src/ov_SC03_109/ov_SC03_109_jr_8017C180.c index 085b112c41..a6fc925a28 100644 --- a/src/ov_SC03_109/ov_SC03_109_jr_8017C180.c +++ b/src/ov_SC03_109/ov_SC03_109_jr_8017C180.c @@ -3246,7 +3246,7 @@ INCLUDE_ASM("asm/ov_SC03_109/nonmatchings/ov_SC03_109_jr_8017C180", func_8017D3C // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3259,7 +3259,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D48C(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_110/ov_SC03_110_jr_8017AE2C.c b/src/ov_SC03_110/ov_SC03_110_jr_8017AE2C.c index 51c91ce2f3..498790b3f6 100644 --- a/src/ov_SC03_110/ov_SC03_110_jr_8017AE2C.c +++ b/src/ov_SC03_110/ov_SC03_110_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A2064; extern SV4 D_801A206C; @@ -3084,7 +3084,7 @@ extern SV4 D_801A206C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A206C) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A206C)) */ diff --git a/src/ov_SC03_110/ov_SC03_110_jr_8017D898.c b/src/ov_SC03_110/ov_SC03_110_jr_8017D898.c index dffc409cdd..13a47808ba 100644 --- a/src/ov_SC03_110/ov_SC03_110_jr_8017D898.c +++ b/src/ov_SC03_110/ov_SC03_110_jr_8017D898.c @@ -3262,7 +3262,7 @@ INCLUDE_ASM("asm/ov_SC03_110/nonmatchings/ov_SC03_110_jr_8017D898", func_8017EB1 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3275,7 +3275,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017EBFC(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_111/ov_SC03_111_jr_8017AE2C.c b/src/ov_SC03_111/ov_SC03_111_jr_8017AE2C.c index bce3d6c456..fc8b85be04 100644 --- a/src/ov_SC03_111/ov_SC03_111_jr_8017AE2C.c +++ b/src/ov_SC03_111/ov_SC03_111_jr_8017AE2C.c @@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B956C; extern SV4 D_801B9574; @@ -3084,7 +3084,7 @@ extern SV4 D_801B9574; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B9574) */ @@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B9574)) */ diff --git a/src/ov_SC03_112/ov_SC03_112_jr_8017AE2C.c b/src/ov_SC03_112/ov_SC03_112_jr_8017AE2C.c index c6b1e9d667..b743a5627f 100644 --- a/src/ov_SC03_112/ov_SC03_112_jr_8017AE2C.c +++ b/src/ov_SC03_112/ov_SC03_112_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801ACDCC; extern SV4 D_801ACDD4; @@ -3083,7 +3083,7 @@ extern SV4 D_801ACDD4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801ACDD4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801ACDD4)) */ diff --git a/src/ov_SC03_113/ov_SC03_113_jr_8017AE2C.c b/src/ov_SC03_113/ov_SC03_113_jr_8017AE2C.c index 7bc313d84e..8cf5e6dc61 100644 --- a/src/ov_SC03_113/ov_SC03_113_jr_8017AE2C.c +++ b/src/ov_SC03_113/ov_SC03_113_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A595C; extern SV4 D_801A5964; @@ -3083,7 +3083,7 @@ extern SV4 D_801A5964; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A5964) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A5964)) */ diff --git a/src/ov_SC03_113/ov_SC03_113_jr_8017C294.c b/src/ov_SC03_113/ov_SC03_113_jr_8017C294.c index f8eb0059c1..1dfa21144e 100644 --- a/src/ov_SC03_113/ov_SC03_113_jr_8017C294.c +++ b/src/ov_SC03_113/ov_SC03_113_jr_8017C294.c @@ -3295,7 +3295,7 @@ INCLUDE_ASM("asm/ov_SC03_113/nonmatchings/ov_SC03_113_jr_8017C294", func_8017F15 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3308,7 +3308,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017F1FC(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_114/ov_SC03_114_jr_8017AE2C.c b/src/ov_SC03_114/ov_SC03_114_jr_8017AE2C.c index 3e0a959c64..7d49106717 100644 --- a/src/ov_SC03_114/ov_SC03_114_jr_8017AE2C.c +++ b/src/ov_SC03_114/ov_SC03_114_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A95F4; extern SV4 D_801A95FC; @@ -3083,7 +3083,7 @@ extern SV4 D_801A95FC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A95FC) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A95FC)) */ diff --git a/src/ov_SC03_115/ov_SC03_115_jr_8017AE2C.c b/src/ov_SC03_115/ov_SC03_115_jr_8017AE2C.c index 000ee67743..752f2844bb 100644 --- a/src/ov_SC03_115/ov_SC03_115_jr_8017AE2C.c +++ b/src/ov_SC03_115/ov_SC03_115_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_80194F4C; extern SV4 D_80194F54; @@ -3083,7 +3083,7 @@ extern SV4 D_80194F54; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80194F54) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80194F54)) */ diff --git a/src/ov_SC03_115/ov_SC03_115_jr_8017BEBC.c b/src/ov_SC03_115/ov_SC03_115_jr_8017BEBC.c index e4fbe47147..52db306a79 100644 --- a/src/ov_SC03_115/ov_SC03_115_jr_8017BEBC.c +++ b/src/ov_SC03_115/ov_SC03_115_jr_8017BEBC.c @@ -3304,7 +3304,7 @@ INCLUDE_ASM("asm/ov_SC03_115/nonmatchings/ov_SC03_115_jr_8017BEBC", func_8017D3B // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3317,7 +3317,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D420(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_116/ov_SC03_116_jr_8017AE2C.c b/src/ov_SC03_116/ov_SC03_116_jr_8017AE2C.c index b23a53dc8d..444711fb30 100644 --- a/src/ov_SC03_116/ov_SC03_116_jr_8017AE2C.c +++ b/src/ov_SC03_116/ov_SC03_116_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX_c1: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_80197ADC; extern SV4 D_80197AE4; @@ -3083,7 +3083,7 @@ extern SV4 D_80197AE4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80197AE4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80197AE4)) */ @@ -3366,7 +3366,7 @@ INCLUDE_ASM("asm/ov_SC03_116/nonmatchings/ov_SC03_116_jr_8017AE2C", func_80180D4 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3379,7 +3379,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_80180DE0(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_117/ov_SC03_117_jr_8017AE2C.c b/src/ov_SC03_117/ov_SC03_117_jr_8017AE2C.c index b1f0ed1e2d..f433c56e97 100644 --- a/src/ov_SC03_117/ov_SC03_117_jr_8017AE2C.c +++ b/src/ov_SC03_117/ov_SC03_117_jr_8017AE2C.c @@ -3069,7 +3069,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801CE254; extern SV4 D_801CE25C; @@ -3077,7 +3077,7 @@ extern SV4 D_801CE25C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CE25C) */ @@ -3115,7 +3115,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CE25C)) */ diff --git a/src/ov_SC03_117/ov_SC03_117_jr_8017BEBC.c b/src/ov_SC03_117/ov_SC03_117_jr_8017BEBC.c index 68a14aeb3a..717482ac05 100644 --- a/src/ov_SC03_117/ov_SC03_117_jr_8017BEBC.c +++ b/src/ov_SC03_117/ov_SC03_117_jr_8017BEBC.c @@ -3427,7 +3427,7 @@ INCLUDE_ASM("asm/ov_SC03_117/nonmatchings/ov_SC03_117_jr_8017BEBC", func_8017E21 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3440,7 +3440,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017E300(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_118/ov_SC03_118_jr_8017AE2C.c b/src/ov_SC03_118/ov_SC03_118_jr_8017AE2C.c index ba5002dedc..29c3dd06e5 100644 --- a/src/ov_SC03_118/ov_SC03_118_jr_8017AE2C.c +++ b/src/ov_SC03_118/ov_SC03_118_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D41A4; extern SV4 D_801D41AC; @@ -3083,7 +3083,7 @@ extern SV4 D_801D41AC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D41AC) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D41AC)) */ diff --git a/src/ov_SC03_119/ov_SC03_119_jr_8017AE2C.c b/src/ov_SC03_119/ov_SC03_119_jr_8017AE2C.c index 826f05aaec..f91e35ae24 100644 --- a/src/ov_SC03_119/ov_SC03_119_jr_8017AE2C.c +++ b/src/ov_SC03_119/ov_SC03_119_jr_8017AE2C.c @@ -3069,7 +3069,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D41A4; extern SV4 D_801D41AC; @@ -3077,7 +3077,7 @@ extern SV4 D_801D41AC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D41AC) */ @@ -3115,7 +3115,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D41AC)) */ diff --git a/src/ov_SC03_121/ov_SC03_121_jr_8017AE2C.c b/src/ov_SC03_121/ov_SC03_121_jr_8017AE2C.c index ab6ecb4f4d..b46a00fc8f 100644 --- a/src/ov_SC03_121/ov_SC03_121_jr_8017AE2C.c +++ b/src/ov_SC03_121/ov_SC03_121_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801AEC4C; extern SV4 D_801AEC54; @@ -3083,7 +3083,7 @@ extern SV4 D_801AEC54; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801AEC54) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801AEC54)) */ diff --git a/src/ov_SC03_121/ov_SC03_121_jr_8017BEBC.c b/src/ov_SC03_121/ov_SC03_121_jr_8017BEBC.c index 15d5ae39c0..ce0a71d004 100644 --- a/src/ov_SC03_121/ov_SC03_121_jr_8017BEBC.c +++ b/src/ov_SC03_121/ov_SC03_121_jr_8017BEBC.c @@ -3297,7 +3297,7 @@ INCLUDE_ASM("asm/ov_SC03_121/nonmatchings/ov_SC03_121_jr_8017BEBC", func_8017D49 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3310,7 +3310,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D4C4(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c b/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c index aba6cf438d..e7026ce61f 100644 --- a/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c +++ b/src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c @@ -3073,7 +3073,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E1774; extern SV4 D_801E177C; @@ -3081,7 +3081,7 @@ extern SV4 D_801E177C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E177C) */ @@ -3119,7 +3119,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E177C)) */ diff --git a/src/ov_SC03_125/ov_SC03_125_jr_8017AE2C.c b/src/ov_SC03_125/ov_SC03_125_jr_8017AE2C.c index bc1dafc718..096d3617f4 100644 --- a/src/ov_SC03_125/ov_SC03_125_jr_8017AE2C.c +++ b/src/ov_SC03_125/ov_SC03_125_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C406C; extern SV4 D_801C4074; @@ -3083,7 +3083,7 @@ extern SV4 D_801C4074; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C4074) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C4074)) */ diff --git a/src/ov_SC03_126/ov_SC03_126_jr_8017AE2C.c b/src/ov_SC03_126/ov_SC03_126_jr_8017AE2C.c index 32a064da9b..8bb682549b 100644 --- a/src/ov_SC03_126/ov_SC03_126_jr_8017AE2C.c +++ b/src/ov_SC03_126/ov_SC03_126_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8018F934; extern SV4 D_8018F93C; @@ -3083,7 +3083,7 @@ extern SV4 D_8018F93C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8018F93C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8018F93C)) */ diff --git a/src/ov_SC04_000/ov_SC04_000_jr_8017AE2C.c b/src/ov_SC04_000/ov_SC04_000_jr_8017AE2C.c index 8bab7d5f38..70a22dc55a 100644 --- a/src/ov_SC04_000/ov_SC04_000_jr_8017AE2C.c +++ b/src/ov_SC04_000/ov_SC04_000_jr_8017AE2C.c @@ -3073,7 +3073,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A99E4; extern SV4 D_801A99EC; @@ -3081,7 +3081,7 @@ extern SV4 D_801A99EC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A99EC) */ @@ -3119,7 +3119,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A99EC)) */ diff --git a/src/ov_SC04_002/ov_SC04_002_jr_8017AE2C.c b/src/ov_SC04_002/ov_SC04_002_jr_8017AE2C.c index 8f65951197..03afb7e93b 100644 --- a/src/ov_SC04_002/ov_SC04_002_jr_8017AE2C.c +++ b/src/ov_SC04_002/ov_SC04_002_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C0CF4; extern SV4 D_801C0CFC; @@ -3083,7 +3083,7 @@ extern SV4 D_801C0CFC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C0CFC) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C0CFC)) */ diff --git a/src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c b/src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c index 909e8f78f8..9732326da5 100644 --- a/src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c +++ b/src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c @@ -3439,7 +3439,7 @@ INCLUDE_ASM("asm/ov_SC04_002/nonmatchings/ov_SC04_002_jr_8017BEBC", func_8017FD3 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3452,7 +3452,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017FE28(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC04_003/ov_SC04_003_jr_8017AE2C.c b/src/ov_SC04_003/ov_SC04_003_jr_8017AE2C.c index edd3b2f673..c6d28f57ea 100644 --- a/src/ov_SC04_003/ov_SC04_003_jr_8017AE2C.c +++ b/src/ov_SC04_003/ov_SC04_003_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019B95C; extern SV4 D_8019B964; @@ -3083,7 +3083,7 @@ extern SV4 D_8019B964; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019B964) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019B964)) */ diff --git a/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c b/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c index 45a7ec06f2..c29d2979a5 100644 --- a/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c +++ b/src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c @@ -3251,7 +3251,7 @@ INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8017BEBC", func_8017D30 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3264,7 +3264,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D3A8(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c b/src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c index 1fd1acdab4..81a563b1ea 100644 --- a/src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c +++ b/src/ov_SC04_004/ov_SC04_004_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX_c1: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B375C; extern SV4 D_801B3764; @@ -3083,7 +3083,7 @@ extern SV4 D_801B3764; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B3764) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B3764)) */ @@ -3449,7 +3449,7 @@ INCLUDE_ASM("asm/ov_SC04_004/nonmatchings/ov_SC04_004_jr_8017AE2C", func_8017ECE // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3462,7 +3462,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017ED84(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC04_005/ov_SC04_005_jr_8017AE2C.c b/src/ov_SC04_005/ov_SC04_005_jr_8017AE2C.c index d94f7ec3ee..22ffaabbd1 100644 --- a/src/ov_SC04_005/ov_SC04_005_jr_8017AE2C.c +++ b/src/ov_SC04_005/ov_SC04_005_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C1934; extern SV4 D_801C193C; @@ -3083,7 +3083,7 @@ extern SV4 D_801C193C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C193C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C193C)) */ diff --git a/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c b/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c index 24f258cd44..cc1d7e50b8 100644 --- a/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c +++ b/src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c @@ -3365,7 +3365,7 @@ INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_8017EFA // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3378,7 +3378,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017F048(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC04_006/ov_SC04_006_jr_8017AE2C.c b/src/ov_SC04_006/ov_SC04_006_jr_8017AE2C.c index d4c4040773..64afe73b9a 100644 --- a/src/ov_SC04_006/ov_SC04_006_jr_8017AE2C.c +++ b/src/ov_SC04_006/ov_SC04_006_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019DBDC; extern SV4 D_8019DBE4; @@ -3083,7 +3083,7 @@ extern SV4 D_8019DBE4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019DBE4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019DBE4)) */ diff --git a/src/ov_SC04_007/ov_SC04_007_jr_8017AE2C.c b/src/ov_SC04_007/ov_SC04_007_jr_8017AE2C.c index d1471d90a5..227a84558e 100644 --- a/src/ov_SC04_007/ov_SC04_007_jr_8017AE2C.c +++ b/src/ov_SC04_007/ov_SC04_007_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B5194; extern SV4 D_801B519C; @@ -3083,7 +3083,7 @@ extern SV4 D_801B519C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B519C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B519C)) */ diff --git a/src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c b/src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c index c899a7d0fb..bea07531a3 100644 --- a/src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c +++ b/src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c @@ -3339,7 +3339,7 @@ INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_8017EC8 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3352,7 +3352,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017ED2C(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC04_008/ov_SC04_008_jr_8017AE2C.c b/src/ov_SC04_008/ov_SC04_008_jr_8017AE2C.c index b6f330aa80..9898e77579 100644 --- a/src/ov_SC04_008/ov_SC04_008_jr_8017AE2C.c +++ b/src/ov_SC04_008/ov_SC04_008_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX_c1: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_80191E6C; extern SV4 D_80191E74; @@ -3083,7 +3083,7 @@ extern SV4 D_80191E74; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80191E74) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80191E74)) */ @@ -3351,7 +3351,7 @@ INCLUDE_ASM("asm/ov_SC04_008/nonmatchings/ov_SC04_008_jr_8017AE2C", func_8017D16 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3364,7 +3364,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D210(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC04_009/ov_SC04_009_jr_8017AE2C.c b/src/ov_SC04_009/ov_SC04_009_jr_8017AE2C.c index f8ce7c2d44..3619280fd9 100644 --- a/src/ov_SC04_009/ov_SC04_009_jr_8017AE2C.c +++ b/src/ov_SC04_009/ov_SC04_009_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019807C; extern SV4 D_80198084; @@ -3083,7 +3083,7 @@ extern SV4 D_80198084; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80198084) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80198084)) */ diff --git a/src/ov_SC04_009/ov_SC04_009_jr_8017BEBC.c b/src/ov_SC04_009/ov_SC04_009_jr_8017BEBC.c index eb1725212b..c9b92bdb1b 100644 --- a/src/ov_SC04_009/ov_SC04_009_jr_8017BEBC.c +++ b/src/ov_SC04_009/ov_SC04_009_jr_8017BEBC.c @@ -3253,7 +3253,7 @@ INCLUDE_ASM("asm/ov_SC04_009/nonmatchings/ov_SC04_009_jr_8017BEBC", func_8017D1A // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3266,7 +3266,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D288(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC04_010/ov_SC04_010_jr_8017AE2C.c b/src/ov_SC04_010/ov_SC04_010_jr_8017AE2C.c index b99af79d6c..5ac87add21 100644 --- a/src/ov_SC04_010/ov_SC04_010_jr_8017AE2C.c +++ b/src/ov_SC04_010/ov_SC04_010_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8018F514; extern SV4 D_8018F51C; @@ -3083,7 +3083,7 @@ extern SV4 D_8018F51C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8018F51C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8018F51C)) */ diff --git a/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.c b/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.c index 5d0df20c77..63df225d8c 100644 --- a/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.c +++ b/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801EEC7C; extern SV4 D_801EEC84; @@ -3083,7 +3083,7 @@ extern SV4 D_801EEC84; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EEC84) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EEC84)) */ diff --git a/src/ov_SC04_012/ov_SC04_012_jr_8017AE2C.c b/src/ov_SC04_012/ov_SC04_012_jr_8017AE2C.c index 0df47fc4ee..b4a06bfa4c 100644 --- a/src/ov_SC04_012/ov_SC04_012_jr_8017AE2C.c +++ b/src/ov_SC04_012/ov_SC04_012_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX_c1: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_80191BEC; extern SV4 D_80191BF4; @@ -3083,7 +3083,7 @@ extern SV4 D_80191BF4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80191BF4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80191BF4)) */ @@ -3364,7 +3364,7 @@ INCLUDE_ASM("asm/ov_SC04_012/nonmatchings/ov_SC04_012_jr_8017AE2C", func_8017D19 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3377,7 +3377,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D248(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c b/src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c index 63da57a3db..6559d607d6 100644 --- a/src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c +++ b/src/ov_SC04_015/ov_SC04_015_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C88D4; extern SV4 D_801C88DC; @@ -3083,7 +3083,7 @@ extern SV4 D_801C88DC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C88DC) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C88DC)) */ diff --git a/src/ov_SC04_016/ov_SC04_016_jr_8017AE2C.c b/src/ov_SC04_016/ov_SC04_016_jr_8017AE2C.c index ed040558b2..fdac3377f3 100644 --- a/src/ov_SC04_016/ov_SC04_016_jr_8017AE2C.c +++ b/src/ov_SC04_016/ov_SC04_016_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A6A7C; extern SV4 D_801A6A84; @@ -3083,7 +3083,7 @@ extern SV4 D_801A6A84; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A6A84) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A6A84)) */ diff --git a/src/ov_SC04_018/ov_SC04_018_jr_8017AE2C.c b/src/ov_SC04_018/ov_SC04_018_jr_8017AE2C.c index d8f9d9d7a7..fbb72ca435 100644 --- a/src/ov_SC04_018/ov_SC04_018_jr_8017AE2C.c +++ b/src/ov_SC04_018/ov_SC04_018_jr_8017AE2C.c @@ -3073,7 +3073,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E6CCC; extern SV4 D_801E6CD4; @@ -3081,7 +3081,7 @@ extern SV4 D_801E6CD4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E6CD4) */ @@ -3119,7 +3119,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E6CD4)) */ diff --git a/src/ov_SC04_019/ov_SC04_019_jr_8017AE2C.c b/src/ov_SC04_019/ov_SC04_019_jr_8017AE2C.c index 589a18682a..d1fc80293d 100644 --- a/src/ov_SC04_019/ov_SC04_019_jr_8017AE2C.c +++ b/src/ov_SC04_019/ov_SC04_019_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E6CCC; extern SV4 D_801E6CD4; @@ -3083,7 +3083,7 @@ extern SV4 D_801E6CD4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E6CD4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E6CD4)) */ diff --git a/src/ov_SC04_020/ov_SC04_020_jr_8017AE2C.c b/src/ov_SC04_020/ov_SC04_020_jr_8017AE2C.c index d2b53c1259..3184c34c4b 100644 --- a/src/ov_SC04_020/ov_SC04_020_jr_8017AE2C.c +++ b/src/ov_SC04_020/ov_SC04_020_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801BC2DC; extern SV4 D_801BC2E4; @@ -3083,7 +3083,7 @@ extern SV4 D_801BC2E4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801BC2E4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801BC2E4)) */ diff --git a/src/ov_SC04_021/ov_SC04_021_jr_8017AE2C.c b/src/ov_SC04_021/ov_SC04_021_jr_8017AE2C.c index 470a3d9ce3..da1ac8ea1f 100644 --- a/src/ov_SC04_021/ov_SC04_021_jr_8017AE2C.c +++ b/src/ov_SC04_021/ov_SC04_021_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8018F934; extern SV4 D_8018F93C; @@ -3083,7 +3083,7 @@ extern SV4 D_8018F93C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8018F93C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8018F93C)) */ diff --git a/src/ov_SC05_000/ov_SC05_000_jr_8017AE2C.c b/src/ov_SC05_000/ov_SC05_000_jr_8017AE2C.c index 415d48ac84..2e431beea9 100644 --- a/src/ov_SC05_000/ov_SC05_000_jr_8017AE2C.c +++ b/src/ov_SC05_000/ov_SC05_000_jr_8017AE2C.c @@ -3073,7 +3073,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019AA64; extern SV4 D_8019AA6C; @@ -3081,7 +3081,7 @@ extern SV4 D_8019AA6C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019AA6C) */ @@ -3119,7 +3119,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019AA6C)) */ diff --git a/src/ov_SC05_000/ov_SC05_000_jr_8017BEBC.c b/src/ov_SC05_000/ov_SC05_000_jr_8017BEBC.c index 0e7811091e..151ed808e5 100644 --- a/src/ov_SC05_000/ov_SC05_000_jr_8017BEBC.c +++ b/src/ov_SC05_000/ov_SC05_000_jr_8017BEBC.c @@ -3275,7 +3275,7 @@ INCLUDE_ASM("asm/ov_SC05_000/nonmatchings/ov_SC05_000_jr_8017BEBC", func_8017D4A // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3288,7 +3288,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D538(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC05_001/ov_SC05_001_jr_8017AE2C.c b/src/ov_SC05_001/ov_SC05_001_jr_8017AE2C.c index fa29b5bcbc..055f87e589 100644 --- a/src/ov_SC05_001/ov_SC05_001_jr_8017AE2C.c +++ b/src/ov_SC05_001/ov_SC05_001_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B5B24; extern SV4 D_801B5B2C; @@ -3083,7 +3083,7 @@ extern SV4 D_801B5B2C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B5B2C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B5B2C)) */ diff --git a/src/ov_SC05_002/ov_SC05_002_jr_8017AE2C.c b/src/ov_SC05_002/ov_SC05_002_jr_8017AE2C.c index e6c4155778..da51c5bdc6 100644 --- a/src/ov_SC05_002/ov_SC05_002_jr_8017AE2C.c +++ b/src/ov_SC05_002/ov_SC05_002_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019FDC4; extern SV4 D_8019FDCC; @@ -3083,7 +3083,7 @@ extern SV4 D_8019FDCC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019FDCC) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019FDCC)) */ diff --git a/src/ov_SC05_002/ov_SC05_002_jr_8017BEBC.c b/src/ov_SC05_002/ov_SC05_002_jr_8017BEBC.c index 00647baa49..dcf127197e 100644 --- a/src/ov_SC05_002/ov_SC05_002_jr_8017BEBC.c +++ b/src/ov_SC05_002/ov_SC05_002_jr_8017BEBC.c @@ -3350,7 +3350,7 @@ INCLUDE_ASM("asm/ov_SC05_002/nonmatchings/ov_SC05_002_jr_8017BEBC", func_8017E1D // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3363,7 +3363,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017E27C(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC05_003/ov_SC05_003_jr_8017AE2C.c b/src/ov_SC05_003/ov_SC05_003_jr_8017AE2C.c index 21373b4371..303246541e 100644 --- a/src/ov_SC05_003/ov_SC05_003_jr_8017AE2C.c +++ b/src/ov_SC05_003/ov_SC05_003_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801AC8D4; extern SV4 D_801AC8DC; @@ -3083,7 +3083,7 @@ extern SV4 D_801AC8DC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801AC8DC) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801AC8DC)) */ diff --git a/src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c b/src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c index 4dfe43ac82..b428c1fb34 100644 --- a/src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c +++ b/src/ov_SC05_003/ov_SC05_003_jr_8017BEBC.c @@ -3338,7 +3338,7 @@ INCLUDE_ASM("asm/ov_SC05_003/nonmatchings/ov_SC05_003_jr_8017BEBC", func_8017E13 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3351,7 +3351,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017E1E8(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC05_004/ov_SC05_004_jr_8017AE2C.c b/src/ov_SC05_004/ov_SC05_004_jr_8017AE2C.c index aef40b2fb8..c3880c138b 100644 --- a/src/ov_SC05_004/ov_SC05_004_jr_8017AE2C.c +++ b/src/ov_SC05_004/ov_SC05_004_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019EF4C; extern SV4 D_8019EF54; @@ -3083,7 +3083,7 @@ extern SV4 D_8019EF54; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019EF54) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019EF54)) */ diff --git a/src/ov_SC05_004/ov_SC05_004_jr_8017BEBC.c b/src/ov_SC05_004/ov_SC05_004_jr_8017BEBC.c index 23ede591f5..135171896d 100644 --- a/src/ov_SC05_004/ov_SC05_004_jr_8017BEBC.c +++ b/src/ov_SC05_004/ov_SC05_004_jr_8017BEBC.c @@ -3289,7 +3289,7 @@ INCLUDE_ASM("asm/ov_SC05_004/nonmatchings/ov_SC05_004_jr_8017BEBC", func_8017E3A // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3302,7 +3302,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017E440(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC05_005/ov_SC05_005_jr_8017AE2C.c b/src/ov_SC05_005/ov_SC05_005_jr_8017AE2C.c index de8dafdd2c..bc316bec16 100644 --- a/src/ov_SC05_005/ov_SC05_005_jr_8017AE2C.c +++ b/src/ov_SC05_005/ov_SC05_005_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B1BB4; extern SV4 D_801B1BBC; @@ -3083,7 +3083,7 @@ extern SV4 D_801B1BBC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B1BBC) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B1BBC)) */ diff --git a/src/ov_SC05_006/ov_SC05_006_jr_8017AE2C.c b/src/ov_SC05_006/ov_SC05_006_jr_8017AE2C.c index 2e9aac038f..ca3aa6fc66 100644 --- a/src/ov_SC05_006/ov_SC05_006_jr_8017AE2C.c +++ b/src/ov_SC05_006/ov_SC05_006_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8018FCEC; extern SV4 D_8018FCF4; @@ -3083,7 +3083,7 @@ extern SV4 D_8018FCF4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8018FCF4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8018FCF4)) */ diff --git a/src/ov_SC05_006/ov_SC05_006_jr_8017BEBC.c b/src/ov_SC05_006/ov_SC05_006_jr_8017BEBC.c index 54fb1a6e7f..35a6509bb9 100644 --- a/src/ov_SC05_006/ov_SC05_006_jr_8017BEBC.c +++ b/src/ov_SC05_006/ov_SC05_006_jr_8017BEBC.c @@ -3347,7 +3347,7 @@ INCLUDE_ASM("asm/ov_SC05_006/nonmatchings/ov_SC05_006_jr_8017BEBC", func_8017EB7 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3360,7 +3360,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017EC74(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC05_007/ov_SC05_007_jr_8017AE2C.c b/src/ov_SC05_007/ov_SC05_007_jr_8017AE2C.c index 8bf47ea821..b59ff88568 100644 --- a/src/ov_SC05_007/ov_SC05_007_jr_8017AE2C.c +++ b/src/ov_SC05_007/ov_SC05_007_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019CCCC; extern SV4 D_8019CCD4; @@ -3083,7 +3083,7 @@ extern SV4 D_8019CCD4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019CCD4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019CCD4)) */ diff --git a/src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c b/src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c index 939e5f485f..5727706a40 100644 --- a/src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c +++ b/src/ov_SC05_007/ov_SC05_007_jr_8017BEBC.c @@ -3251,7 +3251,7 @@ INCLUDE_ASM("asm/ov_SC05_007/nonmatchings/ov_SC05_007_jr_8017BEBC", func_8017D13 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3264,7 +3264,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D1E8(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC05_008/ov_SC05_008_jr_8017AE2C.c b/src/ov_SC05_008/ov_SC05_008_jr_8017AE2C.c index 74702a5ac6..869fb3d185 100644 --- a/src/ov_SC05_008/ov_SC05_008_jr_8017AE2C.c +++ b/src/ov_SC05_008/ov_SC05_008_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX_c1: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A0FFC; extern SV4 D_801A1004; @@ -3083,7 +3083,7 @@ extern SV4 D_801A1004; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A1004) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A1004)) */ @@ -3372,7 +3372,7 @@ INCLUDE_ASM("asm/ov_SC05_008/nonmatchings/ov_SC05_008_jr_8017AE2C", func_8017D90 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3385,7 +3385,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017DAB8(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC05_009/ov_SC05_009_jr_8017AE2C.c b/src/ov_SC05_009/ov_SC05_009_jr_8017AE2C.c index 1430bef330..c57f56be16 100644 --- a/src/ov_SC05_009/ov_SC05_009_jr_8017AE2C.c +++ b/src/ov_SC05_009/ov_SC05_009_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_80196A0C; extern SV4 D_80196A14; @@ -3083,7 +3083,7 @@ extern SV4 D_80196A14; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80196A14) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80196A14)) */ diff --git a/src/ov_SC05_009/ov_SC05_009_jr_8017BEBC.c b/src/ov_SC05_009/ov_SC05_009_jr_8017BEBC.c index 740b4d7e6f..300d89eadf 100644 --- a/src/ov_SC05_009/ov_SC05_009_jr_8017BEBC.c +++ b/src/ov_SC05_009/ov_SC05_009_jr_8017BEBC.c @@ -3269,7 +3269,7 @@ INCLUDE_ASM("asm/ov_SC05_009/nonmatchings/ov_SC05_009_jr_8017BEBC", func_8017D2F // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3282,7 +3282,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D340(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC05_010/ov_SC05_010_jr_8017AE2C.c b/src/ov_SC05_010/ov_SC05_010_jr_8017AE2C.c index 0ce64b4d5f..5dd7627aa6 100644 --- a/src/ov_SC05_010/ov_SC05_010_jr_8017AE2C.c +++ b/src/ov_SC05_010/ov_SC05_010_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801C6E5C; extern SV4 D_801C6E64; @@ -3083,7 +3083,7 @@ extern SV4 D_801C6E64; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C6E64) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C6E64)) */ diff --git a/src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.c b/src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.c index 0b0d2fed69..a85a8318e7 100644 --- a/src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.c +++ b/src/ov_SC05_010/ov_SC05_010_jr_8017C8D0.c @@ -3319,7 +3319,7 @@ INCLUDE_ASM("asm/ov_SC05_010/nonmatchings/ov_SC05_010_jr_8017C8D0", func_8017EAB // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3332,7 +3332,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017EAE4(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC05_011/ov_SC05_011_jr_8017AE2C.c b/src/ov_SC05_011/ov_SC05_011_jr_8017AE2C.c index 92f3abb9ec..8b26cde4b3 100644 --- a/src/ov_SC05_011/ov_SC05_011_jr_8017AE2C.c +++ b/src/ov_SC05_011/ov_SC05_011_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019CFE4; extern SV4 D_8019CFEC; @@ -3083,7 +3083,7 @@ extern SV4 D_8019CFEC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019CFEC) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019CFEC)) */ diff --git a/src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.c b/src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.c index e10064d760..241c8b4292 100644 --- a/src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.c +++ b/src/ov_SC05_017/ov_SC05_017_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801ECB24; extern SV4 D_801ECB2C; @@ -3083,7 +3083,7 @@ extern SV4 D_801ECB2C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801ECB2C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801ECB2C)) */ diff --git a/src/ov_SC05_018/ov_SC05_018_jr_8017AE2C.c b/src/ov_SC05_018/ov_SC05_018_jr_8017AE2C.c index a561c49a7a..20b9ec6b44 100644 --- a/src/ov_SC05_018/ov_SC05_018_jr_8017AE2C.c +++ b/src/ov_SC05_018/ov_SC05_018_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E6264; extern SV4 D_801E626C; @@ -3083,7 +3083,7 @@ extern SV4 D_801E626C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E626C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E626C)) */ diff --git a/src/ov_SC05_019/ov_SC05_019_jr_8017AE2C.c b/src/ov_SC05_019/ov_SC05_019_jr_8017AE2C.c index b337fce042..e3fc1fa1bf 100644 --- a/src/ov_SC05_019/ov_SC05_019_jr_8017AE2C.c +++ b/src/ov_SC05_019/ov_SC05_019_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8018F934; extern SV4 D_8018F93C; @@ -3083,7 +3083,7 @@ extern SV4 D_8018F93C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8018F93C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8018F93C)) */ diff --git a/src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c b/src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c index 18ac179c4c..e90dbe40ca 100644 --- a/src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c +++ b/src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801AE5A4; extern SV4 D_801AE5AC; @@ -3083,7 +3083,7 @@ extern SV4 D_801AE5AC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801AE5AC) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801AE5AC)) */ diff --git a/src/ov_SC06_006/ov_SC06_006_jr_8017AE2C.c b/src/ov_SC06_006/ov_SC06_006_jr_8017AE2C.c index 8ebd542cab..ad09941e15 100644 --- a/src/ov_SC06_006/ov_SC06_006_jr_8017AE2C.c +++ b/src/ov_SC06_006/ov_SC06_006_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801F7FEC; extern SV4 D_801F7FF4; @@ -3083,7 +3083,7 @@ extern SV4 D_801F7FF4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801F7FF4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801F7FF4)) */ diff --git a/src/ov_SC06_008/ov_SC06_008_jr_8017AE2C.c b/src/ov_SC06_008/ov_SC06_008_jr_8017AE2C.c index 9de2df3ab0..1c3443bc66 100644 --- a/src/ov_SC06_008/ov_SC06_008_jr_8017AE2C.c +++ b/src/ov_SC06_008/ov_SC06_008_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A9F6C; extern SV4 D_801A9F74; @@ -3083,7 +3083,7 @@ extern SV4 D_801A9F74; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A9F74) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A9F74)) */ diff --git a/src/ov_SC06_008/ov_SC06_008_jr_8017C294.c b/src/ov_SC06_008/ov_SC06_008_jr_8017C294.c index de2b1176e8..049150f0db 100644 --- a/src/ov_SC06_008/ov_SC06_008_jr_8017C294.c +++ b/src/ov_SC06_008/ov_SC06_008_jr_8017C294.c @@ -3263,7 +3263,7 @@ INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_jr_8017C294", func_8017D52 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3276,7 +3276,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D5A4(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c b/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c index df323d663e..c61dc382b9 100644 --- a/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c +++ b/src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c @@ -3144,7 +3144,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX_c1: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B1FA4; extern SV4 D_801B1FAC; @@ -3152,7 +3152,7 @@ extern SV4 D_801B1FAC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B1FAC) */ @@ -3190,7 +3190,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B1FAC)) */ @@ -3522,7 +3522,7 @@ INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_jr_8017A4AC", func_8017E54 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3535,7 +3535,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017E5CC(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_011/ov_SC06_011_jr_8017AE2C.c b/src/ov_SC06_011/ov_SC06_011_jr_8017AE2C.c index d00cd1edd8..f2bf192347 100644 --- a/src/ov_SC06_011/ov_SC06_011_jr_8017AE2C.c +++ b/src/ov_SC06_011/ov_SC06_011_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801ABB54; extern SV4 D_801ABB5C; @@ -3083,7 +3083,7 @@ extern SV4 D_801ABB5C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801ABB5C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801ABB5C)) */ diff --git a/src/ov_SC06_011/ov_SC06_011_jr_8017BEBC.c b/src/ov_SC06_011/ov_SC06_011_jr_8017BEBC.c index 362f7edfbf..d2f9ee4d91 100644 --- a/src/ov_SC06_011/ov_SC06_011_jr_8017BEBC.c +++ b/src/ov_SC06_011/ov_SC06_011_jr_8017BEBC.c @@ -3289,7 +3289,7 @@ INCLUDE_ASM("asm/ov_SC06_011/nonmatchings/ov_SC06_011_jr_8017BEBC", func_8017D85 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3302,7 +3302,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D8F0(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_013/ov_SC06_013_jr_8017AE2C.c b/src/ov_SC06_013/ov_SC06_013_jr_8017AE2C.c index 349e258611..b7b5dcdcc4 100644 --- a/src/ov_SC06_013/ov_SC06_013_jr_8017AE2C.c +++ b/src/ov_SC06_013/ov_SC06_013_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019AA0C; extern SV4 D_8019AA14; @@ -3083,7 +3083,7 @@ extern SV4 D_8019AA14; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019AA14) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019AA14)) */ diff --git a/src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c b/src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c index 05c4ec16d1..81afd4d32c 100644 --- a/src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c +++ b/src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c @@ -3253,7 +3253,7 @@ INCLUDE_ASM("asm/ov_SC06_013/nonmatchings/ov_SC06_013_jr_8017BEBC", func_8017D2F // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3266,7 +3266,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D39C(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_014/ov_SC06_014_jr_8017AE2C.c b/src/ov_SC06_014/ov_SC06_014_jr_8017AE2C.c index 6faaa258e0..c6d65f13c3 100644 --- a/src/ov_SC06_014/ov_SC06_014_jr_8017AE2C.c +++ b/src/ov_SC06_014/ov_SC06_014_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A13FC; extern SV4 D_801A1404; @@ -3083,7 +3083,7 @@ extern SV4 D_801A1404; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A1404) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A1404)) */ diff --git a/src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c b/src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c index d06eb4af5b..85dd305b51 100644 --- a/src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c +++ b/src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c @@ -3346,7 +3346,7 @@ INCLUDE_ASM("asm/ov_SC06_014/nonmatchings/ov_SC06_014_jr_8017BEBC", func_8017D6D // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3359,7 +3359,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D774(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_015/ov_SC06_015_jr_8017AE2C.c b/src/ov_SC06_015/ov_SC06_015_jr_8017AE2C.c index 5815ce95e1..c2c2980ee9 100644 --- a/src/ov_SC06_015/ov_SC06_015_jr_8017AE2C.c +++ b/src/ov_SC06_015/ov_SC06_015_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801947DC; extern SV4 D_801947E4; @@ -3083,7 +3083,7 @@ extern SV4 D_801947E4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801947E4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801947E4)) */ diff --git a/src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c b/src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c index ecd656f194..41d06c86e0 100644 --- a/src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c +++ b/src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c @@ -3348,7 +3348,7 @@ INCLUDE_ASM("asm/ov_SC06_015/nonmatchings/ov_SC06_015_jr_8017BEBC", func_8017D59 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3361,7 +3361,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D630(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_016/ov_SC06_016_jr_8017AE2C.c b/src/ov_SC06_016/ov_SC06_016_jr_8017AE2C.c index d90a37b559..971fa5adee 100644 --- a/src/ov_SC06_016/ov_SC06_016_jr_8017AE2C.c +++ b/src/ov_SC06_016/ov_SC06_016_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019F5AC; extern SV4 D_8019F5B4; @@ -3083,7 +3083,7 @@ extern SV4 D_8019F5B4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019F5B4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019F5B4)) */ diff --git a/src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c b/src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c index afdeb73c39..ed512505ff 100644 --- a/src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c +++ b/src/ov_SC06_016/ov_SC06_016_jr_8017C8D0.c @@ -3273,7 +3273,7 @@ INCLUDE_ASM("asm/ov_SC06_016/nonmatchings/ov_SC06_016_jr_8017C8D0", func_8017DC3 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3286,7 +3286,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017DD14(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_018/ov_SC06_018_jr_801734BC.c b/src/ov_SC06_018/ov_SC06_018_jr_801734BC.c index 997779a854..d432da6535 100644 --- a/src/ov_SC06_018/ov_SC06_018_jr_801734BC.c +++ b/src/ov_SC06_018/ov_SC06_018_jr_801734BC.c @@ -2596,7 +2596,7 @@ DEFINE_func_801749A8() /* dedup: shared engine-core @0x801749A8 (src/shared) */ // with czr a SEPARATE temp (reusing one var costs 5 more mismatches). // * LUID dial (§49/§50-A): materializing `t28 = *(s16*)(param_1+0x28)` BEFORE `cx = ...` // moves the 0x28 load ahead of the D_80126B5E lui/lh in the expand stream — the last 3. -// * frame: MATRIX at sp+0x10 (t[] at sp+0x24), SVECTOR in at sp+0x30, SVECTOR out at sp+0x38; +// * frame: MATRIX_L48 at sp+0x10 (t[] at sp+0x24), SVECTOR in at sp+0x30, SVECTOR out at sp+0x38; // locals are laid out in DECLARATION order. // * canonical sigs kept (func_8012F14C is `void(s32)` in the TU) -> cast at the call site. diff --git a/src/ov_SC06_018/ov_SC06_018_jr_8017AE2C.c b/src/ov_SC06_018/ov_SC06_018_jr_8017AE2C.c index f81c817fad..67cc6b7b9e 100644 --- a/src/ov_SC06_018/ov_SC06_018_jr_8017AE2C.c +++ b/src/ov_SC06_018/ov_SC06_018_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D4E94; extern SV4 D_801D4E9C; @@ -3083,7 +3083,7 @@ extern SV4 D_801D4E9C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D4E9C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D4E9C)) */ diff --git a/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c b/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c index 77d47d91c4..677d9126e3 100644 --- a/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c +++ b/src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c @@ -3262,7 +3262,7 @@ void func_8017D4A0(void *a0) { INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_jr_8017C24C", func_8017D4DC); // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3275,7 +3275,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D648(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_020/ov_SC06_020_jr_8017AE2C.c b/src/ov_SC06_020/ov_SC06_020_jr_8017AE2C.c index 5e162f863e..2160cd4191 100644 --- a/src/ov_SC06_020/ov_SC06_020_jr_8017AE2C.c +++ b/src/ov_SC06_020/ov_SC06_020_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801BA6AC; extern SV4 D_801BA6B4; @@ -3083,7 +3083,7 @@ extern SV4 D_801BA6B4; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801BA6B4) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801BA6B4)) */ diff --git a/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c b/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c index cac6621bab..74968ff551 100644 --- a/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c +++ b/src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c @@ -3254,7 +3254,7 @@ INCLUDE_ASM("asm/ov_SC06_020/nonmatchings/ov_SC06_020_jr_8017C24C", func_8017D4A // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3267,7 +3267,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D558(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_022/ov_SC06_022_jr_8017AE2C.c b/src/ov_SC06_022/ov_SC06_022_jr_8017AE2C.c index 0ff8745e04..2d73345a11 100644 --- a/src/ov_SC06_022/ov_SC06_022_jr_8017AE2C.c +++ b/src/ov_SC06_022/ov_SC06_022_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E1F14; extern SV4 D_801E1F1C; @@ -3083,7 +3083,7 @@ extern SV4 D_801E1F1C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E1F1C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E1F1C)) */ diff --git a/src/ov_SC06_022/ov_SC06_022_jr_8017BEBC.c b/src/ov_SC06_022/ov_SC06_022_jr_8017BEBC.c index 8828d18866..47d4a823a1 100644 --- a/src/ov_SC06_022/ov_SC06_022_jr_8017BEBC.c +++ b/src/ov_SC06_022/ov_SC06_022_jr_8017BEBC.c @@ -3290,7 +3290,7 @@ INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_jr_8017BEBC", func_8017D8D // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3303,7 +3303,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D9C0(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_024/ov_SC06_024_jr_8017AE2C.c b/src/ov_SC06_024/ov_SC06_024_jr_8017AE2C.c index 2c071b0202..ad4838bdae 100644 --- a/src/ov_SC06_024/ov_SC06_024_jr_8017AE2C.c +++ b/src/ov_SC06_024/ov_SC06_024_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801E1094; extern SV4 D_801E109C; @@ -3083,7 +3083,7 @@ extern SV4 D_801E109C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E109C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E109C)) */ diff --git a/src/ov_SC06_024/ov_SC06_024_jr_8017BEBC.c b/src/ov_SC06_024/ov_SC06_024_jr_8017BEBC.c index d8ebfb6304..089f735d0d 100644 --- a/src/ov_SC06_024/ov_SC06_024_jr_8017BEBC.c +++ b/src/ov_SC06_024/ov_SC06_024_jr_8017BEBC.c @@ -3281,7 +3281,7 @@ INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_jr_8017BEBC", func_8017D55 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3294,7 +3294,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D63C(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_025/ov_SC06_025_jr_8017AE2C.c b/src/ov_SC06_025/ov_SC06_025_jr_8017AE2C.c index d9493ac6a6..d19afe1176 100644 --- a/src/ov_SC06_025/ov_SC06_025_jr_8017AE2C.c +++ b/src/ov_SC06_025/ov_SC06_025_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B125C; extern SV4 D_801B1264; @@ -3083,7 +3083,7 @@ extern SV4 D_801B1264; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B1264) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B1264)) */ diff --git a/src/ov_SC06_025/ov_SC06_025_jr_8017BEBC.c b/src/ov_SC06_025/ov_SC06_025_jr_8017BEBC.c index 017bfcffd9..972c4da04f 100644 --- a/src/ov_SC06_025/ov_SC06_025_jr_8017BEBC.c +++ b/src/ov_SC06_025/ov_SC06_025_jr_8017BEBC.c @@ -3293,7 +3293,7 @@ INCLUDE_ASM("asm/ov_SC06_025/nonmatchings/ov_SC06_025_jr_8017BEBC", func_8017D65 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3306,7 +3306,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D730(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_027/ov_SC06_027_jr_8017AE2C.c b/src/ov_SC06_027/ov_SC06_027_jr_8017AE2C.c index 29a62186a7..e22ea283bf 100644 --- a/src/ov_SC06_027/ov_SC06_027_jr_8017AE2C.c +++ b/src/ov_SC06_027/ov_SC06_027_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019D234; extern SV4 D_8019D23C; @@ -3083,7 +3083,7 @@ extern SV4 D_8019D23C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019D23C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019D23C)) */ diff --git a/src/ov_SC06_029/ov_SC06_029_jr_8017AE2C.c b/src/ov_SC06_029/ov_SC06_029_jr_8017AE2C.c index 0c0d520da5..57761f3590 100644 --- a/src/ov_SC06_029/ov_SC06_029_jr_8017AE2C.c +++ b/src/ov_SC06_029/ov_SC06_029_jr_8017AE2C.c @@ -3069,7 +3069,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801DCB54; extern SV4 D_801DCB5C; @@ -3077,7 +3077,7 @@ extern SV4 D_801DCB5C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801DCB5C) */ @@ -3115,7 +3115,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801DCB5C)) */ diff --git a/src/ov_SC06_030/ov_SC06_030_jr_8017AE2C.c b/src/ov_SC06_030/ov_SC06_030_jr_8017AE2C.c index 35feb4d7be..9835da9a22 100644 --- a/src/ov_SC06_030/ov_SC06_030_jr_8017AE2C.c +++ b/src/ov_SC06_030/ov_SC06_030_jr_8017AE2C.c @@ -3069,7 +3069,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801B9DB4; extern SV4 D_801B9DBC; @@ -3077,7 +3077,7 @@ extern SV4 D_801B9DBC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B9DBC) */ @@ -3115,7 +3115,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B9DBC)) */ diff --git a/src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.c b/src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.c index 09be253bf0..4a0a0e983e 100644 --- a/src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.c +++ b/src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.c @@ -3251,7 +3251,7 @@ INCLUDE_ASM("asm/ov_SC06_030/nonmatchings/ov_SC06_030_jr_8017C8D0", func_8017DB9 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3264,7 +3264,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017DC70(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_032/ov_SC06_032_jr_8017AE2C.c b/src/ov_SC06_032/ov_SC06_032_jr_8017AE2C.c index 88166ea6c5..35398ab303 100644 --- a/src/ov_SC06_032/ov_SC06_032_jr_8017AE2C.c +++ b/src/ov_SC06_032/ov_SC06_032_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D0464; extern SV4 D_801D046C; @@ -3083,7 +3083,7 @@ extern SV4 D_801D046C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D046C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D046C)) */ diff --git a/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c b/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c index 7c8db1ba10..675386c094 100644 --- a/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c +++ b/src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c @@ -3248,7 +3248,7 @@ INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_jr_8017C24C", func_8017D4A // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3261,7 +3261,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D5E4(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC06_033/ov_SC06_033_jr_8017AE2C.c b/src/ov_SC06_033/ov_SC06_033_jr_8017AE2C.c index 9a216a0339..748bca3607 100644 --- a/src/ov_SC06_033/ov_SC06_033_jr_8017AE2C.c +++ b/src/ov_SC06_033/ov_SC06_033_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801D0524; extern SV4 D_801D052C; @@ -3083,7 +3083,7 @@ extern SV4 D_801D052C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D052C) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D052C)) */ diff --git a/src/ov_SC06_033/ov_SC06_033_jr_8017C24C.c b/src/ov_SC06_033/ov_SC06_033_jr_8017C24C.c index f5fe2e8775..f8ce8599da 100644 --- a/src/ov_SC06_033/ov_SC06_033_jr_8017C24C.c +++ b/src/ov_SC06_033/ov_SC06_033_jr_8017C24C.c @@ -3274,7 +3274,7 @@ INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_jr_8017C24C", func_8017D7E // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3287,7 +3287,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017DA78(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC07_000/ov_SC07_000_jr_8017AE2C.c b/src/ov_SC07_000/ov_SC07_000_jr_8017AE2C.c index 392e1c3e87..dd0de63cb2 100644 --- a/src/ov_SC07_000/ov_SC07_000_jr_8017AE2C.c +++ b/src/ov_SC07_000/ov_SC07_000_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801CFA6C; extern SV4 D_801CFA74; @@ -3083,7 +3083,7 @@ extern SV4 D_801CFA74; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CFA74) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CFA74)) */ diff --git a/src/ov_SC07_000/ov_SC07_000_jr_8017BEBC.c b/src/ov_SC07_000/ov_SC07_000_jr_8017BEBC.c index 340843fea7..7f53794234 100644 --- a/src/ov_SC07_000/ov_SC07_000_jr_8017BEBC.c +++ b/src/ov_SC07_000/ov_SC07_000_jr_8017BEBC.c @@ -3235,7 +3235,7 @@ INCLUDE_ASM("asm/ov_SC07_000/nonmatchings/ov_SC07_000_jr_8017BEBC", func_8017DBA // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3248,7 +3248,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017DC68(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC07_001/ov_SC07_001_jr_8017AE2C.c b/src/ov_SC07_001/ov_SC07_001_jr_8017AE2C.c index 1b0892d446..2bc708c277 100644 --- a/src/ov_SC07_001/ov_SC07_001_jr_8017AE2C.c +++ b/src/ov_SC07_001/ov_SC07_001_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801AAB1C; extern SV4 D_801AAB24; @@ -3083,7 +3083,7 @@ extern SV4 D_801AAB24; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801AAB24) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801AAB24)) */ diff --git a/src/ov_SC07_002/ov_SC07_002_jr_8017AE2C.c b/src/ov_SC07_002/ov_SC07_002_jr_8017AE2C.c index 64b4a8141e..d7fdb0a562 100644 --- a/src/ov_SC07_002/ov_SC07_002_jr_8017AE2C.c +++ b/src/ov_SC07_002/ov_SC07_002_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_8019B66C; extern SV4 D_8019B674; @@ -3083,7 +3083,7 @@ extern SV4 D_8019B674; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019B674) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019B674)) */ diff --git a/src/ov_SC07_006/ov_SC07_006_jr_8017AE2C.c b/src/ov_SC07_006/ov_SC07_006_jr_8017AE2C.c index b363457cb4..215d6b2a55 100644 --- a/src/ov_SC07_006/ov_SC07_006_jr_8017AE2C.c +++ b/src/ov_SC07_006/ov_SC07_006_jr_8017AE2C.c @@ -3690,7 +3690,7 @@ s32 func_8017BB34(s32 param_1, s32 param_2) extern s32 D_801F6014; extern SV4_8017B368 D_801F601C; SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801F601C)) */ diff --git a/src/ov_SC07_007/ov_SC07_007_jr_8017AE2C.c b/src/ov_SC07_007/ov_SC07_007_jr_8017AE2C.c index 2f8e438190..41b0b9dc2e 100644 --- a/src/ov_SC07_007/ov_SC07_007_jr_8017AE2C.c +++ b/src/ov_SC07_007/ov_SC07_007_jr_8017AE2C.c @@ -3690,7 +3690,7 @@ s32 func_8017BB34(s32 param_1, s32 param_2) extern s32 D_801C777C; extern SV4_8017B368 D_801C7784; SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C7784)) */ diff --git a/src/ov_SC07_008/ov_SC07_008_jr_8017AE2C.c b/src/ov_SC07_008/ov_SC07_008_jr_8017AE2C.c index 0df19a9636..4413e4c43e 100644 --- a/src/ov_SC07_008/ov_SC07_008_jr_8017AE2C.c +++ b/src/ov_SC07_008/ov_SC07_008_jr_8017AE2C.c @@ -3074,7 +3074,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_80196554; extern SV4 D_8019655C; @@ -3082,7 +3082,7 @@ extern SV4 D_8019655C; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019655C) */ @@ -3120,7 +3120,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019655C)) */ diff --git a/src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c b/src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c index 6b756c5050..cad05ee516 100644 --- a/src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c +++ b/src/ov_SC07_008/ov_SC07_008_jr_8017BEBC.c @@ -3240,7 +3240,7 @@ INCLUDE_ASM("asm/ov_SC07_008/nonmatchings/ov_SC07_008_jr_8017BEBC", func_8017D07 // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3253,7 +3253,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017D11C(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c b/src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c index 15aab448df..31cd71bfcc 100644 --- a/src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c +++ b/src/ov_SC07_009/ov_SC07_009_jr_8017AE2C.c @@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2); /* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */ -/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ +/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */ extern SV4 D_801A3BE4; extern SV4 D_801A3BEC; @@ -3083,7 +3083,7 @@ extern SV4 D_801A3BEC; void func_8017BA3C(s32 param_1, s32 param_2) { SV4 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4 v1; /* sp+0x38 : RotTransSV arg0 */ SV4 svec; /* sp+0x40 : func_8012F214 out */ SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A3BEC) */ @@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2) s32 func_8017BB34(s32 param_1, s32 param_2) { SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A3BEC)) */ diff --git a/src/ov_SC07_010/ov_SC07_010_jr_8015C32C.c b/src/ov_SC07_010/ov_SC07_010_jr_8015C32C.c index 7d534d699c..f26ce7e0af 100644 --- a/src/ov_SC07_010/ov_SC07_010_jr_8015C32C.c +++ b/src/ov_SC07_010/ov_SC07_010_jr_8015C32C.c @@ -5327,8 +5327,8 @@ void func_80169058(s32 a0) { s32 s1 = a0; s16 v10[4]; /* sp+0x10 SVECTOR */ s16 v18[4]; /* sp+0x18 SVECTOR */ - s16 v20[16]; /* sp+0x20 MATRIX */ - s16 v40[16]; /* sp+0x40 MATRIX */ + s16 v20[16]; /* sp+0x20 MATRIX_L48 */ + s16 v40[16]; /* sp+0x40 MATRIX_L48 */ register s32 v1 __asm__("$3"); register s32 v0 __asm__("$2"); v10[0] = *(u16 *)(s1 + 0x6); @@ -5416,8 +5416,8 @@ void func_8016986C(s32 a0) { s32 s1 = a0; s16 v10[4]; /* sp+0x10 SVECTOR */ s16 v18[4]; /* sp+0x18 SVECTOR */ - s16 v20[16]; /* sp+0x20 MATRIX */ - s16 v40[16]; /* sp+0x40 MATRIX */ + s16 v20[16]; /* sp+0x20 MATRIX_L48 */ + s16 v40[16]; /* sp+0x40 MATRIX_L48 */ s32 v1; s32 t; v10[0] = *(u16 *)(s1 + 0x6); diff --git a/src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c b/src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c index 0dfa2dbbdf..c93201642d 100644 --- a/src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c +++ b/src/ov_SC07_010/ov_SC07_010_jr_8017AE2C.c @@ -3167,7 +3167,7 @@ s32 func_8017BB34(s32 param_1, s32 param_2) extern s32 D_801A7C74; extern SV4_8017B368 D_801A7C7C; SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A7C7C)) */ @@ -3523,7 +3523,7 @@ INCLUDE_ASM("asm/ov_SC07_010/nonmatchings/ov_SC07_010_jr_8017AE2C", func_8017DEA // @class: schedule -// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only // lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh // zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1]. @@ -3536,7 +3536,7 @@ extern void func_80049CAC(s32 a0, s32 a1); extern void func_8012F14C(s32); void func_8017DEEC(s32 param_1, s16 *param_2) { - MATRIX_c1 m1; + MATRIX m1; SVECTOR svec_in; SVECTOR svec_out; diff --git a/src/ov_SC07_011/ov_SC07_011_jr_8017AE2C.c b/src/ov_SC07_011/ov_SC07_011_jr_8017AE2C.c index 43d15efc0a..d97e0563da 100644 --- a/src/ov_SC07_011/ov_SC07_011_jr_8017AE2C.c +++ b/src/ov_SC07_011/ov_SC07_011_jr_8017AE2C.c @@ -3723,7 +3723,7 @@ s32 func_8017BB34(s32 param_1, s32 param_2) extern s32 D_8019030C; extern SV4_8017B368 D_80190314; SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */ - MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */ + MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */ SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */ SV4_8017BB34 svec; /* sp+0x40 */ SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80190314)) */ diff --git a/src/shared/engine_core.h b/src/shared/engine_core.h index 70bb36b702..b7057645d3 100644 --- a/src/shared/engine_core.h +++ b/src/shared/engine_core.h @@ -12144,8 +12144,8 @@ s32 s1 = a0; \ s16 v10[4]; /* sp+0x10 SVECTOR */ \ s16 v18[4]; /* sp+0x18 SVECTOR */ \ - s16 v20[16]; /* sp+0x20 MATRIX */ \ - s16 v40[16]; /* sp+0x40 MATRIX */ \ + s16 v20[16]; /* sp+0x20 MATRIX_L48 */ \ + s16 v40[16]; /* sp+0x40 MATRIX_L48 */ \ s32 v1; \ s32 t; \ v10[0] = *(u16 *)(s1 + 0x6); \ @@ -19755,8 +19755,8 @@ s32 s1 = a0; \ s16 v10[4]; /* sp+0x10 SVECTOR */ \ s16 v18[4]; /* sp+0x18 SVECTOR */ \ - s16 v20[16]; /* sp+0x20 MATRIX */ \ - s16 v40[16]; /* sp+0x40 MATRIX */ \ + s16 v20[16]; /* sp+0x20 MATRIX_L48 */ \ + s16 v40[16]; /* sp+0x40 MATRIX_L48 */ \ register s32 v1 __asm__("$3"); \ register s32 v0 __asm__("$2"); \ v10[0] = *(u16 *)(s1 + 0x6); \ @@ -20049,8 +20049,8 @@ void func_80168D94(int a0) { \ int s1 = a0; \ short v10[4]; /* sp+0x10 SVECTOR */ \ - short v18[16]; /* sp+0x18 MATRIX */ \ - short v38[16]; /* sp+0x38 MATRIX */ \ + short v18[16]; /* sp+0x18 MATRIX_L48 */ \ + short v38[16]; /* sp+0x38 MATRIX_L48 */ \ register int v1 __asm__("$3"); \ register int v0 __asm__("$2"); \ v10[0] = *(unsigned short *)(s1 + 0x12); \ @@ -20433,7 +20433,7 @@ register s32 s1 __asm__("$17"); \ s16 v10[4]; /* sp+0x10 SVECTOR */ \ s16 out[4]; /* sp+0x18 SVECTOR */ \ - s16 m[32]; /* sp+0x20 MATRIX (+ trailing reserve to 0x60 — matches target frame) */ \ + s16 m[32]; /* sp+0x20 MATRIX_L48 (+ trailing reserve to 0x60 — matches target frame) */ \ if (*(s32 *)(s2 + 0x2C) == 0) { \ s32 r = rand(); \ s1 = s2 + 0x38; \ @@ -28714,7 +28714,7 @@ extern u8 D_800AF648; \ s32 func_8012E778(int param_1, int param_2) \ { \ - MATRIX *r0; \ + MATRIX_L48 *r0; \ int iVarX; \ int iVarY; \ int iVar3; \ @@ -28723,7 +28723,7 @@ sp[0] = (int)*(short *)(param_1 + 6); \ sp[1] = (int)*(short *)(param_1 + 10); \ sp[2] = (int)*(short *)(param_1 + 0xe); \ - r0 = (MATRIX *)&D_800AF648; \ + r0 = (MATRIX_L48 *)&D_800AF648; \ gte_SetRotMatrix(r0); \ gte_SetTransMatrix(r0); \ gte_ldlv0((VECTOR *)sp); \ diff --git a/src/shared/engine_types.h b/src/shared/engine_types.h index 7b373ffe47..05826690fc 100644 --- a/src/shared/engine_types.h +++ b/src/shared/engine_types.h @@ -7,6 +7,32 @@ * common.h consumers. */ #include "common.h" +/* ===== PsyQ GROUND TRUTH (oracle: Ghidra `types get`, category /LIBGTE.H, psyq400.gdt — Phase 29) ===== + * Recorded because this header accumulated 27 drafter-INVENTED lookalikes of real SDK types, several + * of which are wrong. Matching never noticed: codegen depends on access WIDTH+OFFSET read off the MIPS + * opcode, not on a struct definition, so a wrong layout propagates freely (SESSION-14 finding). + * + * MATRIX 32 bytes: short m[3][3] @+0x00 (18B) ; long t[3] @+0x14 (2 bytes padding after m) + * SVECTOR 8 bytes: short vx, vy, vz, pad + * VECTOR 16 bytes: long vx, vy, vz, pad + * + * STATUS in this header: + * MATRIX = the TRUE PsyQ layout (SESSION-14 renamed it here; it previously named a 48-byte + * invention, which is now MATRIX_L48 — the canonical name held the wrong type). + * MATRIX_L48 = `{s32 m[3][3]; s32 t[3]}`, 48 bytes. NOT a PsyQ type. Kept because ~131 files were + * written against it and it is byte-correct for them; do NOT "fix" it to 32 bytes — + * that changes sizeof/array stride and therefore codegen. + * MATRIX_c2 / MATRIX2 = also the true 32-byte layout under other names (pad spelled explicitly). + * SVECTOR / SVECTOR2 = both the true 8-byte layout. + * VECTOR = `{s32 vx, vy, vz}`, 12 bytes — MISSING PsyQ's trailing `pad`, so 12 vs 16. Left + * UNCHANGED deliberately: it has one live use (engine_core.h `gte_ldlv0((VECTOR*)sp)`). + * vx/vy/vz offsets already agree, so a fix is likely byte-neutral, but it is a LAYOUT + * change and belongs in its own R22-gated commit, not bundled with a rename. + * + * FOR NEW DRAFTS: use an address-suffixed name (`Ent_8016AB6C`) for anything you invent. MEASURED: 7 of + * the 8 same-name-different-layout collisions this fleet accumulated were BARE generic names. + * ==================================================================================================== */ + struct vec; struct V8; struct M8012AF0C; @@ -1138,8 +1164,8 @@ typedef struct { typedef struct { DrawEnv env; u8 pad[0x0C]; } Buf_c2; /* --- lift_types.py fleet lift --- */ -typedef struct { s32 m[3][3]; s32 t[3]; } MATRIX; -typedef struct { short m[3][3]; long t[3]; } MATRIX_c1; +typedef struct { s32 m[3][3]; s32 t[3]; } MATRIX_L48; +typedef struct { short m[3][3]; long t[3]; } MATRIX; typedef struct { short m[3][3]; short pad; s32 t[3]; } MATRIX_c2; /* --- lift_types.py fleet lift --- */