From e1b0cd9acd9feab95bc5c12b9f2265ee2cb7809c Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 31 Jul 2026 11:36:31 -0600 Subject: [PATCH] feat(phase-30): jr cluster family func_8013C414 swept 137/137 (329 ins x137), R22 140/140 The second and last has_mid_jr family of the -O0 cluster. Same route as func_8013C0F8: jtbl_family_bank (the SS81 carve chain per sibling) -> 137 BANKED / 0 failed. Both jr families together: 274 members, 483 ins x137 = ~66k instructions, 0 failures. Neither was bankable before commit:1270 routed the destination TUs to -O0. R22 CLEAN-FLEET: extract-all 139/139 (+main); check-all 140 passed, 0 failed of 140. --- config/overlays.mk | 137 ++++++++++++++++++++++++++++++ config/splat.ov_SC01_000.yaml | 2 +- config/splat.ov_SC01_001.yaml | 2 +- config/splat.ov_SC01_004.yaml | 2 +- config/splat.ov_SC01_005.yaml | 2 +- config/splat.ov_SC01_006.yaml | 2 +- config/splat.ov_SC01_008.yaml | 2 +- config/splat.ov_SC01_009.yaml | 2 +- config/splat.ov_SC01_074.yaml | 2 +- config/splat.ov_SC01_080.yaml | 2 +- config/splat.ov_SC01_084.yaml | 2 +- config/splat.ov_SC02_000.yaml | 2 +- config/splat.ov_SC02_003.yaml | 2 +- config/splat.ov_SC02_004.yaml | 2 +- config/splat.ov_SC02_005.yaml | 2 +- config/splat.ov_SC02_011.yaml | 2 +- config/splat.ov_SC02_015.yaml | 2 +- config/splat.ov_SC02_016.yaml | 2 +- config/splat.ov_SC02_017.yaml | 2 +- config/splat.ov_SC02_021.yaml | 2 +- config/splat.ov_SC02_026.yaml | 2 +- config/splat.ov_SC02_027.yaml | 2 +- config/splat.ov_SC02_028.yaml | 2 +- config/splat.ov_SC02_031.yaml | 2 +- config/splat.ov_SC02_035.yaml | 2 +- config/splat.ov_SC02_039.yaml | 2 +- config/splat.ov_SC02_041.yaml | 2 +- config/splat.ov_SC03_001.yaml | 2 +- config/splat.ov_SC03_002.yaml | 2 +- config/splat.ov_SC03_003.yaml | 2 +- config/splat.ov_SC03_006.yaml | 2 +- config/splat.ov_SC03_007.yaml | 2 +- config/splat.ov_SC03_010.yaml | 2 +- config/splat.ov_SC03_011.yaml | 2 +- config/splat.ov_SC03_012.yaml | 2 +- config/splat.ov_SC03_013.yaml | 2 +- config/splat.ov_SC03_014.yaml | 2 +- config/splat.ov_SC03_015.yaml | 2 +- config/splat.ov_SC03_023.yaml | 2 +- config/splat.ov_SC03_024.yaml | 2 +- config/splat.ov_SC03_028.yaml | 2 +- config/splat.ov_SC03_029.yaml | 2 +- config/splat.ov_SC03_030.yaml | 2 +- config/splat.ov_SC03_031.yaml | 2 +- config/splat.ov_SC03_089.yaml | 2 +- config/splat.ov_SC03_090.yaml | 2 +- config/splat.ov_SC03_091.yaml | 2 +- config/splat.ov_SC03_092.yaml | 2 +- config/splat.ov_SC03_093.yaml | 2 +- config/splat.ov_SC03_094.yaml | 2 +- config/splat.ov_SC03_095.yaml | 2 +- config/splat.ov_SC03_096.yaml | 2 +- config/splat.ov_SC03_097.yaml | 2 +- config/splat.ov_SC03_098.yaml | 2 +- config/splat.ov_SC03_099.yaml | 2 +- config/splat.ov_SC03_100.yaml | 2 +- config/splat.ov_SC03_101.yaml | 2 +- config/splat.ov_SC03_102.yaml | 2 +- config/splat.ov_SC03_103.yaml | 2 +- config/splat.ov_SC03_104.yaml | 2 +- config/splat.ov_SC03_105.yaml | 2 +- config/splat.ov_SC03_108.yaml | 2 +- config/splat.ov_SC03_109.yaml | 2 +- config/splat.ov_SC03_110.yaml | 2 +- config/splat.ov_SC03_111.yaml | 2 +- config/splat.ov_SC03_112.yaml | 2 +- config/splat.ov_SC03_113.yaml | 2 +- config/splat.ov_SC03_114.yaml | 2 +- config/splat.ov_SC03_115.yaml | 2 +- config/splat.ov_SC03_116.yaml | 2 +- config/splat.ov_SC03_117.yaml | 2 +- config/splat.ov_SC03_118.yaml | 2 +- config/splat.ov_SC03_119.yaml | 2 +- config/splat.ov_SC03_121.yaml | 2 +- config/splat.ov_SC03_124.yaml | 2 +- config/splat.ov_SC03_125.yaml | 2 +- config/splat.ov_SC03_126.yaml | 2 +- config/splat.ov_SC04_000.yaml | 2 +- config/splat.ov_SC04_002.yaml | 2 +- config/splat.ov_SC04_003.yaml | 2 +- config/splat.ov_SC04_004.yaml | 2 +- config/splat.ov_SC04_005.yaml | 2 +- config/splat.ov_SC04_006.yaml | 2 +- config/splat.ov_SC04_007.yaml | 2 +- config/splat.ov_SC04_008.yaml | 2 +- config/splat.ov_SC04_009.yaml | 2 +- config/splat.ov_SC04_010.yaml | 2 +- config/splat.ov_SC04_011.yaml | 2 +- config/splat.ov_SC04_012.yaml | 2 +- config/splat.ov_SC04_015.yaml | 2 +- config/splat.ov_SC04_016.yaml | 2 +- config/splat.ov_SC04_018.yaml | 2 +- config/splat.ov_SC04_019.yaml | 2 +- config/splat.ov_SC04_020.yaml | 2 +- config/splat.ov_SC04_021.yaml | 2 +- config/splat.ov_SC05_000.yaml | 2 +- config/splat.ov_SC05_001.yaml | 2 +- config/splat.ov_SC05_002.yaml | 2 +- config/splat.ov_SC05_003.yaml | 2 +- config/splat.ov_SC05_004.yaml | 2 +- config/splat.ov_SC05_005.yaml | 2 +- config/splat.ov_SC05_006.yaml | 2 +- config/splat.ov_SC05_007.yaml | 2 +- config/splat.ov_SC05_008.yaml | 2 +- config/splat.ov_SC05_009.yaml | 2 +- config/splat.ov_SC05_010.yaml | 2 +- config/splat.ov_SC05_011.yaml | 2 +- config/splat.ov_SC05_017.yaml | 2 +- config/splat.ov_SC05_018.yaml | 2 +- config/splat.ov_SC05_019.yaml | 2 +- config/splat.ov_SC06_000.yaml | 2 +- config/splat.ov_SC06_006.yaml | 2 +- config/splat.ov_SC06_008.yaml | 2 +- config/splat.ov_SC06_010.yaml | 2 +- config/splat.ov_SC06_011.yaml | 2 +- config/splat.ov_SC06_013.yaml | 2 +- config/splat.ov_SC06_014.yaml | 2 +- config/splat.ov_SC06_015.yaml | 2 +- config/splat.ov_SC06_016.yaml | 2 +- config/splat.ov_SC06_018.yaml | 2 +- config/splat.ov_SC06_020.yaml | 2 +- config/splat.ov_SC06_022.yaml | 2 +- config/splat.ov_SC06_024.yaml | 2 +- config/splat.ov_SC06_025.yaml | 2 +- config/splat.ov_SC06_027.yaml | 2 +- config/splat.ov_SC06_029.yaml | 2 +- config/splat.ov_SC06_030.yaml | 2 +- config/splat.ov_SC06_032.yaml | 2 +- config/splat.ov_SC06_033.yaml | 2 +- config/splat.ov_SC07_000.yaml | 2 +- config/splat.ov_SC07_001.yaml | 2 +- config/splat.ov_SC07_002.yaml | 2 +- config/splat.ov_SC07_006.yaml | 2 +- config/splat.ov_SC07_007.yaml | 2 +- config/splat.ov_SC07_008.yaml | 2 +- config/splat.ov_SC07_009.yaml | 2 +- config/splat.ov_SC07_010.yaml | 2 +- config/splat.ov_SC07_011.yaml | 2 +- src/ov_SC01_000/ov_SC01_000_o0c.c | 75 +++++++++++++++- src/ov_SC01_001/ov_SC01_001_o0c.c | 75 +++++++++++++++- src/ov_SC01_004/ov_SC01_004_o0c.c | 75 +++++++++++++++- src/ov_SC01_005/ov_SC01_005_o0c.c | 75 +++++++++++++++- src/ov_SC01_006/ov_SC01_006_o0c.c | 75 +++++++++++++++- src/ov_SC01_008/ov_SC01_008_o0c.c | 75 +++++++++++++++- src/ov_SC01_009/ov_SC01_009_o0c.c | 75 +++++++++++++++- src/ov_SC01_074/ov_SC01_074_o0c.c | 75 +++++++++++++++- src/ov_SC01_080/ov_SC01_080_o0c.c | 75 +++++++++++++++- src/ov_SC01_084/ov_SC01_084_o0c.c | 75 +++++++++++++++- src/ov_SC02_000/ov_SC02_000_o0c.c | 75 +++++++++++++++- src/ov_SC02_003/ov_SC02_003_o0c.c | 75 +++++++++++++++- src/ov_SC02_004/ov_SC02_004_o0c.c | 75 +++++++++++++++- src/ov_SC02_005/ov_SC02_005_o0c.c | 75 +++++++++++++++- src/ov_SC02_011/ov_SC02_011_o0c.c | 75 +++++++++++++++- src/ov_SC02_015/ov_SC02_015_o0c.c | 75 +++++++++++++++- src/ov_SC02_016/ov_SC02_016_o0c.c | 75 +++++++++++++++- src/ov_SC02_017/ov_SC02_017_o0c.c | 75 +++++++++++++++- src/ov_SC02_021/ov_SC02_021_o0c.c | 75 +++++++++++++++- src/ov_SC02_026/ov_SC02_026_o0c.c | 75 +++++++++++++++- src/ov_SC02_027/ov_SC02_027_o0c.c | 75 +++++++++++++++- src/ov_SC02_028/ov_SC02_028_o0c.c | 75 +++++++++++++++- src/ov_SC02_031/ov_SC02_031_o0c.c | 75 +++++++++++++++- src/ov_SC02_035/ov_SC02_035_o0c.c | 75 +++++++++++++++- src/ov_SC02_039/ov_SC02_039_o0c.c | 75 +++++++++++++++- src/ov_SC02_041/ov_SC02_041_o0c.c | 75 +++++++++++++++- src/ov_SC03_001/ov_SC03_001_o0c.c | 75 +++++++++++++++- src/ov_SC03_002/ov_SC03_002_o0c.c | 75 +++++++++++++++- src/ov_SC03_003/ov_SC03_003_o0c.c | 75 +++++++++++++++- src/ov_SC03_006/ov_SC03_006_o0c.c | 75 +++++++++++++++- src/ov_SC03_007/ov_SC03_007_o0c.c | 75 +++++++++++++++- src/ov_SC03_010/ov_SC03_010_o0c.c | 75 +++++++++++++++- src/ov_SC03_011/ov_SC03_011_o0c.c | 75 +++++++++++++++- src/ov_SC03_012/ov_SC03_012_o0c.c | 75 +++++++++++++++- src/ov_SC03_013/ov_SC03_013_o0c.c | 75 +++++++++++++++- src/ov_SC03_014/ov_SC03_014_o0e.c | 75 +++++++++++++++- src/ov_SC03_015/ov_SC03_015_o0e.c | 75 +++++++++++++++- src/ov_SC03_023/ov_SC03_023_o0c.c | 75 +++++++++++++++- src/ov_SC03_024/ov_SC03_024_o0c.c | 75 +++++++++++++++- src/ov_SC03_028/ov_SC03_028_o0c.c | 75 +++++++++++++++- src/ov_SC03_029/ov_SC03_029_o0c.c | 75 +++++++++++++++- src/ov_SC03_030/ov_SC03_030_o0c.c | 75 +++++++++++++++- src/ov_SC03_031/ov_SC03_031_o0c.c | 75 +++++++++++++++- src/ov_SC03_089/ov_SC03_089_o0c.c | 75 +++++++++++++++- src/ov_SC03_090/ov_SC03_090_o0c.c | 75 +++++++++++++++- src/ov_SC03_091/ov_SC03_091_o0c.c | 75 +++++++++++++++- src/ov_SC03_092/ov_SC03_092_o0c.c | 75 +++++++++++++++- src/ov_SC03_093/ov_SC03_093_o0c.c | 75 +++++++++++++++- src/ov_SC03_094/ov_SC03_094_o0c.c | 75 +++++++++++++++- src/ov_SC03_095/ov_SC03_095_o0c.c | 75 +++++++++++++++- src/ov_SC03_096/ov_SC03_096_o0c.c | 75 +++++++++++++++- src/ov_SC03_097/ov_SC03_097_o0c.c | 75 +++++++++++++++- src/ov_SC03_098/ov_SC03_098_o0c.c | 75 +++++++++++++++- src/ov_SC03_099/ov_SC03_099_o0c.c | 75 +++++++++++++++- src/ov_SC03_100/ov_SC03_100_o0c.c | 75 +++++++++++++++- src/ov_SC03_101/ov_SC03_101_o0c.c | 75 +++++++++++++++- src/ov_SC03_102/ov_SC03_102_o0c.c | 75 +++++++++++++++- src/ov_SC03_103/ov_SC03_103_o0c.c | 75 +++++++++++++++- src/ov_SC03_104/ov_SC03_104_o0c.c | 75 +++++++++++++++- src/ov_SC03_105/ov_SC03_105_o0c.c | 75 +++++++++++++++- src/ov_SC03_108/ov_SC03_108_o0c.c | 75 +++++++++++++++- src/ov_SC03_109/ov_SC03_109_o0c.c | 75 +++++++++++++++- src/ov_SC03_110/ov_SC03_110_o0c.c | 75 +++++++++++++++- src/ov_SC03_111/ov_SC03_111_o0c.c | 75 +++++++++++++++- src/ov_SC03_112/ov_SC03_112_o0c.c | 75 +++++++++++++++- src/ov_SC03_113/ov_SC03_113_o0c.c | 75 +++++++++++++++- src/ov_SC03_114/ov_SC03_114_o0c.c | 75 +++++++++++++++- src/ov_SC03_115/ov_SC03_115_o0c.c | 75 +++++++++++++++- src/ov_SC03_116/ov_SC03_116_o0c.c | 75 +++++++++++++++- src/ov_SC03_117/ov_SC03_117_o0c.c | 75 +++++++++++++++- src/ov_SC03_118/ov_SC03_118_o0c.c | 75 +++++++++++++++- src/ov_SC03_119/ov_SC03_119_o0c.c | 75 +++++++++++++++- src/ov_SC03_121/ov_SC03_121_o0c.c | 75 +++++++++++++++- src/ov_SC03_124/ov_SC03_124_o0c.c | 75 +++++++++++++++- src/ov_SC03_125/ov_SC03_125_o0c.c | 75 +++++++++++++++- src/ov_SC03_126/ov_SC03_126_o0c.c | 75 +++++++++++++++- src/ov_SC04_000/ov_SC04_000_o0c.c | 75 +++++++++++++++- src/ov_SC04_002/ov_SC04_002_o0c.c | 75 +++++++++++++++- src/ov_SC04_003/ov_SC04_003_o0c.c | 75 +++++++++++++++- src/ov_SC04_004/ov_SC04_004_o0c.c | 75 +++++++++++++++- src/ov_SC04_005/ov_SC04_005_o0c.c | 75 +++++++++++++++- src/ov_SC04_006/ov_SC04_006_o0c.c | 75 +++++++++++++++- src/ov_SC04_007/ov_SC04_007_o0c.c | 75 +++++++++++++++- src/ov_SC04_008/ov_SC04_008_o0c.c | 75 +++++++++++++++- src/ov_SC04_009/ov_SC04_009_o0c.c | 75 +++++++++++++++- src/ov_SC04_010/ov_SC04_010_o0c.c | 75 +++++++++++++++- src/ov_SC04_011/ov_SC04_011_o0c.c | 75 +++++++++++++++- src/ov_SC04_012/ov_SC04_012_o0c.c | 75 +++++++++++++++- src/ov_SC04_015/ov_SC04_015_o0c.c | 75 +++++++++++++++- src/ov_SC04_016/ov_SC04_016_o0c.c | 75 +++++++++++++++- src/ov_SC04_018/ov_SC04_018_o0c.c | 75 +++++++++++++++- src/ov_SC04_019/ov_SC04_019_o0c.c | 75 +++++++++++++++- src/ov_SC04_020/ov_SC04_020_o0c.c | 75 +++++++++++++++- src/ov_SC04_021/ov_SC04_021_o0c.c | 75 +++++++++++++++- src/ov_SC05_000/ov_SC05_000_o0c.c | 75 +++++++++++++++- src/ov_SC05_001/ov_SC05_001_o0c.c | 75 +++++++++++++++- src/ov_SC05_002/ov_SC05_002_o0c.c | 75 +++++++++++++++- src/ov_SC05_003/ov_SC05_003_o0c.c | 75 +++++++++++++++- src/ov_SC05_004/ov_SC05_004_o0c.c | 75 +++++++++++++++- src/ov_SC05_005/ov_SC05_005_o0c.c | 75 +++++++++++++++- src/ov_SC05_006/ov_SC05_006_o0c.c | 75 +++++++++++++++- src/ov_SC05_007/ov_SC05_007_o0c.c | 75 +++++++++++++++- src/ov_SC05_008/ov_SC05_008_o0c.c | 75 +++++++++++++++- src/ov_SC05_009/ov_SC05_009_o0c.c | 75 +++++++++++++++- src/ov_SC05_010/ov_SC05_010_o0c.c | 75 +++++++++++++++- src/ov_SC05_011/ov_SC05_011_o0c.c | 75 +++++++++++++++- src/ov_SC05_017/ov_SC05_017_o0c.c | 75 +++++++++++++++- src/ov_SC05_018/ov_SC05_018_o0c.c | 75 +++++++++++++++- src/ov_SC05_019/ov_SC05_019_o0c.c | 75 +++++++++++++++- src/ov_SC06_000/ov_SC06_000_o0c.c | 75 +++++++++++++++- src/ov_SC06_006/ov_SC06_006_o0c.c | 75 +++++++++++++++- src/ov_SC06_008/ov_SC06_008_o0c.c | 75 +++++++++++++++- src/ov_SC06_010/ov_SC06_010_o0c.c | 75 +++++++++++++++- src/ov_SC06_011/ov_SC06_011_o0c.c | 75 +++++++++++++++- src/ov_SC06_013/ov_SC06_013_o0c.c | 75 +++++++++++++++- src/ov_SC06_014/ov_SC06_014_o0c.c | 75 +++++++++++++++- src/ov_SC06_015/ov_SC06_015_o0c.c | 75 +++++++++++++++- src/ov_SC06_016/ov_SC06_016_o0c.c | 75 +++++++++++++++- src/ov_SC06_018/ov_SC06_018_o0c.c | 75 +++++++++++++++- src/ov_SC06_020/ov_SC06_020_o0c.c | 75 +++++++++++++++- src/ov_SC06_022/ov_SC06_022_o0c.c | 75 +++++++++++++++- src/ov_SC06_024/ov_SC06_024_o0c.c | 75 +++++++++++++++- src/ov_SC06_025/ov_SC06_025_o0c.c | 75 +++++++++++++++- src/ov_SC06_027/ov_SC06_027_o0c.c | 75 +++++++++++++++- src/ov_SC06_029/ov_SC06_029_o0c.c | 75 +++++++++++++++- src/ov_SC06_030/ov_SC06_030_o0c.c | 75 +++++++++++++++- src/ov_SC06_032/ov_SC06_032_o0c.c | 75 +++++++++++++++- src/ov_SC06_033/ov_SC06_033_o0c.c | 75 +++++++++++++++- src/ov_SC07_000/ov_SC07_000_o0c.c | 75 +++++++++++++++- src/ov_SC07_001/ov_SC07_001_o0c.c | 75 +++++++++++++++- src/ov_SC07_002/ov_SC07_002_o0c.c | 75 +++++++++++++++- src/ov_SC07_006/ov_SC07_006_o0c.c | 75 +++++++++++++++- src/ov_SC07_007/ov_SC07_007_o0c.c | 75 +++++++++++++++- src/ov_SC07_008/ov_SC07_008_o0c.c | 75 +++++++++++++++- src/ov_SC07_009/ov_SC07_009_o0c.c | 75 +++++++++++++++- src/ov_SC07_010/ov_SC07_010_o0.c | Bin 5726 -> 8223 bytes src/ov_SC07_011/ov_SC07_011_o0c.c | 75 +++++++++++++++- 275 files changed, 10338 insertions(+), 273 deletions(-) diff --git a/config/overlays.mk b/config/overlays.mk index c3d084ca2..0d051f0f9 100644 --- a/config/overlays.mk +++ b/config/overlays.mk @@ -64,6 +64,7 @@ build/src/ov_SC01_005/ov_SC01_005_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC01_005/ov_SC01_005_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_005/ov_SC01_005_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_005/ov_SC01_005_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC01_005/ov_SC01_005_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC01_005_CHECK_SHA := config/check.ov_SC01_005.sha ov_SC01_005_SYMBOLS := config/symbols.ov_SC01_005.txt ov_SC01_005_SIG := .run/sig.ov_SC01_005.jsonl @@ -96,6 +97,7 @@ build/src/ov_SC01_006/ov_SC01_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC01_006/ov_SC01_006_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_006/ov_SC01_006_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_006/ov_SC01_006_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC01_006/ov_SC01_006_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC01_006_CHECK_SHA := config/check.ov_SC01_006.sha ov_SC01_006_SYMBOLS := config/symbols.ov_SC01_006.txt ov_SC01_006_SIG := .run/sig.ov_SC01_006.jsonl @@ -128,6 +130,7 @@ build/src/ov_SC03_001/ov_SC03_001_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_001/ov_SC03_001_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_001/ov_SC03_001_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_001/ov_SC03_001_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_001/ov_SC03_001_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_001_CHECK_SHA := config/check.ov_SC03_001.sha ov_SC03_001_SYMBOLS := config/symbols.ov_SC03_001.txt ov_SC03_001_SIG := .run/sig.ov_SC03_001.jsonl @@ -160,6 +163,7 @@ build/src/ov_SC01_000/ov_SC01_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC01_000/ov_SC01_000_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_000/ov_SC01_000_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_000/ov_SC01_000_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC01_000/ov_SC01_000_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC01_000_CHECK_SHA := config/check.ov_SC01_000.sha ov_SC01_000_SYMBOLS := config/symbols.ov_SC01_000.txt ov_SC01_000_SIG := .run/sig.ov_SC01_000.jsonl @@ -192,6 +196,7 @@ build/src/ov_SC01_001/ov_SC01_001_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC01_001/ov_SC01_001_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_001/ov_SC01_001_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_001/ov_SC01_001_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC01_001/ov_SC01_001_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC01_001_CHECK_SHA := config/check.ov_SC01_001.sha ov_SC01_001_SYMBOLS := config/symbols.ov_SC01_001.txt ov_SC01_001_SIG := .run/sig.ov_SC01_001.jsonl @@ -224,6 +229,7 @@ build/src/ov_SC02_000/ov_SC02_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_000/ov_SC02_000_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_000/ov_SC02_000_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_000/ov_SC02_000_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_000/ov_SC02_000_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_000_CHECK_SHA := config/check.ov_SC02_000.sha ov_SC02_000_SYMBOLS := config/symbols.ov_SC02_000.txt ov_SC02_000_SIG := .run/sig.ov_SC02_000.jsonl @@ -256,6 +262,7 @@ build/src/ov_SC02_003/ov_SC02_003_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_003/ov_SC02_003_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_003/ov_SC02_003_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_003/ov_SC02_003_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_003/ov_SC02_003_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_003_CHECK_SHA := config/check.ov_SC02_003.sha ov_SC02_003_SYMBOLS := config/symbols.ov_SC02_003.txt ov_SC02_003_SIG := .run/sig.ov_SC02_003.jsonl @@ -288,6 +295,7 @@ build/src/ov_SC03_002/ov_SC03_002_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_002/ov_SC03_002_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_002/ov_SC03_002_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_002/ov_SC03_002_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_002/ov_SC03_002_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_002_CHECK_SHA := config/check.ov_SC03_002.sha ov_SC03_002_SYMBOLS := config/symbols.ov_SC03_002.txt ov_SC03_002_SIG := .run/sig.ov_SC03_002.jsonl @@ -320,6 +328,7 @@ build/src/ov_SC03_006/ov_SC03_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_006/ov_SC03_006_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_006/ov_SC03_006_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_006/ov_SC03_006_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_006/ov_SC03_006_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_006_CHECK_SHA := config/check.ov_SC03_006.sha ov_SC03_006_SYMBOLS := config/symbols.ov_SC03_006.txt ov_SC03_006_SIG := .run/sig.ov_SC03_006.jsonl @@ -352,6 +361,7 @@ build/src/ov_SC04_000/ov_SC04_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_000/ov_SC04_000_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_000/ov_SC04_000_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_000/ov_SC04_000_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_000/ov_SC04_000_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_000_CHECK_SHA := config/check.ov_SC04_000.sha ov_SC04_000_SYMBOLS := config/symbols.ov_SC04_000.txt ov_SC04_000_SIG := .run/sig.ov_SC04_000.jsonl @@ -384,6 +394,7 @@ build/src/ov_SC04_018/ov_SC04_018_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_018/ov_SC04_018_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_018/ov_SC04_018_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_018/ov_SC04_018_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_018/ov_SC04_018_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_018_CHECK_SHA := config/check.ov_SC04_018.sha ov_SC04_018_SYMBOLS := config/symbols.ov_SC04_018.txt ov_SC04_018_SIG := .run/sig.ov_SC04_018.jsonl @@ -416,6 +427,7 @@ build/src/ov_SC04_019/ov_SC04_019_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_019/ov_SC04_019_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_019/ov_SC04_019_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_019/ov_SC04_019_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_019/ov_SC04_019_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_019_CHECK_SHA := config/check.ov_SC04_019.sha ov_SC04_019_SYMBOLS := config/symbols.ov_SC04_019.txt ov_SC04_019_SIG := .run/sig.ov_SC04_019.jsonl @@ -448,6 +460,7 @@ build/src/ov_SC05_000/ov_SC05_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_000/ov_SC05_000_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_000/ov_SC05_000_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_000/ov_SC05_000_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_000/ov_SC05_000_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_000_CHECK_SHA := config/check.ov_SC05_000.sha ov_SC05_000_SYMBOLS := config/symbols.ov_SC05_000.txt ov_SC05_000_SIG := .run/sig.ov_SC05_000.jsonl @@ -480,6 +493,7 @@ build/src/ov_SC06_000/ov_SC06_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_000/ov_SC06_000_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_000/ov_SC06_000_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_000/ov_SC06_000_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_000/ov_SC06_000_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_000_CHECK_SHA := config/check.ov_SC06_000.sha ov_SC06_000_SYMBOLS := config/symbols.ov_SC06_000.txt ov_SC06_000_SIG := .run/sig.ov_SC06_000.jsonl @@ -512,6 +526,7 @@ build/src/ov_SC07_000/ov_SC07_000_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC07_000/ov_SC07_000_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_000/ov_SC07_000_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_000/ov_SC07_000_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC07_000/ov_SC07_000_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC07_000_CHECK_SHA := config/check.ov_SC07_000.sha ov_SC07_000_SYMBOLS := config/symbols.ov_SC07_000.txt ov_SC07_000_SIG := .run/sig.ov_SC07_000.jsonl @@ -544,6 +559,7 @@ build/src/ov_SC01_004/ov_SC01_004_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC01_004/ov_SC01_004_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_004/ov_SC01_004_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_004/ov_SC01_004_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC01_004/ov_SC01_004_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC01_004_CHECK_SHA := config/check.ov_SC01_004.sha ov_SC01_004_SYMBOLS := config/symbols.ov_SC01_004.txt ov_SC01_004_SIG := .run/sig.ov_SC01_004.jsonl @@ -576,6 +592,7 @@ build/src/ov_SC01_008/ov_SC01_008_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC01_008/ov_SC01_008_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_008/ov_SC01_008_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_008/ov_SC01_008_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC01_008/ov_SC01_008_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC01_008_CHECK_SHA := config/check.ov_SC01_008.sha ov_SC01_008_SYMBOLS := config/symbols.ov_SC01_008.txt ov_SC01_008_SIG := .run/sig.ov_SC01_008.jsonl @@ -608,6 +625,7 @@ build/src/ov_SC01_009/ov_SC01_009_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC01_009/ov_SC01_009_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_009/ov_SC01_009_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_009/ov_SC01_009_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC01_009/ov_SC01_009_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC01_009_CHECK_SHA := config/check.ov_SC01_009.sha ov_SC01_009_SYMBOLS := config/symbols.ov_SC01_009.txt ov_SC01_009_SIG := .run/sig.ov_SC01_009.jsonl @@ -640,6 +658,7 @@ build/src/ov_SC01_074/ov_SC01_074_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC01_074/ov_SC01_074_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_074/ov_SC01_074_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_074/ov_SC01_074_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC01_074/ov_SC01_074_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC01_074_CHECK_SHA := config/check.ov_SC01_074.sha ov_SC01_074_SYMBOLS := config/symbols.ov_SC01_074.txt ov_SC01_074_SIG := .run/sig.ov_SC01_074.jsonl @@ -672,6 +691,7 @@ build/src/ov_SC01_080/ov_SC01_080_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC01_080/ov_SC01_080_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_080/ov_SC01_080_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_080/ov_SC01_080_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC01_080/ov_SC01_080_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC01_080_CHECK_SHA := config/check.ov_SC01_080.sha ov_SC01_080_SYMBOLS := config/symbols.ov_SC01_080.txt ov_SC01_080_SIG := .run/sig.ov_SC01_080.jsonl @@ -704,6 +724,7 @@ build/src/ov_SC01_084/ov_SC01_084_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC01_084/ov_SC01_084_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_084/ov_SC01_084_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC01_084/ov_SC01_084_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC01_084/ov_SC01_084_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC01_084_CHECK_SHA := config/check.ov_SC01_084.sha ov_SC01_084_SYMBOLS := config/symbols.ov_SC01_084.txt ov_SC01_084_SIG := .run/sig.ov_SC01_084.jsonl @@ -736,6 +757,7 @@ build/src/ov_SC02_004/ov_SC02_004_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_004/ov_SC02_004_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_004/ov_SC02_004_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_004/ov_SC02_004_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_004/ov_SC02_004_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_004_CHECK_SHA := config/check.ov_SC02_004.sha ov_SC02_004_SYMBOLS := config/symbols.ov_SC02_004.txt ov_SC02_004_SIG := .run/sig.ov_SC02_004.jsonl @@ -768,6 +790,7 @@ build/src/ov_SC02_005/ov_SC02_005_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_005/ov_SC02_005_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_005/ov_SC02_005_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_005/ov_SC02_005_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_005/ov_SC02_005_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_005_CHECK_SHA := config/check.ov_SC02_005.sha ov_SC02_005_SYMBOLS := config/symbols.ov_SC02_005.txt ov_SC02_005_SIG := .run/sig.ov_SC02_005.jsonl @@ -800,6 +823,7 @@ build/src/ov_SC02_011/ov_SC02_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_011/ov_SC02_011_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_011/ov_SC02_011_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_011/ov_SC02_011_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_011/ov_SC02_011_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_011_CHECK_SHA := config/check.ov_SC02_011.sha ov_SC02_011_SYMBOLS := config/symbols.ov_SC02_011.txt ov_SC02_011_SIG := .run/sig.ov_SC02_011.jsonl @@ -832,6 +856,7 @@ build/src/ov_SC02_015/ov_SC02_015_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_015/ov_SC02_015_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_015/ov_SC02_015_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_015/ov_SC02_015_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_015/ov_SC02_015_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_015_CHECK_SHA := config/check.ov_SC02_015.sha ov_SC02_015_SYMBOLS := config/symbols.ov_SC02_015.txt ov_SC02_015_SIG := .run/sig.ov_SC02_015.jsonl @@ -864,6 +889,7 @@ build/src/ov_SC02_016/ov_SC02_016_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_016/ov_SC02_016_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_016/ov_SC02_016_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_016/ov_SC02_016_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_016/ov_SC02_016_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_016_CHECK_SHA := config/check.ov_SC02_016.sha ov_SC02_016_SYMBOLS := config/symbols.ov_SC02_016.txt ov_SC02_016_SIG := .run/sig.ov_SC02_016.jsonl @@ -896,6 +922,7 @@ build/src/ov_SC02_017/ov_SC02_017_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_017/ov_SC02_017_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_017/ov_SC02_017_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_017/ov_SC02_017_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_017/ov_SC02_017_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_017_CHECK_SHA := config/check.ov_SC02_017.sha ov_SC02_017_SYMBOLS := config/symbols.ov_SC02_017.txt ov_SC02_017_SIG := .run/sig.ov_SC02_017.jsonl @@ -928,6 +955,7 @@ build/src/ov_SC02_021/ov_SC02_021_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_021/ov_SC02_021_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_021/ov_SC02_021_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_021/ov_SC02_021_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_021/ov_SC02_021_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_021_CHECK_SHA := config/check.ov_SC02_021.sha ov_SC02_021_SYMBOLS := config/symbols.ov_SC02_021.txt ov_SC02_021_SIG := .run/sig.ov_SC02_021.jsonl @@ -960,6 +988,7 @@ build/src/ov_SC02_026/ov_SC02_026_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_026/ov_SC02_026_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_026/ov_SC02_026_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_026/ov_SC02_026_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_026/ov_SC02_026_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_026_CHECK_SHA := config/check.ov_SC02_026.sha ov_SC02_026_SYMBOLS := config/symbols.ov_SC02_026.txt ov_SC02_026_SIG := .run/sig.ov_SC02_026.jsonl @@ -992,6 +1021,7 @@ build/src/ov_SC02_027/ov_SC02_027_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_027/ov_SC02_027_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_027/ov_SC02_027_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_027/ov_SC02_027_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_027/ov_SC02_027_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_027_CHECK_SHA := config/check.ov_SC02_027.sha ov_SC02_027_SYMBOLS := config/symbols.ov_SC02_027.txt ov_SC02_027_SIG := .run/sig.ov_SC02_027.jsonl @@ -1024,6 +1054,7 @@ build/src/ov_SC02_028/ov_SC02_028_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_028/ov_SC02_028_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_028/ov_SC02_028_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_028/ov_SC02_028_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_028/ov_SC02_028_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_028_CHECK_SHA := config/check.ov_SC02_028.sha ov_SC02_028_SYMBOLS := config/symbols.ov_SC02_028.txt ov_SC02_028_SIG := .run/sig.ov_SC02_028.jsonl @@ -1056,6 +1087,7 @@ build/src/ov_SC02_031/ov_SC02_031_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_031/ov_SC02_031_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_031/ov_SC02_031_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_031/ov_SC02_031_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_031/ov_SC02_031_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_031_CHECK_SHA := config/check.ov_SC02_031.sha ov_SC02_031_SYMBOLS := config/symbols.ov_SC02_031.txt ov_SC02_031_SIG := .run/sig.ov_SC02_031.jsonl @@ -1088,6 +1120,7 @@ build/src/ov_SC02_035/ov_SC02_035_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_035/ov_SC02_035_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_035/ov_SC02_035_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_035/ov_SC02_035_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_035/ov_SC02_035_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_035_CHECK_SHA := config/check.ov_SC02_035.sha ov_SC02_035_SYMBOLS := config/symbols.ov_SC02_035.txt ov_SC02_035_SIG := .run/sig.ov_SC02_035.jsonl @@ -1120,6 +1153,7 @@ build/src/ov_SC02_039/ov_SC02_039_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_039/ov_SC02_039_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_039/ov_SC02_039_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_039/ov_SC02_039_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_039/ov_SC02_039_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_039_CHECK_SHA := config/check.ov_SC02_039.sha ov_SC02_039_SYMBOLS := config/symbols.ov_SC02_039.txt ov_SC02_039_SIG := .run/sig.ov_SC02_039.jsonl @@ -1152,6 +1186,7 @@ build/src/ov_SC02_041/ov_SC02_041_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC02_041/ov_SC02_041_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_041/ov_SC02_041_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC02_041/ov_SC02_041_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC02_041/ov_SC02_041_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC02_041_CHECK_SHA := config/check.ov_SC02_041.sha ov_SC02_041_SYMBOLS := config/symbols.ov_SC02_041.txt ov_SC02_041_SIG := .run/sig.ov_SC02_041.jsonl @@ -1184,6 +1219,7 @@ build/src/ov_SC03_003/ov_SC03_003_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_003/ov_SC03_003_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_003/ov_SC03_003_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_003/ov_SC03_003_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_003/ov_SC03_003_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_003_CHECK_SHA := config/check.ov_SC03_003.sha ov_SC03_003_SYMBOLS := config/symbols.ov_SC03_003.txt ov_SC03_003_SIG := .run/sig.ov_SC03_003.jsonl @@ -1216,6 +1252,7 @@ build/src/ov_SC03_007/ov_SC03_007_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_007/ov_SC03_007_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_007/ov_SC03_007_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_007/ov_SC03_007_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_007/ov_SC03_007_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_007_CHECK_SHA := config/check.ov_SC03_007.sha ov_SC03_007_SYMBOLS := config/symbols.ov_SC03_007.txt ov_SC03_007_SIG := .run/sig.ov_SC03_007.jsonl @@ -1248,6 +1285,7 @@ build/src/ov_SC03_010/ov_SC03_010_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_010/ov_SC03_010_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_010/ov_SC03_010_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_010/ov_SC03_010_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_010/ov_SC03_010_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_010_CHECK_SHA := config/check.ov_SC03_010.sha ov_SC03_010_SYMBOLS := config/symbols.ov_SC03_010.txt ov_SC03_010_SIG := .run/sig.ov_SC03_010.jsonl @@ -1280,6 +1318,7 @@ build/src/ov_SC03_011/ov_SC03_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_011/ov_SC03_011_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_011/ov_SC03_011_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_011/ov_SC03_011_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_011/ov_SC03_011_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_011_CHECK_SHA := config/check.ov_SC03_011.sha ov_SC03_011_SYMBOLS := config/symbols.ov_SC03_011.txt ov_SC03_011_SIG := .run/sig.ov_SC03_011.jsonl @@ -1312,6 +1351,7 @@ build/src/ov_SC03_012/ov_SC03_012_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_012/ov_SC03_012_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_012/ov_SC03_012_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_012/ov_SC03_012_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_012/ov_SC03_012_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_012_CHECK_SHA := config/check.ov_SC03_012.sha ov_SC03_012_SYMBOLS := config/symbols.ov_SC03_012.txt ov_SC03_012_SIG := .run/sig.ov_SC03_012.jsonl @@ -1344,6 +1384,7 @@ build/src/ov_SC03_013/ov_SC03_013_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_013/ov_SC03_013_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_013/ov_SC03_013_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_013/ov_SC03_013_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_013/ov_SC03_013_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_013_CHECK_SHA := config/check.ov_SC03_013.sha ov_SC03_013_SYMBOLS := config/symbols.ov_SC03_013.txt ov_SC03_013_SIG := .run/sig.ov_SC03_013.jsonl @@ -1376,6 +1417,7 @@ build/src/ov_SC03_014/ov_SC03_014_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_014/ov_SC03_014_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_014/ov_SC03_014_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_014/ov_SC03_014_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_014/ov_SC03_014_o0e.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_014_CHECK_SHA := config/check.ov_SC03_014.sha ov_SC03_014_SYMBOLS := config/symbols.ov_SC03_014.txt ov_SC03_014_SIG := .run/sig.ov_SC03_014.jsonl @@ -1408,6 +1450,7 @@ build/src/ov_SC03_015/ov_SC03_015_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_015/ov_SC03_015_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_015/ov_SC03_015_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_015/ov_SC03_015_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_015/ov_SC03_015_o0e.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_015_CHECK_SHA := config/check.ov_SC03_015.sha ov_SC03_015_SYMBOLS := config/symbols.ov_SC03_015.txt ov_SC03_015_SIG := .run/sig.ov_SC03_015.jsonl @@ -1440,6 +1483,7 @@ build/src/ov_SC03_023/ov_SC03_023_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_023/ov_SC03_023_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_023/ov_SC03_023_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_023/ov_SC03_023_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_023/ov_SC03_023_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_023_CHECK_SHA := config/check.ov_SC03_023.sha ov_SC03_023_SYMBOLS := config/symbols.ov_SC03_023.txt ov_SC03_023_SIG := .run/sig.ov_SC03_023.jsonl @@ -1472,6 +1516,7 @@ build/src/ov_SC03_024/ov_SC03_024_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_024/ov_SC03_024_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_024/ov_SC03_024_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_024/ov_SC03_024_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_024/ov_SC03_024_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_024_CHECK_SHA := config/check.ov_SC03_024.sha ov_SC03_024_SYMBOLS := config/symbols.ov_SC03_024.txt ov_SC03_024_SIG := .run/sig.ov_SC03_024.jsonl @@ -1504,6 +1549,7 @@ build/src/ov_SC03_028/ov_SC03_028_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_028/ov_SC03_028_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_028/ov_SC03_028_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_028/ov_SC03_028_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_028/ov_SC03_028_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_028_CHECK_SHA := config/check.ov_SC03_028.sha ov_SC03_028_SYMBOLS := config/symbols.ov_SC03_028.txt ov_SC03_028_SIG := .run/sig.ov_SC03_028.jsonl @@ -1536,6 +1582,7 @@ build/src/ov_SC03_029/ov_SC03_029_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_029/ov_SC03_029_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_029/ov_SC03_029_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_029/ov_SC03_029_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_029/ov_SC03_029_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_029_CHECK_SHA := config/check.ov_SC03_029.sha ov_SC03_029_SYMBOLS := config/symbols.ov_SC03_029.txt ov_SC03_029_SIG := .run/sig.ov_SC03_029.jsonl @@ -1568,6 +1615,7 @@ build/src/ov_SC03_030/ov_SC03_030_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_030/ov_SC03_030_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_030/ov_SC03_030_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_030/ov_SC03_030_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_030/ov_SC03_030_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_030_CHECK_SHA := config/check.ov_SC03_030.sha ov_SC03_030_SYMBOLS := config/symbols.ov_SC03_030.txt ov_SC03_030_SIG := .run/sig.ov_SC03_030.jsonl @@ -1600,6 +1648,7 @@ build/src/ov_SC03_031/ov_SC03_031_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_031/ov_SC03_031_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_031/ov_SC03_031_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_031/ov_SC03_031_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_031/ov_SC03_031_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_031_CHECK_SHA := config/check.ov_SC03_031.sha ov_SC03_031_SYMBOLS := config/symbols.ov_SC03_031.txt ov_SC03_031_SIG := .run/sig.ov_SC03_031.jsonl @@ -1632,6 +1681,7 @@ build/src/ov_SC03_089/ov_SC03_089_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_089/ov_SC03_089_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_089/ov_SC03_089_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_089/ov_SC03_089_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_089/ov_SC03_089_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_089_CHECK_SHA := config/check.ov_SC03_089.sha ov_SC03_089_SYMBOLS := config/symbols.ov_SC03_089.txt ov_SC03_089_SIG := .run/sig.ov_SC03_089.jsonl @@ -1664,6 +1714,7 @@ build/src/ov_SC03_090/ov_SC03_090_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_090/ov_SC03_090_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_090/ov_SC03_090_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_090/ov_SC03_090_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_090/ov_SC03_090_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_090_CHECK_SHA := config/check.ov_SC03_090.sha ov_SC03_090_SYMBOLS := config/symbols.ov_SC03_090.txt ov_SC03_090_SIG := .run/sig.ov_SC03_090.jsonl @@ -1696,6 +1747,7 @@ build/src/ov_SC03_091/ov_SC03_091_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_091/ov_SC03_091_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_091/ov_SC03_091_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_091/ov_SC03_091_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_091/ov_SC03_091_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_091_CHECK_SHA := config/check.ov_SC03_091.sha ov_SC03_091_SYMBOLS := config/symbols.ov_SC03_091.txt ov_SC03_091_SIG := .run/sig.ov_SC03_091.jsonl @@ -1728,6 +1780,7 @@ build/src/ov_SC03_092/ov_SC03_092_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_092/ov_SC03_092_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_092/ov_SC03_092_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_092/ov_SC03_092_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_092/ov_SC03_092_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_092_CHECK_SHA := config/check.ov_SC03_092.sha ov_SC03_092_SYMBOLS := config/symbols.ov_SC03_092.txt ov_SC03_092_SIG := .run/sig.ov_SC03_092.jsonl @@ -1760,6 +1813,7 @@ build/src/ov_SC03_093/ov_SC03_093_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_093/ov_SC03_093_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_093/ov_SC03_093_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_093/ov_SC03_093_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_093/ov_SC03_093_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_093_CHECK_SHA := config/check.ov_SC03_093.sha ov_SC03_093_SYMBOLS := config/symbols.ov_SC03_093.txt ov_SC03_093_SIG := .run/sig.ov_SC03_093.jsonl @@ -1792,6 +1846,7 @@ build/src/ov_SC03_094/ov_SC03_094_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_094/ov_SC03_094_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_094/ov_SC03_094_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_094/ov_SC03_094_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_094/ov_SC03_094_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_094_CHECK_SHA := config/check.ov_SC03_094.sha ov_SC03_094_SYMBOLS := config/symbols.ov_SC03_094.txt ov_SC03_094_SIG := .run/sig.ov_SC03_094.jsonl @@ -1824,6 +1879,7 @@ build/src/ov_SC03_095/ov_SC03_095_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_095/ov_SC03_095_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_095/ov_SC03_095_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_095/ov_SC03_095_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_095/ov_SC03_095_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_095_CHECK_SHA := config/check.ov_SC03_095.sha ov_SC03_095_SYMBOLS := config/symbols.ov_SC03_095.txt ov_SC03_095_SIG := .run/sig.ov_SC03_095.jsonl @@ -1856,6 +1912,7 @@ build/src/ov_SC03_096/ov_SC03_096_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_096/ov_SC03_096_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_096/ov_SC03_096_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_096/ov_SC03_096_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_096/ov_SC03_096_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_096_CHECK_SHA := config/check.ov_SC03_096.sha ov_SC03_096_SYMBOLS := config/symbols.ov_SC03_096.txt ov_SC03_096_SIG := .run/sig.ov_SC03_096.jsonl @@ -1888,6 +1945,7 @@ build/src/ov_SC03_097/ov_SC03_097_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_097/ov_SC03_097_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_097/ov_SC03_097_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_097/ov_SC03_097_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_097/ov_SC03_097_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_097_CHECK_SHA := config/check.ov_SC03_097.sha ov_SC03_097_SYMBOLS := config/symbols.ov_SC03_097.txt ov_SC03_097_SIG := .run/sig.ov_SC03_097.jsonl @@ -1920,6 +1978,7 @@ build/src/ov_SC03_098/ov_SC03_098_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_098/ov_SC03_098_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_098/ov_SC03_098_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_098/ov_SC03_098_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_098/ov_SC03_098_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_098_CHECK_SHA := config/check.ov_SC03_098.sha ov_SC03_098_SYMBOLS := config/symbols.ov_SC03_098.txt ov_SC03_098_SIG := .run/sig.ov_SC03_098.jsonl @@ -1952,6 +2011,7 @@ build/src/ov_SC03_099/ov_SC03_099_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_099/ov_SC03_099_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_099/ov_SC03_099_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_099/ov_SC03_099_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_099/ov_SC03_099_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_099_CHECK_SHA := config/check.ov_SC03_099.sha ov_SC03_099_SYMBOLS := config/symbols.ov_SC03_099.txt ov_SC03_099_SIG := .run/sig.ov_SC03_099.jsonl @@ -1984,6 +2044,7 @@ build/src/ov_SC03_100/ov_SC03_100_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_100/ov_SC03_100_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_100/ov_SC03_100_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_100/ov_SC03_100_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_100/ov_SC03_100_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_100_CHECK_SHA := config/check.ov_SC03_100.sha ov_SC03_100_SYMBOLS := config/symbols.ov_SC03_100.txt ov_SC03_100_SIG := .run/sig.ov_SC03_100.jsonl @@ -2016,6 +2077,7 @@ build/src/ov_SC03_101/ov_SC03_101_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_101/ov_SC03_101_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_101/ov_SC03_101_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_101/ov_SC03_101_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_101/ov_SC03_101_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_101_CHECK_SHA := config/check.ov_SC03_101.sha ov_SC03_101_SYMBOLS := config/symbols.ov_SC03_101.txt ov_SC03_101_SIG := .run/sig.ov_SC03_101.jsonl @@ -2048,6 +2110,7 @@ build/src/ov_SC03_102/ov_SC03_102_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_102/ov_SC03_102_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_102/ov_SC03_102_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_102/ov_SC03_102_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_102/ov_SC03_102_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_102_CHECK_SHA := config/check.ov_SC03_102.sha ov_SC03_102_SYMBOLS := config/symbols.ov_SC03_102.txt ov_SC03_102_SIG := .run/sig.ov_SC03_102.jsonl @@ -2080,6 +2143,7 @@ build/src/ov_SC03_103/ov_SC03_103_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_103/ov_SC03_103_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_103/ov_SC03_103_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_103/ov_SC03_103_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_103/ov_SC03_103_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_103_CHECK_SHA := config/check.ov_SC03_103.sha ov_SC03_103_SYMBOLS := config/symbols.ov_SC03_103.txt ov_SC03_103_SIG := .run/sig.ov_SC03_103.jsonl @@ -2112,6 +2176,7 @@ build/src/ov_SC03_104/ov_SC03_104_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_104/ov_SC03_104_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_104/ov_SC03_104_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_104/ov_SC03_104_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_104/ov_SC03_104_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_104_CHECK_SHA := config/check.ov_SC03_104.sha ov_SC03_104_SYMBOLS := config/symbols.ov_SC03_104.txt ov_SC03_104_SIG := .run/sig.ov_SC03_104.jsonl @@ -2144,6 +2209,7 @@ build/src/ov_SC03_105/ov_SC03_105_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_105/ov_SC03_105_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_105/ov_SC03_105_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_105/ov_SC03_105_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_105/ov_SC03_105_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_105_CHECK_SHA := config/check.ov_SC03_105.sha ov_SC03_105_SYMBOLS := config/symbols.ov_SC03_105.txt ov_SC03_105_SIG := .run/sig.ov_SC03_105.jsonl @@ -2175,6 +2241,7 @@ build/src/ov_SC03_108/ov_SC03_108_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_108/ov_SC03_108_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_108/ov_SC03_108_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_108/ov_SC03_108_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_108/ov_SC03_108_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_108_CHECK_SHA := config/check.ov_SC03_108.sha ov_SC03_108_SYMBOLS := config/symbols.ov_SC03_108.txt ov_SC03_108_SIG := .run/sig.ov_SC03_108.jsonl @@ -2207,6 +2274,7 @@ build/src/ov_SC03_109/ov_SC03_109_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_109/ov_SC03_109_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_109/ov_SC03_109_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_109/ov_SC03_109_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_109/ov_SC03_109_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_109_CHECK_SHA := config/check.ov_SC03_109.sha ov_SC03_109_SYMBOLS := config/symbols.ov_SC03_109.txt ov_SC03_109_SIG := .run/sig.ov_SC03_109.jsonl @@ -2239,6 +2307,7 @@ build/src/ov_SC03_110/ov_SC03_110_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_110/ov_SC03_110_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_110/ov_SC03_110_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_110/ov_SC03_110_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_110/ov_SC03_110_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_110_CHECK_SHA := config/check.ov_SC03_110.sha ov_SC03_110_SYMBOLS := config/symbols.ov_SC03_110.txt ov_SC03_110_SIG := .run/sig.ov_SC03_110.jsonl @@ -2271,6 +2340,7 @@ build/src/ov_SC03_111/ov_SC03_111_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_111/ov_SC03_111_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_111/ov_SC03_111_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_111/ov_SC03_111_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_111/ov_SC03_111_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_111_CHECK_SHA := config/check.ov_SC03_111.sha ov_SC03_111_SYMBOLS := config/symbols.ov_SC03_111.txt ov_SC03_111_SIG := .run/sig.ov_SC03_111.jsonl @@ -2303,6 +2373,7 @@ build/src/ov_SC03_112/ov_SC03_112_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_112/ov_SC03_112_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_112/ov_SC03_112_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_112/ov_SC03_112_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_112/ov_SC03_112_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_112_CHECK_SHA := config/check.ov_SC03_112.sha ov_SC03_112_SYMBOLS := config/symbols.ov_SC03_112.txt ov_SC03_112_SIG := .run/sig.ov_SC03_112.jsonl @@ -2335,6 +2406,7 @@ build/src/ov_SC03_113/ov_SC03_113_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_113/ov_SC03_113_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_113/ov_SC03_113_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_113/ov_SC03_113_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_113/ov_SC03_113_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_113_CHECK_SHA := config/check.ov_SC03_113.sha ov_SC03_113_SYMBOLS := config/symbols.ov_SC03_113.txt ov_SC03_113_SIG := .run/sig.ov_SC03_113.jsonl @@ -2367,6 +2439,7 @@ build/src/ov_SC03_114/ov_SC03_114_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_114/ov_SC03_114_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_114/ov_SC03_114_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_114/ov_SC03_114_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_114/ov_SC03_114_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_114_CHECK_SHA := config/check.ov_SC03_114.sha ov_SC03_114_SYMBOLS := config/symbols.ov_SC03_114.txt ov_SC03_114_SIG := .run/sig.ov_SC03_114.jsonl @@ -2399,6 +2472,7 @@ build/src/ov_SC03_115/ov_SC03_115_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_115/ov_SC03_115_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_115/ov_SC03_115_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_115/ov_SC03_115_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_115/ov_SC03_115_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_115_CHECK_SHA := config/check.ov_SC03_115.sha ov_SC03_115_SYMBOLS := config/symbols.ov_SC03_115.txt ov_SC03_115_SIG := .run/sig.ov_SC03_115.jsonl @@ -2431,6 +2505,7 @@ build/src/ov_SC03_116/ov_SC03_116_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_116/ov_SC03_116_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_116/ov_SC03_116_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_116/ov_SC03_116_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_116/ov_SC03_116_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_116_CHECK_SHA := config/check.ov_SC03_116.sha ov_SC03_116_SYMBOLS := config/symbols.ov_SC03_116.txt ov_SC03_116_SIG := .run/sig.ov_SC03_116.jsonl @@ -2463,6 +2538,7 @@ build/src/ov_SC03_117/ov_SC03_117_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_117/ov_SC03_117_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_117/ov_SC03_117_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_117/ov_SC03_117_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_117/ov_SC03_117_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_117_CHECK_SHA := config/check.ov_SC03_117.sha ov_SC03_117_SYMBOLS := config/symbols.ov_SC03_117.txt ov_SC03_117_SIG := .run/sig.ov_SC03_117.jsonl @@ -2495,6 +2571,7 @@ build/src/ov_SC03_118/ov_SC03_118_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_118/ov_SC03_118_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_118/ov_SC03_118_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_118/ov_SC03_118_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_118/ov_SC03_118_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_118_CHECK_SHA := config/check.ov_SC03_118.sha ov_SC03_118_SYMBOLS := config/symbols.ov_SC03_118.txt ov_SC03_118_SIG := .run/sig.ov_SC03_118.jsonl @@ -2527,6 +2604,7 @@ build/src/ov_SC03_119/ov_SC03_119_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_119/ov_SC03_119_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_119/ov_SC03_119_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_119/ov_SC03_119_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_119/ov_SC03_119_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_119_CHECK_SHA := config/check.ov_SC03_119.sha ov_SC03_119_SYMBOLS := config/symbols.ov_SC03_119.txt ov_SC03_119_SIG := .run/sig.ov_SC03_119.jsonl @@ -2559,6 +2637,7 @@ build/src/ov_SC03_121/ov_SC03_121_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_121/ov_SC03_121_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_121/ov_SC03_121_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_121/ov_SC03_121_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_121/ov_SC03_121_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_121_CHECK_SHA := config/check.ov_SC03_121.sha ov_SC03_121_SYMBOLS := config/symbols.ov_SC03_121.txt ov_SC03_121_SIG := .run/sig.ov_SC03_121.jsonl @@ -2591,6 +2670,7 @@ build/src/ov_SC03_124/ov_SC03_124_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_124/ov_SC03_124_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_124/ov_SC03_124_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_124/ov_SC03_124_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_124/ov_SC03_124_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_124_CHECK_SHA := config/check.ov_SC03_124.sha ov_SC03_124_SYMBOLS := config/symbols.ov_SC03_124.txt ov_SC03_124_SIG := .run/sig.ov_SC03_124.jsonl @@ -2623,6 +2703,7 @@ build/src/ov_SC03_125/ov_SC03_125_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_125/ov_SC03_125_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_125/ov_SC03_125_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_125/ov_SC03_125_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_125/ov_SC03_125_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_125_CHECK_SHA := config/check.ov_SC03_125.sha ov_SC03_125_SYMBOLS := config/symbols.ov_SC03_125.txt ov_SC03_125_SIG := .run/sig.ov_SC03_125.jsonl @@ -2655,6 +2736,7 @@ build/src/ov_SC03_126/ov_SC03_126_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC03_126/ov_SC03_126_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_126/ov_SC03_126_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC03_126/ov_SC03_126_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC03_126/ov_SC03_126_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC03_126_CHECK_SHA := config/check.ov_SC03_126.sha ov_SC03_126_SYMBOLS := config/symbols.ov_SC03_126.txt ov_SC03_126_SIG := .run/sig.ov_SC03_126.jsonl @@ -2687,6 +2769,7 @@ build/src/ov_SC04_002/ov_SC04_002_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_002/ov_SC04_002_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_002/ov_SC04_002_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_002/ov_SC04_002_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_002/ov_SC04_002_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_002_CHECK_SHA := config/check.ov_SC04_002.sha ov_SC04_002_SYMBOLS := config/symbols.ov_SC04_002.txt ov_SC04_002_SIG := .run/sig.ov_SC04_002.jsonl @@ -2719,6 +2802,7 @@ build/src/ov_SC04_003/ov_SC04_003_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_003/ov_SC04_003_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_003/ov_SC04_003_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_003/ov_SC04_003_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_003/ov_SC04_003_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_003_CHECK_SHA := config/check.ov_SC04_003.sha ov_SC04_003_SYMBOLS := config/symbols.ov_SC04_003.txt ov_SC04_003_SIG := .run/sig.ov_SC04_003.jsonl @@ -2751,6 +2835,7 @@ build/src/ov_SC04_004/ov_SC04_004_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_004/ov_SC04_004_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_004/ov_SC04_004_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_004/ov_SC04_004_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_004/ov_SC04_004_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_004_CHECK_SHA := config/check.ov_SC04_004.sha ov_SC04_004_SYMBOLS := config/symbols.ov_SC04_004.txt ov_SC04_004_SIG := .run/sig.ov_SC04_004.jsonl @@ -2783,6 +2868,7 @@ build/src/ov_SC04_005/ov_SC04_005_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_005/ov_SC04_005_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_005/ov_SC04_005_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_005/ov_SC04_005_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_005/ov_SC04_005_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_005_CHECK_SHA := config/check.ov_SC04_005.sha ov_SC04_005_SYMBOLS := config/symbols.ov_SC04_005.txt ov_SC04_005_SIG := .run/sig.ov_SC04_005.jsonl @@ -2815,6 +2901,7 @@ build/src/ov_SC04_006/ov_SC04_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_006/ov_SC04_006_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_006/ov_SC04_006_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_006/ov_SC04_006_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_006/ov_SC04_006_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_006_CHECK_SHA := config/check.ov_SC04_006.sha ov_SC04_006_SYMBOLS := config/symbols.ov_SC04_006.txt ov_SC04_006_SIG := .run/sig.ov_SC04_006.jsonl @@ -2847,6 +2934,7 @@ build/src/ov_SC04_007/ov_SC04_007_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_007/ov_SC04_007_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_007/ov_SC04_007_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_007/ov_SC04_007_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_007/ov_SC04_007_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_007_CHECK_SHA := config/check.ov_SC04_007.sha ov_SC04_007_SYMBOLS := config/symbols.ov_SC04_007.txt ov_SC04_007_SIG := .run/sig.ov_SC04_007.jsonl @@ -2879,6 +2967,7 @@ build/src/ov_SC04_008/ov_SC04_008_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_008/ov_SC04_008_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_008/ov_SC04_008_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_008/ov_SC04_008_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_008/ov_SC04_008_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_008_CHECK_SHA := config/check.ov_SC04_008.sha ov_SC04_008_SYMBOLS := config/symbols.ov_SC04_008.txt ov_SC04_008_SIG := .run/sig.ov_SC04_008.jsonl @@ -2911,6 +3000,7 @@ build/src/ov_SC04_009/ov_SC04_009_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_009/ov_SC04_009_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_009/ov_SC04_009_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_009/ov_SC04_009_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_009/ov_SC04_009_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_009_CHECK_SHA := config/check.ov_SC04_009.sha ov_SC04_009_SYMBOLS := config/symbols.ov_SC04_009.txt ov_SC04_009_SIG := .run/sig.ov_SC04_009.jsonl @@ -2943,6 +3033,7 @@ build/src/ov_SC04_010/ov_SC04_010_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_010/ov_SC04_010_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_010/ov_SC04_010_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_010/ov_SC04_010_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_010/ov_SC04_010_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_010_CHECK_SHA := config/check.ov_SC04_010.sha ov_SC04_010_SYMBOLS := config/symbols.ov_SC04_010.txt ov_SC04_010_SIG := .run/sig.ov_SC04_010.jsonl @@ -2975,6 +3066,7 @@ build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_011/ov_SC04_011_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_011_CHECK_SHA := config/check.ov_SC04_011.sha ov_SC04_011_SYMBOLS := config/symbols.ov_SC04_011.txt ov_SC04_011_SIG := .run/sig.ov_SC04_011.jsonl @@ -3007,6 +3099,7 @@ build/src/ov_SC04_012/ov_SC04_012_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_012/ov_SC04_012_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_012/ov_SC04_012_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_012/ov_SC04_012_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_012/ov_SC04_012_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_012_CHECK_SHA := config/check.ov_SC04_012.sha ov_SC04_012_SYMBOLS := config/symbols.ov_SC04_012.txt ov_SC04_012_SIG := .run/sig.ov_SC04_012.jsonl @@ -3039,6 +3132,7 @@ build/src/ov_SC04_015/ov_SC04_015_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_015/ov_SC04_015_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_015/ov_SC04_015_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_015/ov_SC04_015_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_015/ov_SC04_015_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_015_CHECK_SHA := config/check.ov_SC04_015.sha ov_SC04_015_SYMBOLS := config/symbols.ov_SC04_015.txt ov_SC04_015_SIG := .run/sig.ov_SC04_015.jsonl @@ -3071,6 +3165,7 @@ build/src/ov_SC04_016/ov_SC04_016_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_016/ov_SC04_016_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_016/ov_SC04_016_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_016/ov_SC04_016_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_016/ov_SC04_016_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_016_CHECK_SHA := config/check.ov_SC04_016.sha ov_SC04_016_SYMBOLS := config/symbols.ov_SC04_016.txt ov_SC04_016_SIG := .run/sig.ov_SC04_016.jsonl @@ -3103,6 +3198,7 @@ build/src/ov_SC04_020/ov_SC04_020_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_020/ov_SC04_020_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_020/ov_SC04_020_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_020/ov_SC04_020_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_020/ov_SC04_020_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_020_CHECK_SHA := config/check.ov_SC04_020.sha ov_SC04_020_SYMBOLS := config/symbols.ov_SC04_020.txt ov_SC04_020_SIG := .run/sig.ov_SC04_020.jsonl @@ -3135,6 +3231,7 @@ build/src/ov_SC04_021/ov_SC04_021_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC04_021/ov_SC04_021_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_021/ov_SC04_021_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC04_021/ov_SC04_021_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC04_021/ov_SC04_021_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC04_021_CHECK_SHA := config/check.ov_SC04_021.sha ov_SC04_021_SYMBOLS := config/symbols.ov_SC04_021.txt ov_SC04_021_SIG := .run/sig.ov_SC04_021.jsonl @@ -3167,6 +3264,7 @@ build/src/ov_SC05_001/ov_SC05_001_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_001/ov_SC05_001_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_001/ov_SC05_001_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_001/ov_SC05_001_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_001/ov_SC05_001_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_001_CHECK_SHA := config/check.ov_SC05_001.sha ov_SC05_001_SYMBOLS := config/symbols.ov_SC05_001.txt ov_SC05_001_SIG := .run/sig.ov_SC05_001.jsonl @@ -3199,6 +3297,7 @@ build/src/ov_SC05_002/ov_SC05_002_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_002/ov_SC05_002_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_002/ov_SC05_002_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_002/ov_SC05_002_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_002/ov_SC05_002_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_002_CHECK_SHA := config/check.ov_SC05_002.sha ov_SC05_002_SYMBOLS := config/symbols.ov_SC05_002.txt ov_SC05_002_SIG := .run/sig.ov_SC05_002.jsonl @@ -3231,6 +3330,7 @@ build/src/ov_SC05_003/ov_SC05_003_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_003/ov_SC05_003_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_003/ov_SC05_003_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_003/ov_SC05_003_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_003/ov_SC05_003_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_003_CHECK_SHA := config/check.ov_SC05_003.sha ov_SC05_003_SYMBOLS := config/symbols.ov_SC05_003.txt ov_SC05_003_SIG := .run/sig.ov_SC05_003.jsonl @@ -3263,6 +3363,7 @@ build/src/ov_SC05_004/ov_SC05_004_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_004/ov_SC05_004_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_004/ov_SC05_004_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_004/ov_SC05_004_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_004/ov_SC05_004_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_004_CHECK_SHA := config/check.ov_SC05_004.sha ov_SC05_004_SYMBOLS := config/symbols.ov_SC05_004.txt ov_SC05_004_SIG := .run/sig.ov_SC05_004.jsonl @@ -3295,6 +3396,7 @@ build/src/ov_SC05_005/ov_SC05_005_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_005/ov_SC05_005_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_005/ov_SC05_005_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_005/ov_SC05_005_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_005/ov_SC05_005_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_005_CHECK_SHA := config/check.ov_SC05_005.sha ov_SC05_005_SYMBOLS := config/symbols.ov_SC05_005.txt ov_SC05_005_SIG := .run/sig.ov_SC05_005.jsonl @@ -3327,6 +3429,7 @@ build/src/ov_SC05_006/ov_SC05_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_006/ov_SC05_006_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_006/ov_SC05_006_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_006/ov_SC05_006_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_006/ov_SC05_006_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_006_CHECK_SHA := config/check.ov_SC05_006.sha ov_SC05_006_SYMBOLS := config/symbols.ov_SC05_006.txt ov_SC05_006_SIG := .run/sig.ov_SC05_006.jsonl @@ -3359,6 +3462,7 @@ build/src/ov_SC05_007/ov_SC05_007_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_007/ov_SC05_007_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_007/ov_SC05_007_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_007/ov_SC05_007_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_007/ov_SC05_007_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_007_CHECK_SHA := config/check.ov_SC05_007.sha ov_SC05_007_SYMBOLS := config/symbols.ov_SC05_007.txt ov_SC05_007_SIG := .run/sig.ov_SC05_007.jsonl @@ -3391,6 +3495,7 @@ build/src/ov_SC05_008/ov_SC05_008_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_008/ov_SC05_008_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_008/ov_SC05_008_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_008/ov_SC05_008_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_008/ov_SC05_008_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_008_CHECK_SHA := config/check.ov_SC05_008.sha ov_SC05_008_SYMBOLS := config/symbols.ov_SC05_008.txt ov_SC05_008_SIG := .run/sig.ov_SC05_008.jsonl @@ -3423,6 +3528,7 @@ build/src/ov_SC05_009/ov_SC05_009_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_009/ov_SC05_009_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_009/ov_SC05_009_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_009/ov_SC05_009_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_009/ov_SC05_009_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_009_CHECK_SHA := config/check.ov_SC05_009.sha ov_SC05_009_SYMBOLS := config/symbols.ov_SC05_009.txt ov_SC05_009_SIG := .run/sig.ov_SC05_009.jsonl @@ -3455,6 +3561,7 @@ build/src/ov_SC05_010/ov_SC05_010_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_010/ov_SC05_010_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_010/ov_SC05_010_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_010/ov_SC05_010_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_010/ov_SC05_010_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_010_CHECK_SHA := config/check.ov_SC05_010.sha ov_SC05_010_SYMBOLS := config/symbols.ov_SC05_010.txt ov_SC05_010_SIG := .run/sig.ov_SC05_010.jsonl @@ -3487,6 +3594,7 @@ build/src/ov_SC05_011/ov_SC05_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_011/ov_SC05_011_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_011/ov_SC05_011_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_011/ov_SC05_011_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_011/ov_SC05_011_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_011_CHECK_SHA := config/check.ov_SC05_011.sha ov_SC05_011_SYMBOLS := config/symbols.ov_SC05_011.txt ov_SC05_011_SIG := .run/sig.ov_SC05_011.jsonl @@ -3519,6 +3627,7 @@ build/src/ov_SC05_017/ov_SC05_017_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_017/ov_SC05_017_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_017/ov_SC05_017_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_017/ov_SC05_017_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_017/ov_SC05_017_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_017_CHECK_SHA := config/check.ov_SC05_017.sha ov_SC05_017_SYMBOLS := config/symbols.ov_SC05_017.txt ov_SC05_017_SIG := .run/sig.ov_SC05_017.jsonl @@ -3551,6 +3660,7 @@ build/src/ov_SC05_018/ov_SC05_018_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_018/ov_SC05_018_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_018/ov_SC05_018_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_018/ov_SC05_018_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_018/ov_SC05_018_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_018_CHECK_SHA := config/check.ov_SC05_018.sha ov_SC05_018_SYMBOLS := config/symbols.ov_SC05_018.txt ov_SC05_018_SIG := .run/sig.ov_SC05_018.jsonl @@ -3583,6 +3693,7 @@ build/src/ov_SC05_019/ov_SC05_019_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC05_019/ov_SC05_019_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_019/ov_SC05_019_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC05_019/ov_SC05_019_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC05_019/ov_SC05_019_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC05_019_CHECK_SHA := config/check.ov_SC05_019.sha ov_SC05_019_SYMBOLS := config/symbols.ov_SC05_019.txt ov_SC05_019_SIG := .run/sig.ov_SC05_019.jsonl @@ -3615,6 +3726,7 @@ build/src/ov_SC06_006/ov_SC06_006_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_006/ov_SC06_006_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_006/ov_SC06_006_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_006/ov_SC06_006_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_006/ov_SC06_006_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_006_CHECK_SHA := config/check.ov_SC06_006.sha ov_SC06_006_SYMBOLS := config/symbols.ov_SC06_006.txt ov_SC06_006_SIG := .run/sig.ov_SC06_006.jsonl @@ -3647,6 +3759,7 @@ build/src/ov_SC06_008/ov_SC06_008_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_008/ov_SC06_008_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_008/ov_SC06_008_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_008/ov_SC06_008_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_008/ov_SC06_008_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_008_CHECK_SHA := config/check.ov_SC06_008.sha ov_SC06_008_SYMBOLS := config/symbols.ov_SC06_008.txt ov_SC06_008_SIG := .run/sig.ov_SC06_008.jsonl @@ -3679,6 +3792,7 @@ build/src/ov_SC06_010/ov_SC06_010_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_010/ov_SC06_010_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_010/ov_SC06_010_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_010/ov_SC06_010_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_010/ov_SC06_010_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_010_CHECK_SHA := config/check.ov_SC06_010.sha ov_SC06_010_SYMBOLS := config/symbols.ov_SC06_010.txt ov_SC06_010_SIG := .run/sig.ov_SC06_010.jsonl @@ -3711,6 +3825,7 @@ build/src/ov_SC06_011/ov_SC06_011_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_011/ov_SC06_011_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_011/ov_SC06_011_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_011/ov_SC06_011_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_011/ov_SC06_011_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_011_CHECK_SHA := config/check.ov_SC06_011.sha ov_SC06_011_SYMBOLS := config/symbols.ov_SC06_011.txt ov_SC06_011_SIG := .run/sig.ov_SC06_011.jsonl @@ -3743,6 +3858,7 @@ build/src/ov_SC06_013/ov_SC06_013_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_013/ov_SC06_013_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_013/ov_SC06_013_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_013/ov_SC06_013_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_013/ov_SC06_013_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_013_CHECK_SHA := config/check.ov_SC06_013.sha ov_SC06_013_SYMBOLS := config/symbols.ov_SC06_013.txt ov_SC06_013_SIG := .run/sig.ov_SC06_013.jsonl @@ -3775,6 +3891,7 @@ build/src/ov_SC06_014/ov_SC06_014_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_014/ov_SC06_014_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_014/ov_SC06_014_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_014/ov_SC06_014_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_014/ov_SC06_014_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_014_CHECK_SHA := config/check.ov_SC06_014.sha ov_SC06_014_SYMBOLS := config/symbols.ov_SC06_014.txt ov_SC06_014_SIG := .run/sig.ov_SC06_014.jsonl @@ -3807,6 +3924,7 @@ build/src/ov_SC06_015/ov_SC06_015_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_015/ov_SC06_015_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_015/ov_SC06_015_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_015/ov_SC06_015_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_015/ov_SC06_015_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_015_CHECK_SHA := config/check.ov_SC06_015.sha ov_SC06_015_SYMBOLS := config/symbols.ov_SC06_015.txt ov_SC06_015_SIG := .run/sig.ov_SC06_015.jsonl @@ -3839,6 +3957,7 @@ build/src/ov_SC06_016/ov_SC06_016_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_016/ov_SC06_016_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_016/ov_SC06_016_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_016/ov_SC06_016_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_016/ov_SC06_016_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_016_CHECK_SHA := config/check.ov_SC06_016.sha ov_SC06_016_SYMBOLS := config/symbols.ov_SC06_016.txt ov_SC06_016_SIG := .run/sig.ov_SC06_016.jsonl @@ -3871,6 +3990,7 @@ build/src/ov_SC06_018/ov_SC06_018_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_018/ov_SC06_018_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_018/ov_SC06_018_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_018/ov_SC06_018_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_018/ov_SC06_018_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_018_CHECK_SHA := config/check.ov_SC06_018.sha ov_SC06_018_SYMBOLS := config/symbols.ov_SC06_018.txt ov_SC06_018_SIG := .run/sig.ov_SC06_018.jsonl @@ -3903,6 +4023,7 @@ build/src/ov_SC06_020/ov_SC06_020_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_020/ov_SC06_020_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_020/ov_SC06_020_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_020/ov_SC06_020_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_020/ov_SC06_020_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_020_CHECK_SHA := config/check.ov_SC06_020.sha ov_SC06_020_SYMBOLS := config/symbols.ov_SC06_020.txt ov_SC06_020_SIG := .run/sig.ov_SC06_020.jsonl @@ -3935,6 +4056,7 @@ build/src/ov_SC06_022/ov_SC06_022_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_022/ov_SC06_022_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_022/ov_SC06_022_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_022/ov_SC06_022_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_022/ov_SC06_022_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_022_CHECK_SHA := config/check.ov_SC06_022.sha ov_SC06_022_SYMBOLS := config/symbols.ov_SC06_022.txt ov_SC06_022_SIG := .run/sig.ov_SC06_022.jsonl @@ -3967,6 +4089,7 @@ build/src/ov_SC06_024/ov_SC06_024_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_024/ov_SC06_024_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_024/ov_SC06_024_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_024/ov_SC06_024_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_024/ov_SC06_024_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_024_CHECK_SHA := config/check.ov_SC06_024.sha ov_SC06_024_SYMBOLS := config/symbols.ov_SC06_024.txt ov_SC06_024_SIG := .run/sig.ov_SC06_024.jsonl @@ -3999,6 +4122,7 @@ build/src/ov_SC06_025/ov_SC06_025_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_025/ov_SC06_025_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_025/ov_SC06_025_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_025/ov_SC06_025_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_025/ov_SC06_025_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_025_CHECK_SHA := config/check.ov_SC06_025.sha ov_SC06_025_SYMBOLS := config/symbols.ov_SC06_025.txt ov_SC06_025_SIG := .run/sig.ov_SC06_025.jsonl @@ -4031,6 +4155,7 @@ build/src/ov_SC06_027/ov_SC06_027_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_027/ov_SC06_027_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_027/ov_SC06_027_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_027/ov_SC06_027_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_027/ov_SC06_027_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_027_CHECK_SHA := config/check.ov_SC06_027.sha ov_SC06_027_SYMBOLS := config/symbols.ov_SC06_027.txt ov_SC06_027_SIG := .run/sig.ov_SC06_027.jsonl @@ -4063,6 +4188,7 @@ build/src/ov_SC06_029/ov_SC06_029_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_029/ov_SC06_029_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_029/ov_SC06_029_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_029/ov_SC06_029_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_029/ov_SC06_029_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_029_CHECK_SHA := config/check.ov_SC06_029.sha ov_SC06_029_SYMBOLS := config/symbols.ov_SC06_029.txt ov_SC06_029_SIG := .run/sig.ov_SC06_029.jsonl @@ -4096,6 +4222,7 @@ build/src/ov_SC06_030/ov_SC06_030_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_030/ov_SC06_030_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_030/ov_SC06_030_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 build/src/ov_SC06_030/ov_SC06_030_jr_8017C8D0.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 +build/src/ov_SC06_030/ov_SC06_030_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_030_CHECK_SHA := config/check.ov_SC06_030.sha ov_SC06_030_SYMBOLS := config/symbols.ov_SC06_030.txt ov_SC06_030_SIG := .run/sig.ov_SC06_030.jsonl @@ -4128,6 +4255,7 @@ build/src/ov_SC06_032/ov_SC06_032_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_032/ov_SC06_032_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_032/ov_SC06_032_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_032/ov_SC06_032_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_032/ov_SC06_032_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_032_CHECK_SHA := config/check.ov_SC06_032.sha ov_SC06_032_SYMBOLS := config/symbols.ov_SC06_032.txt ov_SC06_032_SIG := .run/sig.ov_SC06_032.jsonl @@ -4160,6 +4288,7 @@ build/src/ov_SC06_033/ov_SC06_033_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC06_033/ov_SC06_033_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_033/ov_SC06_033_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC06_033/ov_SC06_033_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC06_033/ov_SC06_033_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC06_033_CHECK_SHA := config/check.ov_SC06_033.sha ov_SC06_033_SYMBOLS := config/symbols.ov_SC06_033.txt ov_SC06_033_SIG := .run/sig.ov_SC06_033.jsonl @@ -4192,6 +4321,7 @@ build/src/ov_SC07_001/ov_SC07_001_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC07_001/ov_SC07_001_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_001/ov_SC07_001_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_001/ov_SC07_001_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC07_001/ov_SC07_001_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC07_001_CHECK_SHA := config/check.ov_SC07_001.sha ov_SC07_001_SYMBOLS := config/symbols.ov_SC07_001.txt ov_SC07_001_SIG := .run/sig.ov_SC07_001.jsonl @@ -4224,6 +4354,7 @@ build/src/ov_SC07_002/ov_SC07_002_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC07_002/ov_SC07_002_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_002/ov_SC07_002_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_002/ov_SC07_002_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC07_002/ov_SC07_002_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC07_002_CHECK_SHA := config/check.ov_SC07_002.sha ov_SC07_002_SYMBOLS := config/symbols.ov_SC07_002.txt ov_SC07_002_SIG := .run/sig.ov_SC07_002.jsonl @@ -4256,6 +4387,7 @@ build/src/ov_SC07_008/ov_SC07_008_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC07_008/ov_SC07_008_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_008/ov_SC07_008_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_008/ov_SC07_008_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC07_008/ov_SC07_008_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC07_008_CHECK_SHA := config/check.ov_SC07_008.sha ov_SC07_008_SYMBOLS := config/symbols.ov_SC07_008.txt ov_SC07_008_SIG := .run/sig.ov_SC07_008.jsonl @@ -4288,6 +4420,7 @@ build/src/ov_SC07_009/ov_SC07_009_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC07_009/ov_SC07_009_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_009/ov_SC07_009_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_009/ov_SC07_009_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178 +build/src/ov_SC07_009/ov_SC07_009_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC07_009_CHECK_SHA := config/check.ov_SC07_009.sha ov_SC07_009_SYMBOLS := config/symbols.ov_SC07_009.txt ov_SC07_009_SIG := .run/sig.ov_SC07_009.jsonl @@ -4316,6 +4449,7 @@ build/src/ov_SC07_006/ov_SC07_006_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC07_006/ov_SC07_006_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_006/ov_SC07_006_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_006/ov_SC07_006_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 +build/src/ov_SC07_006/ov_SC07_006_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC07_006_CHECK_SHA := config/check.ov_SC07_006.sha ov_SC07_006_SYMBOLS := config/symbols.ov_SC07_006.txt ov_SC07_006_SIG := .run/sig.ov_SC07_006.jsonl @@ -4344,6 +4478,7 @@ build/src/ov_SC07_007/ov_SC07_007_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC07_007/ov_SC07_007_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_007/ov_SC07_007_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_007/ov_SC07_007_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 +build/src/ov_SC07_007/ov_SC07_007_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC07_007_CHECK_SHA := config/check.ov_SC07_007.sha ov_SC07_007_SYMBOLS := config/symbols.ov_SC07_007.txt ov_SC07_007_SIG := .run/sig.ov_SC07_007.jsonl @@ -4371,6 +4506,7 @@ build/src/ov_SC07_010/ov_SC07_010_jr_80131340.o: JTBL_PADS := 0,0 # §8e pads ( build/src/ov_SC07_010/ov_SC07_010_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18 build/src/ov_SC07_010/ov_SC07_010_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_010/ov_SC07_010_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 +build/src/ov_SC07_010/ov_SC07_010_o0.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC07_010_CHECK_SHA := config/check.ov_SC07_010.sha ov_SC07_010_SYMBOLS := config/symbols.ov_SC07_010.txt ov_SC07_010_SIG := .run/sig.ov_SC07_010.jsonl @@ -4399,6 +4535,7 @@ build/src/ov_SC07_011/ov_SC07_011_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads ( build/src/ov_SC07_011/ov_SC07_011_jr_8013F350.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20 build/src/ov_SC07_011/ov_SC07_011_jr_80154C24.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x24 build/src/ov_SC07_011/ov_SC07_011_jr_801588CC.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x28 +build/src/ov_SC07_011/ov_SC07_011_o0c.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x70 ov_SC07_011_CHECK_SHA := config/check.ov_SC07_011.sha ov_SC07_011_SYMBOLS := config/symbols.ov_SC07_011.txt ov_SC07_011_SIG := .run/sig.ov_SC07_011.jsonl diff --git a/config/splat.ov_SC01_000.yaml b/config/splat.ov_SC01_000.yaml index 1d7e6896c..a61d01b50 100644 --- a/config/splat.ov_SC01_000.yaml +++ b/config/splat.ov_SC01_000.yaml @@ -134,7 +134,7 @@ segments: - [0x7b33c, .rodata, ov_SC01_000_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7b3a0, data, tail6] - [0x7b448, .rodata, ov_SC01_000_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7b4b4, data, tail7] + - [0x7b524, data, tail7] - [0x7b9ac, .rodata, ov_SC01_000_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7b9e0, data, tail8] - [0x7b9e4, .rodata, ov_SC01_000_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC01_001.yaml b/config/splat.ov_SC01_001.yaml index a687b2154..4bc1bb734 100644 --- a/config/splat.ov_SC01_001.yaml +++ b/config/splat.ov_SC01_001.yaml @@ -135,7 +135,7 @@ segments: - [0xc3414, .rodata, ov_SC01_001_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc3478, data, tail6] - [0xc3520, .rodata, ov_SC01_001_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc358c, data, tail7] + - [0xc35fc, data, tail7] - [0xc3a84, .rodata, ov_SC01_001_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc3ab8, data, tail8] - [0xc3abc, .rodata, ov_SC01_001_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC01_004.yaml b/config/splat.ov_SC01_004.yaml index b12b4abfe..18b66c656 100644 --- a/config/splat.ov_SC01_004.yaml +++ b/config/splat.ov_SC01_004.yaml @@ -134,7 +134,7 @@ segments: - [0x657f4, .rodata, ov_SC01_004_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65858, data, tail6] - [0x65900, .rodata, ov_SC01_004_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6596c, data, tail7] + - [0x659dc, data, tail7] - [0x65e64, .rodata, ov_SC01_004_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65e98, data, tail8] - [0x65e9c, .rodata, ov_SC01_004_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC01_005.yaml b/config/splat.ov_SC01_005.yaml index 9813f6b23..e94d1a1d0 100644 --- a/config/splat.ov_SC01_005.yaml +++ b/config/splat.ov_SC01_005.yaml @@ -134,7 +134,7 @@ segments: - [0xa2f54, .rodata, ov_SC01_005_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa2fb8, data, tail6] - [0xa3060, .rodata, ov_SC01_005_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa30cc, data, tail7] + - [0xa313c, data, tail7] - [0xa35c4, .rodata, ov_SC01_005_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa35f8, data, tail8] - [0xa35fc, .rodata, ov_SC01_005_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC01_006.yaml b/config/splat.ov_SC01_006.yaml index d04dfafdb..ffe28703f 100644 --- a/config/splat.ov_SC01_006.yaml +++ b/config/splat.ov_SC01_006.yaml @@ -134,7 +134,7 @@ segments: - [0xa2f54, .rodata, ov_SC01_006_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa2fb8, data, tail6] - [0xa3060, .rodata, ov_SC01_006_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa30cc, data, tail7] + - [0xa313c, data, tail7] - [0xa35c4, .rodata, ov_SC01_006_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa35f8, data, tail8] - [0xa35fc, .rodata, ov_SC01_006_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC01_008.yaml b/config/splat.ov_SC01_008.yaml index cdb368cf5..c77502787 100644 --- a/config/splat.ov_SC01_008.yaml +++ b/config/splat.ov_SC01_008.yaml @@ -134,7 +134,7 @@ segments: - [0x78a04, .rodata, ov_SC01_008_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78a68, data, tail6] - [0x78b10, .rodata, ov_SC01_008_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x78b7c, data, tail7] + - [0x78bec, data, tail7] - [0x79074, .rodata, ov_SC01_008_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x790a8, data, tail8] - [0x790ac, .rodata, ov_SC01_008_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC01_009.yaml b/config/splat.ov_SC01_009.yaml index 783df114f..232adda61 100644 --- a/config/splat.ov_SC01_009.yaml +++ b/config/splat.ov_SC01_009.yaml @@ -134,7 +134,7 @@ segments: - [0xc87c8, .rodata, ov_SC01_009_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc882c, data, tail6] - [0xc88d4, .rodata, ov_SC01_009_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc8940, data, tail7] + - [0xc89b0, data, tail7] - [0xc8e38, .rodata, ov_SC01_009_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc8e6c, data, tail8] - [0xc8e70, .rodata, ov_SC01_009_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC01_074.yaml b/config/splat.ov_SC01_074.yaml index dbba2be20..b3fec760c 100644 --- a/config/splat.ov_SC01_074.yaml +++ b/config/splat.ov_SC01_074.yaml @@ -134,7 +134,7 @@ segments: - [0x71858, .rodata, ov_SC01_074_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x718bc, data, tail6] - [0x71964, .rodata, ov_SC01_074_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x719d0, data, tail7] + - [0x71a40, data, tail7] - [0x71ec8, .rodata, ov_SC01_074_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71efc, data, tail8] - [0x71f00, .rodata, ov_SC01_074_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC01_080.yaml b/config/splat.ov_SC01_080.yaml index 786a53acf..40947f8c5 100644 --- a/config/splat.ov_SC01_080.yaml +++ b/config/splat.ov_SC01_080.yaml @@ -133,7 +133,7 @@ segments: - [0x9b678, .rodata, ov_SC01_080_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9b6dc, data, tail6] - [0x9b784, .rodata, ov_SC01_080_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b7f0, data, tail7] + - [0x9b860, data, tail7] - [0x9bce8, .rodata, ov_SC01_080_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9bd1c, data, tail8] - [0x9bd20, .rodata, ov_SC01_080_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC01_084.yaml b/config/splat.ov_SC01_084.yaml index 3f8ee7542..2393a9626 100644 --- a/config/splat.ov_SC01_084.yaml +++ b/config/splat.ov_SC01_084.yaml @@ -134,7 +134,7 @@ segments: - [0x9d048, .rodata, ov_SC01_084_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9d0ac, data, tail6] - [0x9d154, .rodata, ov_SC01_084_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d1c0, data, tail7] + - [0x9d230, data, tail7] - [0x9d6b8, .rodata, ov_SC01_084_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9d6ec, data, tail8] - [0x9d6f0, .rodata, ov_SC01_084_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_000.yaml b/config/splat.ov_SC02_000.yaml index f6ace03aa..ec3adb6e0 100644 --- a/config/splat.ov_SC02_000.yaml +++ b/config/splat.ov_SC02_000.yaml @@ -134,7 +134,7 @@ segments: - [0xbd89c, .rodata, ov_SC02_000_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbd900, data, tail6] - [0xbd9a8, .rodata, ov_SC02_000_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbda14, data, tail7] + - [0xbda84, data, tail7] - [0xbdf0c, .rodata, ov_SC02_000_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbdf40, data, tail8] - [0xbdf44, .rodata, ov_SC02_000_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_003.yaml b/config/splat.ov_SC02_003.yaml index 3f98895fc..7911a53f8 100644 --- a/config/splat.ov_SC02_003.yaml +++ b/config/splat.ov_SC02_003.yaml @@ -134,7 +134,7 @@ segments: - [0xbd89c, .rodata, ov_SC02_003_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbd900, data, tail6] - [0xbd9a8, .rodata, ov_SC02_003_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbda14, data, tail7] + - [0xbda84, data, tail7] - [0xbdf0c, .rodata, ov_SC02_003_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbdf40, data, tail8] - [0xbdf44, .rodata, ov_SC02_003_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_004.yaml b/config/splat.ov_SC02_004.yaml index 2213c95b5..4bd79d366 100644 --- a/config/splat.ov_SC02_004.yaml +++ b/config/splat.ov_SC02_004.yaml @@ -133,7 +133,7 @@ segments: - [0x6beac, .rodata, ov_SC02_004_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6bf10, data, tail6] - [0x6bfb8, .rodata, ov_SC02_004_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c024, data, tail7] + - [0x6c094, data, tail7] - [0x6c51c, .rodata, ov_SC02_004_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6c550, data, tail8] - [0x6c554, .rodata, ov_SC02_004_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_005.yaml b/config/splat.ov_SC02_005.yaml index f8d2c34dd..f562411e3 100644 --- a/config/splat.ov_SC02_005.yaml +++ b/config/splat.ov_SC02_005.yaml @@ -133,7 +133,7 @@ segments: - [0xb9be0, .rodata, ov_SC02_005_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb9c44, data, tail6] - [0xb9cec, .rodata, ov_SC02_005_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb9d58, data, tail7] + - [0xb9dc8, data, tail7] - [0xba250, .rodata, ov_SC02_005_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xba284, data, tail8] - [0xba288, .rodata, ov_SC02_005_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_011.yaml b/config/splat.ov_SC02_011.yaml index 4551bc83b..59527957d 100644 --- a/config/splat.ov_SC02_011.yaml +++ b/config/splat.ov_SC02_011.yaml @@ -133,7 +133,7 @@ segments: - [0xc0d3c, .rodata, ov_SC02_011_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0da0, data, tail6] - [0xc0e48, .rodata, ov_SC02_011_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc0eb4, data, tail7] + - [0xc0f24, data, tail7] - [0xc13ac, .rodata, ov_SC02_011_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc13e0, data, tail8] - [0xc13e4, .rodata, ov_SC02_011_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_015.yaml b/config/splat.ov_SC02_015.yaml index 1206aee26..00da94c37 100644 --- a/config/splat.ov_SC02_015.yaml +++ b/config/splat.ov_SC02_015.yaml @@ -133,7 +133,7 @@ segments: - [0x65f94, .rodata, ov_SC02_015_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65ff8, data, tail6] - [0x660a0, .rodata, ov_SC02_015_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6610c, data, tail7] + - [0x6617c, data, tail7] - [0x66604, .rodata, ov_SC02_015_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x66638, data, tail8] - [0x6663c, .rodata, ov_SC02_015_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_016.yaml b/config/splat.ov_SC02_016.yaml index b685d5d6a..d2f07866a 100644 --- a/config/splat.ov_SC02_016.yaml +++ b/config/splat.ov_SC02_016.yaml @@ -134,7 +134,7 @@ segments: - [0x89b74, .rodata, ov_SC02_016_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x89bd8, data, tail6] - [0x89c80, .rodata, ov_SC02_016_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x89cec, data, tail7] + - [0x89d5c, data, tail7] - [0x8a1e4, .rodata, ov_SC02_016_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8a218, data, tail8] - [0x8a21c, .rodata, ov_SC02_016_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_017.yaml b/config/splat.ov_SC02_017.yaml index e323121db..76c6fdf0b 100644 --- a/config/splat.ov_SC02_017.yaml +++ b/config/splat.ov_SC02_017.yaml @@ -134,7 +134,7 @@ segments: - [0xc5394, .rodata, ov_SC02_017_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc53f8, data, tail6] - [0xc54a0, .rodata, ov_SC02_017_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc550c, data, tail7] + - [0xc557c, data, tail7] - [0xc5a04, .rodata, ov_SC02_017_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc5a38, data, tail8] - [0xc5a3c, .rodata, ov_SC02_017_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_021.yaml b/config/splat.ov_SC02_021.yaml index 5bf7e2918..302381f9e 100644 --- a/config/splat.ov_SC02_021.yaml +++ b/config/splat.ov_SC02_021.yaml @@ -134,7 +134,7 @@ segments: - [0x68910, .rodata, ov_SC02_021_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x68974, data, tail6] - [0x68a1c, .rodata, ov_SC02_021_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x68a88, data, tail7] + - [0x68af8, data, tail7] - [0x68f80, .rodata, ov_SC02_021_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x68fb4, data, tail8] - [0x68fb8, .rodata, ov_SC02_021_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_026.yaml b/config/splat.ov_SC02_026.yaml index cb223d615..5a0764688 100644 --- a/config/splat.ov_SC02_026.yaml +++ b/config/splat.ov_SC02_026.yaml @@ -134,7 +134,7 @@ segments: - [0xa5d44, .rodata, ov_SC02_026_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa5da8, data, tail6] - [0xa5e50, .rodata, ov_SC02_026_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa5ebc, data, tail7] + - [0xa5f2c, data, tail7] - [0xa63b4, .rodata, ov_SC02_026_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa63e8, data, tail8] - [0xa63ec, .rodata, ov_SC02_026_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_027.yaml b/config/splat.ov_SC02_027.yaml index f8e53fe8e..1c08b2712 100644 --- a/config/splat.ov_SC02_027.yaml +++ b/config/splat.ov_SC02_027.yaml @@ -134,7 +134,7 @@ segments: - [0xafab0, .rodata, ov_SC02_027_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xafb14, data, tail6] - [0xafbbc, .rodata, ov_SC02_027_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xafc28, data, tail7] + - [0xafc98, data, tail7] - [0xb0120, .rodata, ov_SC02_027_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb0154, data, tail8] - [0xb0158, .rodata, ov_SC02_027_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_028.yaml b/config/splat.ov_SC02_028.yaml index 7fe5ac41b..043c865ee 100644 --- a/config/splat.ov_SC02_028.yaml +++ b/config/splat.ov_SC02_028.yaml @@ -134,7 +134,7 @@ segments: - [0xa8a34, .rodata, ov_SC02_028_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa8a98, data, tail6] - [0xa8b40, .rodata, ov_SC02_028_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa8bac, data, tail7] + - [0xa8c1c, data, tail7] - [0xa90a4, .rodata, ov_SC02_028_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa90d8, data, tail8] - [0xa90dc, .rodata, ov_SC02_028_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_031.yaml b/config/splat.ov_SC02_031.yaml index 85be56d77..92020ff2e 100644 --- a/config/splat.ov_SC02_031.yaml +++ b/config/splat.ov_SC02_031.yaml @@ -133,7 +133,7 @@ segments: - [0x8d230, .rodata, ov_SC02_031_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8d294, data, tail6] - [0x8d33c, .rodata, ov_SC02_031_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8d3a8, data, tail7] + - [0x8d418, data, tail7] - [0x8d8a0, .rodata, ov_SC02_031_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8d8d4, data, tail8] - [0x8d8d8, .rodata, ov_SC02_031_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_035.yaml b/config/splat.ov_SC02_035.yaml index a378e3314..ea9261f6e 100644 --- a/config/splat.ov_SC02_035.yaml +++ b/config/splat.ov_SC02_035.yaml @@ -134,7 +134,7 @@ segments: - [0x944f8, .rodata, ov_SC02_035_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9455c, data, tail6] - [0x94604, .rodata, ov_SC02_035_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x94670, data, tail7] + - [0x946e0, data, tail7] - [0x94b68, .rodata, ov_SC02_035_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x94b9c, data, tail8] - [0x94ba0, .rodata, ov_SC02_035_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_039.yaml b/config/splat.ov_SC02_039.yaml index 837438860..ea53e7a29 100644 --- a/config/splat.ov_SC02_039.yaml +++ b/config/splat.ov_SC02_039.yaml @@ -134,7 +134,7 @@ segments: - [0x768e4, .rodata, ov_SC02_039_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76948, data, tail6] - [0x769f0, .rodata, ov_SC02_039_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76a5c, data, tail7] + - [0x76acc, data, tail7] - [0x76f54, .rodata, ov_SC02_039_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76f88, data, tail8] - [0x76f8c, .rodata, ov_SC02_039_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC02_041.yaml b/config/splat.ov_SC02_041.yaml index fe5965e23..3be74952c 100644 --- a/config/splat.ov_SC02_041.yaml +++ b/config/splat.ov_SC02_041.yaml @@ -134,7 +134,7 @@ segments: - [0x8ec50, .rodata, ov_SC02_041_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8ecb4, data, tail6] - [0x8ed5c, .rodata, ov_SC02_041_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8edc8, data, tail7] + - [0x8ee38, data, tail7] - [0x8f2c0, .rodata, ov_SC02_041_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f2f4, data, tail8] - [0x8f2f8, .rodata, ov_SC02_041_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_001.yaml b/config/splat.ov_SC03_001.yaml index 6f15b809b..4d6aa182f 100644 --- a/config/splat.ov_SC03_001.yaml +++ b/config/splat.ov_SC03_001.yaml @@ -133,7 +133,7 @@ segments: - [0xc3d70, .rodata, ov_SC03_001_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc3dd4, data, tail6] - [0xc3e7c, .rodata, ov_SC03_001_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc3ee8, data, tail7] + - [0xc3f58, data, tail7] - [0xc43e0, .rodata, ov_SC03_001_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc4414, data, tail8] - [0xc4418, .rodata, ov_SC03_001_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_002.yaml b/config/splat.ov_SC03_002.yaml index f01bd133f..67330a653 100644 --- a/config/splat.ov_SC03_002.yaml +++ b/config/splat.ov_SC03_002.yaml @@ -134,7 +134,7 @@ segments: - [0xa12cc, .rodata, ov_SC03_002_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa1330, data, tail6] - [0xa13d8, .rodata, ov_SC03_002_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1444, data, tail7] + - [0xa14b4, data, tail7] - [0xa193c, .rodata, ov_SC03_002_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa1970, data, tail8] - [0xa1974, .rodata, ov_SC03_002_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_003.yaml b/config/splat.ov_SC03_003.yaml index 5d1ad3277..227401834 100644 --- a/config/splat.ov_SC03_003.yaml +++ b/config/splat.ov_SC03_003.yaml @@ -133,7 +133,7 @@ segments: - [0x6564c, .rodata, ov_SC03_003_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x656b0, data, tail6] - [0x65758, .rodata, ov_SC03_003_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x657c4, data, tail7] + - [0x65834, data, tail7] - [0x65cbc, .rodata, ov_SC03_003_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65cf0, data, tail8] - [0x65cf4, .rodata, ov_SC03_003_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_006.yaml b/config/splat.ov_SC03_006.yaml index 4bbcbfacf..5ff8657e1 100644 --- a/config/splat.ov_SC03_006.yaml +++ b/config/splat.ov_SC03_006.yaml @@ -133,7 +133,7 @@ segments: - [0xccf08, .rodata, ov_SC03_006_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xccf6c, data, tail6] - [0xcd014, .rodata, ov_SC03_006_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcd080, data, tail7] + - [0xcd0f0, data, tail7] - [0xcd578, .rodata, ov_SC03_006_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcd5ac, data, tail8] - [0xcd5b0, .rodata, ov_SC03_006_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_007.yaml b/config/splat.ov_SC03_007.yaml index 9fd30a31c..c4309472c 100644 --- a/config/splat.ov_SC03_007.yaml +++ b/config/splat.ov_SC03_007.yaml @@ -133,7 +133,7 @@ segments: - [0xbf890, .rodata, ov_SC03_007_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbf8f4, data, tail6] - [0xbf99c, .rodata, ov_SC03_007_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbfa08, data, tail7] + - [0xbfa78, data, tail7] - [0xbff00, .rodata, ov_SC03_007_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbff34, data, tail8] - [0xbff38, .rodata, ov_SC03_007_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_010.yaml b/config/splat.ov_SC03_010.yaml index e087baef9..365e047e3 100644 --- a/config/splat.ov_SC03_010.yaml +++ b/config/splat.ov_SC03_010.yaml @@ -134,7 +134,7 @@ segments: - [0x75b6c, .rodata, ov_SC03_010_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x75bd0, data, tail6] - [0x75c78, .rodata, ov_SC03_010_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75ce4, data, tail7] + - [0x75d54, data, tail7] - [0x761dc, .rodata, ov_SC03_010_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76210, data, tail8] - [0x76214, .rodata, ov_SC03_010_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_011.yaml b/config/splat.ov_SC03_011.yaml index d270c71f1..d131c99f2 100644 --- a/config/splat.ov_SC03_011.yaml +++ b/config/splat.ov_SC03_011.yaml @@ -133,7 +133,7 @@ segments: - [0x77ddc, .rodata, ov_SC03_011_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77e40, data, tail6] - [0x77ee8, .rodata, ov_SC03_011_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77f54, data, tail7] + - [0x77fc4, data, tail7] - [0x7844c, .rodata, ov_SC03_011_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x78480, data, tail8] - [0x784f4, .rodata, ov_SC03_011_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_012.yaml b/config/splat.ov_SC03_012.yaml index 5c4afd347..90841c957 100644 --- a/config/splat.ov_SC03_012.yaml +++ b/config/splat.ov_SC03_012.yaml @@ -133,7 +133,7 @@ segments: - [0x6ac38, .rodata, ov_SC03_012_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6ac9c, data, tail6] - [0x6ad44, .rodata, ov_SC03_012_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6adb0, data, tail7] + - [0x6ae20, data, tail7] - [0x6b2a8, .rodata, ov_SC03_012_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b2dc, data, tail8] - [0x6b2e0, .rodata, ov_SC03_012_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_013.yaml b/config/splat.ov_SC03_013.yaml index 4ebc3d6c9..71c931185 100644 --- a/config/splat.ov_SC03_013.yaml +++ b/config/splat.ov_SC03_013.yaml @@ -134,7 +134,7 @@ segments: - [0x82ed0, .rodata, ov_SC03_013_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x82f34, data, tail6] - [0x82fdc, .rodata, ov_SC03_013_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x83048, data, tail7] + - [0x830b8, data, tail7] - [0x83540, .rodata, ov_SC03_013_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x83574, data, tail8] - [0x83578, .rodata, ov_SC03_013_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_014.yaml b/config/splat.ov_SC03_014.yaml index b92231871..72b417677 100644 --- a/config/splat.ov_SC03_014.yaml +++ b/config/splat.ov_SC03_014.yaml @@ -138,7 +138,7 @@ segments: - [0xc02a4, .rodata, ov_SC03_014_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0308, data, tail6] - [0xc03b0, .rodata, ov_SC03_014_o0e] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc041c, data, tail7] + - [0xc048c, data, tail7] - [0xc0914, .rodata, ov_SC03_014_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0948, data, tail8] - [0xc094c, .rodata, ov_SC03_014_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_015.yaml b/config/splat.ov_SC03_015.yaml index 1315e2bdb..0b345190f 100644 --- a/config/splat.ov_SC03_015.yaml +++ b/config/splat.ov_SC03_015.yaml @@ -138,7 +138,7 @@ segments: - [0xc02a4, .rodata, ov_SC03_015_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0308, data, tail6] - [0xc03b0, .rodata, ov_SC03_015_o0e] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc041c, data, tail7] + - [0xc048c, data, tail7] - [0xc0914, .rodata, ov_SC03_015_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0948, data, tail8] - [0xc094c, .rodata, ov_SC03_015_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_023.yaml b/config/splat.ov_SC03_023.yaml index cb885d9d4..8212b8423 100644 --- a/config/splat.ov_SC03_023.yaml +++ b/config/splat.ov_SC03_023.yaml @@ -133,7 +133,7 @@ segments: - [0x6e87c, .rodata, ov_SC03_023_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6e8e0, data, tail6] - [0x6e988, .rodata, ov_SC03_023_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6e9f4, data, tail7] + - [0x6ea64, data, tail7] - [0x6eeec, .rodata, ov_SC03_023_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6ef20, data, tail8] - [0x6ef24, .rodata, ov_SC03_023_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_024.yaml b/config/splat.ov_SC03_024.yaml index f0c90a7cd..1349f1822 100644 --- a/config/splat.ov_SC03_024.yaml +++ b/config/splat.ov_SC03_024.yaml @@ -134,7 +134,7 @@ segments: - [0x96d04, .rodata, ov_SC03_024_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x96d68, data, tail6] - [0x96e10, .rodata, ov_SC03_024_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x96e7c, data, tail7] + - [0x96eec, data, tail7] - [0x97374, .rodata, ov_SC03_024_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x973a8, data, tail8] - [0x973ac, .rodata, ov_SC03_024_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_028.yaml b/config/splat.ov_SC03_028.yaml index eaa7eacd7..0dca169a0 100644 --- a/config/splat.ov_SC03_028.yaml +++ b/config/splat.ov_SC03_028.yaml @@ -133,7 +133,7 @@ segments: - [0xc0e8c, .rodata, ov_SC03_028_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc0ef0, data, tail6] - [0xc0f98, .rodata, ov_SC03_028_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc1004, data, tail7] + - [0xc1074, data, tail7] - [0xc14fc, .rodata, ov_SC03_028_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc1530, data, tail8] - [0xc1534, .rodata, ov_SC03_028_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_029.yaml b/config/splat.ov_SC03_029.yaml index cb57a866c..5e11a0555 100644 --- a/config/splat.ov_SC03_029.yaml +++ b/config/splat.ov_SC03_029.yaml @@ -134,7 +134,7 @@ segments: - [0xaefc0, .rodata, ov_SC03_029_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaf024, data, tail6] - [0xaf0cc, .rodata, ov_SC03_029_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaf138, data, tail7] + - [0xaf1a8, data, tail7] - [0xaf630, .rodata, ov_SC03_029_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaf664, data, tail8] - [0xaf668, .rodata, ov_SC03_029_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_030.yaml b/config/splat.ov_SC03_030.yaml index 06b855355..00bbb32ce 100644 --- a/config/splat.ov_SC03_030.yaml +++ b/config/splat.ov_SC03_030.yaml @@ -132,7 +132,7 @@ segments: - [0xb7664, .rodata, ov_SC03_030_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb76c8, data, tail6] - [0xb7770, .rodata, ov_SC03_030_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb77dc, data, tail7] + - [0xb784c, data, tail7] - [0xb7cd4, .rodata, ov_SC03_030_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7d08, data, tail8] - [0xb7d7c, .rodata, ov_SC03_030_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_031.yaml b/config/splat.ov_SC03_031.yaml index 4aacacc23..044f03416 100644 --- a/config/splat.ov_SC03_031.yaml +++ b/config/splat.ov_SC03_031.yaml @@ -134,7 +134,7 @@ segments: - [0x9bb08, .rodata, ov_SC03_031_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9bb6c, data, tail6] - [0x9bc14, .rodata, ov_SC03_031_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9bc80, data, tail7] + - [0x9bcf0, data, tail7] - [0x9c178, .rodata, ov_SC03_031_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9c1ac, data, tail8] - [0x9c1b0, .rodata, ov_SC03_031_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_089.yaml b/config/splat.ov_SC03_089.yaml index 39f7202c8..2d8de4506 100644 --- a/config/splat.ov_SC03_089.yaml +++ b/config/splat.ov_SC03_089.yaml @@ -134,7 +134,7 @@ segments: - [0x9c374, .rodata, ov_SC03_089_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9c3d8, data, tail6] - [0x9c480, .rodata, ov_SC03_089_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9c4ec, data, tail7] + - [0x9c55c, data, tail7] - [0x9c9e4, .rodata, ov_SC03_089_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9ca18, data, tail8] - [0x9ca1c, .rodata, ov_SC03_089_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_090.yaml b/config/splat.ov_SC03_090.yaml index 6b33eb421..520822fc2 100644 --- a/config/splat.ov_SC03_090.yaml +++ b/config/splat.ov_SC03_090.yaml @@ -134,7 +134,7 @@ segments: - [0xa17e0, .rodata, ov_SC03_090_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa1844, data, tail6] - [0xa18ec, .rodata, ov_SC03_090_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa1958, data, tail7] + - [0xa19c8, data, tail7] - [0xa1e50, .rodata, ov_SC03_090_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa1e84, data, tail8] - [0xa1e88, .rodata, ov_SC03_090_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_091.yaml b/config/splat.ov_SC03_091.yaml index b50eb5c84..936715c69 100644 --- a/config/splat.ov_SC03_091.yaml +++ b/config/splat.ov_SC03_091.yaml @@ -135,7 +135,7 @@ segments: - [0xa7eac, .rodata, ov_SC03_091_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa7f10, data, tail6] - [0xa7fb8, .rodata, ov_SC03_091_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa8024, data, tail7] + - [0xa8094, data, tail7] - [0xa851c, .rodata, ov_SC03_091_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa8550, data, tail8] - [0xa8554, .rodata, ov_SC03_091_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_092.yaml b/config/splat.ov_SC03_092.yaml index ee1ee06dd..6e3c13bb5 100644 --- a/config/splat.ov_SC03_092.yaml +++ b/config/splat.ov_SC03_092.yaml @@ -133,7 +133,7 @@ segments: - [0x88a84, .rodata, ov_SC03_092_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x88ae8, data, tail6] - [0x88b90, .rodata, ov_SC03_092_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x88bfc, data, tail7] + - [0x88c6c, data, tail7] - [0x890f4, .rodata, ov_SC03_092_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x89128, data, tail8] - [0x8912c, .rodata, ov_SC03_092_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_093.yaml b/config/splat.ov_SC03_093.yaml index 89fa65b47..f017e9070 100644 --- a/config/splat.ov_SC03_093.yaml +++ b/config/splat.ov_SC03_093.yaml @@ -134,7 +134,7 @@ segments: - [0xa1ed8, .rodata, ov_SC03_093_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa1f3c, data, tail6] - [0xa1fe4, .rodata, ov_SC03_093_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa2050, data, tail7] + - [0xa20c0, data, tail7] - [0xa2548, .rodata, ov_SC03_093_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa257c, data, tail8] - [0xa2580, .rodata, ov_SC03_093_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_094.yaml b/config/splat.ov_SC03_094.yaml index 4aa9e1feb..9aaa75c54 100644 --- a/config/splat.ov_SC03_094.yaml +++ b/config/splat.ov_SC03_094.yaml @@ -134,7 +134,7 @@ segments: - [0xa8d14, .rodata, ov_SC03_094_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa8d78, data, tail6] - [0xa8e20, .rodata, ov_SC03_094_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa8e8c, data, tail7] + - [0xa8efc, data, tail7] - [0xa9384, .rodata, ov_SC03_094_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa93b8, data, tail8] - [0xa93bc, .rodata, ov_SC03_094_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_095.yaml b/config/splat.ov_SC03_095.yaml index ca6eddbca..0a141c011 100644 --- a/config/splat.ov_SC03_095.yaml +++ b/config/splat.ov_SC03_095.yaml @@ -134,7 +134,7 @@ segments: - [0x71940, .rodata, ov_SC03_095_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x719a4, data, tail6] - [0x71a4c, .rodata, ov_SC03_095_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71ab8, data, tail7] + - [0x71b28, data, tail7] - [0x71fb0, .rodata, ov_SC03_095_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71fe4, data, tail8] - [0x71fe8, .rodata, ov_SC03_095_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_096.yaml b/config/splat.ov_SC03_096.yaml index 4ad779c32..26d8487d7 100644 --- a/config/splat.ov_SC03_096.yaml +++ b/config/splat.ov_SC03_096.yaml @@ -134,7 +134,7 @@ segments: - [0x703f4, .rodata, ov_SC03_096_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70458, data, tail6] - [0x70500, .rodata, ov_SC03_096_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7056c, data, tail7] + - [0x705dc, data, tail7] - [0x70a64, .rodata, ov_SC03_096_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70a98, data, tail8] - [0x70a9c, .rodata, ov_SC03_096_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_097.yaml b/config/splat.ov_SC03_097.yaml index 8bbb7fb30..7500873ab 100644 --- a/config/splat.ov_SC03_097.yaml +++ b/config/splat.ov_SC03_097.yaml @@ -134,7 +134,7 @@ segments: - [0x80464, .rodata, ov_SC03_097_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x804c8, data, tail6] - [0x80570, .rodata, ov_SC03_097_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x805dc, data, tail7] + - [0x8064c, data, tail7] - [0x80ad4, .rodata, ov_SC03_097_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x80b08, data, tail8] - [0x80b0c, .rodata, ov_SC03_097_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_098.yaml b/config/splat.ov_SC03_098.yaml index fd22fd146..f11f80ccf 100644 --- a/config/splat.ov_SC03_098.yaml +++ b/config/splat.ov_SC03_098.yaml @@ -134,7 +134,7 @@ segments: - [0x9b0e8, .rodata, ov_SC03_098_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9b14c, data, tail6] - [0x9b1f4, .rodata, ov_SC03_098_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9b260, data, tail7] + - [0x9b2d0, data, tail7] - [0x9b758, .rodata, ov_SC03_098_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9b78c, data, tail8] - [0x9b790, .rodata, ov_SC03_098_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_099.yaml b/config/splat.ov_SC03_099.yaml index 097367d46..8b4a86439 100644 --- a/config/splat.ov_SC03_099.yaml +++ b/config/splat.ov_SC03_099.yaml @@ -134,7 +134,7 @@ segments: - [0x94dbc, .rodata, ov_SC03_099_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x94e20, data, tail6] - [0x94ec8, .rodata, ov_SC03_099_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x94f34, data, tail7] + - [0x94fa4, data, tail7] - [0x9542c, .rodata, ov_SC03_099_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x95460, data, tail8] - [0x95464, .rodata, ov_SC03_099_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_100.yaml b/config/splat.ov_SC03_100.yaml index 28af8da3b..413d37ccf 100644 --- a/config/splat.ov_SC03_100.yaml +++ b/config/splat.ov_SC03_100.yaml @@ -134,7 +134,7 @@ segments: - [0x9e040, .rodata, ov_SC03_100_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9e0a4, data, tail6] - [0x9e14c, .rodata, ov_SC03_100_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9e1b8, data, tail7] + - [0x9e228, data, tail7] - [0x9e6b0, .rodata, ov_SC03_100_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9e6e4, data, tail8] - [0x9e6e8, .rodata, ov_SC03_100_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_101.yaml b/config/splat.ov_SC03_101.yaml index c39c211c7..cda195ba0 100644 --- a/config/splat.ov_SC03_101.yaml +++ b/config/splat.ov_SC03_101.yaml @@ -134,7 +134,7 @@ segments: - [0x73908, .rodata, ov_SC03_101_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7396c, data, tail6] - [0x73a14, .rodata, ov_SC03_101_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73a80, data, tail7] + - [0x73af0, data, tail7] - [0x73f78, .rodata, ov_SC03_101_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73fac, data, tail8] - [0x73fb0, .rodata, ov_SC03_101_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_102.yaml b/config/splat.ov_SC03_102.yaml index 6333e2ed1..e309cf8db 100644 --- a/config/splat.ov_SC03_102.yaml +++ b/config/splat.ov_SC03_102.yaml @@ -134,7 +134,7 @@ segments: - [0x8f584, .rodata, ov_SC03_102_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f5e8, data, tail6] - [0x8f690, .rodata, ov_SC03_102_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f6fc, data, tail7] + - [0x8f76c, data, tail7] - [0x8fbf4, .rodata, ov_SC03_102_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8fc28, data, tail8] - [0x8fc2c, .rodata, ov_SC03_102_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_103.yaml b/config/splat.ov_SC03_103.yaml index e80a30dac..77a08a5d1 100644 --- a/config/splat.ov_SC03_103.yaml +++ b/config/splat.ov_SC03_103.yaml @@ -133,7 +133,7 @@ segments: - [0x9a738, .rodata, ov_SC03_103_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9a79c, data, tail6] - [0x9a844, .rodata, ov_SC03_103_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9a8b0, data, tail7] + - [0x9a920, data, tail7] - [0x9ada8, .rodata, ov_SC03_103_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9addc, data, tail8] - [0x9ae50, .rodata, ov_SC03_103_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_104.yaml b/config/splat.ov_SC03_104.yaml index b2e78c2da..f3f4069ee 100644 --- a/config/splat.ov_SC03_104.yaml +++ b/config/splat.ov_SC03_104.yaml @@ -134,7 +134,7 @@ segments: - [0x95c98, .rodata, ov_SC03_104_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x95cfc, data, tail6] - [0x95da4, .rodata, ov_SC03_104_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x95e10, data, tail7] + - [0x95e80, data, tail7] - [0x96308, .rodata, ov_SC03_104_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9633c, data, tail8] - [0x96340, .rodata, ov_SC03_104_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_105.yaml b/config/splat.ov_SC03_105.yaml index a3b9035d0..d5ee83936 100644 --- a/config/splat.ov_SC03_105.yaml +++ b/config/splat.ov_SC03_105.yaml @@ -134,7 +134,7 @@ segments: - [0x8ef90, .rodata, ov_SC03_105_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8eff4, data, tail6] - [0x8f09c, .rodata, ov_SC03_105_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f108, data, tail7] + - [0x8f178, data, tail7] - [0x8f600, .rodata, ov_SC03_105_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f634, data, tail8] - [0x8f638, .rodata, ov_SC03_105_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_108.yaml b/config/splat.ov_SC03_108.yaml index 1ec5f5067..db823e7fb 100644 --- a/config/splat.ov_SC03_108.yaml +++ b/config/splat.ov_SC03_108.yaml @@ -134,7 +134,7 @@ segments: - [0x77498, .rodata, ov_SC03_108_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x774fc, data, tail6] - [0x775a4, .rodata, ov_SC03_108_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77610, data, tail7] + - [0x77680, data, tail7] - [0x77b08, .rodata, ov_SC03_108_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77b3c, data, tail8] - [0x77b40, .rodata, ov_SC03_108_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_109.yaml b/config/splat.ov_SC03_109.yaml index 4bd29603a..d549d8729 100644 --- a/config/splat.ov_SC03_109.yaml +++ b/config/splat.ov_SC03_109.yaml @@ -134,7 +134,7 @@ segments: - [0x6ffa8, .rodata, ov_SC03_109_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7000c, data, tail6] - [0x700b4, .rodata, ov_SC03_109_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70120, data, tail7] + - [0x70190, data, tail7] - [0x70618, .rodata, ov_SC03_109_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7064c, data, tail8] - [0x70650, .rodata, ov_SC03_109_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_110.yaml b/config/splat.ov_SC03_110.yaml index 86f0162e5..efb66d871 100644 --- a/config/splat.ov_SC03_110.yaml +++ b/config/splat.ov_SC03_110.yaml @@ -134,7 +134,7 @@ segments: - [0x77c44, .rodata, ov_SC03_110_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77ca8, data, tail6] - [0x77d50, .rodata, ov_SC03_110_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77dbc, data, tail7] + - [0x77e2c, data, tail7] - [0x782b4, .rodata, ov_SC03_110_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x782e8, data, tail8] - [0x782ec, .rodata, ov_SC03_110_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_111.yaml b/config/splat.ov_SC03_111.yaml index 7efac8007..28b610f14 100644 --- a/config/splat.ov_SC03_111.yaml +++ b/config/splat.ov_SC03_111.yaml @@ -134,7 +134,7 @@ segments: - [0x8f1c4, .rodata, ov_SC03_111_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f228, data, tail6] - [0x8f2d0, .rodata, ov_SC03_111_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8f33c, data, tail7] + - [0x8f3ac, data, tail7] - [0x8f834, .rodata, ov_SC03_111_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f868, data, tail8] - [0x8f86c, .rodata, ov_SC03_111_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_112.yaml b/config/splat.ov_SC03_112.yaml index 0fc9eb51c..84af0ce03 100644 --- a/config/splat.ov_SC03_112.yaml +++ b/config/splat.ov_SC03_112.yaml @@ -134,7 +134,7 @@ segments: - [0x8292c, .rodata, ov_SC03_112_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x82990, data, tail6] - [0x82a38, .rodata, ov_SC03_112_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82aa4, data, tail7] + - [0x82b14, data, tail7] - [0x82f9c, .rodata, ov_SC03_112_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x82fd0, data, tail8] - [0x82fd4, .rodata, ov_SC03_112_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_113.yaml b/config/splat.ov_SC03_113.yaml index bda666f76..698c5b22b 100644 --- a/config/splat.ov_SC03_113.yaml +++ b/config/splat.ov_SC03_113.yaml @@ -134,7 +134,7 @@ segments: - [0x7b5b4, .rodata, ov_SC03_113_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7b618, data, tail6] - [0x7b6c0, .rodata, ov_SC03_113_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7b72c, data, tail7] + - [0x7b79c, data, tail7] - [0x7bc24, .rodata, ov_SC03_113_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7bc58, data, tail8] - [0x7bc5c, .rodata, ov_SC03_113_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_114.yaml b/config/splat.ov_SC03_114.yaml index 9203d947f..50eb45b3e 100644 --- a/config/splat.ov_SC03_114.yaml +++ b/config/splat.ov_SC03_114.yaml @@ -134,7 +134,7 @@ segments: - [0x7f2c0, .rodata, ov_SC03_114_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7f324, data, tail6] - [0x7f3cc, .rodata, ov_SC03_114_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7f438, data, tail7] + - [0x7f4a8, data, tail7] - [0x7f930, .rodata, ov_SC03_114_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7f964, data, tail8] - [0x7f968, .rodata, ov_SC03_114_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_115.yaml b/config/splat.ov_SC03_115.yaml index fd74ac944..2f2236513 100644 --- a/config/splat.ov_SC03_115.yaml +++ b/config/splat.ov_SC03_115.yaml @@ -134,7 +134,7 @@ segments: - [0x6ac34, .rodata, ov_SC03_115_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6ac98, data, tail6] - [0x6ad40, .rodata, ov_SC03_115_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6adac, data, tail7] + - [0x6ae1c, data, tail7] - [0x6b2a4, .rodata, ov_SC03_115_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6b2d8, data, tail8] - [0x6b2dc, .rodata, ov_SC03_115_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_116.yaml b/config/splat.ov_SC03_116.yaml index 74e3bc554..67e3ecf21 100644 --- a/config/splat.ov_SC03_116.yaml +++ b/config/splat.ov_SC03_116.yaml @@ -133,7 +133,7 @@ segments: - [0x6d7d0, .rodata, ov_SC03_116_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6d834, data, tail6] - [0x6d8dc, .rodata, ov_SC03_116_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6d948, data, tail7] + - [0x6d9b8, data, tail7] - [0x6de40, .rodata, ov_SC03_116_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6de74, data, tail8] - [0x6de78, .rodata, ov_SC03_116_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_117.yaml b/config/splat.ov_SC03_117.yaml index 1475c5193..15029d998 100644 --- a/config/splat.ov_SC03_117.yaml +++ b/config/splat.ov_SC03_117.yaml @@ -134,7 +134,7 @@ segments: - [0xa3e70, .rodata, ov_SC03_117_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa3ed4, data, tail6] - [0xa3f7c, .rodata, ov_SC03_117_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa3fe8, data, tail7] + - [0xa4058, data, tail7] - [0xa44e0, .rodata, ov_SC03_117_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa4514, data, tail8] - [0xa4518, .rodata, ov_SC03_117_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_118.yaml b/config/splat.ov_SC03_118.yaml index f27bc8852..ff7b9179d 100644 --- a/config/splat.ov_SC03_118.yaml +++ b/config/splat.ov_SC03_118.yaml @@ -134,7 +134,7 @@ segments: - [0xa9dcc, .rodata, ov_SC03_118_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa9e30, data, tail6] - [0xa9ed8, .rodata, ov_SC03_118_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa9f44, data, tail7] + - [0xa9fb4, data, tail7] - [0xaa43c, .rodata, ov_SC03_118_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaa470, data, tail8] - [0xaa474, .rodata, ov_SC03_118_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_119.yaml b/config/splat.ov_SC03_119.yaml index 6f4ce8af7..791d37b25 100644 --- a/config/splat.ov_SC03_119.yaml +++ b/config/splat.ov_SC03_119.yaml @@ -134,7 +134,7 @@ segments: - [0xa9dcc, .rodata, ov_SC03_119_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa9e30, data, tail6] - [0xa9ed8, .rodata, ov_SC03_119_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa9f44, data, tail7] + - [0xa9fb4, data, tail7] - [0xaa43c, .rodata, ov_SC03_119_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaa470, data, tail8] - [0xaa474, .rodata, ov_SC03_119_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_121.yaml b/config/splat.ov_SC03_121.yaml index feed58caa..0ab7baa97 100644 --- a/config/splat.ov_SC03_121.yaml +++ b/config/splat.ov_SC03_121.yaml @@ -134,7 +134,7 @@ segments: - [0x848d4, .rodata, ov_SC03_121_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x84938, data, tail6] - [0x849e0, .rodata, ov_SC03_121_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x84a4c, data, tail7] + - [0x84abc, data, tail7] - [0x84f44, .rodata, ov_SC03_121_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x84f78, data, tail8] - [0x84f7c, .rodata, ov_SC03_121_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_124.yaml b/config/splat.ov_SC03_124.yaml index 08f6399e8..d66312d55 100644 --- a/config/splat.ov_SC03_124.yaml +++ b/config/splat.ov_SC03_124.yaml @@ -133,7 +133,7 @@ segments: - [0xb7028, .rodata, ov_SC03_124_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb708c, data, tail6] - [0xb7134, .rodata, ov_SC03_124_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb71a0, data, tail7] + - [0xb7210, data, tail7] - [0xb7698, .rodata, ov_SC03_124_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb76cc, data, tail8] - [0xb76d0, .rodata, ov_SC03_124_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_125.yaml b/config/splat.ov_SC03_125.yaml index ec28e5087..16657be14 100644 --- a/config/splat.ov_SC03_125.yaml +++ b/config/splat.ov_SC03_125.yaml @@ -134,7 +134,7 @@ segments: - [0x99d14, .rodata, ov_SC03_125_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x99d78, data, tail6] - [0x99e20, .rodata, ov_SC03_125_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x99e8c, data, tail7] + - [0x99efc, data, tail7] - [0x9a384, .rodata, ov_SC03_125_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9a3b8, data, tail8] - [0x9a3bc, .rodata, ov_SC03_125_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC03_126.yaml b/config/splat.ov_SC03_126.yaml index aa0e9ef01..658ec1c35 100644 --- a/config/splat.ov_SC03_126.yaml +++ b/config/splat.ov_SC03_126.yaml @@ -134,7 +134,7 @@ segments: - [0x65600, .rodata, ov_SC03_126_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65664, data, tail6] - [0x6570c, .rodata, ov_SC03_126_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65778, data, tail7] + - [0x657e8, data, tail7] - [0x65c70, .rodata, ov_SC03_126_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65ca4, data, tail8] - [0x65ca8, .rodata, ov_SC03_126_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_000.yaml b/config/splat.ov_SC04_000.yaml index 292a7c9be..46e537de8 100644 --- a/config/splat.ov_SC04_000.yaml +++ b/config/splat.ov_SC04_000.yaml @@ -134,7 +134,7 @@ segments: - [0x7f67c, .rodata, ov_SC04_000_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7f6e0, data, tail6] - [0x7f788, .rodata, ov_SC04_000_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7f7f4, data, tail7] + - [0x7f864, data, tail7] - [0x7fcec, .rodata, ov_SC04_000_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7fd20, data, tail8] - [0x7fd24, .rodata, ov_SC04_000_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_002.yaml b/config/splat.ov_SC04_002.yaml index e8c77cc33..1385b2533 100644 --- a/config/splat.ov_SC04_002.yaml +++ b/config/splat.ov_SC04_002.yaml @@ -134,7 +134,7 @@ segments: - [0x969cc, .rodata, ov_SC04_002_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x96a30, data, tail6] - [0x96ad8, .rodata, ov_SC04_002_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x96b44, data, tail7] + - [0x96bb4, data, tail7] - [0x9703c, .rodata, ov_SC04_002_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x97070, data, tail8] - [0x97074, .rodata, ov_SC04_002_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_003.yaml b/config/splat.ov_SC04_003.yaml index 2b771918f..1d4877ab0 100644 --- a/config/splat.ov_SC04_003.yaml +++ b/config/splat.ov_SC04_003.yaml @@ -134,7 +134,7 @@ segments: - [0x71648, .rodata, ov_SC04_003_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x716ac, data, tail6] - [0x71754, .rodata, ov_SC04_003_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x717c0, data, tail7] + - [0x71830, data, tail7] - [0x71cb8, .rodata, ov_SC04_003_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71cec, data, tail8] - [0x71cf0, .rodata, ov_SC04_003_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_004.yaml b/config/splat.ov_SC04_004.yaml index ec5eab871..c40083df8 100644 --- a/config/splat.ov_SC04_004.yaml +++ b/config/splat.ov_SC04_004.yaml @@ -133,7 +133,7 @@ segments: - [0x89444, .rodata, ov_SC04_004_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x894a8, data, tail6] - [0x89550, .rodata, ov_SC04_004_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x895bc, data, tail7] + - [0x8962c, data, tail7] - [0x89ab4, .rodata, ov_SC04_004_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x89ae8, data, tail8] - [0x89aec, .rodata, ov_SC04_004_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_005.yaml b/config/splat.ov_SC04_005.yaml index 1071d35f2..2743e20f6 100644 --- a/config/splat.ov_SC04_005.yaml +++ b/config/splat.ov_SC04_005.yaml @@ -134,7 +134,7 @@ segments: - [0x97608, .rodata, ov_SC04_005_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9766c, data, tail6] - [0x97714, .rodata, ov_SC04_005_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x97780, data, tail7] + - [0x977f0, data, tail7] - [0x97c78, .rodata, ov_SC04_005_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x97cac, data, tail8] - [0x97cb0, .rodata, ov_SC04_005_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_006.yaml b/config/splat.ov_SC04_006.yaml index 4bd6ab35d..bb8f92362 100644 --- a/config/splat.ov_SC04_006.yaml +++ b/config/splat.ov_SC04_006.yaml @@ -134,7 +134,7 @@ segments: - [0x738b0, .rodata, ov_SC04_006_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73914, data, tail6] - [0x739bc, .rodata, ov_SC04_006_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73a28, data, tail7] + - [0x73a98, data, tail7] - [0x73f20, .rodata, ov_SC04_006_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73f54, data, tail8] - [0x73f58, .rodata, ov_SC04_006_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_007.yaml b/config/splat.ov_SC04_007.yaml index dd0701422..ec05676f2 100644 --- a/config/splat.ov_SC04_007.yaml +++ b/config/splat.ov_SC04_007.yaml @@ -134,7 +134,7 @@ segments: - [0x8ae6c, .rodata, ov_SC04_007_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8aed0, data, tail6] - [0x8af78, .rodata, ov_SC04_007_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8afe4, data, tail7] + - [0x8b054, data, tail7] - [0x8b4dc, .rodata, ov_SC04_007_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8b510, data, tail8] - [0x8b514, .rodata, ov_SC04_007_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_008.yaml b/config/splat.ov_SC04_008.yaml index fa8eb75e4..b39aae9d3 100644 --- a/config/splat.ov_SC04_008.yaml +++ b/config/splat.ov_SC04_008.yaml @@ -132,7 +132,7 @@ segments: - [0x67b54, .rodata, ov_SC04_008_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x67bb8, data, tail6] - [0x67c60, .rodata, ov_SC04_008_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x67ccc, data, tail7] + - [0x67d3c, data, tail7] - [0x681c4, .rodata, ov_SC04_008_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x681f8, data, tail8] - [0x681fc, .rodata, ov_SC04_008_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_009.yaml b/config/splat.ov_SC04_009.yaml index 823a73a69..5b886bb18 100644 --- a/config/splat.ov_SC04_009.yaml +++ b/config/splat.ov_SC04_009.yaml @@ -134,7 +134,7 @@ segments: - [0x6dd68, .rodata, ov_SC04_009_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6ddcc, data, tail6] - [0x6de74, .rodata, ov_SC04_009_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6dee0, data, tail7] + - [0x6df50, data, tail7] - [0x6e3d8, .rodata, ov_SC04_009_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6e40c, data, tail8] - [0x6e410, .rodata, ov_SC04_009_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_010.yaml b/config/splat.ov_SC04_010.yaml index e552c9954..cc6773e2f 100644 --- a/config/splat.ov_SC04_010.yaml +++ b/config/splat.ov_SC04_010.yaml @@ -134,7 +134,7 @@ segments: - [0x651f4, .rodata, ov_SC04_010_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65258, data, tail6] - [0x65300, .rodata, ov_SC04_010_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6536c, data, tail7] + - [0x653dc, data, tail7] - [0x65864, .rodata, ov_SC04_010_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65898, data, tail8] - [0x6589c, .rodata, ov_SC04_010_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_011.yaml b/config/splat.ov_SC04_011.yaml index 7c13c5275..cd1625b98 100644 --- a/config/splat.ov_SC04_011.yaml +++ b/config/splat.ov_SC04_011.yaml @@ -134,7 +134,7 @@ segments: - [0xc4790, .rodata, ov_SC04_011_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc47f4, data, tail6] - [0xc489c, .rodata, ov_SC04_011_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc4908, data, tail7] + - [0xc4978, data, tail7] - [0xc4e00, .rodata, ov_SC04_011_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc4e34, data, tail8] - [0xc4e38, .rodata, ov_SC04_011_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_012.yaml b/config/splat.ov_SC04_012.yaml index c399ac6f8..59d014260 100644 --- a/config/splat.ov_SC04_012.yaml +++ b/config/splat.ov_SC04_012.yaml @@ -133,7 +133,7 @@ segments: - [0x678d4, .rodata, ov_SC04_012_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x67938, data, tail6] - [0x679e0, .rodata, ov_SC04_012_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x67a4c, data, tail7] + - [0x67abc, data, tail7] - [0x67f44, .rodata, ov_SC04_012_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x67f78, data, tail8] - [0x67f7c, .rodata, ov_SC04_012_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_015.yaml b/config/splat.ov_SC04_015.yaml index e68f3b185..bba9862c5 100644 --- a/config/splat.ov_SC04_015.yaml +++ b/config/splat.ov_SC04_015.yaml @@ -133,7 +133,7 @@ segments: - [0x9e56c, .rodata, ov_SC04_015_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9e5d0, data, tail6] - [0x9e678, .rodata, ov_SC04_015_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9e6e4, data, tail7] + - [0x9e754, data, tail7] - [0x9ebdc, .rodata, ov_SC04_015_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9ec10, data, tail8] - [0x9ec14, .rodata, ov_SC04_015_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_016.yaml b/config/splat.ov_SC04_016.yaml index 025481fde..8c2022c8e 100644 --- a/config/splat.ov_SC04_016.yaml +++ b/config/splat.ov_SC04_016.yaml @@ -134,7 +134,7 @@ segments: - [0x7c724, .rodata, ov_SC04_016_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7c788, data, tail6] - [0x7c830, .rodata, ov_SC04_016_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7c89c, data, tail7] + - [0x7c90c, data, tail7] - [0x7cd94, .rodata, ov_SC04_016_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7cdc8, data, tail8] - [0x7cdcc, .rodata, ov_SC04_016_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_018.yaml b/config/splat.ov_SC04_018.yaml index 8ddfa6ba3..b7e816b7b 100644 --- a/config/splat.ov_SC04_018.yaml +++ b/config/splat.ov_SC04_018.yaml @@ -133,7 +133,7 @@ segments: - [0xbc53c, .rodata, ov_SC04_018_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbc5a0, data, tail6] - [0xbc648, .rodata, ov_SC04_018_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc6b4, data, tail7] + - [0xbc724, data, tail7] - [0xbcbac, .rodata, ov_SC04_018_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbcbe0, data, tail8] - [0xbcbe4, .rodata, ov_SC04_018_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_019.yaml b/config/splat.ov_SC04_019.yaml index e81454488..938330f24 100644 --- a/config/splat.ov_SC04_019.yaml +++ b/config/splat.ov_SC04_019.yaml @@ -133,7 +133,7 @@ segments: - [0xbc53c, .rodata, ov_SC04_019_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbc5a0, data, tail6] - [0xbc648, .rodata, ov_SC04_019_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc6b4, data, tail7] + - [0xbc724, data, tail7] - [0xbcbac, .rodata, ov_SC04_019_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbcbe0, data, tail8] - [0xbcbe4, .rodata, ov_SC04_019_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_020.yaml b/config/splat.ov_SC04_020.yaml index f50188300..b8cfa7179 100644 --- a/config/splat.ov_SC04_020.yaml +++ b/config/splat.ov_SC04_020.yaml @@ -134,7 +134,7 @@ segments: - [0x91f64, .rodata, ov_SC04_020_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x91fc8, data, tail6] - [0x92070, .rodata, ov_SC04_020_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x920dc, data, tail7] + - [0x9214c, data, tail7] - [0x925d4, .rodata, ov_SC04_020_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x92608, data, tail8] - [0x9260c, .rodata, ov_SC04_020_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC04_021.yaml b/config/splat.ov_SC04_021.yaml index 80fe47fa1..6825d95c7 100644 --- a/config/splat.ov_SC04_021.yaml +++ b/config/splat.ov_SC04_021.yaml @@ -134,7 +134,7 @@ segments: - [0x65600, .rodata, ov_SC04_021_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65664, data, tail6] - [0x6570c, .rodata, ov_SC04_021_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65778, data, tail7] + - [0x657e8, data, tail7] - [0x65c70, .rodata, ov_SC04_021_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65ca4, data, tail8] - [0x65ca8, .rodata, ov_SC04_021_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_000.yaml b/config/splat.ov_SC05_000.yaml index f2251e093..a9278bf42 100644 --- a/config/splat.ov_SC05_000.yaml +++ b/config/splat.ov_SC05_000.yaml @@ -134,7 +134,7 @@ segments: - [0x70750, .rodata, ov_SC05_000_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x707b4, data, tail6] - [0x7085c, .rodata, ov_SC05_000_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x708c8, data, tail7] + - [0x70938, data, tail7] - [0x70dc0, .rodata, ov_SC05_000_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70df4, data, tail8] - [0x70df8, .rodata, ov_SC05_000_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_001.yaml b/config/splat.ov_SC05_001.yaml index f9ecab085..05647c239 100644 --- a/config/splat.ov_SC05_001.yaml +++ b/config/splat.ov_SC05_001.yaml @@ -134,7 +134,7 @@ segments: - [0x8b704, .rodata, ov_SC05_001_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8b768, data, tail6] - [0x8b810, .rodata, ov_SC05_001_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8b87c, data, tail7] + - [0x8b8ec, data, tail7] - [0x8bd74, .rodata, ov_SC05_001_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8bda8, data, tail8] - [0x8bdac, .rodata, ov_SC05_001_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_002.yaml b/config/splat.ov_SC05_002.yaml index 54c26c6e4..d3ddcf147 100644 --- a/config/splat.ov_SC05_002.yaml +++ b/config/splat.ov_SC05_002.yaml @@ -134,7 +134,7 @@ segments: - [0x75ab0, .rodata, ov_SC05_002_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x75b14, data, tail6] - [0x75bbc, .rodata, ov_SC05_002_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75c28, data, tail7] + - [0x75c98, data, tail7] - [0x76120, .rodata, ov_SC05_002_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76154, data, tail8] - [0x76158, .rodata, ov_SC05_002_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_003.yaml b/config/splat.ov_SC05_003.yaml index 697e064a4..72312c1ba 100644 --- a/config/splat.ov_SC05_003.yaml +++ b/config/splat.ov_SC05_003.yaml @@ -134,7 +134,7 @@ segments: - [0x825ac, .rodata, ov_SC05_003_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x82610, data, tail6] - [0x826b8, .rodata, ov_SC05_003_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x82724, data, tail7] + - [0x82794, data, tail7] - [0x82c1c, .rodata, ov_SC05_003_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x82c50, data, tail8] - [0x82c54, .rodata, ov_SC05_003_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_004.yaml b/config/splat.ov_SC05_004.yaml index dd7ce0700..ec114d086 100644 --- a/config/splat.ov_SC05_004.yaml +++ b/config/splat.ov_SC05_004.yaml @@ -133,7 +133,7 @@ segments: - [0x74ba0, .rodata, ov_SC05_004_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x74c04, data, tail6] - [0x74cac, .rodata, ov_SC05_004_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x74d18, data, tail7] + - [0x74d88, data, tail7] - [0x75210, .rodata, ov_SC05_004_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x75244, data, tail8] - [0x752b8, .rodata, ov_SC05_004_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_005.yaml b/config/splat.ov_SC05_005.yaml index 5f3884d3f..9aa0583d3 100644 --- a/config/splat.ov_SC05_005.yaml +++ b/config/splat.ov_SC05_005.yaml @@ -134,7 +134,7 @@ segments: - [0x87888, .rodata, ov_SC05_005_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x878ec, data, tail6] - [0x87994, .rodata, ov_SC05_005_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87a00, data, tail7] + - [0x87a70, data, tail7] - [0x87ef8, .rodata, ov_SC05_005_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x87f2c, data, tail8] - [0x87f30, .rodata, ov_SC05_005_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_006.yaml b/config/splat.ov_SC05_006.yaml index 1d71451e1..1e59d81ae 100644 --- a/config/splat.ov_SC05_006.yaml +++ b/config/splat.ov_SC05_006.yaml @@ -134,7 +134,7 @@ segments: - [0x659d8, .rodata, ov_SC05_006_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65a3c, data, tail6] - [0x65ae4, .rodata, ov_SC05_006_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65b50, data, tail7] + - [0x65bc0, data, tail7] - [0x66048, .rodata, ov_SC05_006_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6607c, data, tail8] - [0x66080, .rodata, ov_SC05_006_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_007.yaml b/config/splat.ov_SC05_007.yaml index 69cbf914e..691308b95 100644 --- a/config/splat.ov_SC05_007.yaml +++ b/config/splat.ov_SC05_007.yaml @@ -134,7 +134,7 @@ segments: - [0x729b0, .rodata, ov_SC05_007_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x72a14, data, tail6] - [0x72abc, .rodata, ov_SC05_007_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72b28, data, tail7] + - [0x72b98, data, tail7] - [0x73020, .rodata, ov_SC05_007_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73054, data, tail8] - [0x73058, .rodata, ov_SC05_007_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_008.yaml b/config/splat.ov_SC05_008.yaml index cddc6a63c..2c8e43187 100644 --- a/config/splat.ov_SC05_008.yaml +++ b/config/splat.ov_SC05_008.yaml @@ -133,7 +133,7 @@ segments: - [0x76ce4, .rodata, ov_SC05_008_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x76d48, data, tail6] - [0x76df0, .rodata, ov_SC05_008_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x76e5c, data, tail7] + - [0x76ecc, data, tail7] - [0x77354, .rodata, ov_SC05_008_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77388, data, tail8] - [0x7738c, .rodata, ov_SC05_008_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_009.yaml b/config/splat.ov_SC05_009.yaml index 746f41fa4..964ef9aab 100644 --- a/config/splat.ov_SC05_009.yaml +++ b/config/splat.ov_SC05_009.yaml @@ -133,7 +133,7 @@ segments: - [0x6c6f8, .rodata, ov_SC05_009_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6c75c, data, tail6] - [0x6c804, .rodata, ov_SC05_009_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c870, data, tail7] + - [0x6c8e0, data, tail7] - [0x6cd68, .rodata, ov_SC05_009_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6cd9c, data, tail8] - [0x6cda0, .rodata, ov_SC05_009_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_010.yaml b/config/splat.ov_SC05_010.yaml index a974588df..6a5d43d5f 100644 --- a/config/splat.ov_SC05_010.yaml +++ b/config/splat.ov_SC05_010.yaml @@ -135,7 +135,7 @@ segments: - [0x9c92c, .rodata, ov_SC05_010_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9c990, data, tail6] - [0x9ca38, .rodata, ov_SC05_010_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9caa4, data, tail7] + - [0x9cb14, data, tail7] - [0x9cf9c, .rodata, ov_SC05_010_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9cfd0, data, tail8] - [0x9cfd4, .rodata, ov_SC05_010_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_011.yaml b/config/splat.ov_SC05_011.yaml index fc0a3a235..3bdccbb9b 100644 --- a/config/splat.ov_SC05_011.yaml +++ b/config/splat.ov_SC05_011.yaml @@ -134,7 +134,7 @@ segments: - [0x72c90, .rodata, ov_SC05_011_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x72cf4, data, tail6] - [0x72d9c, .rodata, ov_SC05_011_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x72e08, data, tail7] + - [0x72e78, data, tail7] - [0x73300, .rodata, ov_SC05_011_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x73334, data, tail8] - [0x73338, .rodata, ov_SC05_011_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_017.yaml b/config/splat.ov_SC05_017.yaml index 530875b5a..2893211b8 100644 --- a/config/splat.ov_SC05_017.yaml +++ b/config/splat.ov_SC05_017.yaml @@ -133,7 +133,7 @@ segments: - [0xc2378, .rodata, ov_SC05_017_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc23dc, data, tail6] - [0xc2484, .rodata, ov_SC05_017_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xc24f0, data, tail7] + - [0xc2560, data, tail7] - [0xc29e8, .rodata, ov_SC05_017_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xc2a1c, data, tail8] - [0xc2a20, .rodata, ov_SC05_017_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_018.yaml b/config/splat.ov_SC05_018.yaml index 57ce27cb2..e747ff13b 100644 --- a/config/splat.ov_SC05_018.yaml +++ b/config/splat.ov_SC05_018.yaml @@ -134,7 +134,7 @@ segments: - [0xbbeec, .rodata, ov_SC05_018_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbbf50, data, tail6] - [0xbbff8, .rodata, ov_SC05_018_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xbc064, data, tail7] + - [0xbc0d4, data, tail7] - [0xbc55c, .rodata, ov_SC05_018_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xbc590, data, tail8] - [0xbc594, .rodata, ov_SC05_018_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC05_019.yaml b/config/splat.ov_SC05_019.yaml index 5bfb31564..5c319a57a 100644 --- a/config/splat.ov_SC05_019.yaml +++ b/config/splat.ov_SC05_019.yaml @@ -134,7 +134,7 @@ segments: - [0x65600, .rodata, ov_SC05_019_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65664, data, tail6] - [0x6570c, .rodata, ov_SC05_019_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x65778, data, tail7] + - [0x657e8, data, tail7] - [0x65c70, .rodata, ov_SC05_019_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65ca4, data, tail8] - [0x65ca8, .rodata, ov_SC05_019_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_000.yaml b/config/splat.ov_SC06_000.yaml index 5c4776440..49caacef5 100644 --- a/config/splat.ov_SC06_000.yaml +++ b/config/splat.ov_SC06_000.yaml @@ -132,7 +132,7 @@ segments: - [0x84278, .rodata, ov_SC06_000_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x842dc, data, tail6] - [0x84384, .rodata, ov_SC06_000_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x843f0, data, tail7] + - [0x84460, data, tail7] - [0x848e8, .rodata, ov_SC06_000_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8491c, data, tail8] - [0x84990, .rodata, ov_SC06_000_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_006.yaml b/config/splat.ov_SC06_006.yaml index f346503a8..7ec322432 100644 --- a/config/splat.ov_SC06_006.yaml +++ b/config/splat.ov_SC06_006.yaml @@ -134,7 +134,7 @@ segments: - [0xcdb80, .rodata, ov_SC06_006_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcdbe4, data, tail6] - [0xcdc8c, .rodata, ov_SC06_006_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcdcf8, data, tail7] + - [0xcdd68, data, tail7] - [0xce1f0, .rodata, ov_SC06_006_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xce224, data, tail8] - [0xce228, .rodata, ov_SC06_006_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_008.yaml b/config/splat.ov_SC06_008.yaml index 4fe6a2126..a882a963f 100644 --- a/config/splat.ov_SC06_008.yaml +++ b/config/splat.ov_SC06_008.yaml @@ -134,7 +134,7 @@ segments: - [0x7fc58, .rodata, ov_SC06_008_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7fcbc, data, tail6] - [0x7fd64, .rodata, ov_SC06_008_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7fdd0, data, tail7] + - [0x7fe40, data, tail7] - [0x802c8, .rodata, ov_SC06_008_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x802fc, data, tail8] - [0x80300, .rodata, ov_SC06_008_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_010.yaml b/config/splat.ov_SC06_010.yaml index 6d3b4c158..7a90af8a9 100644 --- a/config/splat.ov_SC06_010.yaml +++ b/config/splat.ov_SC06_010.yaml @@ -131,7 +131,7 @@ segments: - [0x87cac, .rodata, ov_SC06_010_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x87d10, data, tail6] - [0x87db8, .rodata, ov_SC06_010_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x87e24, data, tail7] + - [0x87e94, data, tail7] - [0x8831c, .rodata, ov_SC06_010_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x88350, data, tail8] - [0x883c4, .rodata, ov_SC06_010_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_011.yaml b/config/splat.ov_SC06_011.yaml index a9ff40b9a..7937e2038 100644 --- a/config/splat.ov_SC06_011.yaml +++ b/config/splat.ov_SC06_011.yaml @@ -134,7 +134,7 @@ segments: - [0x8180c, .rodata, ov_SC06_011_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x81870, data, tail6] - [0x81918, .rodata, ov_SC06_011_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x81984, data, tail7] + - [0x819f4, data, tail7] - [0x81e7c, .rodata, ov_SC06_011_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x81eb0, data, tail8] - [0x81eb4, .rodata, ov_SC06_011_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_013.yaml b/config/splat.ov_SC06_013.yaml index b89a2fcbe..6e2519bcd 100644 --- a/config/splat.ov_SC06_013.yaml +++ b/config/splat.ov_SC06_013.yaml @@ -134,7 +134,7 @@ segments: - [0x706e0, .rodata, ov_SC06_013_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70744, data, tail6] - [0x707ec, .rodata, ov_SC06_013_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x70858, data, tail7] + - [0x708c8, data, tail7] - [0x70d50, .rodata, ov_SC06_013_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x70d84, data, tail8] - [0x70d88, .rodata, ov_SC06_013_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_014.yaml b/config/splat.ov_SC06_014.yaml index 04fd153cd..ba2ab2905 100644 --- a/config/splat.ov_SC06_014.yaml +++ b/config/splat.ov_SC06_014.yaml @@ -134,7 +134,7 @@ segments: - [0x770d0, .rodata, ov_SC06_014_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77134, data, tail6] - [0x771dc, .rodata, ov_SC06_014_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x77248, data, tail7] + - [0x772b8, data, tail7] - [0x77740, .rodata, ov_SC06_014_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x77774, data, tail8] - [0x77778, .rodata, ov_SC06_014_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_015.yaml b/config/splat.ov_SC06_015.yaml index 2d7671c5e..5455e90e5 100644 --- a/config/splat.ov_SC06_015.yaml +++ b/config/splat.ov_SC06_015.yaml @@ -134,7 +134,7 @@ segments: - [0x6a4b0, .rodata, ov_SC06_015_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6a514, data, tail6] - [0x6a5bc, .rodata, ov_SC06_015_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6a628, data, tail7] + - [0x6a698, data, tail7] - [0x6ab20, .rodata, ov_SC06_015_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6ab54, data, tail8] - [0x6ab58, .rodata, ov_SC06_015_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_016.yaml b/config/splat.ov_SC06_016.yaml index c1e534941..719cecf48 100644 --- a/config/splat.ov_SC06_016.yaml +++ b/config/splat.ov_SC06_016.yaml @@ -134,7 +134,7 @@ segments: - [0x750f8, .rodata, ov_SC06_016_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7515c, data, tail6] - [0x75204, .rodata, ov_SC06_016_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x75270, data, tail7] + - [0x752e0, data, tail7] - [0x75768, .rodata, ov_SC06_016_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7579c, data, tail8] - [0x757a0, .rodata, ov_SC06_016_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_018.yaml b/config/splat.ov_SC06_018.yaml index 678c511a6..b7212c95a 100644 --- a/config/splat.ov_SC06_018.yaml +++ b/config/splat.ov_SC06_018.yaml @@ -135,7 +135,7 @@ segments: - [0xaa988, .rodata, ov_SC06_018_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xaa9ec, data, tail6] - [0xaaa94, .rodata, ov_SC06_018_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xaab00, data, tail7] + - [0xaab70, data, tail7] - [0xaaff8, .rodata, ov_SC06_018_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xab02c, data, tail8] - [0xab030, .rodata, ov_SC06_018_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_020.yaml b/config/splat.ov_SC06_020.yaml index 94147cd81..e96f78cea 100644 --- a/config/splat.ov_SC06_020.yaml +++ b/config/splat.ov_SC06_020.yaml @@ -134,7 +134,7 @@ segments: - [0x90270, .rodata, ov_SC06_020_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x902d4, data, tail6] - [0x9037c, .rodata, ov_SC06_020_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x903e8, data, tail7] + - [0x90458, data, tail7] - [0x908e0, .rodata, ov_SC06_020_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x90914, data, tail8] - [0x90918, .rodata, ov_SC06_020_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_022.yaml b/config/splat.ov_SC06_022.yaml index 23e82fa83..bb56f28dc 100644 --- a/config/splat.ov_SC06_022.yaml +++ b/config/splat.ov_SC06_022.yaml @@ -134,7 +134,7 @@ segments: - [0xb7a80, .rodata, ov_SC06_022_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7ae4, data, tail6] - [0xb7b8c, .rodata, ov_SC06_022_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb7bf8, data, tail7] + - [0xb7c68, data, tail7] - [0xb80f0, .rodata, ov_SC06_022_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb8124, data, tail8] - [0xb8128, .rodata, ov_SC06_022_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_024.yaml b/config/splat.ov_SC06_024.yaml index 39e73fcf1..5b8ed9c9c 100644 --- a/config/splat.ov_SC06_024.yaml +++ b/config/splat.ov_SC06_024.yaml @@ -134,7 +134,7 @@ segments: - [0xb6bc4, .rodata, ov_SC06_024_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb6c28, data, tail6] - [0xb6cd0, .rodata, ov_SC06_024_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb6d3c, data, tail7] + - [0xb6dac, data, tail7] - [0xb7234, .rodata, ov_SC06_024_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb7268, data, tail8] - [0xb726c, .rodata, ov_SC06_024_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_025.yaml b/config/splat.ov_SC06_025.yaml index 8bfc34bc0..211a12188 100644 --- a/config/splat.ov_SC06_025.yaml +++ b/config/splat.ov_SC06_025.yaml @@ -134,7 +134,7 @@ segments: - [0x86ee4, .rodata, ov_SC06_025_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x86f48, data, tail6] - [0x86ff0, .rodata, ov_SC06_025_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8705c, data, tail7] + - [0x870cc, data, tail7] - [0x87554, .rodata, ov_SC06_025_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x87588, data, tail8] - [0x8758c, .rodata, ov_SC06_025_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_027.yaml b/config/splat.ov_SC06_027.yaml index 262259340..daf426dd2 100644 --- a/config/splat.ov_SC06_027.yaml +++ b/config/splat.ov_SC06_027.yaml @@ -134,7 +134,7 @@ segments: - [0x72f20, .rodata, ov_SC06_027_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x72f84, data, tail6] - [0x7302c, .rodata, ov_SC06_027_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x73098, data, tail7] + - [0x73108, data, tail7] - [0x73590, .rodata, ov_SC06_027_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x735c4, data, tail8] - [0x735c8, .rodata, ov_SC06_027_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_029.yaml b/config/splat.ov_SC06_029.yaml index 58b601c68..78aab920c 100644 --- a/config/splat.ov_SC06_029.yaml +++ b/config/splat.ov_SC06_029.yaml @@ -134,7 +134,7 @@ segments: - [0xb259c, .rodata, ov_SC06_029_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb2600, data, tail6] - [0xb26a8, .rodata, ov_SC06_029_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xb2714, data, tail7] + - [0xb2784, data, tail7] - [0xb2c0c, .rodata, ov_SC06_029_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xb2c40, data, tail8] - [0xb2c44, .rodata, ov_SC06_029_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_030.yaml b/config/splat.ov_SC06_030.yaml index e757915c5..deb5b3bb1 100644 --- a/config/splat.ov_SC06_030.yaml +++ b/config/splat.ov_SC06_030.yaml @@ -134,7 +134,7 @@ segments: - [0x8f900, .rodata, ov_SC06_030_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8f964, data, tail6] - [0x8fa0c, .rodata, ov_SC06_030_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x8fa78, data, tail7] + - [0x8fae8, data, tail7] - [0x8ff70, .rodata, ov_SC06_030_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8ffa4, data, tail8] - [0x8ffa8, .rodata, ov_SC06_030_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_032.yaml b/config/splat.ov_SC06_032.yaml index 52e2a2e11..747875e72 100644 --- a/config/splat.ov_SC06_032.yaml +++ b/config/splat.ov_SC06_032.yaml @@ -134,7 +134,7 @@ segments: - [0xa5f5c, .rodata, ov_SC06_032_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa5fc0, data, tail6] - [0xa6068, .rodata, ov_SC06_032_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa60d4, data, tail7] + - [0xa6144, data, tail7] - [0xa65cc, .rodata, ov_SC06_032_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6600, data, tail8] - [0xa6604, .rodata, ov_SC06_032_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC06_033.yaml b/config/splat.ov_SC06_033.yaml index 2eedf5766..04029154b 100644 --- a/config/splat.ov_SC06_033.yaml +++ b/config/splat.ov_SC06_033.yaml @@ -134,7 +134,7 @@ segments: - [0xa6010, .rodata, ov_SC06_033_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa6074, data, tail6] - [0xa611c, .rodata, ov_SC06_033_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa6188, data, tail7] + - [0xa61f8, data, tail7] - [0xa6680, .rodata, ov_SC06_033_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa66b4, data, tail8] - [0xa66b8, .rodata, ov_SC06_033_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC07_000.yaml b/config/splat.ov_SC07_000.yaml index cc70a9769..477de9388 100644 --- a/config/splat.ov_SC07_000.yaml +++ b/config/splat.ov_SC07_000.yaml @@ -134,7 +134,7 @@ segments: - [0xa566c, .rodata, ov_SC07_000_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa56d0, data, tail6] - [0xa5778, .rodata, ov_SC07_000_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xa57e4, data, tail7] + - [0xa5854, data, tail7] - [0xa5cdc, .rodata, ov_SC07_000_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xa5d10, data, tail8] - [0xa5d14, .rodata, ov_SC07_000_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC07_001.yaml b/config/splat.ov_SC07_001.yaml index 7c688a402..532ecc7a9 100644 --- a/config/splat.ov_SC07_001.yaml +++ b/config/splat.ov_SC07_001.yaml @@ -134,7 +134,7 @@ segments: - [0x80808, .rodata, ov_SC07_001_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x8086c, data, tail6] - [0x80914, .rodata, ov_SC07_001_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x80980, data, tail7] + - [0x809f0, data, tail7] - [0x80e78, .rodata, ov_SC07_001_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x80eac, data, tail8] - [0x80eb0, .rodata, ov_SC07_001_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC07_002.yaml b/config/splat.ov_SC07_002.yaml index 88db0c0df..2f4d8dfdc 100644 --- a/config/splat.ov_SC07_002.yaml +++ b/config/splat.ov_SC07_002.yaml @@ -134,7 +134,7 @@ segments: - [0x711f0, .rodata, ov_SC07_002_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71254, data, tail6] - [0x712fc, .rodata, ov_SC07_002_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x71368, data, tail7] + - [0x713d8, data, tail7] - [0x71860, .rodata, ov_SC07_002_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x71894, data, tail8] - [0x71898, .rodata, ov_SC07_002_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC07_006.yaml b/config/splat.ov_SC07_006.yaml index b613888d1..6bb11dd38 100644 --- a/config/splat.ov_SC07_006.yaml +++ b/config/splat.ov_SC07_006.yaml @@ -125,7 +125,7 @@ segments: - [0xcbc24, .rodata, ov_SC07_006_jr_80135D20] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcbc68, data, tail6] - [0xcbd80, .rodata, ov_SC07_006_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0xcbdec, data, tail7] + - [0xcbe5c, data, tail7] - [0xcc2e4, .rodata, ov_SC07_006_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0xcc318, data, tail8] - [0xcc38c, .rodata, ov_SC07_006_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC07_007.yaml b/config/splat.ov_SC07_007.yaml index 2f678f7f4..9c06b8450 100644 --- a/config/splat.ov_SC07_007.yaml +++ b/config/splat.ov_SC07_007.yaml @@ -124,7 +124,7 @@ segments: - [0x9d400, .rodata, ov_SC07_007_jr_80135D20] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9d444, data, tail6] - [0x9d55c, .rodata, ov_SC07_007_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x9d5c8, data, tail7] + - [0x9d638, data, tail7] - [0x9dac0, .rodata, ov_SC07_007_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x9daf4, data, tail8] - [0x9db68, .rodata, ov_SC07_007_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC07_008.yaml b/config/splat.ov_SC07_008.yaml index b5af61717..e97fa8fbe 100644 --- a/config/splat.ov_SC07_008.yaml +++ b/config/splat.ov_SC07_008.yaml @@ -134,7 +134,7 @@ segments: - [0x6c240, .rodata, ov_SC07_008_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6c2a4, data, tail6] - [0x6c34c, .rodata, ov_SC07_008_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x6c3b8, data, tail7] + - [0x6c428, data, tail7] - [0x6c8b0, .rodata, ov_SC07_008_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6c8e4, data, tail8] - [0x6c8e8, .rodata, ov_SC07_008_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC07_009.yaml b/config/splat.ov_SC07_009.yaml index 8db07b9fa..688e647fc 100644 --- a/config/splat.ov_SC07_009.yaml +++ b/config/splat.ov_SC07_009.yaml @@ -133,7 +133,7 @@ segments: - [0x798cc, .rodata, ov_SC07_009_jr_801380E0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x79930, data, tail6] - [0x799d8, .rodata, ov_SC07_009_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x79a44, data, tail7] + - [0x79ab4, data, tail7] - [0x79f3c, .rodata, ov_SC07_009_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x79f70, data, tail8] - [0x79f74, .rodata, ov_SC07_009_jr_8013FFD8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC07_010.yaml b/config/splat.ov_SC07_010.yaml index 7fecb7725..0323264de 100644 --- a/config/splat.ov_SC07_010.yaml +++ b/config/splat.ov_SC07_010.yaml @@ -123,7 +123,7 @@ segments: - [0x7d8e0, .rodata, ov_SC07_010_jr_80135D20] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7d924, data, tail6] - [0x7da3c, .rodata, ov_SC07_010_o0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x7daa8, data, tail7] + - [0x7db18, data, tail7] - [0x7dfa0, .rodata, ov_SC07_010_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x7dfd4, data, tail8] - [0x7e048, .rodata, ov_SC07_010_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/config/splat.ov_SC07_011.yaml b/config/splat.ov_SC07_011.yaml index 89fecc1e2..def0b9953 100644 --- a/config/splat.ov_SC07_011.yaml +++ b/config/splat.ov_SC07_011.yaml @@ -124,7 +124,7 @@ segments: - [0x65fa8, .rodata, ov_SC07_011_jr_80135D20] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x65fec, data, tail6] - [0x66104, .rodata, ov_SC07_011_o0c] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - - [0x66170, data, tail7] + - [0x661e0, data, tail7] - [0x66668, .rodata, ov_SC07_011_jr_8013F350] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) - [0x6669c, data, tail8] - [0x66710, .rodata, ov_SC07_011_jr_80140608] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py) diff --git a/src/ov_SC01_000/ov_SC01_000_o0c.c b/src/ov_SC01_000/ov_SC01_000_o0c.c index 3c05a124d..68655851a 100644 --- a/src/ov_SC01_000/ov_SC01_000_o0c.c +++ b/src/ov_SC01_000/ov_SC01_000_o0c.c @@ -913,7 +913,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC01_000/nonmatchings/ov_SC01_000_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC01_001/ov_SC01_001_o0c.c b/src/ov_SC01_001/ov_SC01_001_o0c.c index 1a9694243..3d6ae90eb 100644 --- a/src/ov_SC01_001/ov_SC01_001_o0c.c +++ b/src/ov_SC01_001/ov_SC01_001_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC01_001/nonmatchings/ov_SC01_001_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC01_004/ov_SC01_004_o0c.c b/src/ov_SC01_004/ov_SC01_004_o0c.c index 277f2c18d..0f46bc814 100644 --- a/src/ov_SC01_004/ov_SC01_004_o0c.c +++ b/src/ov_SC01_004/ov_SC01_004_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC01_004/nonmatchings/ov_SC01_004_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC01_005/ov_SC01_005_o0c.c b/src/ov_SC01_005/ov_SC01_005_o0c.c index bfc9e2247..40091f9b7 100644 --- a/src/ov_SC01_005/ov_SC01_005_o0c.c +++ b/src/ov_SC01_005/ov_SC01_005_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC01_005/nonmatchings/ov_SC01_005_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC01_006/ov_SC01_006_o0c.c b/src/ov_SC01_006/ov_SC01_006_o0c.c index c5a93da1e..0855b23e8 100644 --- a/src/ov_SC01_006/ov_SC01_006_o0c.c +++ b/src/ov_SC01_006/ov_SC01_006_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC01_006/nonmatchings/ov_SC01_006_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC01_008/ov_SC01_008_o0c.c b/src/ov_SC01_008/ov_SC01_008_o0c.c index ba9b2891e..fb346e79e 100644 --- a/src/ov_SC01_008/ov_SC01_008_o0c.c +++ b/src/ov_SC01_008/ov_SC01_008_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC01_008/nonmatchings/ov_SC01_008_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC01_009/ov_SC01_009_o0c.c b/src/ov_SC01_009/ov_SC01_009_o0c.c index ab288aa65..9e226387e 100644 --- a/src/ov_SC01_009/ov_SC01_009_o0c.c +++ b/src/ov_SC01_009/ov_SC01_009_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC01_009/nonmatchings/ov_SC01_009_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC01_074/ov_SC01_074_o0c.c b/src/ov_SC01_074/ov_SC01_074_o0c.c index 2ece44785..e7ecd8245 100644 --- a/src/ov_SC01_074/ov_SC01_074_o0c.c +++ b/src/ov_SC01_074/ov_SC01_074_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC01_074/nonmatchings/ov_SC01_074_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC01_080/ov_SC01_080_o0c.c b/src/ov_SC01_080/ov_SC01_080_o0c.c index ed1c4360d..4f8e95ffd 100644 --- a/src/ov_SC01_080/ov_SC01_080_o0c.c +++ b/src/ov_SC01_080/ov_SC01_080_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC01_080/nonmatchings/ov_SC01_080_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC01_084/ov_SC01_084_o0c.c b/src/ov_SC01_084/ov_SC01_084_o0c.c index 991c18ce1..a8abc4acf 100644 --- a/src/ov_SC01_084/ov_SC01_084_o0c.c +++ b/src/ov_SC01_084/ov_SC01_084_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC01_084/nonmatchings/ov_SC01_084_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_000/ov_SC02_000_o0c.c b/src/ov_SC02_000/ov_SC02_000_o0c.c index 8eb20e84a..658b09efe 100644 --- a/src/ov_SC02_000/ov_SC02_000_o0c.c +++ b/src/ov_SC02_000/ov_SC02_000_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_000/nonmatchings/ov_SC02_000_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_003/ov_SC02_003_o0c.c b/src/ov_SC02_003/ov_SC02_003_o0c.c index bfd905346..6814d8061 100644 --- a/src/ov_SC02_003/ov_SC02_003_o0c.c +++ b/src/ov_SC02_003/ov_SC02_003_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_003/nonmatchings/ov_SC02_003_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_004/ov_SC02_004_o0c.c b/src/ov_SC02_004/ov_SC02_004_o0c.c index 652d667a4..4caf9a36a 100644 --- a/src/ov_SC02_004/ov_SC02_004_o0c.c +++ b/src/ov_SC02_004/ov_SC02_004_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_004/nonmatchings/ov_SC02_004_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_005/ov_SC02_005_o0c.c b/src/ov_SC02_005/ov_SC02_005_o0c.c index 90331e9fe..06494a515 100644 --- a/src/ov_SC02_005/ov_SC02_005_o0c.c +++ b/src/ov_SC02_005/ov_SC02_005_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_005/nonmatchings/ov_SC02_005_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_011/ov_SC02_011_o0c.c b/src/ov_SC02_011/ov_SC02_011_o0c.c index 682161891..d9af93050 100644 --- a/src/ov_SC02_011/ov_SC02_011_o0c.c +++ b/src/ov_SC02_011/ov_SC02_011_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_011/nonmatchings/ov_SC02_011_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_015/ov_SC02_015_o0c.c b/src/ov_SC02_015/ov_SC02_015_o0c.c index 87c6a904e..cbf235c52 100644 --- a/src/ov_SC02_015/ov_SC02_015_o0c.c +++ b/src/ov_SC02_015/ov_SC02_015_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_015/nonmatchings/ov_SC02_015_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_016/ov_SC02_016_o0c.c b/src/ov_SC02_016/ov_SC02_016_o0c.c index 4d5c2670f..ead657c87 100644 --- a/src/ov_SC02_016/ov_SC02_016_o0c.c +++ b/src/ov_SC02_016/ov_SC02_016_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_016/nonmatchings/ov_SC02_016_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_017/ov_SC02_017_o0c.c b/src/ov_SC02_017/ov_SC02_017_o0c.c index f93d2482e..26a7c3426 100644 --- a/src/ov_SC02_017/ov_SC02_017_o0c.c +++ b/src/ov_SC02_017/ov_SC02_017_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_017/nonmatchings/ov_SC02_017_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_021/ov_SC02_021_o0c.c b/src/ov_SC02_021/ov_SC02_021_o0c.c index 3fa47a2d7..729f78436 100644 --- a/src/ov_SC02_021/ov_SC02_021_o0c.c +++ b/src/ov_SC02_021/ov_SC02_021_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_021/nonmatchings/ov_SC02_021_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_026/ov_SC02_026_o0c.c b/src/ov_SC02_026/ov_SC02_026_o0c.c index 1fda31a7e..a0e30736c 100644 --- a/src/ov_SC02_026/ov_SC02_026_o0c.c +++ b/src/ov_SC02_026/ov_SC02_026_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_026/nonmatchings/ov_SC02_026_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_027/ov_SC02_027_o0c.c b/src/ov_SC02_027/ov_SC02_027_o0c.c index 13af90e8a..816883b42 100644 --- a/src/ov_SC02_027/ov_SC02_027_o0c.c +++ b/src/ov_SC02_027/ov_SC02_027_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_027/nonmatchings/ov_SC02_027_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_028/ov_SC02_028_o0c.c b/src/ov_SC02_028/ov_SC02_028_o0c.c index b92474349..47514a28c 100644 --- a/src/ov_SC02_028/ov_SC02_028_o0c.c +++ b/src/ov_SC02_028/ov_SC02_028_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_028/nonmatchings/ov_SC02_028_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_031/ov_SC02_031_o0c.c b/src/ov_SC02_031/ov_SC02_031_o0c.c index bcb93cef0..d5bab261a 100644 --- a/src/ov_SC02_031/ov_SC02_031_o0c.c +++ b/src/ov_SC02_031/ov_SC02_031_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_031/nonmatchings/ov_SC02_031_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_035/ov_SC02_035_o0c.c b/src/ov_SC02_035/ov_SC02_035_o0c.c index 0aabfca90..307d4e212 100644 --- a/src/ov_SC02_035/ov_SC02_035_o0c.c +++ b/src/ov_SC02_035/ov_SC02_035_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_035/nonmatchings/ov_SC02_035_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_039/ov_SC02_039_o0c.c b/src/ov_SC02_039/ov_SC02_039_o0c.c index 6a032b014..230f6ac13 100644 --- a/src/ov_SC02_039/ov_SC02_039_o0c.c +++ b/src/ov_SC02_039/ov_SC02_039_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_039/nonmatchings/ov_SC02_039_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC02_041/ov_SC02_041_o0c.c b/src/ov_SC02_041/ov_SC02_041_o0c.c index f8026adc9..d384ced48 100644 --- a/src/ov_SC02_041/ov_SC02_041_o0c.c +++ b/src/ov_SC02_041/ov_SC02_041_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC02_041/nonmatchings/ov_SC02_041_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_001/ov_SC03_001_o0c.c b/src/ov_SC03_001/ov_SC03_001_o0c.c index 2181bb1c5..8c24c9dc1 100644 --- a/src/ov_SC03_001/ov_SC03_001_o0c.c +++ b/src/ov_SC03_001/ov_SC03_001_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_002/ov_SC03_002_o0c.c b/src/ov_SC03_002/ov_SC03_002_o0c.c index 0ef4ec92b..ba540a5a7 100644 --- a/src/ov_SC03_002/ov_SC03_002_o0c.c +++ b/src/ov_SC03_002/ov_SC03_002_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_002/nonmatchings/ov_SC03_002_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_003/ov_SC03_003_o0c.c b/src/ov_SC03_003/ov_SC03_003_o0c.c index f2248fb71..64494f483 100644 --- a/src/ov_SC03_003/ov_SC03_003_o0c.c +++ b/src/ov_SC03_003/ov_SC03_003_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_003/nonmatchings/ov_SC03_003_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_006/ov_SC03_006_o0c.c b/src/ov_SC03_006/ov_SC03_006_o0c.c index a647059d6..3b1054411 100644 --- a/src/ov_SC03_006/ov_SC03_006_o0c.c +++ b/src/ov_SC03_006/ov_SC03_006_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_006/nonmatchings/ov_SC03_006_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_007/ov_SC03_007_o0c.c b/src/ov_SC03_007/ov_SC03_007_o0c.c index bd18d4a00..44b0d00f1 100644 --- a/src/ov_SC03_007/ov_SC03_007_o0c.c +++ b/src/ov_SC03_007/ov_SC03_007_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_007/nonmatchings/ov_SC03_007_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_010/ov_SC03_010_o0c.c b/src/ov_SC03_010/ov_SC03_010_o0c.c index d16765807..16c2f112d 100644 --- a/src/ov_SC03_010/ov_SC03_010_o0c.c +++ b/src/ov_SC03_010/ov_SC03_010_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_010/nonmatchings/ov_SC03_010_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_011/ov_SC03_011_o0c.c b/src/ov_SC03_011/ov_SC03_011_o0c.c index 2128a6644..45d90f414 100644 --- a/src/ov_SC03_011/ov_SC03_011_o0c.c +++ b/src/ov_SC03_011/ov_SC03_011_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_011/nonmatchings/ov_SC03_011_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_012/ov_SC03_012_o0c.c b/src/ov_SC03_012/ov_SC03_012_o0c.c index 33d831044..115f23e0f 100644 --- a/src/ov_SC03_012/ov_SC03_012_o0c.c +++ b/src/ov_SC03_012/ov_SC03_012_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_012/nonmatchings/ov_SC03_012_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_013/ov_SC03_013_o0c.c b/src/ov_SC03_013/ov_SC03_013_o0c.c index 0824609b9..2dfdb0c28 100644 --- a/src/ov_SC03_013/ov_SC03_013_o0c.c +++ b/src/ov_SC03_013/ov_SC03_013_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_013/nonmatchings/ov_SC03_013_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_014/ov_SC03_014_o0e.c b/src/ov_SC03_014/ov_SC03_014_o0e.c index c5785ff07..e504a59b2 100644 --- a/src/ov_SC03_014/ov_SC03_014_o0e.c +++ b/src/ov_SC03_014/ov_SC03_014_o0e.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_014/nonmatchings/ov_SC03_014_o0e", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_015/ov_SC03_015_o0e.c b/src/ov_SC03_015/ov_SC03_015_o0e.c index c8b141a1d..d062ba01f 100644 --- a/src/ov_SC03_015/ov_SC03_015_o0e.c +++ b/src/ov_SC03_015/ov_SC03_015_o0e.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_015/nonmatchings/ov_SC03_015_o0e", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_023/ov_SC03_023_o0c.c b/src/ov_SC03_023/ov_SC03_023_o0c.c index 74cba2f24..334ebcc1f 100644 --- a/src/ov_SC03_023/ov_SC03_023_o0c.c +++ b/src/ov_SC03_023/ov_SC03_023_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_023/nonmatchings/ov_SC03_023_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_024/ov_SC03_024_o0c.c b/src/ov_SC03_024/ov_SC03_024_o0c.c index 46afc6770..be2b94a0e 100644 --- a/src/ov_SC03_024/ov_SC03_024_o0c.c +++ b/src/ov_SC03_024/ov_SC03_024_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_028/ov_SC03_028_o0c.c b/src/ov_SC03_028/ov_SC03_028_o0c.c index fefbd9666..dac2c7bef 100644 --- a/src/ov_SC03_028/ov_SC03_028_o0c.c +++ b/src/ov_SC03_028/ov_SC03_028_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_028/nonmatchings/ov_SC03_028_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_029/ov_SC03_029_o0c.c b/src/ov_SC03_029/ov_SC03_029_o0c.c index 2bf641d57..bccfb706b 100644 --- a/src/ov_SC03_029/ov_SC03_029_o0c.c +++ b/src/ov_SC03_029/ov_SC03_029_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_029/nonmatchings/ov_SC03_029_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_030/ov_SC03_030_o0c.c b/src/ov_SC03_030/ov_SC03_030_o0c.c index 98e6913bb..d45875807 100644 --- a/src/ov_SC03_030/ov_SC03_030_o0c.c +++ b/src/ov_SC03_030/ov_SC03_030_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_030/nonmatchings/ov_SC03_030_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_031/ov_SC03_031_o0c.c b/src/ov_SC03_031/ov_SC03_031_o0c.c index 399ea7f6a..06d9eca66 100644 --- a/src/ov_SC03_031/ov_SC03_031_o0c.c +++ b/src/ov_SC03_031/ov_SC03_031_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_031/nonmatchings/ov_SC03_031_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_089/ov_SC03_089_o0c.c b/src/ov_SC03_089/ov_SC03_089_o0c.c index 30c187b5f..f234b105a 100644 --- a/src/ov_SC03_089/ov_SC03_089_o0c.c +++ b/src/ov_SC03_089/ov_SC03_089_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_089/nonmatchings/ov_SC03_089_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_090/ov_SC03_090_o0c.c b/src/ov_SC03_090/ov_SC03_090_o0c.c index 864f7cdeb..33aff7434 100644 --- a/src/ov_SC03_090/ov_SC03_090_o0c.c +++ b/src/ov_SC03_090/ov_SC03_090_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_090/nonmatchings/ov_SC03_090_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_091/ov_SC03_091_o0c.c b/src/ov_SC03_091/ov_SC03_091_o0c.c index 7289592de..c615c41ca 100644 --- a/src/ov_SC03_091/ov_SC03_091_o0c.c +++ b/src/ov_SC03_091/ov_SC03_091_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_091/nonmatchings/ov_SC03_091_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_092/ov_SC03_092_o0c.c b/src/ov_SC03_092/ov_SC03_092_o0c.c index 506fe0c5a..52a41d258 100644 --- a/src/ov_SC03_092/ov_SC03_092_o0c.c +++ b/src/ov_SC03_092/ov_SC03_092_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_092/nonmatchings/ov_SC03_092_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_093/ov_SC03_093_o0c.c b/src/ov_SC03_093/ov_SC03_093_o0c.c index 2ffe9102a..760bd59f9 100644 --- a/src/ov_SC03_093/ov_SC03_093_o0c.c +++ b/src/ov_SC03_093/ov_SC03_093_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_093/nonmatchings/ov_SC03_093_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_094/ov_SC03_094_o0c.c b/src/ov_SC03_094/ov_SC03_094_o0c.c index e097bda7b..1849cac1d 100644 --- a/src/ov_SC03_094/ov_SC03_094_o0c.c +++ b/src/ov_SC03_094/ov_SC03_094_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_094/nonmatchings/ov_SC03_094_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_095/ov_SC03_095_o0c.c b/src/ov_SC03_095/ov_SC03_095_o0c.c index c0a18310d..12b6de0c8 100644 --- a/src/ov_SC03_095/ov_SC03_095_o0c.c +++ b/src/ov_SC03_095/ov_SC03_095_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_095/nonmatchings/ov_SC03_095_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_096/ov_SC03_096_o0c.c b/src/ov_SC03_096/ov_SC03_096_o0c.c index 364ca6602..075d31a7e 100644 --- a/src/ov_SC03_096/ov_SC03_096_o0c.c +++ b/src/ov_SC03_096/ov_SC03_096_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_096/nonmatchings/ov_SC03_096_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_097/ov_SC03_097_o0c.c b/src/ov_SC03_097/ov_SC03_097_o0c.c index e033f45ab..89537ea7a 100644 --- a/src/ov_SC03_097/ov_SC03_097_o0c.c +++ b/src/ov_SC03_097/ov_SC03_097_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_097/nonmatchings/ov_SC03_097_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_098/ov_SC03_098_o0c.c b/src/ov_SC03_098/ov_SC03_098_o0c.c index 21566ba08..fa5308416 100644 --- a/src/ov_SC03_098/ov_SC03_098_o0c.c +++ b/src/ov_SC03_098/ov_SC03_098_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_098/nonmatchings/ov_SC03_098_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_099/ov_SC03_099_o0c.c b/src/ov_SC03_099/ov_SC03_099_o0c.c index 0b7863764..434d777a7 100644 --- a/src/ov_SC03_099/ov_SC03_099_o0c.c +++ b/src/ov_SC03_099/ov_SC03_099_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_099/nonmatchings/ov_SC03_099_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_100/ov_SC03_100_o0c.c b/src/ov_SC03_100/ov_SC03_100_o0c.c index e01fe0779..dc0f5ea2d 100644 --- a/src/ov_SC03_100/ov_SC03_100_o0c.c +++ b/src/ov_SC03_100/ov_SC03_100_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_100/nonmatchings/ov_SC03_100_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_101/ov_SC03_101_o0c.c b/src/ov_SC03_101/ov_SC03_101_o0c.c index 332886a3a..89835d167 100644 --- a/src/ov_SC03_101/ov_SC03_101_o0c.c +++ b/src/ov_SC03_101/ov_SC03_101_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_102/ov_SC03_102_o0c.c b/src/ov_SC03_102/ov_SC03_102_o0c.c index a4a44513c..22dcd04db 100644 --- a/src/ov_SC03_102/ov_SC03_102_o0c.c +++ b/src/ov_SC03_102/ov_SC03_102_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_102/nonmatchings/ov_SC03_102_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_103/ov_SC03_103_o0c.c b/src/ov_SC03_103/ov_SC03_103_o0c.c index 641e4148b..dc5293ad3 100644 --- a/src/ov_SC03_103/ov_SC03_103_o0c.c +++ b/src/ov_SC03_103/ov_SC03_103_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_103/nonmatchings/ov_SC03_103_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_104/ov_SC03_104_o0c.c b/src/ov_SC03_104/ov_SC03_104_o0c.c index 84f7e4dc3..75662aa5b 100644 --- a/src/ov_SC03_104/ov_SC03_104_o0c.c +++ b/src/ov_SC03_104/ov_SC03_104_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_105/ov_SC03_105_o0c.c b/src/ov_SC03_105/ov_SC03_105_o0c.c index 18fc6e3b4..b82ad5e23 100644 --- a/src/ov_SC03_105/ov_SC03_105_o0c.c +++ b/src/ov_SC03_105/ov_SC03_105_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_105/nonmatchings/ov_SC03_105_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_108/ov_SC03_108_o0c.c b/src/ov_SC03_108/ov_SC03_108_o0c.c index 9f2e55098..0cc341530 100644 --- a/src/ov_SC03_108/ov_SC03_108_o0c.c +++ b/src/ov_SC03_108/ov_SC03_108_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_108/nonmatchings/ov_SC03_108_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_109/ov_SC03_109_o0c.c b/src/ov_SC03_109/ov_SC03_109_o0c.c index 9b76d4fce..16a1b36a2 100644 --- a/src/ov_SC03_109/ov_SC03_109_o0c.c +++ b/src/ov_SC03_109/ov_SC03_109_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_109/nonmatchings/ov_SC03_109_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_110/ov_SC03_110_o0c.c b/src/ov_SC03_110/ov_SC03_110_o0c.c index db8befd2c..149fefdff 100644 --- a/src/ov_SC03_110/ov_SC03_110_o0c.c +++ b/src/ov_SC03_110/ov_SC03_110_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_110/nonmatchings/ov_SC03_110_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_111/ov_SC03_111_o0c.c b/src/ov_SC03_111/ov_SC03_111_o0c.c index ca6d3ed07..8031d8407 100644 --- a/src/ov_SC03_111/ov_SC03_111_o0c.c +++ b/src/ov_SC03_111/ov_SC03_111_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_111/nonmatchings/ov_SC03_111_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_112/ov_SC03_112_o0c.c b/src/ov_SC03_112/ov_SC03_112_o0c.c index 59e178ea6..9a3167eb7 100644 --- a/src/ov_SC03_112/ov_SC03_112_o0c.c +++ b/src/ov_SC03_112/ov_SC03_112_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_112/nonmatchings/ov_SC03_112_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_113/ov_SC03_113_o0c.c b/src/ov_SC03_113/ov_SC03_113_o0c.c index ff4abd687..d7b12cc63 100644 --- a/src/ov_SC03_113/ov_SC03_113_o0c.c +++ b/src/ov_SC03_113/ov_SC03_113_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_113/nonmatchings/ov_SC03_113_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_114/ov_SC03_114_o0c.c b/src/ov_SC03_114/ov_SC03_114_o0c.c index 18136c39f..1d8550c5d 100644 --- a/src/ov_SC03_114/ov_SC03_114_o0c.c +++ b/src/ov_SC03_114/ov_SC03_114_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_114/nonmatchings/ov_SC03_114_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_115/ov_SC03_115_o0c.c b/src/ov_SC03_115/ov_SC03_115_o0c.c index 950720fcf..cf650098d 100644 --- a/src/ov_SC03_115/ov_SC03_115_o0c.c +++ b/src/ov_SC03_115/ov_SC03_115_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_115/nonmatchings/ov_SC03_115_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_116/ov_SC03_116_o0c.c b/src/ov_SC03_116/ov_SC03_116_o0c.c index 6a01ba4f5..d12e897ce 100644 --- a/src/ov_SC03_116/ov_SC03_116_o0c.c +++ b/src/ov_SC03_116/ov_SC03_116_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_116/nonmatchings/ov_SC03_116_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_117/ov_SC03_117_o0c.c b/src/ov_SC03_117/ov_SC03_117_o0c.c index 59dbed1c6..96c89883d 100644 --- a/src/ov_SC03_117/ov_SC03_117_o0c.c +++ b/src/ov_SC03_117/ov_SC03_117_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_117/nonmatchings/ov_SC03_117_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_118/ov_SC03_118_o0c.c b/src/ov_SC03_118/ov_SC03_118_o0c.c index 42a757f82..afc638841 100644 --- a/src/ov_SC03_118/ov_SC03_118_o0c.c +++ b/src/ov_SC03_118/ov_SC03_118_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_118/nonmatchings/ov_SC03_118_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_119/ov_SC03_119_o0c.c b/src/ov_SC03_119/ov_SC03_119_o0c.c index fd0e35286..e68aa569d 100644 --- a/src/ov_SC03_119/ov_SC03_119_o0c.c +++ b/src/ov_SC03_119/ov_SC03_119_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_119/nonmatchings/ov_SC03_119_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_121/ov_SC03_121_o0c.c b/src/ov_SC03_121/ov_SC03_121_o0c.c index 3d5b55b3e..4cc8de9b8 100644 --- a/src/ov_SC03_121/ov_SC03_121_o0c.c +++ b/src/ov_SC03_121/ov_SC03_121_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_121/nonmatchings/ov_SC03_121_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_124/ov_SC03_124_o0c.c b/src/ov_SC03_124/ov_SC03_124_o0c.c index 9c7bf4a65..abb0c627a 100644 --- a/src/ov_SC03_124/ov_SC03_124_o0c.c +++ b/src/ov_SC03_124/ov_SC03_124_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_124/nonmatchings/ov_SC03_124_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_125/ov_SC03_125_o0c.c b/src/ov_SC03_125/ov_SC03_125_o0c.c index cf58111f7..60583e712 100644 --- a/src/ov_SC03_125/ov_SC03_125_o0c.c +++ b/src/ov_SC03_125/ov_SC03_125_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_125/nonmatchings/ov_SC03_125_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC03_126/ov_SC03_126_o0c.c b/src/ov_SC03_126/ov_SC03_126_o0c.c index 1de4b20c4..afe901356 100644 --- a/src/ov_SC03_126/ov_SC03_126_o0c.c +++ b/src/ov_SC03_126/ov_SC03_126_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC03_126/nonmatchings/ov_SC03_126_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_000/ov_SC04_000_o0c.c b/src/ov_SC04_000/ov_SC04_000_o0c.c index 469bedc8e..a23e3ea1c 100644 --- a/src/ov_SC04_000/ov_SC04_000_o0c.c +++ b/src/ov_SC04_000/ov_SC04_000_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_000/nonmatchings/ov_SC04_000_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_002/ov_SC04_002_o0c.c b/src/ov_SC04_002/ov_SC04_002_o0c.c index d3e917765..47bbb1bca 100644 --- a/src/ov_SC04_002/ov_SC04_002_o0c.c +++ b/src/ov_SC04_002/ov_SC04_002_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_002/nonmatchings/ov_SC04_002_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_003/ov_SC04_003_o0c.c b/src/ov_SC04_003/ov_SC04_003_o0c.c index 851a9db28..3cc898239 100644 --- a/src/ov_SC04_003/ov_SC04_003_o0c.c +++ b/src/ov_SC04_003/ov_SC04_003_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_004/ov_SC04_004_o0c.c b/src/ov_SC04_004/ov_SC04_004_o0c.c index b81448e50..2f9057d5b 100644 --- a/src/ov_SC04_004/ov_SC04_004_o0c.c +++ b/src/ov_SC04_004/ov_SC04_004_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_004/nonmatchings/ov_SC04_004_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_005/ov_SC04_005_o0c.c b/src/ov_SC04_005/ov_SC04_005_o0c.c index 9efa7aa32..941be2a83 100644 --- a/src/ov_SC04_005/ov_SC04_005_o0c.c +++ b/src/ov_SC04_005/ov_SC04_005_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_006/ov_SC04_006_o0c.c b/src/ov_SC04_006/ov_SC04_006_o0c.c index 8bbb3710b..93ea9e541 100644 --- a/src/ov_SC04_006/ov_SC04_006_o0c.c +++ b/src/ov_SC04_006/ov_SC04_006_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_006/nonmatchings/ov_SC04_006_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_007/ov_SC04_007_o0c.c b/src/ov_SC04_007/ov_SC04_007_o0c.c index b06e37eab..9906a1bac 100644 --- a/src/ov_SC04_007/ov_SC04_007_o0c.c +++ b/src/ov_SC04_007/ov_SC04_007_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_008/ov_SC04_008_o0c.c b/src/ov_SC04_008/ov_SC04_008_o0c.c index b0411bce1..03a60cfce 100644 --- a/src/ov_SC04_008/ov_SC04_008_o0c.c +++ b/src/ov_SC04_008/ov_SC04_008_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_008/nonmatchings/ov_SC04_008_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_009/ov_SC04_009_o0c.c b/src/ov_SC04_009/ov_SC04_009_o0c.c index 9f88fc4b0..19198701d 100644 --- a/src/ov_SC04_009/ov_SC04_009_o0c.c +++ b/src/ov_SC04_009/ov_SC04_009_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_009/nonmatchings/ov_SC04_009_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_010/ov_SC04_010_o0c.c b/src/ov_SC04_010/ov_SC04_010_o0c.c index 286b8ed74..ecd6e609c 100644 --- a/src/ov_SC04_010/ov_SC04_010_o0c.c +++ b/src/ov_SC04_010/ov_SC04_010_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_010/nonmatchings/ov_SC04_010_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_011/ov_SC04_011_o0c.c b/src/ov_SC04_011/ov_SC04_011_o0c.c index 3727c15b0..cf4e135ad 100644 --- a/src/ov_SC04_011/ov_SC04_011_o0c.c +++ b/src/ov_SC04_011/ov_SC04_011_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_011/nonmatchings/ov_SC04_011_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_012/ov_SC04_012_o0c.c b/src/ov_SC04_012/ov_SC04_012_o0c.c index e9bf0bb00..567f79b42 100644 --- a/src/ov_SC04_012/ov_SC04_012_o0c.c +++ b/src/ov_SC04_012/ov_SC04_012_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_012/nonmatchings/ov_SC04_012_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_015/ov_SC04_015_o0c.c b/src/ov_SC04_015/ov_SC04_015_o0c.c index 9d3bc8f83..47958752a 100644 --- a/src/ov_SC04_015/ov_SC04_015_o0c.c +++ b/src/ov_SC04_015/ov_SC04_015_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_015/nonmatchings/ov_SC04_015_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_016/ov_SC04_016_o0c.c b/src/ov_SC04_016/ov_SC04_016_o0c.c index 3105b48a4..8c93bf079 100644 --- a/src/ov_SC04_016/ov_SC04_016_o0c.c +++ b/src/ov_SC04_016/ov_SC04_016_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_016/nonmatchings/ov_SC04_016_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_018/ov_SC04_018_o0c.c b/src/ov_SC04_018/ov_SC04_018_o0c.c index 3f0740188..35040ae9f 100644 --- a/src/ov_SC04_018/ov_SC04_018_o0c.c +++ b/src/ov_SC04_018/ov_SC04_018_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_018/nonmatchings/ov_SC04_018_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_019/ov_SC04_019_o0c.c b/src/ov_SC04_019/ov_SC04_019_o0c.c index 0f0b55520..04fe4aa95 100644 --- a/src/ov_SC04_019/ov_SC04_019_o0c.c +++ b/src/ov_SC04_019/ov_SC04_019_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_019/nonmatchings/ov_SC04_019_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_020/ov_SC04_020_o0c.c b/src/ov_SC04_020/ov_SC04_020_o0c.c index 171d6ce11..67ce0b4e3 100644 --- a/src/ov_SC04_020/ov_SC04_020_o0c.c +++ b/src/ov_SC04_020/ov_SC04_020_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_020/nonmatchings/ov_SC04_020_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC04_021/ov_SC04_021_o0c.c b/src/ov_SC04_021/ov_SC04_021_o0c.c index e727327d4..ce88f606c 100644 --- a/src/ov_SC04_021/ov_SC04_021_o0c.c +++ b/src/ov_SC04_021/ov_SC04_021_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC04_021/nonmatchings/ov_SC04_021_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_000/ov_SC05_000_o0c.c b/src/ov_SC05_000/ov_SC05_000_o0c.c index 26fa1b0fd..6a0fc4d92 100644 --- a/src/ov_SC05_000/ov_SC05_000_o0c.c +++ b/src/ov_SC05_000/ov_SC05_000_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_000/nonmatchings/ov_SC05_000_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_001/ov_SC05_001_o0c.c b/src/ov_SC05_001/ov_SC05_001_o0c.c index 004c2198c..5978768c2 100644 --- a/src/ov_SC05_001/ov_SC05_001_o0c.c +++ b/src/ov_SC05_001/ov_SC05_001_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_001/nonmatchings/ov_SC05_001_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_002/ov_SC05_002_o0c.c b/src/ov_SC05_002/ov_SC05_002_o0c.c index 4c0002cda..3893f861e 100644 --- a/src/ov_SC05_002/ov_SC05_002_o0c.c +++ b/src/ov_SC05_002/ov_SC05_002_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_002/nonmatchings/ov_SC05_002_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_003/ov_SC05_003_o0c.c b/src/ov_SC05_003/ov_SC05_003_o0c.c index a9c61ab8b..f960fc117 100644 --- a/src/ov_SC05_003/ov_SC05_003_o0c.c +++ b/src/ov_SC05_003/ov_SC05_003_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_003/nonmatchings/ov_SC05_003_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_004/ov_SC05_004_o0c.c b/src/ov_SC05_004/ov_SC05_004_o0c.c index 0881d41a8..0abc9d05d 100644 --- a/src/ov_SC05_004/ov_SC05_004_o0c.c +++ b/src/ov_SC05_004/ov_SC05_004_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_004/nonmatchings/ov_SC05_004_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_005/ov_SC05_005_o0c.c b/src/ov_SC05_005/ov_SC05_005_o0c.c index 1786e0faa..c932b7d4b 100644 --- a/src/ov_SC05_005/ov_SC05_005_o0c.c +++ b/src/ov_SC05_005/ov_SC05_005_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_005/nonmatchings/ov_SC05_005_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_006/ov_SC05_006_o0c.c b/src/ov_SC05_006/ov_SC05_006_o0c.c index 1ae63c77f..705e1361f 100644 --- a/src/ov_SC05_006/ov_SC05_006_o0c.c +++ b/src/ov_SC05_006/ov_SC05_006_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_006/nonmatchings/ov_SC05_006_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_007/ov_SC05_007_o0c.c b/src/ov_SC05_007/ov_SC05_007_o0c.c index b4abed3ed..218a65205 100644 --- a/src/ov_SC05_007/ov_SC05_007_o0c.c +++ b/src/ov_SC05_007/ov_SC05_007_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_007/nonmatchings/ov_SC05_007_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_008/ov_SC05_008_o0c.c b/src/ov_SC05_008/ov_SC05_008_o0c.c index 3989bbbe0..b11a9478e 100644 --- a/src/ov_SC05_008/ov_SC05_008_o0c.c +++ b/src/ov_SC05_008/ov_SC05_008_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_008/nonmatchings/ov_SC05_008_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_009/ov_SC05_009_o0c.c b/src/ov_SC05_009/ov_SC05_009_o0c.c index 90163da74..3fdb695dd 100644 --- a/src/ov_SC05_009/ov_SC05_009_o0c.c +++ b/src/ov_SC05_009/ov_SC05_009_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_009/nonmatchings/ov_SC05_009_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_010/ov_SC05_010_o0c.c b/src/ov_SC05_010/ov_SC05_010_o0c.c index 5ccacce1b..4a2d11298 100644 --- a/src/ov_SC05_010/ov_SC05_010_o0c.c +++ b/src/ov_SC05_010/ov_SC05_010_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_010/nonmatchings/ov_SC05_010_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_011/ov_SC05_011_o0c.c b/src/ov_SC05_011/ov_SC05_011_o0c.c index b301ec8a1..2df644ffb 100644 --- a/src/ov_SC05_011/ov_SC05_011_o0c.c +++ b/src/ov_SC05_011/ov_SC05_011_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_011/nonmatchings/ov_SC05_011_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_017/ov_SC05_017_o0c.c b/src/ov_SC05_017/ov_SC05_017_o0c.c index 26d55d9e1..b57043e63 100644 --- a/src/ov_SC05_017/ov_SC05_017_o0c.c +++ b/src/ov_SC05_017/ov_SC05_017_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_017/nonmatchings/ov_SC05_017_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_018/ov_SC05_018_o0c.c b/src/ov_SC05_018/ov_SC05_018_o0c.c index 65dd35d9a..0675afecb 100644 --- a/src/ov_SC05_018/ov_SC05_018_o0c.c +++ b/src/ov_SC05_018/ov_SC05_018_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_018/nonmatchings/ov_SC05_018_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC05_019/ov_SC05_019_o0c.c b/src/ov_SC05_019/ov_SC05_019_o0c.c index a8022a96f..f1bf8fa67 100644 --- a/src/ov_SC05_019/ov_SC05_019_o0c.c +++ b/src/ov_SC05_019/ov_SC05_019_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC05_019/nonmatchings/ov_SC05_019_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_000/ov_SC06_000_o0c.c b/src/ov_SC06_000/ov_SC06_000_o0c.c index a58fa9483..fe2e61be4 100644 --- a/src/ov_SC06_000/ov_SC06_000_o0c.c +++ b/src/ov_SC06_000/ov_SC06_000_o0c.c @@ -917,7 +917,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_000/nonmatchings/ov_SC06_000_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_006/ov_SC06_006_o0c.c b/src/ov_SC06_006/ov_SC06_006_o0c.c index 55a8f874f..8c13293e2 100644 --- a/src/ov_SC06_006/ov_SC06_006_o0c.c +++ b/src/ov_SC06_006/ov_SC06_006_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_006/nonmatchings/ov_SC06_006_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_008/ov_SC06_008_o0c.c b/src/ov_SC06_008/ov_SC06_008_o0c.c index 6346142cf..cd5627f18 100644 --- a/src/ov_SC06_008/ov_SC06_008_o0c.c +++ b/src/ov_SC06_008/ov_SC06_008_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_008/nonmatchings/ov_SC06_008_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_010/ov_SC06_010_o0c.c b/src/ov_SC06_010/ov_SC06_010_o0c.c index ef6cc0d15..a90a13a79 100644 --- a/src/ov_SC06_010/ov_SC06_010_o0c.c +++ b/src/ov_SC06_010/ov_SC06_010_o0c.c @@ -915,7 +915,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_010/nonmatchings/ov_SC06_010_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_011/ov_SC06_011_o0c.c b/src/ov_SC06_011/ov_SC06_011_o0c.c index 109e6703f..8be428f0c 100644 --- a/src/ov_SC06_011/ov_SC06_011_o0c.c +++ b/src/ov_SC06_011/ov_SC06_011_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_011/nonmatchings/ov_SC06_011_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_013/ov_SC06_013_o0c.c b/src/ov_SC06_013/ov_SC06_013_o0c.c index 5e226014a..c4a2735d1 100644 --- a/src/ov_SC06_013/ov_SC06_013_o0c.c +++ b/src/ov_SC06_013/ov_SC06_013_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_013/nonmatchings/ov_SC06_013_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_014/ov_SC06_014_o0c.c b/src/ov_SC06_014/ov_SC06_014_o0c.c index d4d1e1e98..ed710661f 100644 --- a/src/ov_SC06_014/ov_SC06_014_o0c.c +++ b/src/ov_SC06_014/ov_SC06_014_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_014/nonmatchings/ov_SC06_014_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_015/ov_SC06_015_o0c.c b/src/ov_SC06_015/ov_SC06_015_o0c.c index bece37e91..06ec83e28 100644 --- a/src/ov_SC06_015/ov_SC06_015_o0c.c +++ b/src/ov_SC06_015/ov_SC06_015_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_015/nonmatchings/ov_SC06_015_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_016/ov_SC06_016_o0c.c b/src/ov_SC06_016/ov_SC06_016_o0c.c index 4dc5d44cb..d5fb16a7c 100644 --- a/src/ov_SC06_016/ov_SC06_016_o0c.c +++ b/src/ov_SC06_016/ov_SC06_016_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_016/nonmatchings/ov_SC06_016_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_018/ov_SC06_018_o0c.c b/src/ov_SC06_018/ov_SC06_018_o0c.c index 172e2042a..f6b078376 100644 --- a/src/ov_SC06_018/ov_SC06_018_o0c.c +++ b/src/ov_SC06_018/ov_SC06_018_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_018/nonmatchings/ov_SC06_018_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_020/ov_SC06_020_o0c.c b/src/ov_SC06_020/ov_SC06_020_o0c.c index 35c1737de..b4d4b927c 100644 --- a/src/ov_SC06_020/ov_SC06_020_o0c.c +++ b/src/ov_SC06_020/ov_SC06_020_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_020/nonmatchings/ov_SC06_020_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_022/ov_SC06_022_o0c.c b/src/ov_SC06_022/ov_SC06_022_o0c.c index 4fb2ddebc..0e0d521d9 100644 --- a/src/ov_SC06_022/ov_SC06_022_o0c.c +++ b/src/ov_SC06_022/ov_SC06_022_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_022/nonmatchings/ov_SC06_022_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_024/ov_SC06_024_o0c.c b/src/ov_SC06_024/ov_SC06_024_o0c.c index 13811721a..58ee3755d 100644 --- a/src/ov_SC06_024/ov_SC06_024_o0c.c +++ b/src/ov_SC06_024/ov_SC06_024_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_024/nonmatchings/ov_SC06_024_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_025/ov_SC06_025_o0c.c b/src/ov_SC06_025/ov_SC06_025_o0c.c index 482993748..282830be2 100644 --- a/src/ov_SC06_025/ov_SC06_025_o0c.c +++ b/src/ov_SC06_025/ov_SC06_025_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_025/nonmatchings/ov_SC06_025_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_027/ov_SC06_027_o0c.c b/src/ov_SC06_027/ov_SC06_027_o0c.c index 6edcc9027..f45f2800a 100644 --- a/src/ov_SC06_027/ov_SC06_027_o0c.c +++ b/src/ov_SC06_027/ov_SC06_027_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_027/nonmatchings/ov_SC06_027_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_029/ov_SC06_029_o0c.c b/src/ov_SC06_029/ov_SC06_029_o0c.c index 7763adc76..6969fa0b3 100644 --- a/src/ov_SC06_029/ov_SC06_029_o0c.c +++ b/src/ov_SC06_029/ov_SC06_029_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_029/nonmatchings/ov_SC06_029_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_030/ov_SC06_030_o0c.c b/src/ov_SC06_030/ov_SC06_030_o0c.c index 8fab0ae8a..5083cff37 100644 --- a/src/ov_SC06_030/ov_SC06_030_o0c.c +++ b/src/ov_SC06_030/ov_SC06_030_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_030/nonmatchings/ov_SC06_030_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_032/ov_SC06_032_o0c.c b/src/ov_SC06_032/ov_SC06_032_o0c.c index 43fb4b8c5..bd74ba5d7 100644 --- a/src/ov_SC06_032/ov_SC06_032_o0c.c +++ b/src/ov_SC06_032/ov_SC06_032_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_032/nonmatchings/ov_SC06_032_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC06_033/ov_SC06_033_o0c.c b/src/ov_SC06_033/ov_SC06_033_o0c.c index 0cbef31f9..989e3faa1 100644 --- a/src/ov_SC06_033/ov_SC06_033_o0c.c +++ b/src/ov_SC06_033/ov_SC06_033_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC06_033/nonmatchings/ov_SC06_033_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC07_000/ov_SC07_000_o0c.c b/src/ov_SC07_000/ov_SC07_000_o0c.c index 92156d919..90ab11c4e 100644 --- a/src/ov_SC07_000/ov_SC07_000_o0c.c +++ b/src/ov_SC07_000/ov_SC07_000_o0c.c @@ -914,7 +914,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_000/nonmatchings/ov_SC07_000_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC07_001/ov_SC07_001_o0c.c b/src/ov_SC07_001/ov_SC07_001_o0c.c index 87d8514f7..668c2fb3c 100644 --- a/src/ov_SC07_001/ov_SC07_001_o0c.c +++ b/src/ov_SC07_001/ov_SC07_001_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_001/nonmatchings/ov_SC07_001_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC07_002/ov_SC07_002_o0c.c b/src/ov_SC07_002/ov_SC07_002_o0c.c index bd154dc00..eab1e6aed 100644 --- a/src/ov_SC07_002/ov_SC07_002_o0c.c +++ b/src/ov_SC07_002/ov_SC07_002_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_002/nonmatchings/ov_SC07_002_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC07_006/ov_SC07_006_o0c.c b/src/ov_SC07_006/ov_SC07_006_o0c.c index 704fe5ffd..cd9b9ef12 100644 --- a/src/ov_SC07_006/ov_SC07_006_o0c.c +++ b/src/ov_SC07_006/ov_SC07_006_o0c.c @@ -866,7 +866,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_006/nonmatchings/ov_SC07_006_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC07_007/ov_SC07_007_o0c.c b/src/ov_SC07_007/ov_SC07_007_o0c.c index 0ef8c0c20..caf848091 100644 --- a/src/ov_SC07_007/ov_SC07_007_o0c.c +++ b/src/ov_SC07_007/ov_SC07_007_o0c.c @@ -866,7 +866,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_007/nonmatchings/ov_SC07_007_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC07_008/ov_SC07_008_o0c.c b/src/ov_SC07_008/ov_SC07_008_o0c.c index fa5adbdcb..f580f6c75 100644 --- a/src/ov_SC07_008/ov_SC07_008_o0c.c +++ b/src/ov_SC07_008/ov_SC07_008_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_008/nonmatchings/ov_SC07_008_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC07_009/ov_SC07_009_o0c.c b/src/ov_SC07_009/ov_SC07_009_o0c.c index fe9b0362e..8c833e108 100644 --- a/src/ov_SC07_009/ov_SC07_009_o0c.c +++ b/src/ov_SC07_009/ov_SC07_009_o0c.c @@ -912,7 +912,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_009/nonmatchings/ov_SC07_009_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +} diff --git a/src/ov_SC07_010/ov_SC07_010_o0.c b/src/ov_SC07_010/ov_SC07_010_o0.c index 88dfdb21282360d10b1b8ea17e6b8a6db7bd9708..af000f3c21d6c4626a647c105120b52dac5cc70a 100644 GIT binary patch delta 2278 zcmd^AO>War5MEYFStYJmAf!PE!Z-33%=(nvAYmJ--E#bLJySEq>fS=2D&7K3NKK4 z>Bj&_DGP}tM2crY*$mCZ*d!F_Yv>_f*VE!@-SimOj5+#RJusaW;HGH6OOe70V1%Q`xN>uatDT#j0K{q<>L|dR#iHSL z{sv?iICzd^^S?t~vSafIp*bsMMU z_BgP>_5vA=&X3b90k^;_QS!6&1FsT){$@ECK9LwbyBj^^L|6l%_wx5c0paxr7f*(i{_Aqs0K?9@_)HLoVSieaWbM48|ESfx;E>m zg>N(KnyqdU$XA*ZQ>=bCJ2z>tc9s7*+s(&bQU3jtm;2a*5) diff --git a/src/ov_SC07_011/ov_SC07_011_o0c.c b/src/ov_SC07_011/ov_SC07_011_o0c.c index e16a00536..ed29efe49 100644 --- a/src/ov_SC07_011/ov_SC07_011_o0c.c +++ b/src/ov_SC07_011/ov_SC07_011_o0c.c @@ -866,7 +866,80 @@ void func_8013C0F8(int param_1) { DEFINE_func_8013C360() /* dedup: shared engine-core @0x8013C360 (src/shared) */ -INCLUDE_ASM("asm/ov_SC07_011/nonmatchings/ov_SC07_011_o0c", func_8013C414); + +void func_8013C414(s32 param_1, s32 param_2) +{ + s32 base10; /* 0x00 */ + s32 p; /* 0x04 */ + s32 q; /* 0x08 */ + s32 base4008; /* 0x0C */ + s32 lo; /* 0x10 */ + u32 i; /* 0x14 */ + s32 unused; /* 0x18 */ + s32 base8; /* 0x1C */ + T3Reloc *r; /* 0x20 */ + T3Reloc *s; /* 0x24 */ + + if (*(s32 *)(param_2 + 4) == 0) { + base10 = param_2 + 0x10; + base4008 = param_1 + 0x4008; + lo = *(s32 *)(param_2 + 0xC) + base10; + base8 = param_1 + 8; + p = base10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)p = *(s32 *)p + base8; + if (*(s32 *)(p + 4) != 0) { + *(s32 *)(p + 4) = *(s32 *)(p + 4) + base10; + q = *(s32 *)(p + 4); + *(s32 *)q = *(s32 *)q + q; + *(s32 *)(q + 0x14) = *(s32 *)(q + 0x14) + q; + r = (T3Reloc *)*(s32 *)(q + 0x14); + *(s32 *)(q + 0x18) = *(s32 *)(q + 0x18) * 0xC + *(s32 *)(q + 0x14); + s = (T3Reloc *)*(s32 *)(q + 0x18); + while (r < s) { + switch (r->type) { + case 0x24: + case 0x2C: + case 0x34: + case 0x3C: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if ((*(u32 *)r) & 0x800000) { + (*(u32 *)r) = ((*(u32 *)r) & 0x7FFFFF) + lo; + } else { + (*(u32 *)r) = ((*(u32 *)r) & 0xFFFFFF) + base4008; + } + break; + } + r++; + } + } + p = p + 0xC; + } + *(s32 *)(param_2 + 4) = 1; + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + if (*(s32 *)(p + 8) == 0) { + *(s32 *)(p + 8) = *(s32 *)(*(s32 *)p); + } + p = p + 0xC; + } + } else { + p = param_2 + 0x10; + for (i = 0; i < *(u32 *)(param_2 + 8); i++) { + *(s32 *)(*(s32 *)p) = *(s32 *)(p + 8); + p = p + 0xC; + } + } +}