From ef48a0c4995545a4c1026b4eedfa1b74ec7b10f2 Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 11 Sep 2026 01:10:04 -0600 Subject: [PATCH] =?UTF-8?q?phase-36:=20S104=20s104=5Fe7=20=E2=80=94=20func?= =?UTF-8?q?=5F80181BBC=20banked=20at=200=20through=20the=20whole-object=20?= =?UTF-8?q?gate=20+=20propagated=20=E2=80=94=20$4=20pin=20=E2=86=92=200:?= =?UTF-8?q?=20every=20temp=20one=20value=20(a=20multi-death=20local=20is?= =?UTF-8?q?=20refused=20by=20local-alloc.c:472)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../agents/ov_SC02_017__func_80181294/body.c | 69 ++++ .../ov_SC02_017__func_80181294/mechanism.md | 42 ++ .../agents/ov_SC02_017__func_80181BBC/body.c | 17 + .../ov_SC02_017__func_80181BBC/mechanism.md | 36 ++ .../agents/ov_SC02_017__func_80181E98/body.c | 60 +++ .../ov_SC02_017__func_80181E98/mechanism.md | 47 +++ .../agents/ov_SC02_017__func_801831FC/body.c | 35 ++ .../ov_SC02_017__func_801831FC/mechanism.md | 40 ++ .run/P36/delever/calibration.json | 372 +++++++++--------- .run/P36/delever/ledger.jsonl | 1 + src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c | 34 +- 11 files changed, 544 insertions(+), 209 deletions(-) create mode 100644 .run/P36/agents/ov_SC02_017__func_80181294/body.c create mode 100644 .run/P36/agents/ov_SC02_017__func_80181294/mechanism.md create mode 100644 .run/P36/agents/ov_SC02_017__func_80181BBC/body.c create mode 100644 .run/P36/agents/ov_SC02_017__func_80181BBC/mechanism.md create mode 100644 .run/P36/agents/ov_SC02_017__func_80181E98/body.c create mode 100644 .run/P36/agents/ov_SC02_017__func_80181E98/mechanism.md create mode 100644 .run/P36/agents/ov_SC02_017__func_801831FC/body.c create mode 100644 .run/P36/agents/ov_SC02_017__func_801831FC/mechanism.md diff --git a/.run/P36/agents/ov_SC02_017__func_80181294/body.c b/.run/P36/agents/ov_SC02_017__func_80181294/body.c new file mode 100644 index 0000000000..7ae13df5b6 --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_80181294/body.c @@ -0,0 +1,69 @@ +s32 func_80181294(s32 arg0) { + s32 e; /* *(s32 *)(arg0 + 0x20) -- the owned effect/entity */ + s16 *rot; /* (s16 *)(e + 0x10) : rot[0]=0x10 rot[1]=0x12 rot[2]=0x14 */ + s32 i; + s32 t; + s32 t2; + s32 base1; + s32 base2; + u16 sp10[3]; + + e = *(s32 *)(arg0 + 0x20); + rot = (s16 *)(e + 0x10); + + if (rand() & 1) { + *(u16 *)(e + 0x14) += *(s16 *)(arg0 + 0xFC) * (rand() % 8 + 1); + } + + if (rot[2] > 0x38) { + *(s16 *)(arg0 + 0xFC) = -1; + rot[2] = 0x38; + } else if (rot[2] < -0x38) { + *(s16 *)(arg0 + 0xFC) = 1; + rot[2] = -0x38; + } + + if (*(s32 *)(arg0 + 0x1C) % 10 == 0) { + sp10[1] = D_8018E40A; + for (i = 0; i < 5; i++) { + t = rand() % 80; + sp10[0] = ((rand() & 1) == 0) ? -t : t; + t2 = rand() % 16; + sp10[2] = ((rand() & 1) == 0) ? -t2 + 0x40 : t2 + 0x40; + ((void (*)(s32, void *, s32))func_8017DC70)(arg0, sp10, 1); + } + func_8002D4C8(0xBA0, 0); + if (*(s32 *)(arg0 + 0x1C) % 10 == 0) { + sp10[0] = *(u16 *)(arg0 + 0x6); + sp10[1] = *(u16 *)(arg0 + 0xA); + sp10[2] = *(u16 *)(arg0 + 0xE) + 0x50; + for (i = 0; i < 10; i++) { + s32 v; + t = rand() % 80; + base1 = *(s16 *)(arg0 + 0x6); + if ((rand() & 1) == 0) { + v = base1 - t; + } else { + v = base1 + t; + } + sp10[0] = v; + t = rand() % 56; + base2 = *(s16 *)(arg0 + 0xA); + if ((rand() & 1) == 0) { + v = base2 - t; + } else { + v = base2 + t; + } + sp10[1] = v; + func_80143BDC(sp10); + } + } + } + + if (func_8012BEE8(arg0)) { + rot[2] = 0; + func_8012B23C(arg0); + return 1; + } + return 0; +} diff --git a/.run/P36/agents/ov_SC02_017__func_80181294/mechanism.md b/.run/P36/agents/ov_SC02_017__func_80181294/mechanism.md new file mode 100644 index 0000000000..740b3c3116 --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_80181294/mechanism.md @@ -0,0 +1,42 @@ +# func_80181294 — e7 (P36 T7 S104) — score 10 (sweep best 9) -> 0, ZERO levers (was: 1 NEEDED `$2` pin) + +(a) Residual: COUNT 191 vs 192 + v1->v0 on the first loop's jitter value: the target keeps `v = ±t` in `v0` +(`bnez v0,…; move v0,s0` / `negu v0,s0` / `sh v0,16(sp)`), the lever-free text in `v1`; the knock-on moves the second +jitter (`±t2 + 0x40`) into a cross-jumped shape one insn shorter. + +(b) Pass/decision (dump-verified: `scratch/dumps_body_free`, `scratch/dumps_e10`, `.lreg`/`.greg`): + `if ((rand() & 1) == 0) v = -t; else v = t;` is an if/else whose ELSE value is a plain REG, so jump1's + "`if (...) x = a; else x = b;` -> `x = b; if (...) x = a;`" transform (jump.c:699-760; the REG destination test at + :731, the REG/SUBREG/constant source test at :739-741) HOISTS `v = t` above the `andi v0,v0,1; beqz` test (free + `.lreg` insn 479 `(set r121 r76)` sits between the `rand` call_insn 165 and the `and` insn 168). The hoisted copy is + born while the call result is still live in `v0`, so the variable (free r121, shared by both jitter sites, 12 refs) conflicts + with hard `v0` (`.greg` ";; 121 conflicts: 72 74 75 76 121 2 29") and global gives it `v1` ("121 in 3"). + Written as `sp10[0] = cond ? -t : t;`, the conversion to the `u16` slot is folded into the arms and the COND_EXPR is + expanded into a HImode temp (e10 r131, "2 bytes"): the negated arm's destination is `(subreg:SI (reg:HI 131) 0)`, a + SUBREG, so the transform's `SET_DEST == REG` test (jump.c:731) fails, the copy stays in its arm, the temp never + conflicts with `v0` (";; 131 conflicts: 72 74 75 131 29"), prefers `v0` and gets it ("131 in 2"). Reorg later fills + the branch delay slot with the arm's `move v0,s0` — the target's shape. + +(c) Move (one): the first jitter as a conditional expression stored straight into its slot: + `sp10[0] = ((rand() & 1) == 0) ? -t : t;` (scratch/e10.c: this move ALONE scores 0). body.c spells the second + jitter the same way for uniformity (`sp10[2] = ((rand() & 1) == 0) ? -t2 + 0x40 : t2 + 0x40;`, e5 = 0; also + `(… ? -t2 : t2) + 0x40`, e9 = 0). The `s32 v` local is gone. + +(d) GENERATOR PROPOSAL: when a local is assigned in an if/else whose else arm is a plain register copy +(`if (c) v = -x; else v = x;`) and then only stored to a narrower (u16/s16/u8) memory slot, rewrite the pair as +`slot = c ? -x : x;` — the narrowed COND_EXPR temp is a SUBREG destination that jump.c's if-conversion (:731) refuses, +so the copy is not hoisted above the test (the inverse of S104 d1's "never a ternary", which was for a full-width +value). + +(e) Did not work: e1 (two locals `v`/`w`, if/else) 3; e4 (first if/else via `v`, second stores direct) 3; e2/e3 +(if/else storing straight to `sp10[0]` in each arm) 9 COUNT — two stores, cross-jump shape differs; e6 (one `t` for +both modulos) 14; e11 (`v = c ? -t : t; sp10[0] = v;` — SImode ternary into the variable) 10: the SImode COND_EXPR +has a REG destination and jump1 hoists it the same way. The sweep's R7/R8/R10/R12 moves best 9. + +(f) Method: the header's lever note 1 ("as a plain local it is a global_alloc allocno and lands in $v1") was TRUE but +named the symptom; the cause is jump1's if-conversion hoisting the else copy. METHOD S104 (d1) points the other way +("never a ternary", for a full-width value set before a call); the distinguishing fact is the narrowing store. +The header comment's claim 3 (the `+0x40` must be in both arms) is also refuted on bytes (e9 = 0). + +(g) Structs: no. `sp10` is a `u16[3]` local; a struct (x/y/z) would keep the HImode store and the same jump1 decision. +The decision is the if-conversion's destination-code test, not memory aliasing. diff --git a/.run/P36/agents/ov_SC02_017__func_80181BBC/body.c b/.run/P36/agents/ov_SC02_017__func_80181BBC/body.c new file mode 100644 index 0000000000..88d239c4f3 --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_80181BBC/body.c @@ -0,0 +1,17 @@ +void func_80181BBC(s32 a0) +{ + u16 uVar1; + + if (func_8012C438(a0, (s32)D_8018E4F8) == 0) { + return; + } + func_8001D0E8(*(s32 *)(a0 + 0x20), 0x1E0, 0x168); + *(s32 *)(*(s32 *)(a0 + 0x20) + 0x20) = (s32)D_8018E540; + uVar1 = *(u16 *)(*(s32 *)(a0 + 0x64) + 0x36); + *(u8 *)(a0 + 0x75) = 4; + *(u16 *)(a0 + 0xFE) = uVar1; + *(s32 *)(*(s32 *)(a0 + 0x20) + 4) |= 0x8000; + func_8001D0E8(*(s32 *)(a0 + 0x20), 0x1E0, 0x168); + *(u16 *)(a0 + 2) = 1; + *(u16 *)(a0 + 0xA) += 0x36; +} diff --git a/.run/P36/agents/ov_SC02_017__func_80181BBC/mechanism.md b/.run/P36/agents/ov_SC02_017__func_80181BBC/mechanism.md new file mode 100644 index 0000000000..4416bf2af9 --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_80181BBC/mechanism.md @@ -0,0 +1,36 @@ +# func_80181BBC — e7 (P36 T7 S104) — score 9 (sweep best 4) -> 0, ZERO levers (was: 1 NEEDED `$4` pin) + +(a) Residual: REG, a v1/a0 permutation in the single straight-line block between the two `func_8001D0E8` calls — the +target puts the first `*(s0+0x20)` pointer and the `lhu 0x36` value in `v1` and the second `*(s0+0x20)` pointer (the +`|= 0x8000` object) in `a0`; the lever-free text swaps them. Counts equal (39/39). The tree pinned `a0_2` to `$4`. + +(b) Pass/decision (dump-verified, `scratch/dumps_c1` vs `scratch/dumps_c5`, `.lreg`): the decompiler text REUSES two +locals for several values — `v1` = pointer, then the u16, then the constant 1; `v0` = `*(s0+0x64)`, then the flag word, +then the `+0xA` halfword. Each reused local "dies in N places" (`.lreg`: r74 v0 "dies in 3 places", r75 v1 "dies in 2 +places"), so local-alloc refuses it (`local-alloc.c:472`, `reg_n_deaths[i] == 1` required for a block-local quantity) +and it goes to global.c, which fills v0/v1 by priority AFTER local-alloc has already placed the single-death `a0_2` in +`v1` (c5 `.lreg`: ";; Register 76 in 3"). With one pseudo per value every temp is a block-local quantity +(c1 `.lreg`: eleven one-block registers, `a0_2`-equivalent r80 "in 4", the u16 r84 "in 3") and `qty_compare_1`'s +ranking (local-alloc.c:1598) reproduces the target. + +(c) Move (one, joint over two variables): give every value its own temp — either inline them (`body.c`, the house +spelling: `*(s32 *)(*(s32 *)(a0 + 0x20) + 4) |= 0x8000;`, `*(u16 *)(a0 + 0xA) += 0x36;`, one `u16 uVar1` for the +`0x36` read, as sibling func_80181A98 TU:5063 spells it) or rename each value (scratch/c8.c, also 0). The `s0 = a0` +param copy is irrelevant (c3 without it: 9; c4 with it + inlined temps: 0); body.c drops it (d24). +Byte-proven: c1 (body.c) 0, c8 (all renamed) 0, c4 0. + +(d) GENERATOR PROPOSAL: when the residual is a register permutation inside one basic block and `.lreg` shows two or +more body locals that "die in N>1 places", split ALL of them at once (one name per assignment, or inline each +single-use temp) — R23 splitting one variable at a time cannot reach it (c2 splitting only `v1`: 10; c5 only the +first pointer role: 7). + +(e) Did not work: c2 (split v1 alone) 10; c5 (inline the first pointer only) 7; c6 (inline the `|= 0x8000` only) 9; +c7 (inline the `0x64` pointer only) 9; c3 (delete the `s0` copy only) 9. The sweep's R8/R12 moves reached 4 (COUNT). + +(f) Method: METHOD S103 c1/c8 ("a local REUSED across statement groups dies more than once and is refused by +local-alloc — split it") is exactly this; the only extra fact is that BOTH reused locals had to be split together. +The natural rewrite (inline, as the sibling func_80181A98 reads) closed on the first `--try`. + +(g) Structs: no. The decision is block-local quantity eligibility (death count) in local-alloc; a struct type for the +object (`+0x20` sub-object with `+0x04` flags / `+0x20` pointer, `+0x64` owner with `u16 +0x36`, `u8 +0x75`, `u16 +0xFE`) +would change the spelling, not the number of pseudos. diff --git a/.run/P36/agents/ov_SC02_017__func_80181E98/body.c b/.run/P36/agents/ov_SC02_017__func_80181E98/body.c new file mode 100644 index 0000000000..526132369e --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_80181E98/body.c @@ -0,0 +1,60 @@ +s32 func_80181E98_impl(void *arg) +{ + extern void func_8012F214(s32 a0, s32 a1, s32 a2); + extern s32 func_80013478(s32 a0, s32 a1); + extern void func_8002D4C8(s32 a0, s32 a1); + extern s32 D_8018E564; + extern u8 D_800AF648; + extern u8 D_80126B5C; + + struct { + s16 in0[4]; + s16 in1[4]; + s16 sxy[2]; + s32 flag; + } w; + s32 t; + s32 r; + s32 k; + + func_8012F214((s32)arg, (s32)&D_8018E564, (s32)w.in0); + gte_SetRotMatrix(&D_800AF648); + gte_SetTransMatrix(&D_800AF648); + gte_ldv0(w.in0); + gte_rtps(); + gte_stsxy(w.sxy); + gte_stflg(&w.flag); + if (w.flag & 0xFFFFEFFF) { + return 0; + } + t = w.sxy[0]; + if (t < 0) { + t = -t; + } + if (t >= 0xAB || (w.sxy[1] >= 0 ? w.sxy[1] >= 0x83 : -w.sxy[1] >= 0x83)) { + w.in1[0] = *(s16 *)((s32)arg + 6); + w.in1[1] = *(s16 *)((s32)arg + 10); + w.in1[2] = *(s16 *)((s32)arg + 14); + gte_ldv0(w.in1); + gte_rtps(); + gte_stsxy(w.sxy); + gte_stflg(&w.flag); + if (w.flag & 0xFFFFEFFF) { + return 0; + } + t = w.sxy[0]; + if (t < 0) { + t = -t; + } + if (t >= 0x105 || (w.sxy[1] >= 0 ? w.sxy[1] >= 0x8D : -w.sxy[1] >= 0x8D)) { + return 0; + } + } + r = func_80013478((s32)&D_80126B5C, (s32)w.in0); + k = 0x5A0; + if (r <= 0x41010) { + k = 0x59F; + } + func_8002D4C8(k, 0); + return 1; +} diff --git a/.run/P36/agents/ov_SC02_017__func_80181E98/mechanism.md b/.run/P36/agents/ov_SC02_017__func_80181E98/mechanism.md new file mode 100644 index 0000000000..109e101cad --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_80181E98/mechanism.md @@ -0,0 +1,47 @@ +# func_80181E98 — e7 (P36 T7 S104) — score 11 (sweep best 11) -> 0, ZERO levers (was: 1 NEEDED barrier) + +(a) Residual: COUNT 124 vs 129. The second `|sxy[1]| < 0x8D` sign-split test: the target keeps two arms +(`bltz v0,NEG; nop; slti 141; beqz ret; move v0,zero; j pass` / `NEG: negu; slti 141; beqz ret; move v0,zero; pass:`), +the lever-free text merges them into a conditional negate (`bgez L; nop; negu; L: slti 141; beqz ret`), -5 insns. +The tree kept them apart with an empty `__asm__ __volatile__("")` before arm 1's `goto pass`. + +(b) Pass/decision (dump-verified: `scratch/g2_greg.txt` = post-reload RTL entering jump2, vs `scratch/gt_jump2.txt`): + Post-reload cross-jump (toplev.c:3142 `jump_optimize (insns, 1, 1, 0)`; the simplejump case jump.c:1971-1999, + `find_cross_jump` jump.c:2371, minimum 1) compares the insns before arm 1's `j pass` with the insns before label + `pass`. With `goto ret0` (one shared `return 0;` at the end) arm 2 falls straight into `pass`, both streams end + `slt 141; beq ret0` and are merged (every goto spelling, and every if/else spelling, scored 11 in the enumeration). + Written as ONE `if` with a ternary condition and an INLINE `return 0;`: + `if (t >= 0x105 || (w.sxy[1] >= 0 ? w.sxy[1] >= 0x8D : -w.sxy[1] >= 0x8D)) return 0;` + `do_jump`'s COND_EXPR case (expr.c:9124-9150) emits each arm as "branch to the if-false label (`pass`) / else + drop through" and the `return 0` body (`v0 = 0; j return`) is laid out AFTER both arms, i.e. BETWEEN arm 2 and + `pass` (g2: arm 1 = insns 173 slt / 174 `beq ->189` / 175 `j 200`; arm 2 = 182 neg / 184 slt / 185 `bne ->200`; + 189: `v0 = 0; j 248`; 200: pass). The insn before label `pass` is now the return block's `j 248`, not a + condjump, so `find_cross_jump` fails on its first comparison (jump.c:2469-2470) and the arms stay apart. Reorg then + steals `move v0,zero` into each branch's delay slot and inverts arm 2's branch over the return jump — the target's + `beqz ret; move v0,zero` in both arms. + +(c) Moves (joint; found by enumerating 52 structural spellings, `scratch/gen.py` -> `scratch/enum/`): + - every `goto ret0;` -> an inline `return 0;` (the `ret0:` label deleted); + - the second sign-split test -> one condition with a ternary per sign (S104 d11's shape); + - (readability, byte-neutral) the whole goto chain -> structured: `if (t >= 0xAB || (<0x83 ternary>)) { second + projection …; if (flag) return 0; if (t >= 0x105 || (<0x8D ternary>)) return 0; }` then the pass code. + Scores: all 4 variants with inline `return 0` + the 0x8D ternary = 0 (goto/structured first test, `t` by if or + ternary); inline `return 0` with any if/else sign split = 11; `goto ret0` with the ternary = 11; `||`/`&&`-split + sign test = 17/18. body.c = `scratch/g2.c` (0). + +(d) GENERATOR PROPOSAL: when a `barrier` lever sits in one arm of a sign-split range test +(`if (v >= 0) { if (v >= K) goto FAIL; …goto OK; } else { if (-v >= K) goto FAIL; }`) and FAIL is a shared +`return C;` label, rewrite the test as `if (v >= 0 ? v >= K : -v >= K) return C;` with the return INLINE — do_jump +places the return body between the second arm and OK, which cross-jump cannot match (extends S104 d11: the inline +return, not just the ternary, is what closes it here). + +(e) Did not work: 48 of the 52 enumerated spellings (listed above by class); f1/f2 (ternary with `goto ret0`) 11/17. +The sweep's R7/R8 moves all 11 (none changes the return placement or the goto chain). + +(f) Method: METHOD S104 (d11) named the ternary but not the inline return; the enumeration (d14's lesson, 52 bodies in +under a minute with `xargs -P6` over `--try`) found the joint move, the post-reload RTL (`.greg`) explained it. + +(g) Structs: no. The decision is block layout + cross-jump pattern matching; the local `w` is already a struct. +Also noted: the TU's `func_80181E98_impl … __asm__("func_80181E98")` asm-label reconcile (a stale `void` forward +declaration elsewhere in the TU) is untouched — it is a declaration alias, not a lever; fixing the TU's `extern void +func_80181E98(u8 *a0);` to `s32 (void *)` would let the body use its real name (parked, TU-wide change). diff --git a/.run/P36/agents/ov_SC02_017__func_801831FC/body.c b/.run/P36/agents/ov_SC02_017__func_801831FC/body.c new file mode 100644 index 0000000000..5fde9853c0 --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_801831FC/body.c @@ -0,0 +1,35 @@ +void func_801831FC(s32 arg0) { + s16 buf[4]; + s32 base; + s32 s1; + s16 dist; + s32 q; + s16 vol; + + base = (s32)&D_80126B58; + s1 = (s32)D_8018E8EC + (*(s16 *)(arg0 + 0xFC)) * 8; + if (*(s16 *)(s1 + 0x6) == 0) { + return; + } + func_80015978(base + 4, (s32 *)buf); + if (*(s16 *)(arg0 + 0xFC) == 3) { + if (buf[1] < -0xB00) { + return; + } + buf[1] = *(u16 *)(s1 + 0x2); + } + dist = func_80013294((void *)buf, (void *)s1); + if (dist >= 0x800) { + return; + } + q = (0x800 - dist) * 127 / 0x800; + if (q < 0) { + vol = 0; + } else { + vol = q; + } + if (vol >= 0x80) { + vol = 0x7F; + } + func_8002D4C8(*(u16 *)(s1 + 0x6), (u16)(vol | 0x1000)); +} diff --git a/.run/P36/agents/ov_SC02_017__func_801831FC/mechanism.md b/.run/P36/agents/ov_SC02_017__func_801831FC/mechanism.md new file mode 100644 index 0000000000..be1ee61cdd --- /dev/null +++ b/.run/P36/agents/ov_SC02_017__func_801831FC/mechanism.md @@ -0,0 +1,40 @@ +# func_801831FC — e7 (P36 T7 S104) — score 6 (sweep best 6) -> 0, ZERO levers (was: 1 NEEDED `$2` pin) + +(a) Residual: REG, 8 insns: the product `(0x800 - d) * 127` (expanded `t = 0x800-d; u = t<<7; r = u - t`) and the +following `+0x7FF` / `>> 11` live in `v1` in the lever-free text, in `v0` in the target. Counts equal (62/62). + +(b) Pass/decision (dump-verified, `scratch/dumps_free`, `scratch/dumps_d4`; `tools/alloc_table.py`): + The decompiler text spells a SIGNED DIVISION BY 0x800 by hand (`if (v0 < 0) v0 += 0x7FF; v0 = v0 >> 11;`) and writes + the shift back into the same variable, which is ALSO the call-result variable. The dividend pseudo (free r74, global — + it spans the conditional add) then has one preference only: the minus's first operand `u` (`set_preference`, + global.c:1535, `src = XEXP (src, 0)` for a non-copy at :1545-1546) = `v1` -> `find_reg` gives it `v1`. + Written as `q = (0x800 - dist) * 127 / 0x800;`, `expand_divmod` makes the dividend a fresh temp (d4 r109) and the + QUOTIENT a separate pseudo set by `(ashiftrt r109 11)` (insn 120, REG_EQUAL `div … 2048`). The quotient is + block-local, local-alloc puts it in `v0`, and `set_preference (r74=v0, (ashiftrt r109 …))` gives r109 a SECOND + preference, `v0` (d4 table: "r109 prefers v0,v1"). `find_reg`'s preference scan runs from hard reg 0 upward + (global.c:1043-1044), so `v0` (2) is taken before `v1` (3) — the target. + +(c) Moves (joint; each alone scores 6): + - the hand-expanded division -> `/ 0x800` into a NEW variable `q` (d3: new variable, hand shift: 6); + - the call result straight into the `s16 dist` (no shared `v0` temp; d1: `/ 0x800` but the quotient still the + call-result variable: 6). + body.c also renames (`dist`, `q`, `vol`) and drops the `s0 = arg0` copy (both byte-neutral, d5/d6 = 0). + +(d) GENERATOR PROPOSAL: when the text has `if (x < 0) x += 2^k-1; x = x >> k;` (the gcc signed-pow2 division +expansion, `expmed.c` expand_divmod), rewrite it as `y = / 2^k;` into a fresh local and route the +x-producing call result into its own typed local — a decompiler-undone division; the quotient's separate pseudo adds a +`set_preference` that steers the dividend's register. + +(e) Did not work: d1 (`/0x800`, quotient = the call-result variable) 6; d3 (fresh `q`, hand-written add/shift) 6; the +sweep's R4/R6/R7/R8/R9 moves all 6 (none undoes the hand-expanded division). + +(f) Method: the allocation table's "prefers" column was the whole answer (free r74 "prefers v1" only; d4 r109 "prefers +v0,v1"). No METHOD row covers "a hand-expanded division"; add one: `bgez; addiu 2^k-1; sra k` in the target = write `/`. + +(g) Structs: no. The decision is global.c preferences between pseudos of one arithmetic chain; the `D_8018E8EC[idx]` +8-byte record (`s16 +2`, `s16 +6`) as a struct would not change it. + +BONUS (other TU, read-only test): the same shape in `src/ov_SC02_011/ov_SC02_011_jr_80183178.c` func_80188034 (also a +NEEDED `$2` pin, "tus9") closes at 0 with the same move plus the clamp as `if (q < 0) a1v = 0; else a1v = q;` and +`a1v` declared `s16`: `scratch/sib3.c` (`--try … func_80188034 scratch/sib3.c --body` -> score 0). sib2 (same but +`s32 a1v` with `(s16)` casts) scores 9. diff --git a/.run/P36/delever/calibration.json b/.run/P36/delever/calibration.json index 41b9ac0521..296e3eeac0 100644 --- a/.run/P36/delever/calibration.json +++ b/.run/P36/delever/calibration.json @@ -1,7 +1,7 @@ { - "head": "c4c60c917", + "head": "16c9d2fb6", "stamp": "15956e4a96c4", - "generated": "2026-09-11 01:05", + "generated": "2026-09-11 01:09", "aliases": [ "main", "ov_SC03_014", @@ -21,207 +21,207 @@ "main": { "objects": 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b/.run/P36/delever/ledger.jsonl index 6eaaa2b42f..d63e3a0f09 100644 --- a/.run/P36/delever/ledger.jsonl +++ b/.run/P36/delever/ledger.jsonl @@ -29370,3 +29370,4 @@ {"ts": "2026-09-11 00:46:07", "label": "s104_e4", "rung": "E", "calib": {"head": "b06062ac1", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c", "fn": "func_80184754", "addr": 2149074772, "aliases": null, "header": false, "includers": 0, "nhash_before": "c2a6f3a0b78c04029745eb0b1c8d287949aa509d", "nhash_after": "72986c87550de892e6d998262e855e559cec0512", "source": ".run/P36/agents/ov_SC02_017__func_80184754/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.274, "objects": ["build/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.o"], "before_text": "void func_80184754(void *a0)\n{\n s32 s0 = (s32)a0;\n s32 s1;\n\n __asm__ __volatile__(\"\" : \"=r\"(s0) : \"0\"(s0)); // !FAKE: launder \u2014 NEEDED DIFFERS (P36 rung B tus8)\n\n s1 = *(s32 *)(s0 + 0x64);\n\n if (*(s16 *)(s0 + 0xFC) != *(s16 *)(s1 + 0x36)) {\n ((void (*)(void))func_8012C218)();\n return;\n }\n\n if (*(s32 *)(s1 + 0x1C) == 0) {\n func_80132288(&D_801EFA68, &D_801CC38C, D_801CCE84);\n } else {\n *(s32 *)(s0 + 0x4) = *(s32 *)(s1 + 0x4);\n *(s32 *)(s0 + 0x8) = *(s32 *)(s1 + 0x8);\n *(s32 *)(s0 + 0xC) = *(s32 *)(s1 + 0xC);\n *(SV4x_80184754 *)(*(s32 *)(s0 + 0x20) + 0x10) = *(SV4x_80184754 *)(*(s32 *)(s1 + 0x20) + 0x10);\n *(SV4x_80184754 *)(*(s32 *)(s0 + 0x20) + 0x18) = *(SV4x_80184754 *)(*(s32 *)(s1 + 0x20) + 0x18);\n *(u16 *)(*(s32 *)(s0 + 0x20) + 0x2C) = *(u16 *)(*(s32 *)(s1 + 0x20) + 0x2C);\n *(s32 *)(*(s32 *)(s0 + 0x20) + 0x4) = *(s32 *)(*(s32 *)(s1 + 0x20) + 0x4);\n func_8013240C((s32)&D_801EFA68);\n }\n}\n", "after_text": "void func_80184754(void *a0)\n{\n s32 s1;\n\n s1 = *(s32 *)((s32)a0 + 0x64);\n\n if (*(s16 *)((s32)a0 + 0xFC) != *(s16 *)(s1 + 0x36)) {\n func_8012C218(a0);\n return;\n }\n\n if (*(s32 *)(s1 + 0x1C) == 0) {\n func_80132288(&D_801EFA68, &D_801CC38C, D_801CCE84);\n } else {\n *(s32 *)((s32)a0 + 0x4) = *(s32 *)(s1 + 0x4);\n *(s32 *)((s32)a0 + 0x8) = *(s32 *)(s1 + 0x8);\n *(s32 *)((s32)a0 + 0xC) = *(s32 *)(s1 + 0xC);\n *(SV4x_80184754 *)(*(s32 *)((s32)a0 + 0x20) + 0x10) = *(SV4x_80184754 *)(*(s32 *)(s1 + 0x20) + 0x10);\n *(SV4x_80184754 *)(*(s32 *)((s32)a0 + 0x20) + 0x18) = *(SV4x_80184754 *)(*(s32 *)(s1 + 0x20) + 0x18);\n *(u16 *)(*(s32 *)((s32)a0 + 0x20) + 0x2C) = *(u16 *)(*(s32 *)(s1 + 0x20) + 0x2C);\n *(s32 *)(*(s32 *)((s32)a0 + 0x20) + 0x4) = *(s32 *)(*(s32 *)(s1 + 0x20) + 0x4);\n func_8013240C((s32)&D_801EFA68);\n }\n}\n"} {"ts": "2026-09-11 00:47:00", "label": "s104_e4", "rung": "E", "calib": {"head": "bb7973c04", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c", "fn": "func_80186770", "addr": 2149082992, "aliases": null, "header": false, "includers": 0, "nhash_before": "7fc443e8e9bc6f61af024b9adeedc7849902e6d2", "nhash_after": "1d413cb518a360b40a4f9860d3a2f58a76725efc", "source": ".run/P36/agents/ov_SC02_017__func_80186770/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.363, "objects": ["build/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.o"], "before_text": "void func_80186770(s32 param_1)\n{\n struct { s32 vx, vy, vz, pad; } vec;\n s32 v;\n s32 d;\n s32 b178arg;\n void *target;\n\n switch (*(u16 *)(param_1 + 0x34)) {\n case 0:\n v = func_8012B8E4(param_1, 4);\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) += v;\n if (*(s32 *)(param_1 + 0x1C) == 0xF) {\n func_80142414(param_1, -0x78);\n func_8002D4C8(0x6A9, 0);\n }\n if (func_8012BEE8(param_1) != 0) {\n *(s16 *)(param_1 + 0x2) = 3;\n if ((*(u16 *)(param_1 + 0x86) & 2) != 0) {\n *(s16 *)(param_1 + 0x34) = 1;\n *(s32 *)(param_1 + 0x1C) = 0x28;\n if ((*(u16 *)(param_1 + 0x70) & 0x200) != 0) {\n func_8012A828(param_1, &D_801E1AFC);\n } else {\n func_8012A828(param_1, &D_801E11DC);\n }\n *(u16 *)(param_1 + 0xFE) = 0;\n } else {\n *(s16 *)(param_1 + 0x34) = 0;\n func_8012A828(param_1, &D_801E1264);\n *(s32 *)(param_1 + 0x1C) = 0x19;\n *(u16 *)(param_1 + 0x86) |= 2;\n }\n }\n break;\n case 1:\n v = func_8012B8E4(param_1, 6);\n b178arg = D_801D619C;\n {\n u16 *pp;\n register s32 nv __asm__(\"$6\"); // !FAKE: pin $6 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n\n pp = (u16 *)(*(s32 *)(param_1 + 0x20) + 0x12);\n nv = *pp + v;\n *pp = nv;\n }\n func_8012B178(param_1, b178arg);\n d = ((s32 (*)(s32))func_8012CBA4)(param_1);\n if ((d & 0x1000) != 0) {\n func_80131E00(param_1, 0x12);\n } else if (d != 0x2000) {\n func_8012ADE4((u8 *)param_1);\n }\n func_80185F88(param_1);\n v = *(u16 *)(param_1 + 0xFE) - 1;\n *(u16 *)(param_1 + 0xFE) = v;\n if ((v << 16) <= 0) {\n func_80143B6C(param_1, 0);\n *(u16 *)(param_1 + 0xFE) = 8;\n }\n if ((*(u16 *)(param_1 + 0x70) & 0x200) != 0) {\n func_80186C38(param_1, 0x11);\n }\n target = (void *)(param_1 + 0x88);\n vec.vx = *(s16 *)(param_1 + 6) - *(s16 *)(param_1 + 0x88);\n vec.vy = 0;\n vec.vz = *(s16 *)(param_1 + 0xE) - *(s16 *)(param_1 + 0x8C);\n Square0(&vec.vx, &vec.vx);\n if (vec.vx + vec.vz > 0x8FFFF || (d = func_8012BCCC(param_1), d > 0x24000)) {\n *(s16 *)(param_1 + 0x2) = 1;\n *(s16 *)(param_1 + 0x34) = 0;\n *(u16 *)(param_1 + 0x5C) = 0xAA10;\n *(s32 *)(param_1 + 0x1C) = (rand() & 0x1F) + 0x28;\n vec.vx = *(s16 *)(param_1 + 6) - *(s16 *)(param_1 + 0x88);\n vec.vy = 0;\n vec.vz = *(s16 *)(param_1 + 0xE) - *(s16 *)(param_1 + 0x8C);\n Square0(&vec.vx, &vec.vx);\n if (vec.vx + vec.vz > 0x8FFFF) {\n *(u16 *)(param_1 + 0xFC) = func_8012B744((void *)(param_1 + 4), target);\n } else {\n s32 t = rand() & 0x3FF;\n s32 off = t - 0x200;\n\n if (off < 0) {\n off = t - 0x500;\n } else {\n off = t + 0x100;\n }\n *(u16 *)(param_1 + 0xFC) =\n (*(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) + off) & 0xFFF;\n }\n func_8012A828(param_1, &D_801E1134);\n }\n if ((*(u16 *)(param_1 + 0x70) & 0x100) == 0) {\n if (func_8012BD3C(param_1, 0x400, 0x1000) != 0) {\n if ((*(u16 *)(param_1 + 0x70) & 0xF00) == 0) {\n ((void (*)(s32))func_80186B08)(param_1);\n } else {\n func_80186B34(param_1);\n }\n }\n } else {\n if (func_8012BD3C(param_1, 0x400, 0x40000) != 0) {\n func_80186B7C(param_1);\n }\n }\n break;\n }\n}\n", "after_text": "void func_80186770(s32 param_1)\n{\n struct { s32 vx, vy, vz, pad; } vec;\n s32 v;\n s32 d;\n void *target;\n\n switch (*(u16 *)(param_1 + 0x34)) {\n case 0:\n v = func_8012B8E4(param_1, 4);\n *(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) += v;\n if (*(s32 *)(param_1 + 0x1C) == 0xF) {\n func_80142414(param_1, -0x78);\n func_8002D4C8(0x6A9, 0);\n }\n if (func_8012BEE8(param_1) != 0) {\n *(s16 *)(param_1 + 0x2) = 3;\n if ((*(u16 *)(param_1 + 0x86) & 2) != 0) {\n *(s16 *)(param_1 + 0x34) = 1;\n *(s32 *)(param_1 + 0x1C) = 0x28;\n if ((*(u16 *)(param_1 + 0x70) & 0x200) != 0) {\n func_8012A828(param_1, &D_801E1AFC);\n } else {\n func_8012A828(param_1, &D_801E11DC);\n }\n *(u16 *)(param_1 + 0xFE) = 0;\n } else {\n *(s16 *)(param_1 + 0x34) = 0;\n func_8012A828(param_1, &D_801E1264);\n *(s32 *)(param_1 + 0x1C) = 0x19;\n *(u16 *)(param_1 + 0x86) |= 2;\n }\n }\n break;\n case 1:\n v = func_8012B8E4(param_1, 6);\n (*(u16 **)(param_1 + 0x20))[9] += v;\n func_8012B178(param_1, D_801D619C);\n d = ((s32 (*)(s32))func_8012CBA4)(param_1);\n if ((d & 0x1000) != 0) {\n func_80131E00(param_1, 0x12);\n } else if (d != 0x2000) {\n func_8012ADE4((u8 *)param_1);\n }\n func_80185F88(param_1);\n v = *(u16 *)(param_1 + 0xFE) - 1;\n *(u16 *)(param_1 + 0xFE) = v;\n if ((v << 16) <= 0) {\n func_80143B6C(param_1, 0);\n *(u16 *)(param_1 + 0xFE) = 8;\n }\n if ((*(u16 *)(param_1 + 0x70) & 0x200) != 0) {\n func_80186C38(param_1, 0x11);\n }\n target = (void *)(param_1 + 0x88);\n vec.vx = *(s16 *)(param_1 + 6) - *(s16 *)(param_1 + 0x88);\n vec.vy = 0;\n vec.vz = *(s16 *)(param_1 + 0xE) - *(s16 *)(param_1 + 0x8C);\n Square0(&vec.vx, &vec.vx);\n if (vec.vx + vec.vz > 0x8FFFF || (d = func_8012BCCC(param_1), d > 0x24000)) {\n *(s16 *)(param_1 + 0x2) = 1;\n *(s16 *)(param_1 + 0x34) = 0;\n *(u16 *)(param_1 + 0x5C) = 0xAA10;\n *(s32 *)(param_1 + 0x1C) = (rand() & 0x1F) + 0x28;\n vec.vx = *(s16 *)(param_1 + 6) - *(s16 *)(param_1 + 0x88);\n vec.vy = 0;\n vec.vz = *(s16 *)(param_1 + 0xE) - *(s16 *)(param_1 + 0x8C);\n Square0(&vec.vx, &vec.vx);\n if (vec.vx + vec.vz > 0x8FFFF) {\n *(u16 *)(param_1 + 0xFC) = func_8012B744((void *)(param_1 + 4), target);\n } else {\n s32 t = rand() & 0x3FF;\n s32 off = t - 0x200;\n\n if (off < 0) {\n off = t - 0x500;\n } else {\n off = t + 0x100;\n }\n *(u16 *)(param_1 + 0xFC) =\n (*(u16 *)(*(s32 *)(param_1 + 0x20) + 0x12) + off) & 0xFFF;\n }\n func_8012A828(param_1, &D_801E1134);\n }\n if ((*(u16 *)(param_1 + 0x70) & 0x100) == 0) {\n if (func_8012BD3C(param_1, 0x400, 0x1000) != 0) {\n if ((*(u16 *)(param_1 + 0x70) & 0xF00) == 0) {\n ((void (*)(s32))func_80186B08)(param_1);\n } else {\n func_80186B34(param_1);\n }\n }\n } else {\n if (func_8012BD3C(param_1, 0x400, 0x40000) != 0) {\n func_80186B7C(param_1);\n }\n }\n break;\n }\n}\n"} {"ts": "2026-09-11 01:05:57", "label": "s104_e3", "rung": "E", "calib": {"head": "c4c60c917", "stamp": "15956e4a96c4"}, "tu": "src/800_c.c", "fn": "func_80036FB0", "addr": 2147708848, "aliases": null, "header": false, "includers": 0, "nhash_before": "4c9ae2c827bb1e0345b6af0f0de266b44d262aa8", "nhash_after": "ea847aa1537017f7171e23041f21172a7eedd9c1", "source": ".run/P36/agents/main__func_80036FB0/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.262, "objects": ["build/src/800_c.o"], "before_text": "void func_80036FB0(s32 arg0, s32 arg1) {\n extern s32 D_8006AEE8;\n extern s32 D_80078F10;\n f64 hole;\n s32 count;\n s32 i;\n s32 *p;\n\n __asm__ volatile(\"\" :: // !FAKE: keepalive \u2014 NEEDED DIFFERS (P36 rung B tus9)\n \"m\"(hole));\n if (D_8006AEE8 > 0) {\n i = 0;\n count = D_8006AEE8;\n p = &D_80078F10;\n do {\n if (*p == arg0) {\n *p = arg1;\n }\n p++;\n i++;\n } while (i < count);\n }\n}\n", "after_text": "void func_80036FB0(s32 arg0, s32 arg1) {\n s32 i;\n\n for (i = 0; i < D_8006AEE8; i++) {\n if ((&D_80078F10)[i] == arg0) {\n (&D_80078F10)[i] = arg1;\n }\n }\n}\n"} +{"ts": "2026-09-11 01:10:00", "label": "s104_e7", "rung": "E", "calib": {"head": "16c9d2fb6", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c", "fn": "func_80181BBC", "addr": 2149063612, "aliases": null, "header": false, "includers": 0, "nhash_before": "217715202856ca5a105bd3c3896400d44a7d0471", "nhash_after": "f8d6d5bb2ea3d5eeec80daa771204389013958d8", "source": ".run/P36/agents/ov_SC02_017__func_80181BBC/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.346, "objects": ["build/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.o"], "before_text": "void func_80181BBC(s32 a0)\n{\n s32 s0;\n s32 v0;\n s32 v1;\n register s32 a0_2 __asm__(\"$4\"); // !FAKE: pin $4 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n\n s0 = a0;\n if (func_8012C438(s0, (s32)D_8018E4F8) == 0) {\n return;\n }\n func_8001D0E8(*(s32 *)(s0 + 0x20), 0x1E0, 0x168);\n v1 = *(s32 *)(s0 + 0x20);\n *(s32 *)(v1 + 0x20) = (s32)D_8018E540;\n v0 = *(s32 *)(s0 + 0x64);\n a0_2 = *(s32 *)(s0 + 0x20);\n v1 = *(u16 *)(v0 + 0x36);\n *(s8 *)(s0 + 0x75) = 4;\n *(u16 *)(s0 + 0xFE) = v1;\n v0 = *(s32 *)(a0_2 + 4);\n v0 |= 0x8000;\n *(s32 *)(a0_2 + 4) = v0;\n func_8001D0E8(*(s32 *)(s0 + 0x20), 0x1E0, 0x168);\n v0 = *(u16 *)(s0 + 0xA);\n v1 = 1;\n *(s16 *)(s0 + 2) = v1;\n v0 += 0x36;\n *(s16 *)(s0 + 0xA) = v0;\n}\n", "after_text": "void func_80181BBC(s32 a0)\n{\n u16 uVar1;\n\n if (func_8012C438(a0, (s32)D_8018E4F8) == 0) {\n return;\n }\n func_8001D0E8(*(s32 *)(a0 + 0x20), 0x1E0, 0x168);\n *(s32 *)(*(s32 *)(a0 + 0x20) + 0x20) = (s32)D_8018E540;\n uVar1 = *(u16 *)(*(s32 *)(a0 + 0x64) + 0x36);\n *(u8 *)(a0 + 0x75) = 4;\n *(u16 *)(a0 + 0xFE) = uVar1;\n *(s32 *)(*(s32 *)(a0 + 0x20) + 4) |= 0x8000;\n func_8001D0E8(*(s32 *)(a0 + 0x20), 0x1E0, 0x168);\n *(u16 *)(a0 + 2) = 1;\n *(u16 *)(a0 + 0xA) += 0x36;\n}\n"} diff --git a/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c b/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c index 643c827390..82fb05208e 100644 --- a/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c +++ b/src/ov_SC02_017/ov_SC02_017_jr_8017DF34.c @@ -5116,32 +5116,20 @@ extern u8 D_8018E4F8[]; void func_80181BBC(s32 a0) { - s32 s0; - s32 v0; - s32 v1; - register s32 a0_2 __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus8) + u16 uVar1; - s0 = a0; - if (func_8012C438(s0, (s32)D_8018E4F8) == 0) { + if (func_8012C438(a0, (s32)D_8018E4F8) == 0) { return; } - func_8001D0E8(*(s32 *)(s0 + 0x20), 0x1E0, 0x168); - v1 = *(s32 *)(s0 + 0x20); - *(s32 *)(v1 + 0x20) = (s32)D_8018E540; - v0 = *(s32 *)(s0 + 0x64); - a0_2 = *(s32 *)(s0 + 0x20); - v1 = *(u16 *)(v0 + 0x36); - *(s8 *)(s0 + 0x75) = 4; - *(u16 *)(s0 + 0xFE) = v1; - v0 = *(s32 *)(a0_2 + 4); - v0 |= 0x8000; - *(s32 *)(a0_2 + 4) = v0; - func_8001D0E8(*(s32 *)(s0 + 0x20), 0x1E0, 0x168); - v0 = *(u16 *)(s0 + 0xA); - v1 = 1; - *(s16 *)(s0 + 2) = v1; - v0 += 0x36; - *(s16 *)(s0 + 0xA) = v0; + func_8001D0E8(*(s32 *)(a0 + 0x20), 0x1E0, 0x168); + *(s32 *)(*(s32 *)(a0 + 0x20) + 0x20) = (s32)D_8018E540; + uVar1 = *(u16 *)(*(s32 *)(a0 + 0x64) + 0x36); + *(u8 *)(a0 + 0x75) = 4; + *(u16 *)(a0 + 0xFE) = uVar1; + *(s32 *)(*(s32 *)(a0 + 0x20) + 4) |= 0x8000; + func_8001D0E8(*(s32 *)(a0 + 0x20), 0x1E0, 0x168); + *(u16 *)(a0 + 2) = 1; + *(u16 *)(a0 + 0xA) += 0x36; }