From f5bdfd8bac9f4d057c9a1f9a6d7741d9cefcf568 Mon Sep 17 00:00:00 2001 From: Drew T <50529377+Druthulu@users.noreply.github.com> Date: Fri, 11 Sep 2026 03:14:10 -0600 Subject: [PATCH] phase-36: S104 e21 (5) + e24 (6) banked; e26/e27 packs --- .run/P36/agents/ORDER.tsv | 10 +- .../agents/main__func_800377D8/body_free.c | 125 ++++++++++++ .../agents/main__func_800377D8/body_tree.c | 128 ++++++++++++ .../agents/main__func_800377D8/history.txt | 14 ++ .../agents/main__func_800377D8/neighbours.txt | 1 + .../agents/main__func_800377D8/related.txt | 171 ++++++++++++++++ .../agents/main__func_800377D8/residual.txt | 69 +++++++ .run/P36/agents/main__func_800377D8/sites.txt | 5 + .run/P36/agents/main__func_800377D8/tu.txt | 2 + .../agents/main__func_800383A4/residual.txt | 1 + .../ov_SC06_010__func_8017E764/body_free.c | 193 ++++++++++++++++++ .../ov_SC06_010__func_8017E764/body_tree.c | 193 ++++++++++++++++++ .../ov_SC06_010__func_8017E764/history.txt | 14 ++ .../ov_SC06_010__func_8017E764/neighbours.txt | 51 +++++ .../ov_SC06_010__func_8017E764/related.txt | 103 ++++++++++ .../ov_SC06_010__func_8017E764/residual.txt | 10 + .../ov_SC06_010__func_8017E764/sites.txt | 2 + .../agents/ov_SC06_010__func_8017E764/tu.txt | 2 + .../ov_SC06_010__func_8017F024/body_free.c | 12 ++ .../ov_SC06_010__func_8017F024/body_tree.c | 12 ++ .../ov_SC06_010__func_8017F024/history.txt | 14 ++ .../ov_SC06_010__func_8017F024/neighbours.txt | 81 ++++++++ .../ov_SC06_010__func_8017F024/related.txt | 131 ++++++++++++ .../ov_SC06_010__func_8017F024/residual.txt | 8 + .../ov_SC06_010__func_8017F024/sites.txt | 2 + .../agents/ov_SC06_010__func_8017F024/tu.txt | 2 + .../ov_SC06_010__func_8017F438/body_free.c | 54 +++++ .../ov_SC06_010__func_8017F438/body_tree.c | 56 +++++ .../ov_SC06_010__func_8017F438/history.txt | 14 ++ .../ov_SC06_010__func_8017F438/neighbours.txt | 81 ++++++++ .../ov_SC06_010__func_8017F438/related.txt | 49 +++++ .../ov_SC06_010__func_8017F438/residual.txt | 23 +++ .../ov_SC06_010__func_8017F438/sites.txt | 4 + .../agents/ov_SC06_010__func_8017F438/tu.txt | 2 + .../ov_SC06_010__func_8017F600/body_free.c | 104 ++++++++++ .../ov_SC06_010__func_8017F600/body_tree.c | 106 ++++++++++ .../ov_SC06_010__func_8017F600/history.txt | 14 ++ .../ov_SC06_010__func_8017F600/neighbours.txt | 81 ++++++++ .../ov_SC06_010__func_8017F600/related.txt | 129 ++++++++++++ .../ov_SC06_010__func_8017F600/residual.txt | 23 +++ .../ov_SC06_010__func_8017F600/sites.txt | 4 + .../agents/ov_SC06_010__func_8017F600/tu.txt | 2 + .run/P36/census/lever_census.json | 80 ++++---- .run/P36/census/lever_census.txt | 26 +-- 44 files changed, 2151 insertions(+), 57 deletions(-) create mode 100644 .run/P36/agents/main__func_800377D8/body_free.c create mode 100644 .run/P36/agents/main__func_800377D8/body_tree.c create mode 100644 .run/P36/agents/main__func_800377D8/history.txt create mode 100644 .run/P36/agents/main__func_800377D8/neighbours.txt create mode 100644 .run/P36/agents/main__func_800377D8/related.txt create mode 100644 .run/P36/agents/main__func_800377D8/residual.txt create mode 100644 .run/P36/agents/main__func_800377D8/sites.txt create mode 100644 .run/P36/agents/main__func_800377D8/tu.txt create mode 100644 .run/P36/agents/main__func_800383A4/residual.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017E764/body_free.c create mode 100644 .run/P36/agents/ov_SC06_010__func_8017E764/body_tree.c create mode 100644 .run/P36/agents/ov_SC06_010__func_8017E764/history.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017E764/neighbours.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017E764/related.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017E764/residual.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017E764/sites.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017E764/tu.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F024/body_free.c create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F024/body_tree.c create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F024/history.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F024/neighbours.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F024/related.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F024/residual.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F024/sites.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F024/tu.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F438/body_free.c create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F438/body_tree.c create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F438/history.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F438/neighbours.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F438/related.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F438/residual.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F438/sites.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F438/tu.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F600/body_free.c create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F600/body_tree.c create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F600/history.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F600/neighbours.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F600/related.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F600/residual.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F600/sites.txt create mode 100644 .run/P36/agents/ov_SC06_010__func_8017F600/tu.txt diff --git a/.run/P36/agents/ORDER.tsv b/.run/P36/agents/ORDER.tsv index cd6b9a2d1..2b61e1d06 100644 --- a/.run/P36/agents/ORDER.tsv +++ b/.run/P36/agents/ORDER.tsv @@ -1,5 +1,7 @@ rank fn alias copies best needed kinds regs tu -132 func_800167F0 main 2 5 3 barrier,pin $0,$3 src/800.c -41 func_80013B64 main 1 6 3 barrier,pin $2 src/800.c -358 func_800279AC main 1 11 2 barrier,launder src/800.c -357 func_800277DC main 1 49 2 pin $8,$9 src/800.c +60 func_8017F024 ov_SC06_010 1 5 2 launder,pin $2 src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c +58 func_8017E764 ov_SC06_010 1 6 2 cast,pin $3 src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c +64 func_8017F438 ov_SC06_010 1 18 4 barrier,pin $2 src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c +65 func_8017F600 ov_SC06_010 1 18 4 barrier,pin $2 src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c +27 func_800377D8 main 1 19 4 barrier,pin $2 src/800_c.c +6 func_800383A4 main 1 None 1 pin $2 src/800_c.c diff --git a/.run/P36/agents/main__func_800377D8/body_free.c b/.run/P36/agents/main__func_800377D8/body_free.c new file mode 100644 index 000000000..b2a8d2dda --- /dev/null +++ b/.run/P36/agents/main__func_800377D8/body_free.c @@ -0,0 +1,125 @@ +void func_800377D8(u8 arg0) { + s32 *pInt; + u8 *pSt; + s32 pos; + s32 idx; + s32 ptr; + s32 nxt; + u16 *pCnt; + s32 cnt; + + if (arg0 != 1) goto err; + if (func_80043994(D_800762A0, 3) == 0) goto err; + pos = CdPosToInt((CdlLOC *)D_800762A0); + pInt = &D_8007623C; + if (pos != *pInt) goto err; + *pInt = pos + 1; + + switch (gD_80076243) { + case 1: + if (func_80043994((void *)gD_80076228, 0x200) == 0) goto err; + if (sD_80076240 == 0 && *(s32 *)gD_80076228 != 0x7671732E) { + D_80076298 = 1; + D_80076250[gD_80076294 * 16] = 2; + goto err; + } + { + s32 rnxt; + s32 rcnt; + pCnt = &hD_80076240; + rnxt = gD_80076228 + 0x800; + rcnt = *pCnt + 1; + *pCnt = rcnt; + gD_80076228 = rnxt; + if ((s16)rcnt != 0xE) { + return; + } + } + if (D_80076248[gD_80076294].unk00 & 0x1000) { + D_80076250[gD_80076294 * 16] = 1; + idx = gD_80076294 + 1; + gD_80076294 = idx; + if (idx < 5 && (&D_80076251)[idx * 16] != 0) { + if (D_80076248[idx].unk00 & 0x2000) { + gD_80076243 = 1; + } else { + gD_80076243 = 2; + } + D_80076298 = 0; + hD_80076240 = 0; + gD_80076228 = D_80076244[gD_80076294].unk00; + gD_80076238 = D_80076244[gD_80076294].unk08; + return; + } + gD_80076243 = 4; + D_8006AEF4 = D_8006AEF4 & 0xFD; + return; + } + gD_80076243 = 2; + *pCnt = 0; + return; + + case 2: + if (func_80043994((void *)gD_80076228, 0x200) == 0) goto err; + gD_80076228 = gD_80076228 + 0x800; + hD_80076240 = hD_80076240 + 1; + if ((s16)hD_80076240 != 7) { + return; + } + gD_80076243 = 3; + hD_80076240 = 0; + if (gD_80076242 != 0) { + if (func_8003C4F0(0) == 0) { + return; + } + gD_80076242 = 0; + } + return; + + case 3: + if (func_80043994((void *)gD_80076228, 0x200) == 0) goto err; + hD_80076240 = hD_80076240 + 1; + if (gD_80076242 != 0) { + if (func_8003C4F0(0) == 0) goto err; + } + if (((s32 (*)(s32))func_8003C498)(gD_80076238) == 0) goto err; + ptr = gD_80076228; + if (sD_80076240 == *(s16 *)(ptr - 4)) { + SpuWrite(ptr, *(s16 *)(ptr - 2)); + gD_80076242 = 1; + D_8006AEF4 = D_8006AEF4 | 1; + D_80076250[gD_80076294 * 16] = 1; + idx = gD_80076294 + 1; + gD_80076294 = idx; + if (idx < 5 && (&D_80076251)[idx * 16] != 0) { + if (D_80076248[idx].unk00 & 0x2000) { + gD_80076243 = 1; + } else { + gD_80076243 = 2; + } + D_80076298 = 0; + hD_80076240 = 0; + gD_80076228 = D_80076244[gD_80076294].unk00; + gD_80076238 = D_80076244[gD_80076294].unk08; + return; + } + gD_80076243 = 4; + D_8006AEF4 = D_8006AEF4 & 0xFD; + return; + } + SpuWrite(ptr, 0x800); + gD_80076242 = 1; + D_8006AEF4 = D_8006AEF4 | 1; + gD_80076238 = gD_80076238 + 0x800; + return; + } + return; + +err: + pSt = &gD_80076243; + if (*pSt == 0) return; + if (*pSt == 4) return; + if (*pSt == 5) return; + *pSt = 5; + D_8006AEF4 = D_8006AEF4 & 0xFD; +} diff --git a/.run/P36/agents/main__func_800377D8/body_tree.c b/.run/P36/agents/main__func_800377D8/body_tree.c new file mode 100644 index 000000000..e7d1abf98 --- /dev/null +++ b/.run/P36/agents/main__func_800377D8/body_tree.c @@ -0,0 +1,128 @@ +void func_800377D8(u8 arg0) { + s32 *pInt; + u8 *pSt; + s32 pos; + s32 idx; + s32 ptr; + s32 nxt; + u16 *pCnt; + s32 cnt; + + if (arg0 != 1) goto err; + if (func_80043994(D_800762A0, 3) == 0) goto err; + pos = CdPosToInt((CdlLOC *)D_800762A0); + pInt = &D_8007623C; + if (pos != *pInt) goto err; + *pInt = pos + 1; + + switch (gD_80076243) { + case 1: + if (func_80043994((void *)gD_80076228, 0x200) == 0) goto err; + if (sD_80076240 == 0 && *(s32 *)gD_80076228 != 0x7671732E) { + D_80076298 = 1; + D_80076250[gD_80076294 * 16] = 2; + goto err; + } + { + register s32 rnxt __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus9) + s32 rcnt; + pCnt = &hD_80076240; + rnxt = gD_80076228 + 0x800; + rcnt = *pCnt + 1; + *pCnt = rcnt; + gD_80076228 = rnxt; + if ((s16)rcnt != 0xE) { + return; + } + } + if (D_80076248[gD_80076294].unk00 & 0x1000) { + D_80076250[gD_80076294 * 16] = 1; + idx = gD_80076294 + 1; + gD_80076294 = idx; + if (idx < 5 && (&D_80076251)[idx * 16] != 0) { + if (D_80076248[idx].unk00 & 0x2000) { + gD_80076243 = 1; + __asm__ __volatile__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) + } else { + gD_80076243 = 2; + } + D_80076298 = 0; + hD_80076240 = 0; + __asm__ __volatile__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) + gD_80076228 = D_80076244[gD_80076294].unk00; + gD_80076238 = D_80076244[gD_80076294].unk08; + return; + } + gD_80076243 = 4; + D_8006AEF4 = D_8006AEF4 & 0xFD; + return; + } + gD_80076243 = 2; + *pCnt = 0; + return; + + case 2: + if (func_80043994((void *)gD_80076228, 0x200) == 0) goto err; + gD_80076228 = gD_80076228 + 0x800; + hD_80076240 = hD_80076240 + 1; + if ((s16)hD_80076240 != 7) { + return; + } + gD_80076243 = 3; + hD_80076240 = 0; + if (gD_80076242 != 0) { + if (func_8003C4F0(0) == 0) { + return; + } + gD_80076242 = 0; + } + return; + + case 3: + if (func_80043994((void *)gD_80076228, 0x200) == 0) goto err; + hD_80076240 = hD_80076240 + 1; + if (gD_80076242 != 0) { + if (func_8003C4F0(0) == 0) goto err; + } + if (((s32 (*)(s32))func_8003C498)(gD_80076238) == 0) goto err; + ptr = gD_80076228; + if (sD_80076240 == *(s16 *)(ptr - 4)) { + SpuWrite(ptr, *(s16 *)(ptr - 2)); + gD_80076242 = 1; + D_8006AEF4 = D_8006AEF4 | 1; + D_80076250[gD_80076294 * 16] = 1; + idx = gD_80076294 + 1; + gD_80076294 = idx; + if (idx < 5 && (&D_80076251)[idx * 16] != 0) { + if (D_80076248[idx].unk00 & 0x2000) { + gD_80076243 = 1; + } else { + gD_80076243 = 2; + } + D_80076298 = 0; + hD_80076240 = 0; + __asm__ __volatile__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus9) + gD_80076228 = D_80076244[gD_80076294].unk00; + gD_80076238 = D_80076244[gD_80076294].unk08; + return; + } + gD_80076243 = 4; + D_8006AEF4 = D_8006AEF4 & 0xFD; + return; + } + SpuWrite(ptr, 0x800); + gD_80076242 = 1; + D_8006AEF4 = D_8006AEF4 | 1; + gD_80076238 = gD_80076238 + 0x800; + return; + } + return; + +err: + pSt = &gD_80076243; + if (*pSt == 0) return; + if (*pSt == 4) return; + if (*pSt == 5) return; + *pSt = 5; + D_8006AEF4 = D_8006AEF4 & 0xFD; +} diff --git a/.run/P36/agents/main__func_800377D8/history.txt b/.run/P36/agents/main__func_800377D8/history.txt new file mode 100644 index 000000000..0b67f6d80 --- /dev/null +++ b/.run/P36/agents/main__func_800377D8/history.txt @@ -0,0 +1,14 @@ +s6: verdict NO-MATCH start 42 best 19 compiles 186 path R7 do-while @2132 +best-scoring single candidates of the last trace (move -> score [residual class]): + R7 do-while @2132 -> 19 [COUNT] (from 42) + R12 width cnt s32->u16 @2111 -> 19 [COUNT] (from 19) + R8 hoist tmp0 @2133 -> 19 [COUNT] (from 19) + R7 block @2205 -> 19 [COUNT] (from 19) + R10 param-copy arg0 @2112 -> 19 [COUNT] (from 19) + R12 width cnt s32->s16 @2111 -> 19 [COUNT] (from 19) + R9 swap-stmts @2151 -> 19 [COUNT] (from 19) + R12 width cnt s32->u8 @2111 -> 19 [COUNT] (from 19) + R18 bystander @2152->2150 -> 19 [COUNT] (from 19) + R12 width nxt s32->u16 @2109 -> 19 [COUNT] (from 19) + R7 block @2150 -> 19 [COUNT] (from 19) + R12 width nxt s32->s16 @2109 -> 19 [COUNT] (from 19) diff --git a/.run/P36/agents/main__func_800377D8/neighbours.txt b/.run/P36/agents/main__func_800377D8/neighbours.txt new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/.run/P36/agents/main__func_800377D8/neighbours.txt @@ -0,0 +1 @@ + diff --git a/.run/P36/agents/main__func_800377D8/related.txt b/.run/P36/agents/main__func_800377D8/related.txt new file mode 100644 index 000000000..e4a0a5c47 --- /dev/null +++ b/.run/P36/agents/main__func_800377D8/related.txt @@ -0,0 +1,171 @@ +=== lever-free bodies in main sharing a callee or global with func_800377D8 (21 found; top 6 by shared symbols) — read them for the SHAPE === +--- func_800373D0 (src/800_c.c:1869) shares 4: D_80076248 D_80076250 D_80076251 D_80076298 --- +void func_800373D0(void) { + StructA4E88 *sp2; + u8 *sp3; + Rsc16 *p; + s32 i; + + sp2 = &D_800A4E88; + sp3 = D_800BA320; + + p = D_80076248; + i = 0; + do { + if ((&D_80076251)[i] != 0) { + if (D_80076250[i] != 0) { + if (p->unk00 & 0x3000) { + sp2->unk00 = p->unk00 & 0xFFF; + sp2->unk06 |= 0x20; + func_8002D7FC((s32) sp3); + if (!(p->unk00 & 0x1000)) { + func_8002FDE8(D_80065438[sp2->unk00].f0, sp3 + 0x7000); + } + } + } + } + p++; + i += 0x10; + } while ((s32) p < (s32) &D_80076298); +} + +--- func_8003750C (src/800_c.c:1928) shares 4: D_8006AEF4 D_80076248 D_80076298 func_8003C4F0 --- +s32 func_8003750C(void) { + s32 i; + s32 val; + s32 k; + s32 h; + + switch (D_8007629C) { + case 0: + if (D_8006AEF4 & 2) { + return 0; + } + D_8006AEF4 |= 2; + D_8007629C = 1; + /* fallthrough */ + case 1: + if (D_8006AEF4 & 1) { + if (func_8003C4F0(0) == 0) { + return 0; + } + } + D_8007629C = D_8007629C + 1; + /* fallthrough */ + case 2: + for (i = 0; i < 5; i++) { + if (D_80076248[i].unk09 == 0) { + continue; + } + val = D_80076248[i].unk00; + k = D_80076248[i].unk0A; + if (val & 0x6000) { + continue; + } + h = D_800A4640[k].unk04; + if (h != 0 && h != D_80064D4A[val].unk00) { + D_800C532A[D_800A4640[k].unk08 * 2] = -1; + D_800A4640[k].unk04 = 0; + D_800A4640[k].unk08 = 0; + } + if (D_800A4640[k].unk10 != 0) { + continue; + } + D_800A4640[k].unk10 = 1; + D_800C5328[D_800A4640[k].unk00 * 2] = -1; + if (D_800A4640[i].unk02 >= 0) { + func_800415A8(D_800A4640[i].unk02); + D_800A4640[i].unk02 = -1; + } + func_80031A98(); + } + D_8007629C = 0; + D_80076298 = 0; + return 1; + default: + return 0; + } +} + +--- func_8002FC64 (src/800_b_2.c:2743) shares 3: D_8006AEF4 func_8003C498 func_8003C4F0 --- +int func_8002FC64(int nbytes, u32 *src) +{ + s32 s2 = nbytes; + u32 *s1 = src; + s32 *s0; + s32 result; + + if (D_8006AEF4 & 1) { + if (func_8003C4F0(0) == 0) { + func_80037D74(); + return 0; + } + } + + s0 = (s32 *)(&D_800A46C8); + result = ((s32 (*)(s32))func_8003C498)(*s0); + + if (result != 0) { + SpuWrite((s32)s1, s2); + *s0 += s2; + D_8006AEF4 |= 1; + return 1; + } + + func_80037D74(); + return 0; +} + +--- func_800304C8 (src/800_b_2.c:3175) shares 2: D_8006AEF4 func_8003C4F0 --- +s32 func_800304C8(void) { + s16 *p; + + if (D_8006AEF4 & 1) { + if (func_8003C4F0(0) != 0) { + D_8006AEF4 &= 0xFE; + } + } else { + p = &D_800A46CC; + (*p)++; + } + return 0; +} + +--- func_8003775C (src/800_c.c:1992) shares 2: D_8006AEF4 func_8003C4F0 --- +int func_8003775C(void) { + u32 t; + + if (D_80076242_.v != 0) { + if (func_8003C4F0(0) == 0) { + return 0; + } + D_80076242_.v = 0; + t = D_8006AEF4; + } else { + t = D_8006AEF4; + } + D_8006AEF4 = t & 0xFC; + func_800373D0(); + return 1; +} + +--- func_80037368 (src/800_c.c:1827) shares 2: D_80076250 D_80076251 --- +void *func_80037368(int *out) { + int count = 0; + u8 *ptr = D_80076220; + int i; + + for (i = 0; i < 0x50; i += 0x10) { + *ptr = 0; + ptr++; + + if ((&D_80076251)[i] != 0) { + D_80076220[count] = D_80076250[i]; + count++; + } + } + + *out = count; + return D_80076220; +} + diff --git a/.run/P36/agents/main__func_800377D8/residual.txt b/.run/P36/agents/main__func_800377D8/residual.txt new file mode 100644 index 000000000..45119e99e --- /dev/null +++ b/.run/P36/agents/main__func_800377D8/residual.txt @@ -0,0 +1,69 @@ +src/800_c.c:func_800377D8: score 42 (COUNT; mine 314 ins, target 316) — not yet + register pairs (mine -> target, count): v0->v1 x5, v1->v0 x2 + replace mine[5:6] target[5:6] + 5 bne s1,v0,29f8 | bne s1,v0,2a00 + replace mine[12:13] target[12:13] + 12 beqz v0,29f8 | beqz v0,2a00 + replace mine[20:21] target[20:21] + 20 bne v0,v1,29f8 | bne v0,v1,2a00 + replace mine[26:27] target[26:27] + 26 beq v1,v0,277c | beq v1,v0,2784 + replace mine[32:33] target[32:33] + 32 j 2a38 | j 2a40 + replace mine[35:36] target[35:36] + 35 beq v1,v0,2810 | beq v1,v0,2818 + replace mine[37:38] target[37:38] + 37 j 2a38 | j 2a40 + replace mine[43:44] target[43:44] + 43 beqz v0,29f8 | beqz v0,2a00 + replace mine[66:67] target[66:67] + 66 j 29f8 | j 2a00 + replace mine[70:78] target[70:78] + 70 lhu v0,0(a0) | lui v0,0x0 + 71 lui v1,0x0 | lw v0,0(v0) + 72 lw v1,0(v1) | lhu v1,0(a0) + 73 addiu v0,v0,1 | addiu v0,v0,2048 + 74 addiu v1,v1,2048 | addiu v1,v1,1 + 75 sh v0,0(a0) | sh v1,0(a0) + 76 sll v0,v0,0x10 | sll v1,v1,0x10 + 77 sra v0,v0,0x10 | sra v1,v1,0x10 + replace mine[79:82] target[79:82] + 79 sw v1,0(at) | sw v0,0(at) + 80 li v1,14 | li v0,14 + 81 bne v0,v1,2a38 | bne v1,v0,2a40 + replace mine[92:93] target[92:93] + 92 beqz v0,276c | beqz v0,2774 + replace mine[105:106] target[105:106] + 105 beqz v0,2750 | beqz v0,2758 + replace mine[111:112] target[111:112] + 111 beqz v0,2750 | beqz v0,2758 + replace mine[118:119] target[118:119] + 118 bnez v0,2930 | beqz v0,2948 + replace mine[120:121] target[120:123] + 120 j 2940 | lui at,0x0 + 121 -- | sb a0,0(at) + 122 -- | j 2950 + replace mine[127:128] target[129:130] + 127 j 2a30 | j 2a38 + replace mine[131:132] target[133:134] + 131 j 2a38 | j 2a40 + replace mine[168:169] target[170:171] + 168 j 2a38 | j 2a40 + replace mine[244:245] target[246:247] + 244 j 2948 | j 2950 + insert mine[248:248] target[250:254] + 248 -- | lui at,0x0 + 249 -- | sb zero,0(at) + 250 -- | lui at,0x0 + 251 -- | sh zero,0(at) + delete mine[258:262] target[264:264] + 258 lui at,0x0 | -- + 259 sb zero,0(at) | -- + 260 lui at,0x0 | -- + 261 sh zero,0(at) | -- + replace mine[266:267] target[268:269] + 266 j 2a38 | j 2a40 + replace mine[273:274] target[275:276] + 273 j 2a30 | j 2a38 + replace mine[290:291] target[292:293] + 290 j 2a38 | j 2a40 diff --git a/.run/P36/agents/main__func_800377D8/sites.txt b/.run/P36/agents/main__func_800377D8/sites.txt new file mode 100644 index 000000000..a89837c87 --- /dev/null +++ b/.run/P36/agents/main__func_800377D8/sites.txt @@ -0,0 +1,5 @@ +NEEDED pin $2 line 2129 +REMOVED pin $3 line 2130 +NEEDED barrier line 2147 +NEEDED barrier line 2153 +NEEDED barrier line 2206 diff --git a/.run/P36/agents/main__func_800377D8/tu.txt b/.run/P36/agents/main__func_800377D8/tu.txt new file mode 100644 index 000000000..57500d8fe --- /dev/null +++ b/.run/P36/agents/main__func_800377D8/tu.txt @@ -0,0 +1,2 @@ +src/800_c.c +func_800377D8 diff --git a/.run/P36/agents/main__func_800383A4/residual.txt b/.run/P36/agents/main__func_800383A4/residual.txt new file mode 100644 index 000000000..657eb07c9 --- /dev/null +++ b/.run/P36/agents/main__func_800383A4/residual.txt @@ -0,0 +1 @@ +UNSTRIPPABLE [('instruction', 2555, 'instruction `sll` has no C spelling in the table')] diff --git a/.run/P36/agents/ov_SC06_010__func_8017E764/body_free.c b/.run/P36/agents/ov_SC06_010__func_8017E764/body_free.c new file mode 100644 index 000000000..8916bc5ac --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017E764/body_free.c @@ -0,0 +1,193 @@ +void func_8017E764(s32 param_1) +{ + s16 pos[4]; + s16 adv[4]; + s16 mv[4]; + s32 src3[4]; + s32 dst2[4]; + s32 mid[4]; + u16 angle; + s32 angle2; + s32 t; + s32 i; + s32 j; + s32 k; + s32 m; + s32 self; + s32 found; + s32 flag; + s32 val; + s32 hundred; + u16 *row; + u16 *np; + s32 *midp; + u8 *ent; + + i = *(s16 *)&D_80126B66; + if ((u32)(i - 0x44E) >= 0x32C5U) { + if (*(s16 *)(param_1 + 0x84) != 0) { + *(s16 *)(param_1 + 0x84) = 0; + func_8002D4C8(4, 0x931); + } + } else { + *(s16 *)(param_1 + 0x84) = 1; + if (i < 0x5CE) { + func_8002D4C8(0x931, (((i - 0x44E) * 0x7F / 0x180) | 0x1000) & 0xFFFF); + } else if (i >= 0x3593) { + func_8002D4C8(0x931, (((i - 0x3592) * 0x7F / 0x180) | 0x1000) & 0xFFFF); + } else { + func_8002D4C8(0x931, 0x107F); + } + } + + if (*(u16 *)(param_1 + 2) == 0) { + hundred = 100; + row = &D_8018A5A2; + for (i = 0x13F; i >= 0; i--) { + *row = hundred; + row += 4; + } + *(s32 *)(param_1 + 0xCC) = func_8012C658(0x238, 0xA, param_1); + *(u16 *)(param_1 + 2) += 1; + *(u16 *)(param_1 + 0xE) += 0x5F0; + } + + ent = D_801202A0; + pos[0] = *(u16 *)(param_1 + 6); + { + u16 *vp; + u16 t; + vp = (u16 *)&D_80126B66; + t = *(volatile u16 *)vp; + pos[1] = *(u16 *)(param_1 + 0xA); + pos[2] = t + 8; + } + i = 0; + np = (u16 *)D_801152A8; + t = (ratan2(*(s16 *)&D_80126B62 - *(s16 *)(param_1 + 0xA), + *(s16 *)&D_80126B5E - *(s16 *)(param_1 + 6)) - 0x400) & 0xFFF; + angle = t; + adv[0] = pos[0] - (func_8004787C(t) >> 3); + adv[1] = pos[1] + (func_80047948(t) >> 3); + adv[2] = pos[2]; + self = *(s32 *)(param_1 + 0xCC); + angle2 = t; + *(u16 *)(self + 0x5C) = 0; + + for (; i < 0x60; ent += 0x10C, i++) { + if (*(u16 *)ent != 0x238) { + continue; + } + flag = *(u16 *)(ent + 0x34); + if (flag != 1) { + continue; + } + if (func_80135888(*(s32 *)(ent + 0x20), *(s32 *)(ent + 0x58), (s32)pos, (s32)adv) == 0) { + continue; + } + found = 0; + *(u16 *)(self + 0x5C) = 0x4C08; + if (*(u8 *)(self + 0x74) != 0) { + *(s32 *)(param_1 + 0xDC) = flag; + if (*(s16 *)(ent + 0x70) == 0) { + mv[0] = D_80126B5E; + mv[1] = D_80126B62; + mv[2] = D_80126B66; + np[0] = -np[0]; + np[1] = -np[1]; + np[2] = -np[2]; + func_8012F568(1, 0x4018, 0, 0x20, (s32)mv, (s32)np); + } + j = *(s16 *)&D_80126B66 - *(s16 *)(param_1 + 0xE) + 0x98; + j = j / 0x130; + val = (&D_8018A5A0)[j * 0x20]; + if (val == flag) { + goto Lup; + } + if (val < 2) { + if (val == 0) { + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle; + } + goto Ldone; + } + if (val == 2) { + goto Ldown; + } + goto Ldone; + Lup: + *(s16 *)(*(s32 *)(self + 0x20) + 0x14) = + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) + 0x10; + found = 1; + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) &= 0xFFF; + goto Ldone; + Ldown: + *(s16 *)(*(s32 *)(self + 0x20) + 0x14) = + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) - 0x10; + found = 1; + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) &= 0xFFF; + } else { + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle; + } + Ldone: + *(s32 *)(self + 4) = *(s32 *)(param_1 + 4) + - func_8004787C(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40; + *(s32 *)(self + 8) = *(s32 *)(param_1 + 8) + + func_80047948(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40; + *(s32 *)(self + 0xC) = D_80126B64; + if (found != 0) { + src3[0] = *(s32 *)&D_80126B5C; + src3[1] = D_80126B60; + src3[2] = *(s32 *)(&D_80126B5C + 8); + midp = mid; + func_8012F0BC((s32 *)(*(s32 *)(self + 0x20) + 0x34), src3, midp); + midp = 0; + func_8012B2CC(self); + func_8012F1A4((s32 *)(*(s32 *)(self + 0x20) + 0x34), mid, dst2); + *(s32 *)&D_80126B5C = dst2[0]; + D_80126B60 = dst2[1]; + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle; + *(s32 *)(self + 4) = *(s32 *)(param_1 + 4) + - func_8004787C(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40; + *(s32 *)(self + 8) = *(s32 *)(param_1 + 8) + + func_80047948(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40; + func_8012B2CC(self); + } + if (*(s32 *)(param_1 + 0xDC) != 0) { + i = *(s16 *)&D_80126B5E - *(s16 *)(param_1 + 6); + j = *(s16 *)&D_80126B62 - *(s16 *)(param_1 + 0xA); + if (i * i + j * j > 0x14D10) { + *(s32 *)&D_80126B5C = *(s32 *)(param_1 + 4) - func_8004787C(angle2) * 0x1240; + D_80126B60 = *(s32 *)(param_1 + 8) + func_80047948(angle2) * 0x1240; + } + } + } + + if (*(u16 *)(self + 0x5C) == 0) { + *(s32 *)(param_1 + 0xDC) = 0; + } + *(u16 *)(param_1 + 0xFC) = (*(u16 *)(param_1 + 0xFC) + 0x10) & 0xFFF; + i = *(s16 *)&D_80126B66 - *(s16 *)(param_1 + 0xE); + j = i / 0x130; + j -= 2; + row = &D_8018A59C + j * 0x20; + for (k = 0; k < 7; k++, j++) { + if ((u32)j < 0x28) { + for (m = 0; m < 8; m++) { + row += 3; + if (*row == 100) { + row -= 3; + ent = (u8 *)func_8012C658(0x238, *row, param_1); + if (ent == 0) { + return; + } + *(s32 *)(ent + 0xCC) = (s32)row; + row += 3; + } + *row = j; + row++; + } + } else { + row += 0x20; + } + } +} diff --git a/.run/P36/agents/ov_SC06_010__func_8017E764/body_tree.c b/.run/P36/agents/ov_SC06_010__func_8017E764/body_tree.c new file mode 100644 index 000000000..bbfac168c --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017E764/body_tree.c @@ -0,0 +1,193 @@ +void func_8017E764(s32 param_1) +{ + s16 pos[4]; + s16 adv[4]; + s16 mv[4]; + s32 src3[4]; + s32 dst2[4]; + s32 mid[4]; + u16 angle; + s32 angle2; + s32 t; + s32 i; + s32 j; + s32 k; + s32 m; + s32 self; + s32 found; + s32 flag; + s32 val; + s32 hundred; + u16 *row; + u16 *np; + s32 *midp; + u8 *ent; + + i = *(s16 *)&D_80126B66; + if ((u32)(i - 0x44E) >= 0x32C5U) { + if (*(s16 *)(param_1 + 0x84) != 0) { + *(s16 *)(param_1 + 0x84) = 0; + func_8002D4C8(4, 0x931); + } + } else { + *(s16 *)(param_1 + 0x84) = 1; + if (i < 0x5CE) { + func_8002D4C8(0x931, (((i - 0x44E) * 0x7F / 0x180) | 0x1000) & 0xFFFF); + } else if (i >= 0x3593) { + func_8002D4C8(0x931, (((i - 0x3592) * 0x7F / 0x180) | 0x1000) & 0xFFFF); + } else { + func_8002D4C8(0x931, 0x107F); + } + } + + if (*(u16 *)(param_1 + 2) == 0) { + hundred = 100; + row = &D_8018A5A2; + for (i = 0x13F; i >= 0; i--) { + *row = hundred; + row += 4; + } + *(s32 *)(param_1 + 0xCC) = func_8012C658(0x238, 0xA, param_1); + *(u16 *)(param_1 + 2) += 1; + *(u16 *)(param_1 + 0xE) += 0x5F0; + } + + ent = D_801202A0; + pos[0] = *(u16 *)(param_1 + 6); + { + register u16 *vp __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus7) + u16 t; + vp = (u16 *)&D_80126B66; + t = *(volatile u16 *)vp; + pos[1] = *(u16 *)(param_1 + 0xA); + pos[2] = t + 8; + } + i = 0; + np = (u16 *)D_801152A8; + t = (ratan2(*(s16 *)&D_80126B62 - *(s16 *)(param_1 + 0xA), + *(s16 *)&D_80126B5E - *(s16 *)(param_1 + 6)) - 0x400) & 0xFFF; + angle = t; + adv[0] = pos[0] - (func_8004787C(t) >> 3); + adv[1] = pos[1] + (func_80047948(t) >> 3); + adv[2] = pos[2]; + self = *(s32 *)(param_1 + 0xCC); + angle2 = t; + *(u16 *)(self + 0x5C) = 0; + + for (; i < 0x60; ent += 0x10C, i++) { + if (*(u16 *)ent != 0x238) { + continue; + } + flag = *(u16 *)(ent + 0x34); + if (flag != 1) { + continue; + } + if (func_80135888(*(s32 *)(ent + 0x20), *(s32 *)(ent + 0x58), (s32)pos, (s32)adv) == 0) { + continue; + } + found = 0; + *(u16 *)(self + 0x5C) = 0x4C08; + if (*(u8 *)(self + 0x74) != 0) { + *(s32 *)(param_1 + 0xDC) = flag; + if (*(s16 *)(ent + 0x70) == 0) { + mv[0] = D_80126B5E; + mv[1] = D_80126B62; + mv[2] = D_80126B66; + np[0] = -np[0]; + np[1] = -np[1]; + np[2] = -np[2]; + func_8012F568(1, 0x4018, 0, 0x20, (s32)mv, (s32)np); + } + j = *(s16 *)&D_80126B66 - *(s16 *)(param_1 + 0xE) + 0x98; + j = j / 0x130; + val = (&D_8018A5A0)[j * 0x20]; + if (val == flag) { + goto Lup; + } + if (val < 2) { + if (val == 0) { + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle; + } + goto Ldone; + } + if (val == 2) { + goto Ldown; + } + goto Ldone; + Lup: + *(s16 *)(*(s32 *)(self + 0x20) + 0x14) = + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) + 0x10; + found = 1; + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) &= 0xFFF; + goto Ldone; + Ldown: + *(s16 *)(*(s32 *)(self + 0x20) + 0x14) = + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) - 0x10; + found = 1; + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) &= 0xFFF; + } else { + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle; + } + Ldone: + *(s32 *)(self + 4) = *(s32 *)(param_1 + 4) + - func_8004787C(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40; + *(s32 *)(self + 8) = *(s32 *)(param_1 + 8) + + func_80047948(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40; + *(s32 *)(self + 0xC) = D_80126B64; + if (found != 0) { + src3[0] = *(s32 *)&D_80126B5C; + src3[1] = D_80126B60; + src3[2] = *(s32 *)(&D_80126B5C + 8); + midp = mid; + func_8012F0BC((s32 *)(*(s32 *)(self + 0x20) + 0x34), src3, midp); + midp = 0; + func_8012B2CC(self); + func_8012F1A4((s32 *)(*(s32 *)(self + 0x20) + 0x34), mid, dst2); + *(s32 *)&D_80126B5C = dst2[0]; + D_80126B60 = dst2[1]; + *(u16 *)(*(s32 *)(self + 0x20) + 0x14) = angle; + *(s32 *)(self + 4) = *(s32 *)(param_1 + 4) + - func_8004787C(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40; + *(s32 *)(self + 8) = *(s32 *)(param_1 + 8) + + func_80047948(*(s16 *)(*(s32 *)(self + 0x20) + 0x14)) * 0x1A40; + func_8012B2CC(self); + } + if (*(s32 *)(param_1 + 0xDC) != 0) { + i = *(s16 *)&D_80126B5E - *(s16 *)(param_1 + 6); + j = *(s16 *)&D_80126B62 - *(s16 *)(param_1 + 0xA); + if (i * i + j * j > 0x14D10) { + *(s32 *)&D_80126B5C = *(s32 *)(param_1 + 4) - func_8004787C(angle2) * 0x1240; + D_80126B60 = *(s32 *)(param_1 + 8) + func_80047948(angle2) * 0x1240; + } + } + } + + if (*(u16 *)(self + 0x5C) == 0) { + *(s32 *)(param_1 + 0xDC) = 0; + } + *(u16 *)(param_1 + 0xFC) = (*(u16 *)(param_1 + 0xFC) + 0x10) & 0xFFF; + i = *(s16 *)&D_80126B66 - *(s16 *)(param_1 + 0xE); + j = i / 0x130; + j -= 2; + row = &D_8018A59C + j * 0x20; + for (k = 0; k < 7; k++, j++) { + if ((u32)j < 0x28) { + for (m = 0; m < 8; m++) { + row += 3; + if (*row == 100) { + row -= 3; + ent = (u8 *)func_8012C658(0x238, *row, param_1); + if (ent == 0) { + return; + } + *(s32 *)(ent + 0xCC) = (s32)row; + row += 3; + } + *row = j; + row++; + } + } else { + row += 0x20; + } + } +} diff --git a/.run/P36/agents/ov_SC06_010__func_8017E764/history.txt b/.run/P36/agents/ov_SC06_010__func_8017E764/history.txt new file mode 100644 index 000000000..c2c39dea5 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017E764/history.txt @@ -0,0 +1,14 @@ +s6: verdict NO-MATCH start 6 best 6 compiles 181 path +best-scoring single candidates of the last trace (move -> score [residual class]): + R12 width hundred s32->u16 @5095 -> 6 [COUNT] (from 6) + R7 block @5114 -> 6 [COUNT] (from 6) + R9 swap-stmts @5119 -> 6 [COUNT] (from 6) + R10 param-copy param_1 @5100 -> 6 [COUNT] (from 6) + R12 width hundred s32->s16 @5095 -> 6 [COUNT] (from 6) + R6 inline vp @5135 -> 6 [COUNT] (from 6) + R7 do-while @5114 -> 6 [COUNT] (from 6) + R7 block @5112 -> 6 [COUNT] (from 6) + R5 swap + @5146 -> 6 [COUNT] (from 6) + R8 base tmp0 @5126 -> 6 [COUNT] (from 6) + R7 do-while @5112 -> 6 [COUNT] (from 6) + R7 block @5110 -> 6 [COUNT] (from 6) diff --git a/.run/P36/agents/ov_SC06_010__func_8017E764/neighbours.txt b/.run/P36/agents/ov_SC06_010__func_8017E764/neighbours.txt new file mode 100644 index 000000000..7c49c9eb1 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017E764/neighbours.txt @@ -0,0 +1,51 @@ +--- every @class/@stuck/@crack note in this translation unit --- +// @class: plumbing +// @stuck: none — MATCH +// @class: regalloc-order — simplified sibling of matched func_8017B614. +// @stuck: none. Block-moves are align-1 struct-assigns (u8[8]) -> emit_block_move +// @class: struct +// @stuck: none — MATCH (74 ins) +// @class: regalloc-order + T1 memcpy-builtin→call re-crack +// @stuck: 0 (iso). Register lever = $16 pin + in-place re-tie on the memcpy-branch src (keeps +// @class: plumbing +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH (63 ins) +// @class: struct +// @stuck: none — MATCH (62 ins) +// @class: struct +// @stuck: none — MATCH (65 ins) +// @class: regalloc-order +// @stuck: pending self-check — register order param=$s2 counter=$s1 ptr=$s0 +// @class: plumbing +// @stuck: none — MATCH (expected); short-typed global increment + signed compare, store-2 on overflow +// @class: plumbing +// @stuck: none — MATCH expected (simple short-increment + guarded call) +// @class: regalloc-order +// @stuck: none — MATCH (branch-polarity invert: fn-ptr non-zero call is the fall-through arm) +// @class: regalloc-order +// @stuck: none — MATCH (83 ins). $s3 is a dual-copy of iVar3 used only in the ==0 tail block; natural C coalesces to one $s0, so pin iVar3=$s0 and iVar3b=$s3 (different hard regs prevent gcc coalescing the copy). Also: outer+inner branch polarity inverted (if!=0 / if!=0 puts both short blocks at the tail as beqz targets); base = (int)D_801B203C + idx*0x40 (materialize form, arg to callees). +// @class: regalloc-order +// @stuck: none — MATCH (223 ins). Giant GTE coord transform. Two levers: (1) vy = {int t=vy-0x10; t+(r&0x1f);} +// @class: schedule +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @class: regalloc-order +// @stuck: none — MATCH (145/145 ins, match_one confirmed) +// @class: regalloc-order +// @stuck: none — MATCH (168 ins). Keys: (1) pin param->$s1 via `register int self __asm__("$17")=param_1` +// @class: schedule +// @stuck: none — MATCH (132 ins, match_one). Levers: (1) block2 statement order — compute sv1.vz (with the *(p+0xe) load) right after the 2nd call so gcc hoists that load into $v1, forcing the sv2.vx=sv1.vx copy through $a3, which globally pushes every `func*param>>12` product from $a3 to $t0; (2) sv2 store order vx-before-vy; (3) SHARED return-0 join via gotos placed BEFORE the copy block (ret0: before docopy:) — this blocks gcc's conditional-jump-over-jump inversion + return-threading, so the copy block falls through to the epilogue with v0=1 preset in the beqz delay slot (drops the extra `li v0,1`). +// @class: plumbing +// @stuck: none — MATCH (126 ins). Keys: (1) cVar1 as `int` (not unsigned char) so the +// @class: schedule +// @stuck: none — MATCH; success-block placed last via `goto big` (bnez forward into epilogue), single cae4 merge kept +// @class: plumbing +// @stuck: none — MATCH (126 ins). Keys: (1) cVar1 as `int` (not unsigned char) so the +// @class: struct +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access. diff --git a/.run/P36/agents/ov_SC06_010__func_8017E764/related.txt b/.run/P36/agents/ov_SC06_010__func_8017E764/related.txt new file mode 100644 index 000000000..c286509de --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017E764/related.txt @@ -0,0 +1,103 @@ +=== lever-free bodies in ov_SC06_010 sharing a callee or global with func_8017E764 (129 found; top 6 by shared symbols) — read them for the SHAPE === +--- func_8012D664 (src/ov_SC06_010/ov_SC06_010_jr_8012ACE0.c:555) shares 4: D_80126B5E D_80126B62 D_80126B66 func_8012F568 --- +int func_8012D664(int arg0, int arg1, int arg2) { + extern int func_8012F568(); + extern int D_80186D2C; + + struct S8012D664_8012D664 s; + int ret; + int t; + + s.a = (*(unsigned short*)&D_80126B5E); + s.b = (*(unsigned short*)&D_80126B62) - 0x40; + s.c = (*(unsigned short*)&D_80126B66); + ret = ((int(*)())func_800132BC)(arg0, &s); + t = arg1 + 0x20; + if (ret < t * t) { + func_8012F568(1, 1, 0, arg2, arg0, &D_80186D2C); + return 1; + } + return 0; +} + +--- func_8012E138 (src/shared/ov/func_8012E138.h:10) shares 4: D_80126B5E D_80126B62 D_80126B66 func_80135888 --- +void func_8012E138(int model) { + struct Cam8012E138 cam; + int bufB[2]; + int bufA[2]; + int m; + short s; + cam.a = D_80126B5E; + cam.b = D_80126B62; + cam.c = D_80126B66; + func_8012F038(*(int *)(model + 0x20) + 0x34, &cam, bufA); + m = *(int *)(model + 0x20); + if (m != 0) { + int mm; + func_80049CAC(m + 0x10, m + 0x34); + mm = *(int *)(model + 0x20); + s = *(u16 *)(model + 6) + *(u16 *)(model + 0x50); + *(u16 *)(mm + 8) = s; + *(int *)(mm + 0x48) = s; + s = *(u16 *)(model + 0xA) + *(u16 *)(model + 0x52); + *(u16 *)(mm + 0xA) = s; + *(int *)(mm + 0x4C) = s; + s = *(u16 *)(model + 0xE) + *(u16 *)(model + 0x54); + *(u16 *)(mm + 0xC) = s; + *(u16 *)(mm + 0x2C) = *(u16 *)(mm + 0x2C) | 1; + *(int *)(mm + 0x50) = s; + } + func_8012F14C(*(int *)(model + 0x20) + 0x34, bufA, bufB); + if (func_80135888(*(int *)(model + 0x20), *(int *)(model + 0x58), bufB, &cam)) { + D_80126B5E = cam.a; + D_80126B62 = cam.b; + D_80126B66 = cam.c; + } +} + +--- func_8012BE54 (src/shared/ov/func_8012BE54.h:7) shares 3: D_80126B5E D_80126B62 D_80126B66 --- +void func_8012BE54(s32 a0) { + u16 sp[3]; + sp[0] = D_80126B5E; + sp[1] = D_80126B62; + sp[2] = D_80126B66; + func_8012BE98(a0, sp); +} + +--- func_80136DFC (src/shared/ov/func_80136DFC.h:9) shares 3: D_80126B5E D_80126B62 D_80126B66 --- +void func_80136DFC(void) { + ((void (*)(s32, s32, s32, s32, s32, s32))func_800153CC)(0xA, (*(s16 *)&D_80126B5E), 0x110, 0x3C, 4, 0); + ((void (*)(s32, s32, s32, s32, s32, s32))func_800153CC)(0xB, (*(s16 *)&D_80126B62), 0x110, 0x44, 4, 0); + ((void (*)(s32, s32, s32, s32, s32, s32))func_800153CC)(0xC, (*(s16 *)&D_80126B66), 0x110, 0x4C, 4, 0); + ((void (*)(s32, s32, s32, s32, s32, s32))func_800153CC)(0xD, *(s16 *)((s32)D_80126B78 + 0x12), 0x110, 0x54, 4, 0); + ((void (*)(s32, s32, s32, s32, s32, s32))func_800153CC)(0xE, D_80126CC4, 0x110, 0x5C, 4, 0); +} + +--- func_8012A048 (src/shared/ov/func_8012A048.h:9) shares 3: D_80126B5E D_80126B62 D_80126B66 --- +void func_8012A048(void *a0, s32 a1, u8 a2) { + *(s32 *)((s32)a0 + 0x0) = a1; + *(u8 *)((s32)a0 + 0x4) = a2; + *(s32 *)((s32)a0 + 0x9C) = 0; + *(s16 *)((s32)a0 + 0xA0) = 0; + *(s16 *)((s32)a0 + 0xA2) = 0; + D_80126940 = D_80126B5E; + D_80126942 = D_80126B62; + D_80126944 = D_80126B66; +} + +--- func_8012DF34 (src/shared/ov/func_8012DF34.h:7) shares 3: D_801152A8 func_8012F568 func_80135888 --- +s32 func_8012DF34(s32 a0, s32 a1, s32 a2) { + s32 s0 = a2; + s32 *p = &D_80126B58; + if (a0 != 0) { + if (*(s16 *)(a0 + 0xAA) != 0) { + return 0; + } + } + if (func_80135888(*(s32 *)((s32)p + 0x20), *(s32 *)((s32)p + 0x38), a1, s0) != 0) { + func_8012F568(1, 1, 0, 0xA, s0, (s32)D_801152A8); + return 1; + } + return 0; +} + diff --git a/.run/P36/agents/ov_SC06_010__func_8017E764/residual.txt b/.run/P36/agents/ov_SC06_010__func_8017E764/residual.txt new file mode 100644 index 000000000..871dc6092 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017E764/residual.txt @@ -0,0 +1,10 @@ +src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:func_8017E764: score 6 (COUNT; mine 438 ins, target 438) — not yet + insert mine[85:85] target[85:86] + 85 -- | move s4,zero + replace mine[86:87] target[87:89] + 86 move s4,zero | lui v1,0x0 + 87 -- | addiu v1,v1,0 + replace mine[88:91] target[90:91] + 88 lui v0,0x0 | lhu v0,0(v1) + 89 addiu v0,v0,0 | -- + 90 lhu v0,0(v0) | -- diff --git a/.run/P36/agents/ov_SC06_010__func_8017E764/sites.txt b/.run/P36/agents/ov_SC06_010__func_8017E764/sites.txt new file mode 100644 index 000000000..4cf6d1507 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017E764/sites.txt @@ -0,0 +1,2 @@ +NEEDED pin $3 line 5306 +NEEDED cast volatile u16 * line 5309 diff --git a/.run/P36/agents/ov_SC06_010__func_8017E764/tu.txt b/.run/P36/agents/ov_SC06_010__func_8017E764/tu.txt new file mode 100644 index 000000000..cbfa4494a --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017E764/tu.txt @@ -0,0 +1,2 @@ +src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c +func_8017E764 diff --git a/.run/P36/agents/ov_SC06_010__func_8017F024/body_free.c b/.run/P36/agents/ov_SC06_010__func_8017F024/body_free.c new file mode 100644 index 000000000..2ecca2758 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F024/body_free.c @@ -0,0 +1,12 @@ +void func_8017F024(s32 a0) { + s32 *p; + s32 self; + + D_8018AFBC[*(u16 *)(a0 + 2)](); + if (*(u16 *)a0 != 0) { + self = a0; + p = *(s32 **)(a0 + 0x20); + p[1] |= 0x80000000; + func_8012B2CC(self); + } +} diff --git a/.run/P36/agents/ov_SC06_010__func_8017F024/body_tree.c b/.run/P36/agents/ov_SC06_010__func_8017F024/body_tree.c new file mode 100644 index 000000000..b42f07f5f --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F024/body_tree.c @@ -0,0 +1,12 @@ +void func_8017F024(s32 a0) { + register s32 *p __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus7) + s32 self; + + D_8018AFBC[*(u16 *)(a0 + 2)](); + if (*(u16 *)a0 != 0) { + __asm__ __volatile__("" : "=r"(self) : "0"(a0)); // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus7) + p = *(s32 **)(a0 + 0x20); + p[1] |= 0x80000000; + func_8012B2CC(self); + } +} diff --git a/.run/P36/agents/ov_SC06_010__func_8017F024/history.txt b/.run/P36/agents/ov_SC06_010__func_8017F024/history.txt new file mode 100644 index 000000000..3d285f9eb --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F024/history.txt @@ -0,0 +1,14 @@ +s6: verdict NO-MATCH start 5 best 5 compiles 121 path +best-scoring single candidates of the last trace (move -> score [residual class]): + R12 width self s32->u16 @5333 -> 5 [COUNT] (from 5) + R6 inline self @5337 -> 5 [COUNT] (from 5) + R8 temp tmp0 @5338 -> 5 [COUNT] (from 5) + R7 block @5339 -> 5 [COUNT] (from 5) + R10 param-alias self->a0 @5337 -> 5 [COUNT] (from 5) + R4 decl-move p 0->1 -> 5 [COUNT] (from 5) + R6 inline p @5338 -> 5 [COUNT] (from 5) + R8 base tmp0 @5338 -> 5 [COUNT] (from 5) + R18 bystander @5337->5340 -> 5 [COUNT] (from 5) + R9 swap-stmts @5337 -> 5 [COUNT] (from 5) + R10 param-copy a0 @5334 -> 5 [COUNT] (from 5) + R12 width self s32->u8 @5333 -> 5 [COUNT] (from 5) diff --git a/.run/P36/agents/ov_SC06_010__func_8017F024/neighbours.txt b/.run/P36/agents/ov_SC06_010__func_8017F024/neighbours.txt new file mode 100644 index 000000000..0eeeb9a43 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F024/neighbours.txt @@ -0,0 +1,81 @@ +--- func_8017F10C (line 5381) --- +/* func_8017F10C -- ov_SC06_010, TU ov_SC06_010_jr_8017A4AC.c (91 ins). + * + * RTP_SND positional-sound sibling of aF8017EF54 / func_80181AD8 in this same + * TU: project the parent entity's world position (a0+0x20 -> +0x48/+0x4C/+0x50) + * with RotTransPers, gate on the screen X/Y window, then play sound id `a1` + * with a pan taken from screen X and a volume that here falls off with DEPTH + * (D_80126B66 - (a0->0xE - 0x680)) rather than with |screen X| as in the twins. + * + * THREE byte-proven levers (each ablated against this .s): + * 1. `d` and the volume are ONE C variable. The distance `d` ($a1 at + * 8017F1E0) and the divided volume ($a1 at 8017F21C) share a register: + * spelling them as two locals (`s32 d` + `s32 av`) gives `d` -> $a0 + * (global_alloc's first free reg) AND reverses the two magic-multiply + * chains, because a separate `av` dies at the end of the block while the + * `bne` keeps the /0x1E chain on the critical path. Reusing `d` extends + * its allocno over the $a0-clobbering tail, which both forces $a1 and + * lifts the /0x900 chain's priority -- 18 mismatched -> MATCH. + * (An `__asm__("" : "=r"(av) : "0"(av))` launder buys the schedule alone, + * but then leaves `d` on $a0: 4 residual. The one-variable form is the + * real shape.) + * 2. §164-75: `D_80126B66 - (field - 0x680)` written inline lets fold + * re-associate the constant onto the LOAD's register (`addiu $v0,$v0,0x680` + * + swapped subu operands). The `t` statement boundary pins it. + * 3. The a1 -> $s2 parameter copy is scheduled LAST in the prologue block + * (8017F15C, after `addu $a0,$s0,$zero`), not into the second lw's load + * delay. A plain `func_8002D4C8(a1 & 0xFFFF, ...)` puts that copy in the + * earliest slot (6 residual, entry window); pinning the carrier to $s2 and + * assigning it right before the first call reproduces the target order. + */ +--- every @class/@stuck/@crack note in this translation unit --- +// @class: plumbing +// @stuck: none — MATCH +// @class: regalloc-order — simplified sibling of matched func_8017B614. +// @stuck: none. Block-moves are align-1 struct-assigns (u8[8]) -> emit_block_move +// @class: struct +// @stuck: none — MATCH (74 ins) +// @class: regalloc-order + T1 memcpy-builtin→call re-crack +// @stuck: 0 (iso). Register lever = $16 pin + in-place re-tie on the memcpy-branch src (keeps +// @class: plumbing +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH (63 ins) +// @class: struct +// @stuck: none — MATCH (62 ins) +// @class: struct +// @stuck: none — MATCH (65 ins) +// @class: regalloc-order +// @stuck: pending self-check — register order param=$s2 counter=$s1 ptr=$s0 +// @class: plumbing +// @stuck: none — MATCH (expected); short-typed global increment + signed compare, store-2 on overflow +// @class: plumbing +// @stuck: none — MATCH expected (simple short-increment + guarded call) +// @class: regalloc-order +// @stuck: none — MATCH (branch-polarity invert: fn-ptr non-zero call is the fall-through arm) +// @class: regalloc-order +// @stuck: none — MATCH (83 ins). $s3 is a dual-copy of iVar3 used only in the ==0 tail block; natural C coalesces to one $s0, so pin iVar3=$s0 and iVar3b=$s3 (different hard regs prevent gcc coalescing the copy). Also: outer+inner branch polarity inverted (if!=0 / if!=0 puts both short blocks at the tail as beqz targets); base = (int)D_801B203C + idx*0x40 (materialize form, arg to callees). +// @class: regalloc-order +// @stuck: none — MATCH (223 ins). Giant GTE coord transform. Two levers: (1) vy = {int t=vy-0x10; t+(r&0x1f);} +// @class: schedule +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @class: regalloc-order +// @stuck: none — MATCH (145/145 ins, match_one confirmed) +// @class: regalloc-order +// @stuck: none — MATCH (168 ins). Keys: (1) pin param->$s1 via `register int self __asm__("$17")=param_1` +// @class: schedule +// @stuck: none — MATCH (132 ins, match_one). Levers: (1) block2 statement order — compute sv1.vz (with the *(p+0xe) load) right after the 2nd call so gcc hoists that load into $v1, forcing the sv2.vx=sv1.vx copy through $a3, which globally pushes every `func*param>>12` product from $a3 to $t0; (2) sv2 store order vx-before-vy; (3) SHARED return-0 join via gotos placed BEFORE the copy block (ret0: before docopy:) — this blocks gcc's conditional-jump-over-jump inversion + return-threading, so the copy block falls through to the epilogue with v0=1 preset in the beqz delay slot (drops the extra `li v0,1`). +// @class: plumbing +// @stuck: none — MATCH (126 ins). Keys: (1) cVar1 as `int` (not unsigned char) so the +// @class: schedule +// @stuck: none — MATCH; success-block placed last via `goto big` (bnez forward into epilogue), single cae4 merge kept +// @class: plumbing +// @stuck: none — MATCH (126 ins). Keys: (1) cVar1 as `int` (not unsigned char) so the +// @class: struct +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access. diff --git a/.run/P36/agents/ov_SC06_010__func_8017F024/related.txt b/.run/P36/agents/ov_SC06_010__func_8017F024/related.txt new file mode 100644 index 000000000..9e87f77bd --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F024/related.txt @@ -0,0 +1,131 @@ +=== lever-free bodies in ov_SC06_010 sharing a callee or global with func_8017F024 (3 found; top 6 by shared symbols) — read them for the SHAPE === +--- func_801788B8 (src/shared/ov/func_801788B8.h:6) shares 1: func_8012B2CC --- +s32 func_801788B8(s32 arg0, s32 arg1) { + s32 iVar1; + u16 buf[4]; + iVar1 = func_8012C658(0x83, (s32)*(s16 *)((u8 *)arg0 + 0x70), 0); + if (iVar1 == 0) { + return 0; + } + *(s32 *)((u8 *)iVar1 + 0x64) = arg0; + buf[0] = *(u16 *)((u8 *)arg0 + 0x6); + buf[1] = *(u16 *)((u8 *)arg0 + 0xA); + buf[2] = *(u16 *)((u8 *)arg0 + 0xE); + if (*(s32 *)((u8 *)arg0 + 0x20) != 0) { + buf[3] = *(u16 *)((u8 *)(*(s32 *)((u8 *)arg0 + 0x20)) + 0x12); + } else { + buf[3] = 0; + } + func_8012E8E0(iVar1, (s32)buf); + func_8012B2CC(iVar1); + *(s32 *)((u8 *)iVar1 + 0xDC) = arg1; + return iVar1; +} + +--- func_80181FC4 (src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:7320) shares 1: func_8012B2CC --- +void func_80181FC4(s32 a0) +{ + + extern s32 D_801A4C64; + SV4 in; + SV4 out; + u16 uStack_c; + + if (*(u16 *)(a0 + 0x34) == 0) { + *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) = + *(u16 *)(*(s32 *)(*(s32 *)(a0 + 0x64) + 0x20) + 0x12); + func_8012B2CC(a0); + func_8012B23C(a0); + func_8012B14C(a0, *(s16 *)(a0 + 0x70) * 12 + (s32)&D_801A4C64); + + in.a = 0; + in.b = 0; + in.c = 0x10; + func_8012F214(a0, (s32)&in, (s32)&out); + *(u16 *)(a0 + 6) = out.a; + *(u16 *)(a0 + 0xa) = out.b; + uStack_c = out.c; + *(s32 *)(a0 + 0x1c) = 0x5a; + *(u16 *)(a0 + 0x34) = 1; + *(u16 *)(a0 + 0xe) = uStack_c; + } + + *(u16 *)(*(s32 *)(a0 + 0x20) + 0x10) += -0x80; + *(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) += 4; + *(u16 *)(*(s32 *)(a0 + 0x20) + 0x14) += *(u16 *)(a0 + 0xfc); + + *(s32 *)(a0 + 0xdc) = *(s32 *)(a0 + 0x14); + if ((((s32 (*)(s32))func_8012CBCC)(a0)) & 0x6000) { + *(s32 *)(a0 + 0x14) = -*(s32 *)(a0 + 0xdc); + if (--*(s16 *)(a0 + 0xac) == 0) { + func_8012C218((void *)a0); + } + } + + { + s32 iVar3 = *(s32 *)(a0 + 0x1c) - 1; + *(s32 *)(a0 + 0x1c) = iVar3; + if (iVar3 == 0) { + func_8012C218((void *)a0); + } + } +} + +--- func_80131B14 (src/ov_SC06_010/ov_SC06_010_jr_8012ACE0.c:1692) shares 1: func_8012B2CC --- +void func_80131B14() { + extern void func_8002A520(void *); + extern void func_8002A790(void *); + extern u8 D_80186EB0; + + u8 *a0v; + u8 *p = a0v; + + + s32 e = *(u8 *)(p + 0x5E); + + if (*(s16 *)(p + 0x60) != 0) { + if (e == 0x1D) { + *(s16 *)(p + 0x82) = 0; + *(s16 *)(p + 0x7C) = *(u16 *)(p + 0x06); + *(s16 *)(p + 0x7E) = *(u16 *)(p + 0x0A); + *(s16 *)(p + 0x80) = *(u16 *)(p + 0x0E); + } + { + s32 dec; + s32 q = *(s32 *)(p + 0x78); + if (q != 0) { + dec = ((s32)*(s16 *)(p + 0x60) * (s32)*(s16 *)(q + 0x30)) >> 12; + if (dec <= 0) dec = 1; + } + *(u16 *)(p + 0x76) = *(u16 *)(p + 0x76) - dec; + } + ((void (*)(void *))func_8016AA50)(p); + if (*(u16 *)(p + 0x82) & 1) { + ((void (*)(void *))func_8016B428)(p); + ((void(*)(void *))func_80019064)(&D_80186EB0); + } + } + + *(u16 *)(p + 0x5C) = *(u16 *)(p + 0x5C) & 0xFFFE; + + if (e != 0x1D) { + if (*(u8 *)(p + 0xC8)) func_8002A520(p); + if (*(u8 *)(p + 0xC9)) func_8002A790(p); + } + + if (*(s16 *)(p + 0x76) <= 0) *(s16 *)(p + 0x5C) = 0; + + { + s32 r = *(s32 *)(p + 0x20); + *(s16 *)(r + 0x12) = (*(u16 *)(p + 0x62) + 0x800) & 0xFFF; + { + s32 r2 = *(s32 *)(p + 0x20); + *(s16 *)(r2 + 0x14) = 0; + *(s16 *)(r2 + 0x10) = 0; + } + } + + ((void (*)(void *))func_8012B2CC)(p); + ((void (*)(void *))func_8012B23C)(p); +} + diff --git a/.run/P36/agents/ov_SC06_010__func_8017F024/residual.txt b/.run/P36/agents/ov_SC06_010__func_8017F024/residual.txt new file mode 100644 index 000000000..7bc780ef9 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F024/residual.txt @@ -0,0 +1,8 @@ +src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:func_8017F024: score 5 (COUNT; mine 30 ins, target 29) — not yet + replace mine[15:17] target[15:17] + 15 beqz v0,4bdc | beqz v0,4bd8 + 16 lui a0,0x8000 | move a0,s0 + replace mine[20:23] target[20:22] + 20 nop | lui a1,0x8000 + 21 or v1,v1,a0 | or v1,v1,a1 + 22 move a0,s0 | -- diff --git a/.run/P36/agents/ov_SC06_010__func_8017F024/sites.txt b/.run/P36/agents/ov_SC06_010__func_8017F024/sites.txt new file mode 100644 index 000000000..de4a6ac24 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F024/sites.txt @@ -0,0 +1,2 @@ +NEEDED pin $2 line 5505 +NEEDED launder line 5510 diff --git a/.run/P36/agents/ov_SC06_010__func_8017F024/tu.txt b/.run/P36/agents/ov_SC06_010__func_8017F024/tu.txt new file mode 100644 index 000000000..b84ffa74c --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F024/tu.txt @@ -0,0 +1,2 @@ +src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c +func_8017F024 diff --git a/.run/P36/agents/ov_SC06_010__func_8017F438/body_free.c b/.run/P36/agents/ov_SC06_010__func_8017F438/body_free.c new file mode 100644 index 000000000..23cd17465 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F438/body_free.c @@ -0,0 +1,54 @@ +void func_8017F438(s32 param_1) { + u8 *s0 = (u8 *)param_1; + s32 pad_[4]; + s32 t1; + s32 t2; + s32 p; + s32 q; + u32 uVar1; + + t1 = *(s16 *)(s0 + 6); + t2 = *(s16 *)(s0 + 0xA); + if (t1 * t1 + (t2 + 0x482) * (t2 + 0x482) > 0x1323F) { + func_8012ADE4(param_1); + *(s32 *)(s0 + 0x14) = 0; + } + + func_8002D4C8(0xB32, 0); + + if (*(u16 *)s0 != 0) { + p = *(s32 *)(s0 + 0xCC); + *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6); + *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA); + *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE); + *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10); + *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFC); + *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14); + q = *(s32 *)(s0 + 0x20); + if (*(s32 *)(q + 4) < 0) { + u32 val; + val = *(u32 *)(p + 4); + uVar1 = val | 0x80000000; + } else { + uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF; + } + *(u32 *)(p + 4) = uVar1; + + p = *(s32 *)(s0 + 0xD0); + *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6); + *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA); + *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE); + *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10); + *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFE); + *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14); + q = *(s32 *)(s0 + 0x20); + if (*(s32 *)(q + 4) < 0) { + u32 val; + val = *(u32 *)(p + 4); + uVar1 = val | 0x80000000; + } else { + uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF; + } + *(u32 *)(p + 4) = uVar1; + } +} diff --git a/.run/P36/agents/ov_SC06_010__func_8017F438/body_tree.c b/.run/P36/agents/ov_SC06_010__func_8017F438/body_tree.c new file mode 100644 index 000000000..bae981ef1 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F438/body_tree.c @@ -0,0 +1,56 @@ +void func_8017F438(s32 param_1) { + u8 *s0 = (u8 *)param_1; + s32 pad_[4]; + s32 t1; + s32 t2; + s32 p; + s32 q; + u32 uVar1; + + t1 = *(s16 *)(s0 + 6); + t2 = *(s16 *)(s0 + 0xA); + if (t1 * t1 + (t2 + 0x482) * (t2 + 0x482) > 0x1323F) { + func_8012ADE4(param_1); + *(s32 *)(s0 + 0x14) = 0; + } + + func_8002D4C8(0xB32, 0); + + if (*(u16 *)s0 != 0) { + p = *(s32 *)(s0 + 0xCC); + *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6); + *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA); + *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE); + *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10); + *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFC); + *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14); + q = *(s32 *)(s0 + 0x20); + if (*(s32 *)(q + 4) < 0) { + register u32 val __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus7) + val = *(u32 *)(p + 4); + uVar1 = val | 0x80000000; + } else { + __asm__ __volatile__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus7) + uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF; + } + *(u32 *)(p + 4) = uVar1; + + p = *(s32 *)(s0 + 0xD0); + *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6); + *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA); + *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE); + *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10); + *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFE); + *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14); + q = *(s32 *)(s0 + 0x20); + if (*(s32 *)(q + 4) < 0) { + register u32 val __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus7) + val = *(u32 *)(p + 4); + uVar1 = val | 0x80000000; + } else { + __asm__ __volatile__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus7) + uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF; + } + *(u32 *)(p + 4) = uVar1; + } +} diff --git a/.run/P36/agents/ov_SC06_010__func_8017F438/history.txt b/.run/P36/agents/ov_SC06_010__func_8017F438/history.txt new file mode 100644 index 000000000..3e41dc5e1 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F438/history.txt @@ -0,0 +1,14 @@ +s6: verdict NO-MATCH start 18 best 18 compiles 190 path +best-scoring single candidates of the last trace (move -> score [residual class]): + R8 temp tmp0 @5565 -> 18 [COUNT] (from 18) + R7 block @5565 -> 18 [COUNT] (from 18) + R10 param-copy param_1 @5527 -> 18 [COUNT] (from 18) + R8 base tmp0 @5565 -> 18 [COUNT] (from 18) + R7 do-while @5565 -> 18 [COUNT] (from 18) + R8 temp tmp0 @5548 -> 18 [COUNT] (from 18) + R7 block @5566 -> 18 [COUNT] (from 18) + R6 inline q @5545 -> 18 [COUNT] (from 18) + R8 base tmp0 @5548 -> 18 [COUNT] (from 18) + R7 do-while @5566 -> 18 [COUNT] (from 18) + R7 block @5548 -> 18 [COUNT] (from 18) + R6 inline q @5562 -> 18 [COUNT] (from 18) diff --git a/.run/P36/agents/ov_SC06_010__func_8017F438/neighbours.txt b/.run/P36/agents/ov_SC06_010__func_8017F438/neighbours.txt new file mode 100644 index 000000000..0eeeb9a43 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F438/neighbours.txt @@ -0,0 +1,81 @@ +--- func_8017F10C (line 5381) --- +/* func_8017F10C -- ov_SC06_010, TU ov_SC06_010_jr_8017A4AC.c (91 ins). + * + * RTP_SND positional-sound sibling of aF8017EF54 / func_80181AD8 in this same + * TU: project the parent entity's world position (a0+0x20 -> +0x48/+0x4C/+0x50) + * with RotTransPers, gate on the screen X/Y window, then play sound id `a1` + * with a pan taken from screen X and a volume that here falls off with DEPTH + * (D_80126B66 - (a0->0xE - 0x680)) rather than with |screen X| as in the twins. + * + * THREE byte-proven levers (each ablated against this .s): + * 1. `d` and the volume are ONE C variable. The distance `d` ($a1 at + * 8017F1E0) and the divided volume ($a1 at 8017F21C) share a register: + * spelling them as two locals (`s32 d` + `s32 av`) gives `d` -> $a0 + * (global_alloc's first free reg) AND reverses the two magic-multiply + * chains, because a separate `av` dies at the end of the block while the + * `bne` keeps the /0x1E chain on the critical path. Reusing `d` extends + * its allocno over the $a0-clobbering tail, which both forces $a1 and + * lifts the /0x900 chain's priority -- 18 mismatched -> MATCH. + * (An `__asm__("" : "=r"(av) : "0"(av))` launder buys the schedule alone, + * but then leaves `d` on $a0: 4 residual. The one-variable form is the + * real shape.) + * 2. §164-75: `D_80126B66 - (field - 0x680)` written inline lets fold + * re-associate the constant onto the LOAD's register (`addiu $v0,$v0,0x680` + * + swapped subu operands). The `t` statement boundary pins it. + * 3. The a1 -> $s2 parameter copy is scheduled LAST in the prologue block + * (8017F15C, after `addu $a0,$s0,$zero`), not into the second lw's load + * delay. A plain `func_8002D4C8(a1 & 0xFFFF, ...)` puts that copy in the + * earliest slot (6 residual, entry window); pinning the carrier to $s2 and + * assigning it right before the first call reproduces the target order. + */ +--- every @class/@stuck/@crack note in this translation unit --- +// @class: plumbing +// @stuck: none — MATCH +// @class: regalloc-order — simplified sibling of matched func_8017B614. +// @stuck: none. Block-moves are align-1 struct-assigns (u8[8]) -> emit_block_move +// @class: struct +// @stuck: none — MATCH (74 ins) +// @class: regalloc-order + T1 memcpy-builtin→call re-crack +// @stuck: 0 (iso). Register lever = $16 pin + in-place re-tie on the memcpy-branch src (keeps +// @class: plumbing +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH (63 ins) +// @class: struct +// @stuck: none — MATCH (62 ins) +// @class: struct +// @stuck: none — MATCH (65 ins) +// @class: regalloc-order +// @stuck: pending self-check — register order param=$s2 counter=$s1 ptr=$s0 +// @class: plumbing +// @stuck: none — MATCH (expected); short-typed global increment + signed compare, store-2 on overflow +// @class: plumbing +// @stuck: none — MATCH expected (simple short-increment + guarded call) +// @class: regalloc-order +// @stuck: none — MATCH (branch-polarity invert: fn-ptr non-zero call is the fall-through arm) +// @class: regalloc-order +// @stuck: none — MATCH (83 ins). $s3 is a dual-copy of iVar3 used only in the ==0 tail block; natural C coalesces to one $s0, so pin iVar3=$s0 and iVar3b=$s3 (different hard regs prevent gcc coalescing the copy). Also: outer+inner branch polarity inverted (if!=0 / if!=0 puts both short blocks at the tail as beqz targets); base = (int)D_801B203C + idx*0x40 (materialize form, arg to callees). +// @class: regalloc-order +// @stuck: none — MATCH (223 ins). Giant GTE coord transform. Two levers: (1) vy = {int t=vy-0x10; t+(r&0x1f);} +// @class: schedule +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @class: regalloc-order +// @stuck: none — MATCH (145/145 ins, match_one confirmed) +// @class: regalloc-order +// @stuck: none — MATCH (168 ins). Keys: (1) pin param->$s1 via `register int self __asm__("$17")=param_1` +// @class: schedule +// @stuck: none — MATCH (132 ins, match_one). Levers: (1) block2 statement order — compute sv1.vz (with the *(p+0xe) load) right after the 2nd call so gcc hoists that load into $v1, forcing the sv2.vx=sv1.vx copy through $a3, which globally pushes every `func*param>>12` product from $a3 to $t0; (2) sv2 store order vx-before-vy; (3) SHARED return-0 join via gotos placed BEFORE the copy block (ret0: before docopy:) — this blocks gcc's conditional-jump-over-jump inversion + return-threading, so the copy block falls through to the epilogue with v0=1 preset in the beqz delay slot (drops the extra `li v0,1`). +// @class: plumbing +// @stuck: none — MATCH (126 ins). Keys: (1) cVar1 as `int` (not unsigned char) so the +// @class: schedule +// @stuck: none — MATCH; success-block placed last via `goto big` (bnez forward into epilogue), single cae4 merge kept +// @class: plumbing +// @stuck: none — MATCH (126 ins). Keys: (1) cVar1 as `int` (not unsigned char) so the +// @class: struct +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access. diff --git a/.run/P36/agents/ov_SC06_010__func_8017F438/related.txt b/.run/P36/agents/ov_SC06_010__func_8017F438/related.txt new file mode 100644 index 000000000..cee81afbe --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F438/related.txt @@ -0,0 +1,49 @@ +=== lever-free bodies in ov_SC06_010 sharing a callee or global with func_8017F438 (32 found; top 6 by shared symbols) — read them for the SHAPE === +--- func_80141C0C (src/ov_SC06_010/ov_SC06_010_jr_80140608.c:1546) shares 1: func_8002D4C8 --- +void func_80141C0C(s32 param_1) +{ + func_8002D4C8(*(u16 *)(&D_80187D44 + (((param_1 << 16) >> 15) + (u32)D_80115110) * 2), 0); +} + +--- func_801821FC (src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:7407) shares 1: func_8002D4C8 --- +void func_801821FC(void *a0) { + func_8002D4C8(0xB32, 0); + ((void (*)(void *))func_80181234)(a0); +} + +--- func_80145BF8 (src/shared/ov/func_80145BF8.h:7) shares 1: func_8002D4C8 --- +void func_80145BF8(void) { + func_8002D4C8(0x21, func_80028FBC() & 0xFFFF); + func_8002D4C8(0x22, func_80029000() & 0xFFFF); + func_8002D4C8(func_80028D9C() == 0 ? 0xC : 0xB, 0); +} + +--- func_801710DC (src/shared/ov/func_801710DC.h:7) shares 1: func_8002D4C8 --- +void func_801710DC(u8 * arg0) +{ + ((M2C_UNK (*)(u16, u16))func_8002D4C8)(D_8011F738, D_8011F73A); + ((M2C_UNK (*)(s32))func_80171928)(arg0); +} + +--- func_80131AC8 (src/shared/ov/func_80131AC8.h:5) shares 1: func_8002D4C8 --- +s32 func_80131AC8(void *a0) { + s32 s0 = func_80131CF4(*(s32 *)((u8 *)a0 + 0xBC)) & 0xFFFF; + if (s0 != 0) { + func_8002D4C8(s0, 0); + return s0; + } + return 0; +} + +--- func_80147364 (src/shared/ov/func_80147364.h:9) shares 1: func_8002D4C8 --- +void aF80147364(u16 param_1, u16 param_2) { + s32 sp10[2]; + s32 *p = &D_80126B58; + if (currentLocationId == 0x308d) { + ((void (*)(void *, void *))func_80015978)(p + 1, sp10); + ((void (*)(void *, s32, s32))aF8012E5CC)(sp10, param_1, param_2); + } else { + func_8002D4C8(param_1, param_2); + } +} + diff --git a/.run/P36/agents/ov_SC06_010__func_8017F438/residual.txt b/.run/P36/agents/ov_SC06_010__func_8017F438/residual.txt new file mode 100644 index 000000000..bc963dcba --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F438/residual.txt @@ -0,0 +1,23 @@ +src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:func_8017F438: score 18 (COUNT; mine 114 ins, target 114) — not yet + replace mine[59:60] target[59:64] + 59 bgez v0,5090 | bgez v0,508c + 60 -- | lui v1,0x8000 + 61 -- | lw v0,4(a0) + 62 -- | j 509c + 63 -- | or v0,v0,v1 + delete mine[61:65] target[65:65] + 61 lw v1,4(a0) | -- + 62 lui v0,0x8000 | -- + 63 j 509c | -- + 64 or v0,v1,v0 | -- + replace mine[99:100] target[99:104] + 99 bgez v0,5130 | bgez v0,512c + 100 -- | lui v1,0x8000 + 101 -- | lw v0,4(a0) + 102 -- | j 513c + 103 -- | or v0,v0,v1 + delete mine[101:105] target[105:105] + 101 lw v1,4(a0) | -- + 102 lui v0,0x8000 | -- + 103 j 513c | -- + 104 or v0,v1,v0 | -- diff --git a/.run/P36/agents/ov_SC06_010__func_8017F438/sites.txt b/.run/P36/agents/ov_SC06_010__func_8017F438/sites.txt new file mode 100644 index 000000000..a03c58a34 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F438/sites.txt @@ -0,0 +1,4 @@ +NEEDED pin $2 line 5720 +NEEDED barrier line 5724 +NEEDED pin $2 line 5738 +NEEDED barrier line 5742 diff --git a/.run/P36/agents/ov_SC06_010__func_8017F438/tu.txt b/.run/P36/agents/ov_SC06_010__func_8017F438/tu.txt new file mode 100644 index 000000000..9116838a5 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F438/tu.txt @@ -0,0 +1,2 @@ +src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c +func_8017F438 diff --git a/.run/P36/agents/ov_SC06_010__func_8017F600/body_free.c b/.run/P36/agents/ov_SC06_010__func_8017F600/body_free.c new file mode 100644 index 000000000..f7243a8e3 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F600/body_free.c @@ -0,0 +1,104 @@ +void func_8017F600(s32 param_1) { + + extern s32 D_801151D4; + + u8 *s0 = (u8 *)param_1; + u16 nv[4]; + s32 pad_[4]; + s32 g; + s32 iv; + s32 idx; + s32 t1; + s32 t2; + s32 p; + s32 q; + u32 uVar1; + + g = D_801151D4; + + if (*(u16 *)s0 == 0) { + return; + } + + t1 = *(s16 *)(s0 + 6); + t2 = *(s16 *)(s0 + 0xA); + if (t1 * t1 + (t2 + 0x482) * (t2 + 0x482) > 0x1323F) { + func_8012ADE4(param_1); + *(s32 *)(s0 + 0x14) = 0; + } + + idx = *(s32 *)(s0 + 0x1C) & 3; + switch (idx) { + case 0: + iv = func_8012C588(0x281, (s32)s0); + if (iv != 0) { + *(s32 *)(iv + 0x1C) = 2; + *(s16 *)(iv + 0x12) = (rand() & 0x1F) - 0x10; + *(s16 *)(iv + 0x16) = -((rand() & 0xF) + 0x10); + *(s16 *)(iv + 0x1A) = (rand() & 0x1F) - 0x10; + } + break; + case 1: + break; + case 2: + case 3: + iv = (s32)func_8012913C(0x23); + if (iv != 0) { + *(s16 *)(iv + 0x6) = *(u16 *)(s0 + 0x6) + (rand() & 0x3F) - 0x20; + *(s16 *)(iv + 0xA) = *(u16 *)(s0 + 0xA) + (rand() & 0x3F) - 0x30; + { + s32 r = rand(); + s32 t = *(u16 *)(s0 + 0xE); + *(s32 *)(iv + 0x18) = 0; + *(s32 *)(iv + 0x14) = 0; + *(s32 *)(iv + 0x10) = 0; + *(s16 *)(iv + 0xE) = t + (r & 0x3F) - 0x20; + } + *(s16 *)(iv + 0x34) = (rand() & 0x17FF) + 0x800; + nv[0] = *(s32 *)(g + 0x5C) - *(u16 *)(iv + 0x6); + nv[1] = *(s32 *)(g + 0x60) - *(u16 *)(iv + 0xA); + nv[2] = *(s32 *)(g + 0x64) - *(u16 *)(iv + 0xE); + VectorNormalSS(nv, nv); + *(s16 *)(iv + 0x6) = *(u16 *)(iv + 0x6) + ((s16)nv[0] >> 6); + *(s16 *)(iv + 0xA) = *(u16 *)(iv + 0xA) + ((s16)nv[1] >> 6); + *(s16 *)(iv + 0xE) = *(u16 *)(iv + 0xE) + ((s16)nv[2] >> 6); + } + break; + } + + if (*(u16 *)s0 != 0) { + p = *(s32 *)(s0 + 0xCC); + *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6); + *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA); + *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE); + *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10); + *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFC); + *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14); + q = *(s32 *)(s0 + 0x20); + if (*(s32 *)(q + 4) < 0) { + u32 val; + val = *(u32 *)(p + 4); + uVar1 = val | 0x80000000; + } else { + uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF; + } + *(u32 *)(p + 4) = uVar1; + + p = *(s32 *)(s0 + 0xD0); + *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6); + *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA); + *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE); + *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10); + *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFE); + *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14); + q = *(s32 *)(s0 + 0x20); + if (*(s32 *)(q + 4) < 0) { + u32 val; + val = *(u32 *)(p + 4); + uVar1 = val | 0x80000000; + } else { + uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF; + } + *(u32 *)(p + 4) = uVar1; + } +} diff --git a/.run/P36/agents/ov_SC06_010__func_8017F600/body_tree.c b/.run/P36/agents/ov_SC06_010__func_8017F600/body_tree.c new file mode 100644 index 000000000..4319cb0ee --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F600/body_tree.c @@ -0,0 +1,106 @@ +void func_8017F600(s32 param_1) { + + extern s32 D_801151D4; + + u8 *s0 = (u8 *)param_1; + u16 nv[4]; + s32 pad_[4]; + s32 g; + s32 iv; + s32 idx; + s32 t1; + s32 t2; + s32 p; + s32 q; + u32 uVar1; + + g = D_801151D4; + + if (*(u16 *)s0 == 0) { + return; + } + + t1 = *(s16 *)(s0 + 6); + t2 = *(s16 *)(s0 + 0xA); + if (t1 * t1 + (t2 + 0x482) * (t2 + 0x482) > 0x1323F) { + func_8012ADE4(param_1); + *(s32 *)(s0 + 0x14) = 0; + } + + idx = *(s32 *)(s0 + 0x1C) & 3; + switch (idx) { + case 0: + iv = func_8012C588(0x281, (s32)s0); + if (iv != 0) { + *(s32 *)(iv + 0x1C) = 2; + *(s16 *)(iv + 0x12) = (rand() & 0x1F) - 0x10; + *(s16 *)(iv + 0x16) = -((rand() & 0xF) + 0x10); + *(s16 *)(iv + 0x1A) = (rand() & 0x1F) - 0x10; + } + break; + case 1: + break; + case 2: + case 3: + iv = (s32)func_8012913C(0x23); + if (iv != 0) { + *(s16 *)(iv + 0x6) = *(u16 *)(s0 + 0x6) + (rand() & 0x3F) - 0x20; + *(s16 *)(iv + 0xA) = *(u16 *)(s0 + 0xA) + (rand() & 0x3F) - 0x30; + { + s32 r = rand(); + s32 t = *(u16 *)(s0 + 0xE); + *(s32 *)(iv + 0x18) = 0; + *(s32 *)(iv + 0x14) = 0; + *(s32 *)(iv + 0x10) = 0; + *(s16 *)(iv + 0xE) = t + (r & 0x3F) - 0x20; + } + *(s16 *)(iv + 0x34) = (rand() & 0x17FF) + 0x800; + nv[0] = *(s32 *)(g + 0x5C) - *(u16 *)(iv + 0x6); + nv[1] = *(s32 *)(g + 0x60) - *(u16 *)(iv + 0xA); + nv[2] = *(s32 *)(g + 0x64) - *(u16 *)(iv + 0xE); + VectorNormalSS(nv, nv); + *(s16 *)(iv + 0x6) = *(u16 *)(iv + 0x6) + ((s16)nv[0] >> 6); + *(s16 *)(iv + 0xA) = *(u16 *)(iv + 0xA) + ((s16)nv[1] >> 6); + *(s16 *)(iv + 0xE) = *(u16 *)(iv + 0xE) + ((s16)nv[2] >> 6); + } + break; + } + + if (*(u16 *)s0 != 0) { + p = *(s32 *)(s0 + 0xCC); + *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6); + *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA); + *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE); + *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10); + *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFC); + *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14); + q = *(s32 *)(s0 + 0x20); + if (*(s32 *)(q + 4) < 0) { + register u32 val __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus7) + val = *(u32 *)(p + 4); + uVar1 = val | 0x80000000; + } else { + __asm__ __volatile__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus7) + uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF; + } + *(u32 *)(p + 4) = uVar1; + + p = *(s32 *)(s0 + 0xD0); + *(u16 *)(p + 0x8) = *(u16 *)(s0 + 0x6); + *(u16 *)(p + 0xA) = *(u16 *)(s0 + 0xA); + *(u16 *)(p + 0xC) = *(u16 *)(s0 + 0xE); + *(u16 *)(p + 0x10) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x10); + *(u16 *)(p + 0x12) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x12) + *(u16 *)(s0 + 0xFE); + *(u16 *)(p + 0x14) = *(u16 *)(*(s32 *)(s0 + 0x20) + 0x14); + q = *(s32 *)(s0 + 0x20); + if (*(s32 *)(q + 4) < 0) { + register u32 val __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus7) + val = *(u32 *)(p + 4); + uVar1 = val | 0x80000000; + } else { + __asm__ __volatile__(""); // !FAKE: barrier — NEEDED DIFFERS (P36 rung B tus7) + uVar1 = *(u32 *)(p + 4) & 0x7FFFFFFF; + } + *(u32 *)(p + 4) = uVar1; + } +} diff --git a/.run/P36/agents/ov_SC06_010__func_8017F600/history.txt b/.run/P36/agents/ov_SC06_010__func_8017F600/history.txt new file mode 100644 index 000000000..d3205abcb --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F600/history.txt @@ -0,0 +1,14 @@ +s6: verdict NO-MATCH start 18 best 18 compiles 191 path +best-scoring single candidates of the last trace (move -> score [residual class]): + R8 temp tmp0 @5681 -> 18 [COUNT] (from 18) + R7 block @5682 -> 18 [COUNT] (from 18) + R10 param-copy param_1 @5600 -> 18 [COUNT] (from 18) + R6 inline q @5661 -> 18 [COUNT] (from 18) + R8 base tmp0 @5681 -> 18 [COUNT] (from 18) + R7 do-while @5682 -> 18 [COUNT] (from 18) + R8 temp tmp0 @5664 -> 18 [COUNT] (from 18) + R7 block @5681 -> 18 [COUNT] (from 18) + R5 swap + @5648 -> 18 [COUNT] (from 18) + R8 base tmp0 @5664 -> 18 [COUNT] (from 18) + R7 do-while @5681 -> 18 [COUNT] (from 18) + R5 swap + @5647 -> 18 [COUNT] (from 18) diff --git a/.run/P36/agents/ov_SC06_010__func_8017F600/neighbours.txt b/.run/P36/agents/ov_SC06_010__func_8017F600/neighbours.txt new file mode 100644 index 000000000..0eeeb9a43 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F600/neighbours.txt @@ -0,0 +1,81 @@ +--- func_8017F10C (line 5381) --- +/* func_8017F10C -- ov_SC06_010, TU ov_SC06_010_jr_8017A4AC.c (91 ins). + * + * RTP_SND positional-sound sibling of aF8017EF54 / func_80181AD8 in this same + * TU: project the parent entity's world position (a0+0x20 -> +0x48/+0x4C/+0x50) + * with RotTransPers, gate on the screen X/Y window, then play sound id `a1` + * with a pan taken from screen X and a volume that here falls off with DEPTH + * (D_80126B66 - (a0->0xE - 0x680)) rather than with |screen X| as in the twins. + * + * THREE byte-proven levers (each ablated against this .s): + * 1. `d` and the volume are ONE C variable. The distance `d` ($a1 at + * 8017F1E0) and the divided volume ($a1 at 8017F21C) share a register: + * spelling them as two locals (`s32 d` + `s32 av`) gives `d` -> $a0 + * (global_alloc's first free reg) AND reverses the two magic-multiply + * chains, because a separate `av` dies at the end of the block while the + * `bne` keeps the /0x1E chain on the critical path. Reusing `d` extends + * its allocno over the $a0-clobbering tail, which both forces $a1 and + * lifts the /0x900 chain's priority -- 18 mismatched -> MATCH. + * (An `__asm__("" : "=r"(av) : "0"(av))` launder buys the schedule alone, + * but then leaves `d` on $a0: 4 residual. The one-variable form is the + * real shape.) + * 2. §164-75: `D_80126B66 - (field - 0x680)` written inline lets fold + * re-associate the constant onto the LOAD's register (`addiu $v0,$v0,0x680` + * + swapped subu operands). The `t` statement boundary pins it. + * 3. The a1 -> $s2 parameter copy is scheduled LAST in the prologue block + * (8017F15C, after `addu $a0,$s0,$zero`), not into the second lw's load + * delay. A plain `func_8002D4C8(a1 & 0xFFFF, ...)` puts that copy in the + * earliest slot (6 residual, entry window); pinning the carrier to $s2 and + * assigning it right before the first call reproduces the target order. + */ +--- every @class/@stuck/@crack note in this translation unit --- +// @class: plumbing +// @stuck: none — MATCH +// @class: regalloc-order — simplified sibling of matched func_8017B614. +// @stuck: none. Block-moves are align-1 struct-assigns (u8[8]) -> emit_block_move +// @class: struct +// @stuck: none — MATCH (74 ins) +// @class: regalloc-order + T1 memcpy-builtin→call re-crack +// @stuck: 0 (iso). Register lever = $16 pin + in-place re-tie on the memcpy-branch src (keeps +// @class: plumbing +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH +// @class: struct +// @stuck: none — MATCH (63 ins) +// @class: struct +// @stuck: none — MATCH (62 ins) +// @class: struct +// @stuck: none — MATCH (65 ins) +// @class: regalloc-order +// @stuck: pending self-check — register order param=$s2 counter=$s1 ptr=$s0 +// @class: plumbing +// @stuck: none — MATCH (expected); short-typed global increment + signed compare, store-2 on overflow +// @class: plumbing +// @stuck: none — MATCH expected (simple short-increment + guarded call) +// @class: regalloc-order +// @stuck: none — MATCH (branch-polarity invert: fn-ptr non-zero call is the fall-through arm) +// @class: regalloc-order +// @stuck: none — MATCH (83 ins). $s3 is a dual-copy of iVar3 used only in the ==0 tail block; natural C coalesces to one $s0, so pin iVar3=$s0 and iVar3b=$s3 (different hard regs prevent gcc coalescing the copy). Also: outer+inner branch polarity inverted (if!=0 / if!=0 puts both short blocks at the tail as beqz targets); base = (int)D_801B203C + idx*0x40 (materialize form, arg to callees). +// @class: regalloc-order +// @stuck: none — MATCH (223 ins). Giant GTE coord transform. Two levers: (1) vy = {int t=vy-0x10; t+(r&0x1f);} +// @class: schedule +// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only +// @class: regalloc-order +// @stuck: none — MATCH (145/145 ins, match_one confirmed) +// @class: regalloc-order +// @stuck: none — MATCH (168 ins). Keys: (1) pin param->$s1 via `register int self __asm__("$17")=param_1` +// @class: schedule +// @stuck: none — MATCH (132 ins, match_one). Levers: (1) block2 statement order — compute sv1.vz (with the *(p+0xe) load) right after the 2nd call so gcc hoists that load into $v1, forcing the sv2.vx=sv1.vx copy through $a3, which globally pushes every `func*param>>12` product from $a3 to $t0; (2) sv2 store order vx-before-vy; (3) SHARED return-0 join via gotos placed BEFORE the copy block (ret0: before docopy:) — this blocks gcc's conditional-jump-over-jump inversion + return-threading, so the copy block falls through to the epilogue with v0=1 preset in the beqz delay slot (drops the extra `li v0,1`). +// @class: plumbing +// @stuck: none — MATCH (126 ins). Keys: (1) cVar1 as `int` (not unsigned char) so the +// @class: schedule +// @stuck: none — MATCH; success-block placed last via `goto big` (bnez forward into epilogue), single cae4 merge kept +// @class: plumbing +// @stuck: none — MATCH (126 ins). Keys: (1) cVar1 as `int` (not unsigned char) so the +// @class: struct +// @stuck: none — MATCH +// @class: schedule +// @stuck: none — MATCH. Two levers: (1) split rand()-result into its own var (shared iVar1 forced an extra move a0,v0); (2) reorder decrement before sp[0] to group the two lhu loads as target's scheduler does; (3) materialize &D_80126B96 via a local u16* to CSE the address (lui+addiu once) instead of %hi/%lo split-per-access. diff --git a/.run/P36/agents/ov_SC06_010__func_8017F600/related.txt b/.run/P36/agents/ov_SC06_010__func_8017F600/related.txt new file mode 100644 index 000000000..f2d800e1e --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F600/related.txt @@ -0,0 +1,129 @@ +=== lever-free bodies in ov_SC06_010 sharing a callee or global with func_8017F600 (37 found; top 6 by shared symbols) — read them for the SHAPE === +--- func_801815B4 (src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:6839) shares 3: D_801151D4 func_8012913C func_8012C588 --- +void func_801815B4(s32 a0) +{ + + extern s32 D_801151D4; + u16 nv[4]; + s32 g; + s32 s0; + s32 idx; + + g = D_801151D4; + + if (*(u16 *)a0 != 0) { + idx = *(s32 *)(a0 + 0x1C) & 3; + switch (idx) { + case 0: + s0 = func_8012C588(0x281, a0); + if (s0 != 0) { + *(s32 *)(s0 + 0x1C) = 2; + *(s16 *)(s0 + 0x12) = (rand() & 0x1F) - 0x10; + *(s16 *)(s0 + 0x16) = -((rand() & 0xF) + 0x10); + *(s16 *)(s0 + 0x1A) = (rand() & 0x1F) - 0x10; + } + break; + case 1: + break; + case 2: + case 3: + s0 = (s32)func_8012913C(0x23); + if (s0 != 0) { + *(s16 *)(s0 + 0x6) = *(u16 *)(a0 + 0x6) + (rand() & 0x3F) - 0x20; + *(s16 *)(s0 + 0xA) = *(u16 *)(a0 + 0xA) + (rand() & 0x3F) - 0x30; + { + s32 r = rand(); + s32 t = *(u16 *)(a0 + 0xE); + *(s32 *)(s0 + 0x18) = 0; + *(s32 *)(s0 + 0x14) = 0; + *(s32 *)(s0 + 0x10) = 0; + *(s16 *)(s0 + 0xE) = t + (r & 0x3F) - 0x20; + } + *(s16 *)(s0 + 0x34) = (rand() & 0x17FF) + 0x800; + nv[0] = *(s32 *)(g + 0x5C) - *(u16 *)(s0 + 0x6); + nv[1] = *(s32 *)(g + 0x60) - *(u16 *)(s0 + 0xA); + nv[2] = *(s32 *)(g + 0x64) - *(u16 *)(s0 + 0xE); + VectorNormalSS(nv, nv); + *(s16 *)(s0 + 0x6) = *(u16 *)(s0 + 0x6) + ((s16)nv[0] >> 6); + *(s16 *)(s0 + 0xA) = *(u16 *)(s0 + 0xA) + ((s16)nv[1] >> 6); + *(s16 *)(s0 + 0xE) = *(u16 *)(s0 + 0xE) + ((s16)nv[2] >> 6); + } + break; + } + ((void (*)(s32))func_80181234)(a0); + } +} + +--- func_8012F968 (src/shared/ov/func_8012F968.h:8) shares 2: D_801151D4 func_8012C588 --- +void func_8012F968(s32 param_1) { + s32 iVar3; + s32 iVar2; + u32 uVar4; + struct { s16 a; s16 b; s16 c; } sp; + iVar3 = D_801151D4; + *(u8 *)(param_1 + 0xc1) = 0x12; + if ((*(u32 *)(param_1 + 0xb4) & 0x10000) != 0) { + sp.a = *(s32 *)(iVar3 + 0x5c); + sp.b = *(s32 *)(iVar3 + 0x60); + sp.c = *(s32 *)(iVar3 + 0x64); + iVar2 = *(s32 *)(param_1 + 0x20); + *(s16 *)(param_1 + 0x5c) = 0; + *(s16 *)(param_1 + 0x54) = 0; + *(s16 *)(param_1 + 0x52) = 0; + *(s16 *)(param_1 + 0x50) = 0; + *(s16 *)(iVar2 + 0x14) = 0; + *(s16 *)(iVar2 + 0x10) = 0; + *(s16 *)(*(s32 *)(param_1 + 0x20) + 0x12) = ((s16 (*)(s32, s32))func_8012B744)(param_1 + 4, (s32)&sp); + *(s32 *)(param_1 + 0x1c) = 0x2d; + if (*(u32 *)(param_1 + 0x58) != 0) { + uVar4 = *(u32 *)(param_1 + 0x58) & 0xfffffff | 0x80000000; + *(s16 *)(param_1 + 0xac) = + (s16)((s32)*(s16 *)(uVar4 + 8) + (s32)*(s16 *)(uVar4 + 10) >> 1); + } else { + *(s16 *)(param_1 + 0xac) = 0; + } + *(s32 *)(param_1 + 0x10) = + ((*(s32 *)(iVar3 + 0x5c) - (s32)*(s16 *)(param_1 + 6)) * 0x10000) / 0x1e; + *(s32 *)(param_1 + 0x14) = + (((*(s32 *)(iVar3 + 0x60) - (s32)*(s16 *)(param_1 + 10)) - + (s32)*(s16 *)(param_1 + 0xac)) * 0x10000) / 0x1e; + *(s32 *)(param_1 + 0x18) = + ((*(s32 *)(iVar3 + 0x64) - (s32)*(s16 *)(param_1 + 0xe)) * 0x10000) / 0x1e; + *(s16 *)(param_1 + 0x98) = 0; + if (func_80131A34(param_1, 0x24) == 0) { + *(u32 *)(param_1 + 0xc4) = *(u32 *)(param_1 + 0xc4) & 0xfffffffb; + if (func_80131A34(param_1, 0x20) != 0) { + *(u32 *)(param_1 + 0xc4) = *(u32 *)(param_1 + 0xc4) | 4; + } else { + *(s16 *)(param_1 + 0x98) = 0; + } + } + ((void (*)(s32, s32))func_8012C588)(0x289, param_1); + } + func_80131CA8(param_1, 0x35); +} + +--- func_80143970 (src/shared/ov/func_80143970.h:4) shares 1: func_8012C588 --- +s32 func_80143970(s32 a0) { + return func_8012C588(0x1B, a0); +} + +--- func_8012A464 (src/shared/ov/func_8012A464.h:5) shares 1: D_801151D4 --- +void func_8012A464(void) +{ + D_80114F24 = *(Vec8 *)(*(s32 *)&D_801151D4 + 0x3C); +} + +--- func_801829FC (src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:7776) shares 1: func_8012C588 --- +s32 func_801829FC(s32 a0, s32 a1) { + D_801B2B08 = a1; + return func_8012C588(0x85, a0); +} + +--- func_8012A4BC (src/shared/ov/func_8012A4BC.h:7) shares 1: D_801151D4 --- +void func_8012A4BC(void) { + D_80126DB8 = *(struct BigCopy *)D_801151D4; + *(struct BigCopy *)D_801151D4 = D_80114EE8; + D_80127504 = 0x30; +} + diff --git a/.run/P36/agents/ov_SC06_010__func_8017F600/residual.txt b/.run/P36/agents/ov_SC06_010__func_8017F600/residual.txt new file mode 100644 index 000000000..d24551478 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F600/residual.txt @@ -0,0 +1,23 @@ +src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c:func_8017F600: score 18 (COUNT; mine 222 ins, target 222) — not yet + replace mine[165:166] target[165:170] + 165 bgez v0,5400 | bgez v0,53fc + 166 -- | lui v1,0x8000 + 167 -- | lw v0,4(a0) + 168 -- | j 540c + 169 -- | or v0,v0,v1 + delete mine[167:171] target[171:171] + 167 lw v1,4(a0) | -- + 168 lui v0,0x8000 | -- + 169 j 540c | -- + 170 or v0,v1,v0 | -- + replace mine[205:206] target[205:210] + 205 bgez v0,54a0 | bgez v0,549c + 206 -- | lui v1,0x8000 + 207 -- | lw v0,4(a0) + 208 -- | j 54ac + 209 -- | or v0,v0,v1 + delete mine[207:211] target[211:211] + 207 lw v1,4(a0) | -- + 208 lui v0,0x8000 | -- + 209 j 54ac | -- + 210 or v0,v1,v0 | -- diff --git a/.run/P36/agents/ov_SC06_010__func_8017F600/sites.txt b/.run/P36/agents/ov_SC06_010__func_8017F600/sites.txt new file mode 100644 index 000000000..bd03466ed --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F600/sites.txt @@ -0,0 +1,4 @@ +NEEDED pin $2 line 5836 +NEEDED barrier line 5840 +NEEDED pin $2 line 5854 +NEEDED barrier line 5858 diff --git a/.run/P36/agents/ov_SC06_010__func_8017F600/tu.txt b/.run/P36/agents/ov_SC06_010__func_8017F600/tu.txt new file mode 100644 index 000000000..d051813a8 --- /dev/null +++ b/.run/P36/agents/ov_SC06_010__func_8017F600/tu.txt @@ -0,0 +1,2 @@ +src/ov_SC06_010/ov_SC06_010_jr_8017A4AC.c +func_8017F600 diff --git a/.run/P36/census/lever_census.json b/.run/P36/census/lever_census.json index 70987019a..f5685251b 100644 --- a/.run/P36/census/lever_census.json +++ b/.run/P36/census/lever_census.json @@ -53,7 +53,7 @@ }, "kinds": { "asm-body/direct": 13, - "barrier/direct": 313, + "barrier/direct": 309, "barrier/via-macro": 2, "gte-lever/direct": 357, "gte-lever/via-macro": 94, @@ -70,8 +70,9 @@ }, "binaries": 218, "cfake_markers": { - "count": 44, + "count": 43, "sample": [ + "src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c:9325", "src/800.c:12640", "src/md_SC07_003/md_SC07_003.c:3577", "src/md_SC07_004/md_SC07_004.c:280", @@ -93,7 +94,6 @@ "src/ov_SC03_124/ov_SC03_124_jr_8017AE2C.c:6576", "src/ov_SC03_124/ov_SC03_124_jr_80188544.c:4422", "src/ov_SC04_002/ov_SC04_002_jr_8017BEBC.c:10069", - "src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c:9323", "src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c:6630", "src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:7484", "src/ov_SC04_011/ov_SC04_011_jr_8017D494.c:10288", @@ -104,38 +104,38 @@ "src/ov_SC05_018/ov_SC05_018_jr_8017D604.c:4942", "src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c:8489", "src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c:8816", - "src/ov_SC06_016/ov_SC06_016_jr_801816DC.c:3082", "src/ov_SC06_018/ov_SC06_018_jr_80187AEC.c:3125", "src/ov_SC06_018/ov_SC06_018_jr_80187AEC.c:5384", "src/ov_SC06_020/ov_SC06_020_jr_80180B04.c:3714", "src/ov_SC06_022/ov_SC06_022_jr_80184A28.c:3757", "src/ov_SC06_024/ov_SC06_024_jr_80186F00.c:3771", "src/ov_SC06_024/ov_SC06_024_jr_80186F00.c:5414", - "src/ov_SC06_029/ov_SC06_029_jr_8017C954.c:6666" + "src/ov_SC06_029/ov_SC06_029_jr_8017C954.c:6666", + "src/ov_SC06_032/ov_SC06_032_jr_80182890.c:2961" ] }, "classes": { "A": { - "bodies": 1450, - "distinct_bodies": 614, + "bodies": 1445, + "distinct_bodies": 609, "file_scope": 0, - "in_bodies": 2334, + "in_bodies": 2329, "kinds": { - "pin": 2334 + "pin": 2329 }, - "marked": 2334, - "sites": 2334, + "marked": 2329, + "sites": 2329, "tus": 1082, "unmarked": 0 }, "B": { - "bodies": 4691, - "distinct_bodies": 751, + "bodies": 4687, + "distinct_bodies": 747, "file_scope": 13, - "in_bodies": 11320, + "in_bodies": 11316, "kinds": { "asm-body": 13, - "barrier": 315, + "barrier": 311, "gte": 6346, "gte-lever": 451, "gte-unsigned": 270, @@ -144,8 +144,8 @@ "launder": 687, "verbatim-body": 2682 }, - "marked": 2520, - "sites": 11333, + "marked": 2516, + "sites": 11329, "tus": 1428, "unmarked": 8813 }, @@ -251,9 +251,9 @@ "coverage": { "asm": { "comment_dead": 6782, - "live": 15309, + "live": 15300, "macro_block": 194, - "raw": 22285 + "raw": 22276 }, "attribute": { "comment_dead": 0, @@ -269,9 +269,9 @@ }, "register": { "comment_dead": 8573, - "live": 2384, + "live": 2379, "macro_block": 18, - "raw": 10975 + "raw": 10970 }, "volatile": { "comment_dead": 2605, @@ -281,7 +281,7 @@ } }, "coverage_ok": true, - "elapsed_s": 26.9, + "elapsed_s": 24.3, "generated": "2026-09-11", "gte_levers": { "direct": 357, @@ -292,15 +292,15 @@ "via_macro": 94, "what": "GTE ops whose clobbers exceed the canonical macro's (a scheduling steer): class-B levers INSIDE the headline number since T5 (2026-09-09), marked, 0 at the close" }, - "head": "51fe62d2c", + "head": "cc27144fa", "headers": 3181, "levers_AB": { - "asm": 2035, - "bodies": 2136, - "distinct_bodies": 823, - "marked": 4369, - "pins": 2334, - "sites": 4369, + "asm": 2031, + "bodies": 2127, + "distinct_bodies": 814, + "marked": 4360, + "pins": 2329, + "sites": 4360, "unmarked": 0, "what": "register pins + asm statements excluding GTE ops: the classes the phase drives to 0" }, @@ -436,14 +436,14 @@ "bare_name": 15, "init": 213, "registers": { - "$0": 64, + "$0": 63, "$10": 10, "$11": 5, "$12": 9, "$13": 6, "$14": 5, "$15": 1, - "$16": 94, + "$16": 91, "$17": 37, "$18": 31, "$19": 19, @@ -454,7 +454,7 @@ "$23": 6, "$25": 1, "$29": 13, - "$3": 182, + "$3": 181, "$4": 504, "$5": 380, "$6": 62, @@ -467,29 +467,29 @@ "v0": 2, "v1": 3 }, - "sites": 2334, + "sites": 2329, "sp": 13, "spelling": { - "__asm__": 2305, + "__asm__": 2300, "asm": 29 }, "volatile_qualified": 0, - "zero": 64 + "zero": 63 }, - "src_stamp": "d7b4868d162e9ee5", + "src_stamp": "b100d05dc3ffdab7", "tus": 4121, "unclassified": 0, "union_AD": { - "bodies": 5895, + "bodies": 5886, "by_kind": { - "main": 147, + "main": 142, "md": 117, - "ov": 5460, + "ov": 5456, "resident": 10, "shared": 161 }, "copies_in_multi": 4863, - "distinct_bodies": 1149, + "distinct_bodies": 1140, "multi_copy_classes": 117 }, "verbatim_excluded": { diff --git a/.run/P36/census/lever_census.txt b/.run/P36/census/lever_census.txt index 9243e5e06..2c16805ab 100644 --- a/.run/P36/census/lever_census.txt +++ b/.run/P36/census/lever_census.txt @@ -1,32 +1,32 @@ lever_census: 218 binaries · 4,121 TUs + 3,181 headers · coverage OK · unclassified 0 · verbatim excluded 13 fn / 14 sites (manifest 13) - coverage asm raw 22285 = live 15309 + macro-block 194 + comment/dead 6782 - coverage register raw 10975 = live 2384 + macro-block 18 + comment/dead 8573 + coverage asm raw 22276 = live 15300 + macro-block 194 + comment/dead 6782 + coverage register raw 10970 = live 2379 + macro-block 18 + comment/dead 8573 coverage volatile raw 4372 = live 1685 + macro-block 82 + comment/dead 2605 coverage builtin raw 599 = live 445 + macro-block 0 + comment/dead 154 coverage attribute raw 76 = live 76 + macro-block 0 + comment/dead 0 class sites in-bodies file-scope bodies distinct TUs marked unmarked kinds - A pins 2334 2334 0 1450 614 1082 2334 0 {'pin': 2334} - B asm 11333 11320 13 4691 751 1428 2520 8813 {'gte': 6346, 'gte-lever': 451, 'barrier': 315, 'gte-unsigned': 270, 'launder': 687, 'instruction': 229, 'asm-body': 13, 'keepalive': 340, 'verbatim-body': 2682} - C volatile 1589 1437 152 495 94 609 14 1575 {'decl-body': 58, 'decl-file': 152, 'cast': 1377, 'param': 2} + A pins 2329 2329 0 1445 609 1082 2329 0 {'pin': 2329} + B asm 11329 11316 13 4687 747 1428 2516 8813 {'barrier': 311, 'instruction': 229, 'launder': 687, 'keepalive': 340, 'gte': 6346, 'gte-lever': 451, 'gte-unsigned': 270, 'asm-body': 13, 'verbatim-body': 2682} + C volatile 1589 1437 152 495 94 609 14 1575 {'cast': 1377, 'decl-body': 58, 'decl-file': 152, 'param': 2} D register 50 50 0 47 47 6 0 50 {'register': 50} E asm-label 7788 1364 6424 1096 157 2090 0 7788 {'asm-label': 7788} F builtin 445 445 0 428 27 302 0 445 {'builtin': 445} G attribute 76 1 75 1 1 40 0 76 {'attribute': 76} - UNION A–D: 5,895 bodies · 1,149 distinct (addresses normalized) · 117 multi-copy classes holding 4,863 bodies · by kind {'main': 147, 'ov': 5460, 'shared': 161, 'md': 117, 'resident': 10} - THE PHASE'S NUMBER (pins + asm statements, GTE excluded): 4,369 sites in 2,136 bodies (823 distinct) · marked !FAKE 4,369 · UNMARKED 0 + UNION A–D: 5,886 bodies · 1,140 distinct (addresses normalized) · 117 multi-copy classes holding 4,863 bodies · by kind {'ov': 5456, 'main': 142, 'shared': 161, 'md': 117, 'resident': 10} + THE PHASE'S NUMBER (pins + asm statements, GTE excluded): 4,360 sites in 2,127 bodies (814 distinct) · marked !FAKE 4,360 · UNMARKED 0 orphan !FAKE markers (no pin/asm site on the line nor below): 0 - marked ordinary-C fakes kept by Drew's S104 ruling (a) (`do { } while (0)`, dead initialisers; NOT levers): 44 + marked ordinary-C fakes kept by Drew's S104 ruling (a) (`do { } while (0)`, dead initialisers; NOT levers): 43 GTE levers (clobbers beyond the canonical macro's): 451 sites (94 via a variant macro, 357 direct) · marked 451 · UNMARKED 0 · unsigned GTE statements 270 per-TU asm macro definitions outside the GTE header: 314 {'gte': 150, 'launder': 154, 'instruction': 9, 'barrier': 1} (GTE variants 64) - pins: 2,334 · $0 64 · $sp 13 · with initializer 213 · volatile-qualified 0 · bare-name 15 · spellings {'__asm__': 2305, 'asm': 29} + pins: 2,329 · $0 63 · $sp 13 · with initializer 213 · volatile-qualified 0 · bare-name 15 · spellings {'__asm__': 2300, 'asm': 29} whole-body asm routines in C shells, manifest PERMANENT (hand asm, NOT levers): 22 routines · 2,682 sites (2,660 private copies + 22 shared headers); asm-bodies NOT permanent (levers): 13 site(s) ['func_8001E378:DECOMPILE-NOW', 'func_80020F34:DECOMPILE-NOW', 'func_800249F0:DECOMPILE-NOW', 'func_80025CBC:DECOMPILE-NOW', 'func_80026514:UNCERTAIN', 'func_800268D0:UNCERTAIN', 'func_80027058:DECOMPILE-NOW', 'func_80027200:DECOMPILE-NOW', 'func_800CBA44:DECOMPILE-NOW', 'func_8017D810:DECOMPILE-NOW', 'func_8017E26C:UNCERTAIN', 'func_80184440:DECOMPILE-NOW', 'func_801A3BCC:DECOMPILE-NOW'] - asm kinds: {'asm-body/direct': 13, 'barrier/direct': 313, 'barrier/via-macro': 2, 'gte/direct': 198, 'gte/via-macro': 6148, 'gte-lever/direct': 357, 'gte-lever/via-macro': 94, 'gte-unsigned/direct': 270, 'instruction/direct': 207, 'instruction/via-macro': 22, 'keepalive/direct': 340, 'launder/direct': 645, 'launder/via-macro': 42, 'verbatim-body/direct': 2682} - instruction mnemonics: {'la': 139, 'addu': 23, 'addiu': 22, 'RTP_SND': 22, '.section': 7, 'lui': 4, 'lh': 3, 'and': 2, 'mult': 1, 'mfhi': 1, 'sll': 1, 'li': 1, 'lw': 1, 'nop': 1, 'srl': 1} - gte mnemonics: {'gte_ldv0': 758, 'gte_stlvnl': 593, 'gte_stsxy': 448, 'gte_rtps': 439, 'gte_stflg': 415, 'gte_rtpt': 352, 'gte_SetRotMatrix': 252, 'gte_stsxy3': 236, 'gte_SetTransMatrix': 231, 'gte_rtv0tr': 228, 'gte_ldv3c': 184, 'gte_ldv3': 177, 'gte_stsv': 161, 'lwc2': 158, 'gte_stsz4': 149, 'gte_stsz3': 147, 'gte_stszotz': 134, 'gte_dpcl': 134, 'gte_stclmv': 111, 'gte_stsxy3_f3': 111, 'gte_nclip': 108, 'gte_stopz': 108, 'gte_stsxy3c': 108, 'gte_stsxy3_ft3': 79, 'gte_rtir': 78, 'gte_ldclmv': 75, 'gte_avsz4': 56, 'gte_stotz': 52, 'gte_ldrgb': 30, 'gte_nccs': 25} + asm kinds: {'asm-body/direct': 13, 'barrier/direct': 309, 'barrier/via-macro': 2, 'gte/direct': 198, 'gte/via-macro': 6148, 'gte-lever/direct': 357, 'gte-lever/via-macro': 94, 'gte-unsigned/direct': 270, 'instruction/direct': 207, 'instruction/via-macro': 22, 'keepalive/direct': 340, 'launder/direct': 645, 'launder/via-macro': 42, 'verbatim-body/direct': 2682} + instruction mnemonics: {'la': 139, 'addu': 23, 'addiu': 22, 'RTP_SND': 22, '.section': 7, 'lui': 4, 'lh': 3, 'and': 2, 'sll': 1, 'mult': 1, 'mfhi': 1, 'li': 1, 'lw': 1, 'nop': 1, 'srl': 1} + gte mnemonics: {'gte_ldv0': 758, 'gte_stlvnl': 593, 'gte_stsxy': 448, 'gte_rtps': 439, 'gte_stflg': 415, 'gte_rtpt': 352, 'gte_SetRotMatrix': 252, 'gte_stsxy3': 236, 'gte_SetTransMatrix': 231, 'gte_rtv0tr': 228, 'gte_ldv3c': 184, 'gte_ldv3': 177, 'gte_stsv': 161, 'lwc2': 158, 'gte_stsz4': 149, 'gte_stsz3': 147, 'gte_stszotz': 134, 'gte_dpcl': 134, 'gte_stsxy3_f3': 111, 'gte_stclmv': 111, 'gte_nclip': 108, 'gte_stopz': 108, 'gte_stsxy3c': 108, 'gte_stsxy3_ft3': 79, 'gte_rtir': 78, 'gte_ldclmv': 75, 'gte_avsz4': 56, 'gte_stotz': 52, 'gte_ldrgb': 30, 'gte_nccs': 25} asm-bearing macro definitions: 314 (20 names, 3 with >1 text) kinds {'gte': 150, 'launder': 154, 'instruction': 9, 'barrier': 1} controls (R39): src/800.c func_800226C0 pins got 14 expected 45 N-A src/shared/ov/func_80178004.h pins got 8 expected 26 N-A ov_SC03_006 func_80184034 bare-name pins got 0 expected 3 N-A engine_prelude.h asm sites (a macro definition only) got 0 expected 0 OK - elapsed 26.9 s + elapsed 24.3 s