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https://github.com/Druthulu/BFM-decomp
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feat(phase-32): T4c hand pass — main:func_80039308 (518 ins) BANKED byte-identical with ZERO pins: the phantom frame slot is a combine ghost (a self-update chain on the s0[1] load), the hoisted volume base is three inline (b2 * 0x100) temps merged by loop.c's combine_movables with a u16 vol accumulator so cse leaves the arms on the hoisted register, and the else head reuses the note-on arm's s17/s18 (S85) — main has NO INCLUDE_ASM stubs left
- gate_main .run/P32/t4e/slate_39308.json --apply: "slate 1 -> 1 compatible … BANKED 1 main functions -- 143dbb89f34491258bbc27810d0a12ec8b43a8dd BYTE-IDENTICAL" (clean main rebuild) - draft .run/P32/t4e/bank/func_80039308.c = b56 (no register pins, no fences, no asm bodies); the 56-variant route is in .run/P32/t4e/NOTES.md - the S84 PLATEAU's two causes were both compiler mechanisms missing from the censuses: combine.c:2306 (i2dest_in_i2src skips the ref decrement → reload1.c:658 slot) and loop.c:695-700 (a named variable set after a jump is never a movable; cse.c make_regs_eqv folds the arms onto the later-mentioned copy target unless the copy is a subreg move) - fleet: INCLUDE_ASM stubs 2 -> 0; every game-code function of every binary is C
This commit is contained in:
Drew T
+319
-1
@@ -3428,7 +3428,325 @@ void func_800391D4(s32 arg0, s16 arg1, s16 arg2) {
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void func_80039300(void) {
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}
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INCLUDE_ASM("asm/nonmatchings/800_c", func_80039308);
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/* func_80039308 (main, src/800_c.c, 518 ins) -- BANKED byte-identical, P32 T4c hand pass (S85, 2026-09-06),
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* ZERO register pins, zero fences, zero asm bodies. Sequencer note-on / voice allocation: walks the track's
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* 16 voice records (D_800C6DD0, 0x60 each), allocates or steals a voice for note b2 at velocity b3, computes
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* pan/volume/pitch through D_8006AF08 / D_8006ACD8 / D_8006AB30 / D_8006ABD8, and updates the D_800A2B98 /
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* D_800C7D20 / D_800C7D2C / D_800A2BA0 voice masks; the else arm releases the voices playing note b2.
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*
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* The three mechanisms that closed the S84 PLATEAU (cookbook §501-Q, §501-R, accelerators (15)-(16)):
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* 1. THE PHANTOM 8-BYTE FRAME SLOT ([arg1 @0][8 no-traffic bytes @8][cnt @0x10]) is a combine GHOST: the chain
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* `gx = s0[1]; gx -= 0x100; v = b3 * (u8)gx;` compiles to the same `lbu` as `s0[1]`, but combine deletes the
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* self-update with `i2dest_in_i2src` (combine.c:2306 skips the reference decrement), the load then merges into
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* the (u8) use, and the pseudo `gx` keeps stale refs with no insns -- reload's initial alter_reg loop mints an
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* 8-byte slot for it in regno order, between arg1's spill and cnt's eviction slot. Reproducers: .run/P32/t4e/ghost/.
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* 2. THE HOISTED VOLUME BASE `sll $s2,$s5,8` sits between two hoisted constants ([li 2][sll][li 1]) and is read
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* three times ($s2 in the copy and both pan arms): loop.c's combine_movables merges the three inline
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* `(b2 * 0x100)` temps into ONE hoisted movable (savings 3), which needs (a) a compiler TEMP, not a named
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* variable (a user variable set after the inner loop's jumps is never a movable: loop.c:695-700), and (b) cse1
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* NOT folding the arms onto `vol`: with `u16 vol`, the copy `vol = b2 * 0x100` is a subreg move, so `vol` never
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* joins the shift's quantity (cse.c make_regs_eqv prefers the later-mentioned register) and the arms keep the
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* temp. The copy-first form is what puts `vol` in $a1 (born while pan is live in $a0) and in the first
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* branch's delay slot; every copy-last / named-vbase / pinned form was measured (b13-b51, NOTES.md).
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* 3. THE ELSE HEAD ($t1/$t0): the release loop's pointer and compare temp are the note-on arm's `s17`/`s18`
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* variables reused (the target's rows 410/411 and 440/441 share the registers); a fresh `tb`/`k2` pair lands in
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* $t0/$s2 instead.
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* Kept from the S83/S84 drafts: `s16 b4` + `n = b4` (the widening copy), the pan sum split, `bb` as the first pan
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* load, the offset local `v` computed before t9, the cross-arm k2 reading of the +6 store ... see the S83 notes in
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* git history (this header replaces them).
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*/
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typedef struct { u32 w; } VMask;
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extern u8 *D_800762B0;
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extern u8 D_800762B3[];
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extern u8 D_800762B4[];
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extern s32 D_80073140[][1]; /* [][1] spelling: load-bearing for func_800391D4 (S79 lever; §500-I) */
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extern u16 D_8006AB30[];
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extern u16 D_8006ABD8[];
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extern u16 D_8006ACD8[];
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extern s16 D_8006AF08[];
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extern s32 D_800A2B98;
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extern s32 D_800A2BA0;
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extern u8 D_800A4F19;
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extern u8 D_800C6DD0[];
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extern u8 D_800C6DD4[];
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extern u8 D_800C6DDD[];
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extern s32 D_800C7D20;
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extern s32 D_800C7D2C;
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void func_80039308(u8 **arg0, s16 arg1) {
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u8 *src;
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u8 *s0;
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u8 *t9;
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u8 *a3;
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u8 *t1;
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u8 *a1p;
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u8 *a0p;
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u8 *p;
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u8 *q;
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u8 *r;
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u8 *tb;
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s32 b2;
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s32 b3;
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s16 b4;
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s32 bb;
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u8 t3;
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u8 t5;
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s16 t7;
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s16 cc;
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s32 i;
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s32 cnt;
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s32 a2;
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s32 t0;
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s32 v1;
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s32 res;
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s32 idx1;
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u8 *cb;
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s32 *mm;
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s32 *mp;
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s32 mv2;
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s32 two;
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s32 tmp;
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s32 pan;
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s32 pan1;
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s32 x;
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s32 s17;
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s32 s18;
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s32 v;
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s32 u26;
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s32 n;
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s32 off;
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u32 t2;
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u16 vol;
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u32 vv;
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u32 prod;
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s32 k2;
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u8 *tbl;
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s32 tmp2;
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s32 coff;
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s32 xoff;
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s32 mv;
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s32 j;
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s32 ax;
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s32 ax2;
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u8 *pb;
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s32 c7;
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u32 gx;
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src = *arg0;
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*arg0 = src + 1;
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b2 = src[0];
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*arg0 = src + 2;
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b3 = src[1];
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if (b3 != 0) {
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if ((((u8 *)arg0 + arg1)[0x1BA] & 1) == 0) {
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s0 = (u8 *)arg0 + (arg1 * 26 + 26);
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i = 0;
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b4 = *s0;
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n = b4;
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v = n * 0x10;
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t9 = *(u8 **)((u8 *)arg0 + 0x1E0) + n * 0x200;
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cnt = *(*(u8 **)((u8 *)arg0 + 0x1DC) + v);
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if (cnt != 0) {
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u26 = b2;
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do {
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if (u26 >= t9[6] && u26 <= t9[7]) {
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t2 = 0x100;
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t3 = 0;
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t5 = 0;
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t7 = -1;
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t0 = 0;
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a3 = D_800C6DDD;
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a2 = 1;
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t1 = D_800762B0;
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do {
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if (a3[0x4E] != 0) {
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bb = a3[0];
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if ((u8)bb < (t2 & 0xFF)) {
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t3 = a2;
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t2 = bb & 0xFF;
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} else if ((u8)bb == (t2 & 0xFF)) {
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if (D_800762B3[a2] == 0 && *t1 == 2) {
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t3 = a2;
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}
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}
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} else {
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t5 = 1;
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t7 = t0;
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break;
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}
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a2++;
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t1++;
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t0++;
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a3 += 0x60;
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} while (t0 < 0x10);
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if (t5 == 0) {
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if (*t9 >= t2) {
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t7 = t3 - 1;
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} else {
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a1p = D_800762B0;
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a0p = D_800762B4;
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v1 = 0;
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while (v1 < 0x10) {
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if (*a1p == 2 && *a0p == 0) {
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res = v1;
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goto found;
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}
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v1++;
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a1p++;
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a0p++;
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}
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res = -1;
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found:
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t7 = res;
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}
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}
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if (t7 >= 0) {
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p = &D_800C6DD0[t7 * 0x60];
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q = p + 0x10;
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p[0xD] = *t9;
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if (p[0x5C] != 0 && *(s16 *)(p + 8) == b4 && p[0xC] == i &&
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*(s16 *)(*(u32 *)(p + 0x50) + 0x1EC) == *(s16 *)((u8 *)arg0 + 0x1EC)) {
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*(s32 *)(p + 0x14) = 0x13;
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} else {
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tmp = *(s16 *)(t9 + 0x16) - 1;
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tbl = *(u8 **)((u8 *)arg0 + 0x1DC) + (tmp >> 1) * 0x10;
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if (tmp & 1) {
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x = *(s16 *)(tbl + 0xE) << 3;
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} else {
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x = *(s16 *)(tbl + 0xC) << 3;
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}
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*(s32 *)(q + 0x1C) = x;
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*(u16 *)(q + 0x3A) = *(u16 *)(t9 + 0x10);
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*(u16 *)(q + 0x3C) = *(u16 *)(t9 + 0x12);
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*(s32 *)(q + 4) = 0x6009F;
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}
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gx = s0[1];
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gx -= 0x100;
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v = b3 * (u8)gx;
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v >>= 7;
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v = v * t9[2];
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v >>= 7;
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v = D_8006ACD8[v];
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v = v * *(s16 *)((u8 *)arg0 + 0x1F2);
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v >>= 7;
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if (D_800A4F19 != 0) {
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bb = s0[4];
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pan1 = bb + t9[3]; pan1 -= 0x40;
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cc = pan1;
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if (pan1 < 0) {
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cc = 0;
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} else if (pan1 >= 0x80) {
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cc = 0x7F;
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}
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if (cc > 0) {
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s17 = v * D_8006AF08[0x80 - cc] * 4 >> 16;
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} else {
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s17 = (s16)v;
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}
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s18 = v * D_8006AF08[cc] * 4 >> 16;
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} else {
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s17 = s18 = v * 0x2D41 >> 14;
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}
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*(s16 *)(q + 8) = (u32)((s16)s17 * *(s16 *)((u8 *)arg0 + 0x10)) >> 14;
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*(s16 *)(q + 0xA) = (u32)((s16)s18 * *(s16 *)((u8 *)arg0 + 0x10)) >> 14;
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pan = *(s16 *)(s0 + 2);
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vol = b2 * 0x100;
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if (pan >= 0x41) {
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vol = (b2 * 0x100) + (u32)((pan - 0x40) * t9[0xD] * 4);
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} else if (pan < 0x40) {
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vol = (b2 * 0x100) - (u32)((0x40 - pan) * t9[0xC] * 4);
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}
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tmp2 = t9[4] * 0x100 - t9[5];
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*(s32 *)(p + 0x54) = tmp2;
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tmp2 -= 0x3C00;
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vol -= (u32)tmp2;
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p[0x58] = t9[0xC];
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p[0x59] = t9[0xD];
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vv = (u16)vol;
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if (vv >= 0x5301) {
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*(s16 *)(q + 0x14) = 0x3FFF;
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} else {
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prod = D_8006AB30[vv >> 8];
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prod *= D_8006ABD8[(vv & 0xFE) / 2];
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*(s16 *)(q + 0x14) = prod >> 15;
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}
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p[0x5D] = 1;
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D_800A2B98 &= ~((VMask *)q)->w;
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D_800C7D20 |= ((VMask *)q)->w;
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D_800762B4[t7] = 1;
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if (t9[1] & 4) {
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D_800A2BA0 &= ~((VMask *)q)->w;
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D_800C7D2C |= ((VMask *)q)->w;
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} else {
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D_800C7D2C &= ~((VMask *)q)->w;
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D_800A2BA0 |= ((VMask *)q)->w;
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}
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idx1 = t7;
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r = &D_800C6DD0[idx1 * 0x60];
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p = r;
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if (r[0x5A] != 0) {
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coff = *(s16 *)&r[6] * 26;
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*(u8 *)(*(u32 *)&r[0x50] + coff + idx1 + 0x23) = 0;
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r[0x5A] = 0;
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}
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r = 0;
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*(s0 + idx1 + 9) = 1;
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*(s16 *)(p + 4) = b2;
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*(s16 *)(p + 8) = b4;
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p[0xC] = i;
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p[0x5C] = 1;
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*(s16 *)(p + 0) = s17;
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*(s16 *)(p + 2) = s18;
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*(s16 *)(p + 6) = arg1;
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*(u32 *)(p + 0x50) = (u32)arg0;
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p[0x5B] = 1;
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if (*((u8 *)arg0 + 0x1F4) != 0) {
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p[0x5A] = 2;
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} else {
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p[0x5A] = 1;
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}
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}
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}
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i++;
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t9 += 0x20;
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} while (i < cnt);
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}
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}
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} else {
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j = 0;
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s17 = (s32)((u8 *)arg0 + arg1 * 26);
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s18 = b2;
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off = 0;
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do {
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if (((u8 *)s17 + j)[0x23] != 0 && *(s16 *)&D_800C6DD4[off] == s18) {
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idx1 = (s16)j;
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xoff = idx1 * 0x60;
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cb = D_800C6DD0;
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r = cb + xoff;
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if (r[0x5A] != 0) {
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coff = *(s16 *)&r[6] * 26;
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*(u8 *)(*(u32 *)&r[0x50] + coff + idx1 + 0x23) = 0;
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r[0x5A] = 0;
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}
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mm = (s32 *)D_80073140;
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D_800C7D20 &= ~mm[j];
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D_800A2B98 |= mm[j];
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pb = D_800762B0 + j;
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two = 2;
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*pb = two;
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D_800762B4[j] = 0;
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}
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cb = 0;
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mm = 0;
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two = 0;
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j++;
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off += 0x60;
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} while (j < 0x10);
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}
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}
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extern s32 D_80073140[][1]; /* [][1] spelling: load-bearing for func_800391D4 (S79 lever; §500-I) */
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extern u8 *D_800762B0;
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