268 a register __asm__ pin on a call-clobbered register is honored EXACTLY when the
pinned range crosses no call — turning 257-2's 'pins are silently ignored' into a
rule with a precondition, and explaining both faces: a pin that does nothing
(range crosses a jal, gcc silently falls back) and a pin that fixes a REGALLOC
residual in a function that has calls (range sits between them). Three A/B'd cards.
269 ten addenda, plus the 266 solo-lever sweep table.
THE HEADLINE IS THE INERT-RIDER RATE. 19 strip-tests across 13 banked bodies: 6 of 19
credited levers are byte-inert (32%), against 4 of 8 last batch. One in three 'this is
what made it match' claims credits something that changes nothing — and one whole
proposed section dissolved under its own strip test. 67 of 82 candidates (81.7%) were
already covered, matching the previous batch's re-derivation rate.
265 the verbatim-asm bank lane — two in-tree precedents, the MASPSX decimal-immediate
rule, and a REVIEW-ADDED accounting caveat: an __asm__ body is not an INCLUDE_ASM
stub, so corpus.stubs() counts it as MATCHED. Bytes proven, function not
decompiled. Fine for hand-written asm; for an -O0 C function the right answer is
the -O0 object, and this lane is a temporary hold at best.
266 the inert-rider law — a lever is only citable when its solo removal breaks the
match. Measured 4 of 8 credited levers on this batch were byte-inert: a $2 pin
silently dropped, a volatile the scheduler already ordered, a named zero, and a
statement split. The banked artifact CONTAINS the rider precisely because it is
inert, which reads as proof. R40 applied to the flywheel itself.
267 eleven addenda to existing sections, six with fresh match_one A/Bs.
The batch's real headline: 145 of 165 candidates were ALREADY COVERED, and 8 claims
were refuted (4 by live A/B) — the harvest is mostly re-derivation, and an unchecked
wrong law is worse than no law.
Drew T