mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-09-28 06:49:47 -04:00
Drew T
5f38df2368
One clean whole-EXE rebuild verified the batch (gate_main), and main re-checked BYTE-IDENTICAL against config/check.us.sha before anything was credited. DsReadyCallback SetIR123 func_8001D074 func_80028E00 func_800538BC func_8005FBA8
124 lines
3.0 KiB
C
124 lines
3.0 KiB
C
#include "common.h"
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INCLUDE_ASM("asm/nonmatchings/gsgap5", SetVertex0);
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INCLUDE_ASM("asm/nonmatchings/gsgap5", SetVertex1);
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INCLUDE_ASM("asm/nonmatchings/gsgap5", SetVertex2);
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void SetVertexTri(long *r0, long *r1, long *r2)
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{
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__asm__ volatile(
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"lwc2 $0, 0( %0 );"
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"lwc2 $1, 4( %0 );"
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"lwc2 $2, 0( %1 );"
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"lwc2 $3, 4( %1 );"
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"lwc2 $4, 0( %2 );"
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"lwc2 $5, 4( %2 )"
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:
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: "r"(r0), "r"(r1), "r"(r2));
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}
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void SetRGBfifo(void* r0, void* r1, void* r2)
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{
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__asm__ __volatile__ (
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"lwc2 $20, 0( %0 );"
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"lwc2 $21, 0( %1 );"
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"lwc2 $22, 0( %2 )"
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:
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: "r"( r0 ), "r"( r1 ), "r"( r2 )
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: "memory" );
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}
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void SetIR123(long r0, long r1, long r2)
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{
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__asm__ __volatile__(
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"mtc2 %0, $9\n"
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"mtc2 %1, $10\n"
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"mtc2 %2, $11"
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:
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: "r"(r0), "r"(r1), "r"(r2));
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}
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INCLUDE_ASM("asm/nonmatchings/gsgap5", SetIR0);
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/* SetSZfifo3 (0x80053A4C) -- handwritten GTE fifo-load wrapper (splat marks it
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* "Handwritten function"): three mtc2 stores of the incoming $a0-$a2 words into
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* cop2 data registers SZ1/SZ2/SZ3 ($17/$18/$19), then the frameless leaf return.
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* gcc-2.7.2 -O2 cannot emit bare cop2 register writes from C, so the body is
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* transcribed verbatim as a file-scope asm block (cookbook §265 lane 1,
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* func_800D0440 form @ src/md_MAIN_003/md_MAIN_003.c:329): the block carries the
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* .globl/.ent directives and the explicit jr $ra + nop tail -- no C codegen and
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* no declaration surface at all. No relocations, no symbol references.
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*/
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__asm__(".text\n.align 2\n.globl SetSZfifo3\n.ent\tSetSZfifo3\n"
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"SetSZfifo3:\n"
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".set\tnoreorder\n"
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"mtc2 $4, $17\n"
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"mtc2 $5, $18\n"
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"mtc2 $6, $19\n"
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"jr $ra\n"
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"nop\n"
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".set\treorder\n"
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".end\tSetSZfifo3\n");
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/* probe: naive spelling -- no volatile, no .set noreorder */
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void SetSZfifo4()
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{
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__asm__(
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"mtc2 $4, $16\n"
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"mtc2 $5, $17\n"
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"mtc2 $6, $18\n"
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"mtc2 $7, $19\n");
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}
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void SetSXSYfifo(long r0, long r1, long r2)
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{
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__asm__ __volatile__(
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"mtc2 %0, $12\n"
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"mtc2 %1, $13\n"
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"mtc2 %2, $14"
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:
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: "r"(r0), "r"(r1), "r"(r2));
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}
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void SetRii()
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{
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__asm__ __volatile__(
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".set\tnoreorder\n"
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"ctc2 $4, $0\n"
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"ctc2 $5, $2\n"
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"ctc2 $6, $4\n"
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".set\treorder\n");
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}
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void SetMAC123(long r0, long r1, long r2)
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{
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__asm__ __volatile__(
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"mtc2 %0, $25\n"
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"mtc2 %1, $26\n"
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"mtc2 %2, $27"
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:
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: "r"(r0), "r"(r1), "r"(r2));
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}
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INCLUDE_ASM("asm/nonmatchings/gsgap5", SetData32);
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INCLUDE_ASM("asm/nonmatchings/gsgap5", SetDQA);
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INCLUDE_ASM("asm/nonmatchings/gsgap5", SetDQB);
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void func_80053AD8()
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{
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__asm__ __volatile__(
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".set\tnoreorder\n"
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"sll $4, $4, 4\n"
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"sll $5, $5, 4\n"
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"sll $6, $6, 4\n"
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"ctc2 $4, $21\n"
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"ctc2 $5, $22\n"
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"ctc2 $6, $23\n"
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".set\treorder\n"
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);
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}
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