mirror of
https://github.com/Druthulu/BFM-decomp
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Drew T
72e6a096ca
CAUGHT BY VERIFYING THE CHECKPOINT INSTEAD OF ASSERTING IT. `.run/wave22/` was covered by the blanket `/.run/*` ignore, so the 13 UNBANKED drafts — 6 NEAR with precise residual diagnoses and 7 that reached match_one MATCH but did not bank whole-binary — existed only on disk. My own checkpoint's "START HERE" list names them as next-session fuel, and they cost ~2.59M subagent tokens to produce. One `git clean -fdx` would have destroyed them: exactly the exposure the .run/giants Fable5 cracks had before Phase 27 curated them (R20). Now allowlisted: .run/wave22/*.c + .run/wave22_targets.json (the per-target canonical callee/data declarations resolved from the real TU scope — the §17a-1 lever the wave was built on). Also commits docs/family-hseq.md, regenerated by this session's family_hseq runs.
86 lines
3.7 KiB
C
86 lines
3.7 KiB
C
/* func_80140D68 — SPRT (0x14) primitive builder + PsyQ addPrim() into OT_800D29F8[2].
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*
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* @class: schedule
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* @status: NEAR 9/65 — 65/65 instructions, every instruction byte-correct, ONE positional drift.
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* @stuck: the 0xFFFFFF mask register ($t1) builds ATOMICALLY here (lui idx2 / ori idx3); the target
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* SPLITS the pair (lui idx2 ... ori idx13, between `sra $a2,$a2,14` and `addiu $a3,$a3,-0xD`).
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* Everything from idx15 on is byte-identical; idx3..13 is a pure shift-by-one caused solely by
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* that one `ori`. gcc-2.7.2 splits the large constant BEFORE sched2 (verified with
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* -fno-schedule-insns2: cc1 emits `li $9,0x00ff0000` + `ori $9,$9,0xffff` as two insns), so the
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* position is decided by the pre-sched2 RTL LUID of the `ori`, which is NOT reachable from the
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* source in this shape. Explored and byte-measured (~200 compiles):
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* - 126 header-statement orderings (q/dx/x/y/w/h permutations) -> all 9, ori pinned at idx3
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* - PTag bitfield layouts (u32:24+u32:8 / u32:24+u8 / u32:24) -> all 9
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* - plain-local and `register __asm__("$9")` mask + redundant `& mlo`, swept over 12 source
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* positions -> 9 or 12, never 13
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* - `volatile short` decl instead of a cast at use -> 40+
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* The ONE family that moves the `ori` is: pointer-cast header (no Sprt struct) + a SHARED
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* `u32 *ot` local + LITERAL masks — there the constant sinks in RTL to just after the volatile
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* lhu and schedules at idx14 (one slot late). Best of that family is kept at
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* .run/wave22/_a80140D68/x_pin2.c (closeness 12: idx13/14 ori<->addiu swap + a clean $v0/$v1
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* swap in the second addPrim half, because a single shared `ot` pseudo cannot take two registers
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* while splitting it into two pseudos moves the `ori` back to idx23). Permuter-shaped.
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*
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* Signature (read off the asm): a0 = SPRT out, a1 = s16 *src, a2 = s16 idx (in-callee
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* sll16/sra14 => K&R narrow param, cookbook §99), a3 = s32 dx, 0x10($sp) = s16 ofs (K&R narrow;
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* ANSI `s16 ofs` yields `lh`+`sll 1` = 2 ins instead of the target's lw+sll16+sra15).
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*
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* Draft-local shims: these two typedefs already exist VERBATIM in src/shared/engine_types.h
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* (Hw4 @833, Env_800D29F8). The guard makes the draft self-contained for match_one (which only
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* prepends common.h) while collapsing to nothing once banked into a TU that includes the header. */
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#ifndef BFM_ENGINE_TYPES_H
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typedef struct { s16 x; s16 y; } Hw4;
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typedef struct {
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u32 *ot; /* 0x00 */
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u32 pad[4]; /* 0x04..0x13 */
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} Env_800D29F8; /* 0x14 stride */
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#endif
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extern Hw4 D_8011516A[];
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extern short D_800B9A02;
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extern Env_800D29F8 D_800AE7BC[];
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#define OT8_80140D68 (*(u32 *)(D_800AE7BC[*(volatile u16 *)&D_800B9A02].ot + 2))
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u32 *func_80140D68(out, src, idx, dx, ofs)
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u32 *out;
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s16 *src;
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s16 idx;
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s32 dx;
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s16 ofs;
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{
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typedef struct {
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u32 tag; /* 0x00 */
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u32 code; /* 0x04 */
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s16 x, y; /* 0x08 */
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u8 u, v; /* 0x0C */
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u16 clut; /* 0x0E */
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s16 w, h; /* 0x10 */
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} Sprt_80140D68; /* 0x14 */
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typedef struct { u32 addr : 24; u32 len : 8; } PTag_80140D68;
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register u32 mhi __asm__("$8");
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Sprt_80140D68 *p;
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s16 *q;
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p = (Sprt_80140D68 *)out;
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p->tag = 0x04000000;
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p->u = 0x70;
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p->v = 0x10;
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mhi = 0x64808080;
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p->code = mhi;
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p->clut = 0x4056;
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dx -= 0xD;
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q = (s16 *)(ofs * 2 + (s32)src);
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p->x = q[0] + D_8011516A[idx].x + dx;
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p->y = q[1] - 4;
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p->h = 0x10;
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p->w = 0x10;
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((PTag_80140D68 *)p)->addr = ((PTag_80140D68 *)&OT8_80140D68)->addr;
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((PTag_80140D68 *)&OT8_80140D68)->addr = (u32)p;
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return out + 5;
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}
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