mirror of
https://github.com/Druthulu/BFM-decomp
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Drew T
72e6a096ca
CAUGHT BY VERIFYING THE CHECKPOINT INSTEAD OF ASSERTING IT. `.run/wave22/` was covered by the blanket `/.run/*` ignore, so the 13 UNBANKED drafts — 6 NEAR with precise residual diagnoses and 7 that reached match_one MATCH but did not bank whole-binary — existed only on disk. My own checkpoint's "START HERE" list names them as next-session fuel, and they cost ~2.59M subagent tokens to produce. One `git clean -fdx` would have destroyed them: exactly the exposure the .run/giants Fable5 cracks had before Phase 27 curated them (R20). Now allowlisted: .run/wave22/*.c + .run/wave22_targets.json (the per-target canonical callee/data declarations resolved from the real TU scope — the §17a-1 lever the wave was built on). Also commits docs/family-hseq.md, regenerated by this session's family_hseq runs.
276 lines
9.3 KiB
C
276 lines
9.3 KiB
C
/* func_80176734 — ov_SC01_077 HUD sync. NEAR: 366/371 ins, close=217, LENGTH-DRIFT -5.
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*
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* Base idiom = the matched sibling func_80176218 in the same TU:
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* st=&D_8011F7A8 ($s3), cach=st+0x48 ($s1), flag=st+0xE0 ($s2), cur=D_80078E78 ($s4),
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* param copy ($s6), chg ($s5), r/chg2 ($s0). Index expr written OFFSET-FIRST
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* (((p<<16)>>14) + st + 0x28) so gcc emits `addu rd,off,st` like the target.
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* `u8 zbuf[8]` is NOT dead weight: it is what makes get_frame_size() give the target's
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* 0x40 frame (verified — without it the prologue is `addiu sp,sp,-56`). buf[4] works too.
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* The 0x2E block writes the EQUAL case first so gcc emits `bne` (not `beq`) — byte-verified.
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* The tail routes t+5 / t+9 through temps so gcc emits `addiu $a2,$v1,5; addu $v0,$v0,$a2`
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* instead of reassociating to (lhu+5)+t.
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*
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* RESIDUAL — 5 instructions the target's gcc kept and this draft's gcc optimizes away.
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* All 5 are "target gcc was LESS aggressive"; each was isolated and reproduced, but every
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* known lever for them wrecks the register allocation (see below), so none are applied.
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* b1 (+3): missing `andi $v0,$v1,0xFF` (an explicit QI->SI zero-extend of the D_8011F7B0
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* lbu that combine deletes here via nonzero_bits), missing `addiu $a0,$a1,0x3C`
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* (cse folds `p[4]` into `sb 0x40($a1)`), missing the load-delay `nop` after
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* `lh D_801152BA` (sched1 hoists the lh here, target keeps it at the branch).
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* b2 (-3): `*(u8*)(st+8)` is const-folded to `lui/%lo(D_8011F7A8)+8` here; the target
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* keeps `lbu/sb 0x8($s3)`. cse knows st's constant in that block for us and
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* not for the target. This fold also costs `st` two references, which is why
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* global-alloc gives st $s5 and chg $s3 here (target: st $s3, chg $s5).
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* chg (+1)/switch(+1): the target keeps the uncoalesced copies `addu $s5,$v0,$zero` and
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* `addu $v0,$s0,$zero` (one copy at .L80176AF4, gas duplicates it into 4 delay
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* slots); here cse unifies the temp with the variable and the copy dies.
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* end (+2): the target keeps the provably-redundant `beqz $v1,.L80176C84` (re-test of
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* chg==0) and the `j .L80176C88`/`sb` split; cse's record_jump_equiv kills it here.
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*
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* PROVEN LEVERS (each reproduces its target instruction, all rejected as net-negative):
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* __asm__("" : "=r"(p) : "0"(p)) before the store -> `addiu $a0,$a1,0x3C` appears (369 ins)
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* __asm__("" : "=r"(st) : "0"(st)) before the RMW -> `lbu/sb 0x8($s3)` appears (b2 exact)
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* __asm__("" : "=r"(rv) : "0"(r)) before `if (r)` -> switch region becomes 42/42 exact
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* Each launder is also a scheduling/liveness barrier: it re-shuffles the call-saved
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* allocation and drops aligned agreement from 138/371 to as low as 60/371. A real fix
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* has to make cse weaker WITHOUT a barrier (i.e. find the source shape that ends cse's
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* extended basic block at .L801767BC), not paper over each instruction.
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*/
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extern void func_800183E0(s32);
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extern s32 func_801619D0(void*);
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extern s32 func_80161A00(s32);
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extern s32 func_80161A30(s32);
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extern s32 func_80161A60(s32);
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void func_801775E0(s32, s32);
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extern u8 D_80078E78[];
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extern u8 D_800B9A13;
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extern u8 D_800D43D4;
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extern u8 D_800D4414;
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extern u8 D_800D45D4;
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extern u8 D_8011F7A8;
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extern s32 D_80126B58;
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extern s16 D_80126D20;
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extern u16 D_8018A238;
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extern u8 D_8018A2CC[];
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extern s32 D_8018A2E4[];
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/* derived from the asm (not in sig_hints) */
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extern s16 D_801152BA;
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extern u8 D_80115214;
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extern u8 D_8011F7B0;
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extern s16 D_80126CE0;
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extern u16 D_8018A22A[];
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extern u8 D_8018A2D8[];
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void func_80176734(s32 param_1)
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{
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s32 st = (s32)&D_8011F7A8;
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s32 cach = st + 0x48;
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s32 flag = st + 0xE0;
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s32 cur = (s32)D_80078E78;
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s32 e;
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s32 b;
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s32 chg;
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s32 chg2;
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u16 g;
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s32 r;
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u8 fv;
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u8 zbuf[8];
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e = *(s32 *)(((param_1 << 16) >> 14) + st + 0x28);
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if (D_801152BA != 0) {
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u8 *p = (u8 *)(e + 0x3C);
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s32 vv = D_8011F7B0 - 0x80;
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if (D_8011F7B0 >= 0x80) {
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vv = ~D_8011F7B0 - 0x80;
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}
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p[4] = vv;
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*(u8 *)(e + 4) = vv;
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*(u8 *)(st + 8) = *(u8 *)(st + 8) + D_80115214;
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} else {
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*(u8 *)(e + 0x40) = 0x80;
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*(u8 *)(e + 4) = 0x80;
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}
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fv = *(u8 *)(flag + 0x48);
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if (fv != 0) {
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b = ((param_1 << 16) >> 14) + st;
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*(u8 *)(*(s32 *)(b + 0x28) + 0xD) = D_8018A2D8[fv];
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fv = *(u8 *)(flag + 0x48);
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if (fv < 4) {
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*(u8 *)(flag + 0x48) = fv + 1;
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} else {
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u8 cv = *(u8 *)(cach + 0x48);
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s32 ee = *(s32 *)(b + 0x28);
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if (cv & 0x80) {
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*(u16 *)(ee + 0x20) = D_8018A238;
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func_800183E0((s32)&D_800D45D4);
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} else if (cv != 0) {
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*(u16 *)(ee + 0x20) = D_8018A22A[cv];
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func_800183E0(D_8018A2E4[*(u8 *)(cach + 0x48)]);
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}
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fv = *(u8 *)(flag + 0x48);
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if (fv == 5) {
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if (*(u8 *)(cach + 0x48) == 0) {
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*(u8 *)(flag + 0x48) = 0;
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} else {
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*(u8 *)(flag + 0x48) = fv + 1;
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}
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} else if (fv == 10) {
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*(u8 *)(flag + 0x48) = 0;
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} else {
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*(u8 *)(flag + 0x48) = fv + 1;
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}
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}
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} else {
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u8 cv = *(u8 *)(cach + 0x48);
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u8 sv = *(u8 *)(cur + 0x48);
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if (cv != sv) {
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if (cv == 0 && sv != 0) {
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*(u8 *)(flag + 0x48) = 5;
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} else {
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*(u8 *)(flag + 0x48) = 0;
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}
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*(u8 *)(cach + 0x48) = *(u8 *)(cur + 0x48);
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{
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s32 bb2 = ((param_1 << 16) >> 14) + st;
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u8 f2 = *(u8 *)(flag + 0x48);
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s32 ee = *(s32 *)(bb2 + 0x28);
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*(u8 *)(flag + 0x48) = f2 + 1;
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*(u8 *)(ee + 0xD) = D_8018A2D8[f2];
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}
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}
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}
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{
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s16 sv2 = *(s16 *)(cur + 0x2E);
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if (*(s16 *)(cach + 0x2E) == sv2) {
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if (*(s16 *)(flag + 0x2E) == 0) goto L9C0;
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*(s16 *)(flag + 0x2E) = 0;
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} else {
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*(s16 *)(cach + 0x2E) = sv2;
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*(s16 *)(flag + 0x2E) = 1;
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}
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}
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{
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s32 ee = *(s32 *)(((param_1 << 16) >> 14) + st + 0x28);
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s32 t = (s32)(*(u16 *)(cach + 0x2E)) << 16;
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if (t != 0) {
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*(u8 *)(ee + 0x49) = D_8018A2CC[t >> 20];
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} else {
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*(u8 *)(ee + 0x49) = 0xA0;
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}
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}
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L9C0:
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{
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s32 fa = *(s16 *)(cach + 0x1E) & 0x8000;
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s32 fb = *(s16 *)(cur + 0x1E) & 0x8000;
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if (fa != fb) {
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s32 arg;
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if (fa != 0) {
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arg = (s32)&D_800D43D4;
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*(s16 *)(cach + 0x1E) = 0;
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} else {
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*(s16 *)(cach + 0x1E) = -0x8000;
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arg = (s32)&D_800D4414;
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}
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func_800183E0(arg);
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}
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}
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{
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u8 cc3 = D_800B9A13;
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if (cc3 == 3) {
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chg = 0;
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} else {
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chg = (*(u8 *)(st + 7) != cc3);
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if (chg != 0) {
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*(u8 *)(st + 7) = cc3;
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}
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}
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}
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r = 0;
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switch (*(u8 *)(cur + 0x48)) {
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case 3:
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if (func_801619D0(&D_80126B58) != 0) r = 0xFF;
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break;
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case 4:
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if (func_80161A00((s32)&D_80126B58) != 0) r = 0xFF;
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break;
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case 5:
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if (func_80161A30((s32)&D_80126B58) != 0) r = 0xFF;
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break;
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case 6:
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if (func_80161A60((s32)&D_80126B58) != 0) r = 0xBA;
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break;
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}
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if (r != 0) {
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*(u8 *)(flag + 0x47) = 1;
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*(u8 *)(cach + 0x4B) = *(u8 *)(cur + 0x48) | 0xF0;
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*(u8 *)(cach + 0x47) = ((s32)D_80126D20 << 7) / r;
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goto LC88;
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}
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if (*(u8 *)(cach + 0x4B) >= 0xF0) {
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*(u8 *)(cach + 0x4B) = 0;
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}
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if (D_80126CE0 != 0) {
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g = *(u16 *)&D_80126CE0;
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*(u8 *)(cach + 0x4B) = g;
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chg2 = (*(u8 *)(cach + 0x47) != (u8)g);
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} else {
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g = *(u8 *)(cur + 0x47);
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chg2 = 0;
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if (*(u8 *)(cach + 0x47) != (u8)g || *(u8 *)(cach + 0x47) == 0x80) {
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chg2 = 1;
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}
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if (*(u8 *)(cur + 0x47) != 0 && *(u8 *)(cach + 0x4B) != 0) {
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*(u8 *)(cach + 0x4B) = 0;
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*(u8 *)(cach + 0x47) = *(u8 *)(cur + 0x47);
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}
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}
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if (chg2 == 0 && chg == 0) {
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if (*(u8 *)(flag + 0x47) == 0) goto LC88;
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if (chg == 0) {
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*(u8 *)(flag + 0x47) = 0;
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goto LC88;
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}
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}
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{
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u8 c47 = *(u8 *)(cach + 0x47);
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if (c47 < (s16)g) {
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*(u8 *)(cach + 0x47) = g;
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} else {
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if ((s16)g != 0) {
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*(u8 *)(cach + 0x47) = c47 - 3;
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} else {
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*(u8 *)(cach + 0x47) = c47 - 8;
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}
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c47 = *(u8 *)(cach + 0x47);
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if (c47 == 0 || c47 > 0x80) {
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*(u8 *)(cach + 0x47) = 0;
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*(u8 *)(cach + 0x4B) = 0;
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} else if (c47 < (s16)g) {
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*(u8 *)(cach + 0x47) = g;
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}
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}
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*(u8 *)(flag + 0x47) = 1;
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}
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LC88:
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b = ((param_1 << 16) >> 14) + st;
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{
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s32 t = (*(u8 *)(st + 7) != 0) << 8;
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s32 t5 = t + 5;
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s32 t9 = t + 9;
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*(s16 *)(*(s32 *)(b + 0x28) + 0x32) = *(u16 *)(st + 0x12) + t5;
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func_801775E0(*(s32 *)(b + 0x28) + 0x64,
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(s16)(*(u16 *)(st + 0x12) + t9));
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}
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}
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