mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-09-26 16:59:35 -04:00
refactor: added more instructions decoder
This commit is contained in:
Ran-j
@@ -34,6 +34,26 @@ namespace ps2recomp
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inst.isReturn = false;
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inst.hasDelaySlot = false;
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inst.isMultimedia = false;
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inst.isLoad = false;
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inst.isStore = false;
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// Initialize the enhanced fields
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inst.mmiType = 0;
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inst.mmiFunction = 0;
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inst.pmfhlVariation = 0;
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inst.vuFunction = 0;
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inst.vectorInfo.isVector = false;
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inst.vectorInfo.usesQReg = false;
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inst.vectorInfo.usesPReg = false;
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inst.vectorInfo.modifiesMAC = false;
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inst.vectorInfo.vectorField = 0xF; // All fields (xyzw)
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inst.modificationInfo.modifiesGPR = false;
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inst.modificationInfo.modifiesFPR = false;
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inst.modificationInfo.modifiesVFR = false;
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inst.modificationInfo.modifiesMemory = false;
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inst.modificationInfo.modifiesControl = false;
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switch (inst.opcode)
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{
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@@ -86,18 +106,21 @@ namespace ps2recomp
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decodeMMI(inst);
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inst.isMMI = true;
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inst.isMultimedia = true;
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inst.modificationInfo.modifiesGPR = true;
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break;
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case OPCODE_LQ:
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decodeIType(inst);
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inst.isLoad = true;
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inst.isMultimedia = true; // 128-bit load
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inst.modificationInfo.modifiesGPR = true;
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break;
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case OPCODE_SQ:
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decodeIType(inst);
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inst.isStore = true;
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inst.isMultimedia = true; // 128-bit store
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inst.modificationInfo.modifiesMemory = true;
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break;
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case OPCODE_LB:
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@@ -462,71 +485,341 @@ namespace ps2recomp
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void R5900Decoder::decodeCOP2(Instruction &inst) const
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{
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// COP2 (VU0 macro mode) instructions
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inst.isVU = true;
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inst.isMultimedia = true;
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uint32_t rs = inst.rs; // The VU0 format field
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uint32_t rs = inst.rs; // The format field
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if (rs == COP2_MFC2)
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switch (rs)
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{
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// Move From COP2 register
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case COP2_QMFC2: // Move From COP2 (128-bit)
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case COP2_CFC2: // Move Control From COP2
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case COP2_QMTC2: // Move To COP2 (128-bit)
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case COP2_CTC2: // Move Control To COP2
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// Register transfer operations
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break;
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case COP2_BC2: // Branch on COP2 condition
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{
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uint32_t rt = inst.rt; // The condition code
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if (rt == COP2_BCF || rt == COP2_BCT ||
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rt == COP2_BCFL || rt == COP2_BCTL ||
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rt == COP2_BCEF || rt == COP2_BCET ||
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rt == COP2_BCEFL || rt == COP2_BCETL)
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{
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inst.isBranch = true;
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inst.hasDelaySlot = true;
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}
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}
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else if (rs == COP2_CFC2)
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break;
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case COP2_CO: // VU0 vector operations
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{
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// Move From COP2 Control register
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uint32_t function = inst.function;
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switch (function)
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{
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case VU0_VADD:
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case VU0_VSUB:
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case VU0_VMUL:
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// Basic vector math operations
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break;
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case VU0_VDIV:
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case VU0_VSQRT:
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case VU0_VRSQRT:
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// Division and square root operations
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break;
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case VU0_VMULQ:
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// Multiply by Q register
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break;
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case VU0_VIADD:
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case VU0_VISUB:
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case VU0_VIADDI:
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// Integer operations
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break;
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case VU0_VIAND:
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case VU0_VIOR:
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// Logical operations
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break;
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case VU0_VILWR:
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case VU0_VISWR:
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// Load/Store operations
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inst.isLoad = (function == VU0_VILWR);
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inst.isStore = (function == VU0_VISWR);
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break;
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case VU0_VCALLMS:
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case VU0_VCALLMSR:
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// VU0 microprogram calls
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inst.isCall = true;
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break;
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case VU0_VRGET:
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// Get random number from R register
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break;
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default:
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// Other VU0 operations
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break;
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}
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}
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else if (rs == COP2_MTC2)
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break;
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case COP2_CTCVU: // Control Transfer to VU0
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case COP2_MTVUCF: // Move To VU Control/Flag register
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case COP2_VMTIR: // Move To VU0 I Register
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// Special register operations
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break;
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case COP2_VU0OPS: // Additional VU0 operations
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{
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// Move To COP2 register
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uint32_t function = inst.function;
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switch (function)
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{
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case VU0OPS_QMFC2_NI: // Non-incrementing QMFC2
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case VU0OPS_QMFC2_I: // Incrementing QMFC2
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case VU0OPS_QMTC2_NI: // Non-incrementing QMTC2
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case VU0OPS_QMTC2_I: // Incrementing QMTC2
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// Extended register transfer operations
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break;
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case VU0OPS_VMFIR: // Move From Integer Register
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// Move operations
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break;
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case VU0OPS_VXITOP: // Execute Interrupt on VU0
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break;
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case VU0OPS_VWAITQ: // Wait for Q register operations
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break;
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default:
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// Unknown VU0OPS
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break;
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}
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}
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else if (rs == COP2_CTC2)
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{
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// Move To COP2 Control register
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}
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else if (rs == COP2_BCF || rs == COP2_BCT)
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{
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// VU0 Branch on Condition
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inst.isBranch = true;
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inst.hasDelaySlot = true;
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}
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else
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{
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// VU0 vector operations
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// These would need detailed decoding based on function field
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break;
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default:
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// Unknown COP2 format
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break;
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}
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}
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void R5900Decoder::decodeMMI0(Instruction &inst) const
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{
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// Decode MMI0 subfunctions (based on function field)
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uint32_t subFunction = inst.function & 0x3F;
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uint32_t sa = inst.sa;
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// The implementation would set appropriate flags or properties based on the specific MMI0 operation
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switch (sa)
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{
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case MMI0_PADDW:
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case MMI0_PSUBW:
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case MMI0_PCGTW:
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case MMI0_PMAXW:
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case MMI0_PADDH:
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case MMI0_PSUBH:
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case MMI0_PCGTH:
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case MMI0_PMAXH:
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case MMI0_PADDB:
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case MMI0_PSUBB:
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case MMI0_PCGTB:
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// Arithmetic and comparison operations
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break;
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case MMI0_PADDSW:
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case MMI0_PSUBSW:
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case MMI0_PADDSH:
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case MMI0_PSUBSH:
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case MMI0_PADDSB:
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case MMI0_PSUBSB:
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// Saturated arithmetic operations
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break;
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case MMI0_PEXTLW:
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case MMI0_PPACW:
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case MMI0_PEXTLH:
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case MMI0_PPACH:
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case MMI0_PEXTLB:
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case MMI0_PPACB:
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case MMI0_PEXT5:
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case MMI0_PPAC5:
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// Data packing/unpacking operations
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break;
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default:
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// Unknown MMI0 operation
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break;
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}
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}
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void R5900Decoder::decodeMMI1(Instruction &inst) const
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{
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// Decode MMI1 subfunctions (based on function field)
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uint32_t subFunction = inst.function & 0x3F;
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// The implementation would set appropriate flags or properties based on the specific MMI1 operation
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uint32_t sa = inst.sa;
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switch (sa)
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{
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case MMI1_PABSW:
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case MMI1_PABSH:
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// Absolute value operations
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break;
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case MMI1_PCEQW:
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case MMI1_PCEQH:
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case MMI1_PCEQB:
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// Equality comparison operations
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break;
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case MMI1_PMINW:
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case MMI1_PMINH:
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// Minimum value operations
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break;
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case MMI1_PADDUW:
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case MMI1_PSUBUW:
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case MMI1_PEXTUW:
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case MMI1_PADDUH:
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case MMI1_PSUBUH:
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case MMI1_PEXTUH:
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case MMI1_PADDUB:
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case MMI1_PSUBUB:
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case MMI1_PEXTUB:
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// Unsigned arithmetic and extension operations
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break;
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case MMI1_QFSRV:
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// Quadword funnel shift right variable
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inst.isMultimedia = true;
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break;
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default:
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// Unknown MMI1 operation
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break;
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}
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}
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void R5900Decoder::decodeMMI2(Instruction &inst) const
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{
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// Decode MMI2 subfunctions (based on function field)
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uint32_t subFunction = inst.function & 0x3F;
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uint32_t sa = inst.sa;
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// The implementation would set appropriate flags or properties based on the specific MMI2 operation
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switch (sa)
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{
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case MMI2_PMADDW:
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case MMI2_PMSUBW:
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case MMI2_PMADDH:
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case MMI2_PHMADH:
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case MMI2_PMSUBH:
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case MMI2_PHMSBH:
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case MMI2_PMULTH:
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// Multiply/multiply-add operations
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inst.isMultimedia = true;
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break;
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case MMI2_PSLLVW:
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case MMI2_PSRLVW:
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// Variable shift operations
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break;
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case MMI2_PMFHI:
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case MMI2_PMFLO:
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// Move from HI/LO registers
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break;
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case MMI2_PINTH:
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// Interleave half words
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break;
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case MMI2_PMULTW:
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case MMI2_PDIVW:
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case MMI2_PDIVBW:
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// Multiply/divide operations
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inst.isMultimedia = true;
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break;
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case MMI2_PCPYLD:
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// Copy lower doubleword
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break;
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case MMI2_PAND:
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case MMI2_PXOR:
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// Logical operations
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break;
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case MMI2_PEXEH:
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case MMI2_PREVH:
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case MMI2_PEXEW:
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case MMI2_PROT3W:
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// Data permutation operations
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break;
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default:
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// Unknown MMI2 operation
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break;
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}
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}
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void R5900Decoder::decodeMMI3(Instruction &inst) const
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{
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// Decode MMI3 subfunctions (based on function field)
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uint32_t subFunction = inst.function & 0x3F;
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uint32_t sa = inst.sa;
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// The implementation would set appropriate flags or properties based on the specific MMI3 operation
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switch (sa)
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{
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case MMI3_PMADDUW:
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// Unsigned multiply-add
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inst.isMultimedia = true;
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break;
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case MMI3_PSRAVW:
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// Packed shift right arithmetic variable word
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break;
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case MMI3_PMTHI:
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inst.mmiFunction = MMI3_PMTHI;
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inst.modificationInfo.modifiesControl = true; // HI register is modified
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break;
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case MMI3_PMTLO:
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inst.mmiFunction = MMI3_PMTLO;
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inst.modificationInfo.modifiesControl = true; // LO register is modified
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break;
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case MMI3_PINTEH:
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// Interleave even halfwords
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break;
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case MMI3_PMULTUW:
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case MMI3_PDIVUW:
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// Unsigned multiply/divide operations
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inst.isMultimedia = true;
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break;
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case MMI3_PCPYUD:
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// Copy upper doubleword
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break;
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case MMI3_POR:
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case MMI3_PNOR:
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// Logical operations
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break;
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case MMI3_PEXCH:
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case MMI3_PCPYH:
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case MMI3_PEXCW:
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// Data permutation operations
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break;
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default:
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// Unknown MMI3 operation
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break;
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}
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}
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void R5900Decoder::decodePMFHL(Instruction &inst) const
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