mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-09-26 16:59:35 -04:00
feat: added more instructions with revision
This commit is contained in:
Ran-j
@@ -580,15 +580,78 @@ namespace ps2recomp
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case OPCODE_BLEZL:
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case OPCODE_BGTZL:
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return fmt::format("// Likely branch instruction at 0x{:X} - Handled by branch logic", inst.address);
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case OPCODE_LDL:
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return fmt::format("{{ uint32_t addr = ADD32(GPR_U32(ctx, {}), {}); "
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"uint32_t shift = (addr & 7) << 3; "
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"uint64_t mask = 0xFFFFFFFFFFFFFFFFULL << shift; "
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"uint64_t aligned_data = READ64(addr & ~7ULL); "
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"SET_GPR_U64(ctx, {}, (GPR_U64(ctx, {}) & ~mask) | (aligned_data & mask)); }}",
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inst.rs, inst.simmediate, inst.rt, inst.rt);
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case OPCODE_LDR:
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case OPCODE_SDL:
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case OPCODE_SDR:
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return fmt::format("{{ uint32_t addr = ADD32(GPR_U32(ctx, {}), {}); "
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"uint32_t shift = ((~addr) & 7) << 3; "
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"uint64_t mask = 0xFFFFFFFFFFFFFFFFULL >> shift; "
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"uint64_t aligned_data = READ64(addr & ~7ULL); "
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"SET_GPR_U64(ctx, {}, (GPR_U64(ctx, {}) & ~mask) | (aligned_data & mask)); }}",
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inst.rs, inst.simmediate, inst.rt, inst.rt);
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case OPCODE_LWL:
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return fmt::format("{{ uint32_t addr = ADD32(GPR_U32(ctx, {}), {}); "
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"uint32_t shift = (addr & 3) << 3; "
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"uint32_t mask = 0xFFFFFFFF << shift; "
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"uint32_t aligned_data = READ32(addr & ~3); "
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"SET_GPR_U32(ctx, {}, (GPR_U32(ctx, {}) & ~mask) | (aligned_data & mask)); }}",
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inst.rs, inst.simmediate, inst.rt, inst.rt);
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case OPCODE_LWR:
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return fmt::format("{{ uint32_t addr = ADD32(GPR_U32(ctx, {}), {}); "
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"uint32_t shift = ((~addr) & 3) << 3; "
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"uint32_t mask = 0xFFFFFFFF >> shift; "
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"uint32_t aligned_data = READ32(addr & ~3); "
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"SET_GPR_U32(ctx, {}, (GPR_U32(ctx, {}) & ~mask) | (aligned_data & mask)); }}",
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inst.rs, inst.simmediate, inst.rt, inst.rt);
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case OPCODE_SWL:
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return fmt::format("{{ uint32_t addr = ADD32(GPR_U32(ctx, {}), {}); "
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"uint32_t shift = (addr & 3) << 3; "
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"uint32_t mask = 0xFFFFFFFF << shift; "
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"uint32_t aligned_addr = addr & ~3; "
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"uint32_t old_data = READ32(aligned_addr); "
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"uint32_t new_data = (old_data & ~mask) | (GPR_U32(ctx, {}) & mask); "
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"WRITE32(aligned_addr, new_data); }}",
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inst.rs, inst.simmediate, inst.rt);
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case OPCODE_SWR:
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return fmt::format("//Unhandled Unaligned load/store instruction 0x{:X} not implemented", inst.opcode);
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return fmt::format("{{ uint32_t addr = ADD32(GPR_U32(ctx, {}), {}); "
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"uint32_t shift = ((~addr) & 3) << 3; "
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"uint32_t mask = 0xFFFFFFFF >> shift; "
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"uint32_t aligned_addr = addr & ~3; "
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"uint32_t old_data = READ32(aligned_addr); "
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"uint32_t new_data = (old_data & ~mask) | (GPR_U32(ctx, {}) & mask); "
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"WRITE32(aligned_addr, new_data); }}",
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inst.rs, inst.simmediate, inst.rt);
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case OPCODE_SDL:
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return fmt::format("{{ uint32_t addr = ADD32(GPR_U32(ctx, {}), {}); "
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"uint32_t shift = (addr & 7) << 3; "
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"uint64_t mask = 0xFFFFFFFFFFFFFFFFULL << shift; "
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"uint64_t aligned_addr = addr & ~7ULL; "
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"uint64_t old_data = READ64(aligned_addr); "
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"uint64_t new_data = (old_data & ~mask) | (GPR_U64(ctx, {}) & mask); "
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"WRITE64(aligned_addr, new_data); }}",
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inst.rs, inst.simmediate, inst.rt);
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case OPCODE_SDR:
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return fmt::format("{{ uint32_t addr = ADD32(GPR_U32(ctx, {}), {}); "
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"uint32_t shift = ((~addr) & 7) << 3; "
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"uint64_t mask = 0xFFFFFFFFFFFFFFFFULL >> shift; "
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"uint64_t aligned_addr = addr & ~7ULL; "
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"uint64_t old_data = READ64(aligned_addr); "
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"uint64_t new_data = (old_data & ~mask) | (GPR_U64(ctx, {}) & mask); "
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"WRITE64(aligned_addr, new_data); }}",
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inst.rs, inst.simmediate, inst.rt);
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case OPCODE_CACHE:
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return "// CACHE instruction (ignored)";
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case OPCODE_PREF:
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@@ -645,7 +708,20 @@ namespace ps2recomp
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case SPECIAL_DIVU:
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return fmt::format("{{ uint32_t divisor = GPR_U32(ctx, {}); if (divisor != 0) {{ ctx->lo = GPR_U32(ctx, {}) / divisor; ctx->hi = GPR_U32(ctx, {}) % divisor; }} else {{ ctx->lo = 0xFFFFFFFF; ctx->hi = GPR_U32(ctx,{}); }} }}", inst.rt, inst.rs, inst.rt, inst.rs, inst.rt);
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case SPECIAL_ADD:
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return fmt::format("SET_GPR_S32(ctx, {}, ADD32(GPR_U32(ctx, {}), GPR_U32(ctx, {})));", inst.rd, inst.rs, inst.rt);
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return fmt::format(
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"if (runtime->check_overflow) {{ "
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" int32_t rs_val = GPR_S32(ctx, {}); "
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" int32_t rt_val = GPR_S32(ctx, {}); "
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" int64_t result = (int64_t)rs_val + (int64_t)rt_val; "
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" if (result > INT32_MAX || result < INT32_MIN) {{ "
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" runtime->SignalException(ctx, EXCEPTION_INTEGER_OVERFLOW); "
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" }} else {{ "
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" SET_GPR_S32(ctx, {}, (int32_t)result); "
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" }} "
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"}} else {{ "
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" SET_GPR_S32(ctx, {}, ADD32(GPR_S32(ctx, {}), GPR_S32(ctx, {}))); "
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"}}",
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inst.rs, inst.rt, inst.rd, inst.rd, inst.rs, inst.rt);
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case SPECIAL_ADDU:
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return fmt::format("SET_GPR_U32(ctx, {}, ADD32(GPR_U32(ctx, {}), GPR_U32(ctx, {})));", inst.rd, inst.rs, inst.rt);
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case SPECIAL_SUB:
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@@ -1349,14 +1425,56 @@ namespace ps2recomp
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_status);", rt);
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case VU0_CR_MAC:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_mac_flags);", rt);
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case VU0_CR_CLIP:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_clip_flags);", rt);
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case VU0_CR_VPU_STAT:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_vpu_stat);", rt);
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case VU0_CR_R:
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return fmt::format("SET_GPR_VEC(ctx, {}, (__m128i)ctx->vu0_r);", rt);
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case VU0_CR_I:
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return fmt::format("SET_GPR_U32(ctx, {}, *(uint32_t*)&ctx->vu0_i);", rt);
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case VU0_CR_CLIP:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_clip_flags);", rt);
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case VU0_CR_TPC:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_tpc);", rt);
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case VU0_CR_CMSAR0:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_cmsar0);", rt);
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case VU0_CR_FBRST:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_fbrst);", rt);
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case VU0_CR_VPU_STAT2:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_vpu_stat2);", rt);
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case VU0_CR_TPC2:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_tpc2);", rt);
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case VU0_CR_CMSAR1:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_cmsar1);", rt);
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case VU0_CR_FBRST2:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_fbrst2);", rt);
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case VU0_CR_VPU_STAT3:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_vpu_stat3);", rt);
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case VU0_CR_CMSAR2:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_cmsar2);", rt);
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case VU0_CR_FBRST3:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_fbrst3);", rt);
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case VU0_CR_VPU_STAT4:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_vpu_stat4);", rt);
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case VU0_CR_CMSAR3:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_cmsar3);", rt);
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case VU0_CR_FBRST4:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_fbrst4);", rt);
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case VU0_CR_ACC:
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return fmt::format("SET_GPR_VEC(ctx, {}, (__m128i)ctx->vu0_acc);", rt);
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case VU0_CR_INFO:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_info);", rt);
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case VU0_CR_CLIP2:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_clip_flags2);", rt);
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case VU0_CR_P:
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return fmt::format("SET_GPR_U32(ctx, {}, *(uint32_t*)&ctx->vu0_p);", rt);
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case VU0_CR_XITOP:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_xitop);", rt);
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case VU0_CR_ITOP:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_itop);", rt);
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case VU0_CR_TOP:
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return fmt::format("SET_GPR_U32(ctx, {}, ctx->vu0_top);", rt);
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default:
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return fmt::format("// Unhandled CFC2 VU CReg: {}", rd);
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return fmt::format("// Unimplemented CFC2 VU CReg: {}", rt);
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}
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}
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case COP2_QMTC2:
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@@ -1369,14 +1487,56 @@ namespace ps2recomp
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return fmt::format("ctx->vu0_status = GPR_U32(ctx, {}) & 0xFFFF;", rt);
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case VU0_CR_MAC:
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return fmt::format("ctx->vu0_mac_flags = GPR_U32(ctx, {});", rt);
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case VU0_CR_VPU_STAT:
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return fmt::format("ctx->vu0_vpu_stat = GPR_U32(ctx, {});", rt);
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case VU0_CR_CLIP:
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return fmt::format("ctx->vu0_clip_flags = GPR_U32(ctx, {});", rt);
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case VU0_CR_R:
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return fmt::format("ctx->vu0_r = (__m128)GPR_VEC(ctx, {});", rt);
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case VU0_CR_I:
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return fmt::format("ctx->vu0_i = *(float*)&GPR_U32(ctx, {});", rt);
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case VU0_CR_TPC:
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return fmt::format("ctx->vu0_tpc = GPR_U32(ctx, {});", rt);
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case VU0_CR_CMSAR0:
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return fmt::format("ctx->vu0_cmsar0 = GPR_U32(ctx, {});", rt);
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case VU0_CR_FBRST:
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return fmt::format("ctx->vu0_fbrst = GPR_U32(ctx, {});", rt);
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case VU0_CR_VPU_STAT2:
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return fmt::format("ctx->vu0_vpu_stat2 = GPR_U32(ctx, {});", rt);
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case VU0_CR_TPC2:
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return fmt::format("ctx->vu0_tpc2 = GPR_U32(ctx, {});", rt);
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case VU0_CR_CMSAR1:
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return fmt::format("ctx->vu0_cmsar1 = GPR_U32(ctx, {});", rt);
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case VU0_CR_FBRST2:
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return fmt::format("ctx->vu0_fbrst2 = GPR_U32(ctx, {});", rt);
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case VU0_CR_VPU_STAT3:
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return fmt::format("ctx->vu0_vpu_stat3 = GPR_U32(ctx, {});", rt);
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case VU0_CR_CMSAR2:
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return fmt::format("ctx->vu0_cmsar2 = GPR_U32(ctx, {});", rt);
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case VU0_CR_FBRST3:
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return fmt::format("ctx->vu0_fbrst3 = GPR_U32(ctx, {});", rt);
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case VU0_CR_VPU_STAT4:
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return fmt::format("ctx->vu0_vpu_stat4 = GPR_U32(ctx, {});", rt);
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case VU0_CR_CMSAR3:
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return fmt::format("ctx->vu0_cmsar3 = GPR_U32(ctx, {});", rt);
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case VU0_CR_FBRST4:
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return fmt::format("ctx->vu0_fbrst4 = GPR_U32(ctx, {});", rt);
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case VU0_CR_ACC:
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return fmt::format("ctx->vu0_acc = (__m128)GPR_VEC(ctx, {});", rt);
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case VU0_CR_INFO:
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return fmt::format("ctx->vu0_info = GPR_U32(ctx, {});", rt);
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case VU0_CR_CLIP2:
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return fmt::format("ctx->vu0_clip_flags2 = GPR_U32(ctx, {});", rt);
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case VU0_CR_P:
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return fmt::format("ctx->vu0_p = *(float*)&GPR_U32(ctx, {});", rt);
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case VU0_CR_XITOP:
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return fmt::format("ctx->vu0_xitop = GPR_U32(ctx, {}) & 0x3FF;", rt);
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case VU0_CR_ITOP:
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return fmt::format("ctx->vu0_itop = GPR_U32(ctx, {}) & 0x3FF;", rt);
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case VU0_CR_TOP:
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return fmt::format("ctx->vu0_top = GPR_U32(ctx, {}) & 0x3FF;", rt);
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default:
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return fmt::format("// Unhandled CTC2 VU CReg: {}", rd);
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return fmt::format("// Unimplemented CTC2 VU CReg: {}", rd);
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}
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}
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case COP2_BC:
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@@ -1490,6 +1650,27 @@ namespace ps2recomp
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return fmt::format("ctx->vu0_vf[{}] = PS2_VSUB(ctx->vu0_vf[{}], _mm_set1_ps(ctx->vu0_i));", inst.rd, inst.rs);
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case VU0_S1_VMULi:
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return fmt::format("ctx->vu0_vf[{}] = PS2_VMUL(ctx->vu0_vf[{}], _mm_set1_ps(ctx->vu0_i));", inst.rd, inst.rs);
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case VU0_S1_VMADDx:
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case VU0_S1_VMADDy:
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case VU0_S1_VMADDz:
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case VU0_S1_VMADDw:
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return translateVU_VMADD_Field(inst);
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case VU0_S1_VMAXx:
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return fmt::format("ctx->vu0_vf[{}] = _mm_max_ps(ctx->vu0_vf[{}], _mm_shuffle_ps(ctx->vu0_vf[{}], ctx->vu0_vf[{}], _MM_SHUFFLE(0,0,0,0)));", inst.rd, inst.rs, inst.rt, inst.rt);
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case VU0_S1_VMAXz:
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return fmt::format("ctx->vu0_vf[{}] = _mm_max_ps(ctx->vu0_vf[{}], _mm_shuffle_ps(ctx->vu0_vf[{}], ctx->vu0_vf[{}], _MM_SHUFFLE(2,2,2,2)));", inst.rd, inst.rs, inst.rt, inst.rt);
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case VU0_S1_VMINIx:
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case VU0_S1_VMINIy:
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case VU0_S1_VMINIw:
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return translateVU_VMINI_Field(inst);
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case VU0_S1_VMADD:
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return translateVU_VMADD(inst);
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case VU0_S1_VMAX:
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return translateVU_VMAX(inst);
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case VU0_S1_VOPMSUB:
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return translateVU_VOPMSUB(inst);
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case VU0_S1_VMINI:
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return translateVU_VMINI(inst);
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default:
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return fmt::format("// Unhandled VU0 Special1 function: 0x{:X}", vu_func);
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}
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@@ -1808,6 +1989,93 @@ namespace ps2recomp
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return fmt::format("// Unhandled VU0 VRNEXT instruction: 0x{:X}", inst.function);
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}
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std::string CodeGenerator::translateVU_VMADD_Field(const Instruction &inst)
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{
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uint8_t dest_mask = inst.vectorInfo.vectorField;
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uint8_t field = inst.function & 0x3; // Extract field from function code
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// Pre-construct the shuffle pattern to avoid format string issues
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std::string shuffle_pattern = fmt::format("_MM_SHUFFLE({},{},{},{})", field, field, field, field);
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return fmt::format("{{ __m128 mul_res = PS2_VMUL(ctx->vu0_vf[{}], _mm_shuffle_ps(ctx->vu0_vf[{}], ctx->vu0_vf[{}], {})); "
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"__m128 res = PS2_VADD(ctx->vu0_acc, mul_res); "
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"__m128i mask = _mm_set_epi32({}, {}, {}, {}); "
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"ctx->vu0_vf[{}] = _mm_blendv_ps(ctx->vu0_vf[{}], res, _mm_castsi128_ps(mask)); "
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"ctx->vu0_acc = res; }}",
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inst.rs, inst.rt, inst.rt, shuffle_pattern,
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(dest_mask & 0x8) ? -1 : 0, (dest_mask & 0x4) ? -1 : 0,
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(dest_mask & 0x2) ? -1 : 0, (dest_mask & 0x1) ? -1 : 0,
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inst.rd, inst.rd);
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}
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std::string CodeGenerator::translateVU_VMINI_Field(const Instruction &inst)
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{
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uint8_t dest_mask = inst.vectorInfo.vectorField;
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uint8_t field = inst.function & 0x3;
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std::string shuffle_pattern = fmt::format("_MM_SHUFFLE({},{},{},{})", field, field, field, field);
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return fmt::format("{{ __m128 res = _mm_min_ps(ctx->vu0_vf[{}], _mm_shuffle_ps(ctx->vu0_vf[{}], ctx->vu0_vf[{}], {})); "
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"__m128i mask = _mm_set_epi32({}, {}, {}, {}); "
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"ctx->vu0_vf[{}] = _mm_blendv_ps(ctx->vu0_vf[{}], res, _mm_castsi128_ps(mask)); }}",
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inst.rs, inst.rt, inst.rt, shuffle_pattern,
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(dest_mask & 0x8) ? -1 : 0, (dest_mask & 0x4) ? -1 : 0,
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(dest_mask & 0x2) ? -1 : 0, (dest_mask & 0x1) ? -1 : 0,
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inst.rd, inst.rd);
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}
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std::string CodeGenerator::translateVU_VMADD(const Instruction &inst)
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{
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uint8_t dest_mask = inst.vectorInfo.vectorField;
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return fmt::format("{{ __m128 mul_res = PS2_VMUL(ctx->vu0_vf[{}], ctx->vu0_vf[{}]); "
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"__m128 res = PS2_VADD(ctx->vu0_acc, mul_res); "
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"__m128i mask = _mm_set_epi32({}, {}, {}, {}); "
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"ctx->vu0_vf[{}] = _mm_blendv_ps(ctx->vu0_vf[{}], res, _mm_castsi128_ps(mask)); "
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"ctx->vu0_acc = res; }}",
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inst.rs, inst.rt,
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(dest_mask & 0x8) ? -1 : 0, (dest_mask & 0x4) ? -1 : 0,
|
||||
(dest_mask & 0x2) ? -1 : 0, (dest_mask & 0x1) ? -1 : 0,
|
||||
inst.rd, inst.rd);
|
||||
}
|
||||
|
||||
std::string CodeGenerator::translateVU_VMAX(const Instruction &inst)
|
||||
{
|
||||
uint8_t dest_mask = inst.vectorInfo.vectorField;
|
||||
return fmt::format("{{ __m128 res = _mm_max_ps(ctx->vu0_vf[{}], ctx->vu0_vf[{}]); "
|
||||
"__m128i mask = _mm_set_epi32({}, {}, {}, {}); "
|
||||
"ctx->vu0_vf[{}] = _mm_blendv_ps(ctx->vu0_vf[{}], res, _mm_castsi128_ps(mask)); }}",
|
||||
inst.rs, inst.rt,
|
||||
(dest_mask & 0x8) ? -1 : 0, (dest_mask & 0x4) ? -1 : 0,
|
||||
(dest_mask & 0x2) ? -1 : 0, (dest_mask & 0x1) ? -1 : 0,
|
||||
inst.rd, inst.rd);
|
||||
}
|
||||
|
||||
std::string CodeGenerator::translateVU_VOPMSUB(const Instruction &inst)
|
||||
{
|
||||
uint8_t dest_mask = inst.vectorInfo.vectorField;
|
||||
return fmt::format("{{ __m128 mul_res = PS2_VMUL(ctx->vu0_vf[{}], ctx->vu0_vf[{}]); "
|
||||
"__m128 res = PS2_VSUB(ctx->vu0_acc, mul_res); "
|
||||
"__m128i mask = _mm_set_epi32({}, {}, {}, {}); "
|
||||
"ctx->vu0_vf[{}] = _mm_blendv_ps(ctx->vu0_vf[{}], res, _mm_castsi128_ps(mask)); "
|
||||
"ctx->vu0_acc = res; }}",
|
||||
inst.rs, inst.rt,
|
||||
(dest_mask & 0x8) ? -1 : 0, (dest_mask & 0x4) ? -1 : 0,
|
||||
(dest_mask & 0x2) ? -1 : 0, (dest_mask & 0x1) ? -1 : 0,
|
||||
inst.rd, inst.rd);
|
||||
}
|
||||
|
||||
std::string CodeGenerator::translateVU_VMINI(const Instruction &inst)
|
||||
{
|
||||
uint8_t dest_mask = inst.vectorInfo.vectorField;
|
||||
return fmt::format("{{ __m128 res = _mm_min_ps(ctx->vu0_vf[{}], ctx->vu0_vf[{}]); "
|
||||
"__m128i mask = _mm_set_epi32({}, {}, {}, {}); "
|
||||
"ctx->vu0_vf[{}] = _mm_blendv_ps(ctx->vu0_vf[{}], res, _mm_castsi128_ps(mask)); }}",
|
||||
inst.rs, inst.rt,
|
||||
(dest_mask & 0x8) ? -1 : 0, (dest_mask & 0x4) ? -1 : 0,
|
||||
(dest_mask & 0x2) ? -1 : 0, (dest_mask & 0x1) ? -1 : 0,
|
||||
inst.rd, inst.rd);
|
||||
}
|
||||
|
||||
std::string CodeGenerator::translateVU_VRGET(const Instruction &inst)
|
||||
{
|
||||
uint8_t dest_mask = inst.vectorInfo.vectorField;
|
||||
|
||||
Reference in New Issue
Block a user