mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-09-26 08:51:05 -04:00
Feature/runtime review codegen fixes (#87)
* feat: small fixes on code gen * feat: added code gen test * feat: rename IOP * fix: fix special case on JR feat: added code generator test * feat: ps2 logs now need special macros * feat: a lot of regressions test feat: use test to fix bugs on runtime fix: fix incorrect instructions on code generator feat: added missing decode on r5900 decoder feat: added scissor on rasterizer * feat: better ghidra plugin analyzer fix: fix real bug on function finding on elf analyzer * feat: some logs on GS feat: added more syscalls stubs feat: added more ps2 stubs * feat: added missing stub
This commit is contained in:
Ranieri
@@ -112,6 +112,46 @@ void register_code_generator_tests()
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{
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MiniTest::Case("CodeGenerator", [](TestCase &tc)
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{
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tc.Run("R5900 MULT writes rd when rd is non-zero", [](TestCase &t) {
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CodeGenerator gen({}, {});
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Instruction mult{};
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mult.opcode = OPCODE_SPECIAL;
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mult.function = SPECIAL_MULT;
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mult.rs = 4;
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mult.rt = 5;
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mult.rd = 3;
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std::string generated = gen.translateInstruction(mult);
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printGeneratedCode("R5900 MULT writes rd when rd is non-zero", generated);
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t.IsTrue(generated.find("SET_GPR_S32(ctx, 3, (int32_t)result);") != std::string::npos,
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"MULT should write low product to rd on R5900");
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mult.rd = 0;
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generated = gen.translateInstruction(mult);
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t.IsTrue(generated.find("SET_GPR_S32(") == std::string::npos,
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"MULT should not write rd when rd is zero");
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});
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tc.Run("R5900 MMI MULT1 writes rd when rd is non-zero", [](TestCase &t) {
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CodeGenerator gen({}, {});
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Instruction mult1{};
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mult1.opcode = OPCODE_MMI;
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mult1.isMMI = true;
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mult1.function = MMI_MULT1;
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mult1.rs = 8;
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mult1.rt = 9;
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mult1.rd = 10;
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std::string generated = gen.translateInstruction(mult1);
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printGeneratedCode("R5900 MMI MULT1 writes rd when rd is non-zero", generated);
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t.IsTrue(generated.find("SET_GPR_S32(ctx, 10, (int32_t)result);") != std::string::npos,
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"MULT1 should write low product to rd on R5900");
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});
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tc.Run("emits labels and gotos for internal branches", [](TestCase &t) {
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Function func;
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func.name = "test_func";
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@@ -393,6 +433,158 @@ void register_code_generator_tests()
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t.IsTrue(ctc2Code.find("Unimplemented CTC2 VU CReg") == std::string::npos, "CTC2 should not hit unimplemented CReg path");
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});
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tc.Run("scalar logical immediates emit low64 operations", [](TestCase &t) {
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CodeGenerator gen({}, {});
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Instruction andi{};
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andi.opcode = OPCODE_ANDI;
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andi.rs = 4;
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andi.rt = 5;
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andi.immediate = 0xABCD;
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std::string andiCode = gen.translateInstruction(andi);
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t.IsTrue(andiCode.find("SET_GPR_U64(ctx, 5, GPR_U64(ctx, 4) & (uint64_t)(uint16_t)43981);") != std::string::npos,
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"ANDI should use low64 scalar emission");
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t.IsTrue(andiCode.find("SET_GPR_VEC") == std::string::npos,
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"ANDI should not use vector emission");
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Instruction ori{};
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ori.opcode = OPCODE_ORI;
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ori.rs = 6;
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ori.rt = 7;
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ori.immediate = 0x1234;
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std::string oriCode = gen.translateInstruction(ori);
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t.IsTrue(oriCode.find("SET_GPR_U64(ctx, 7, GPR_U64(ctx, 6) | (uint64_t)(uint16_t)4660);") != std::string::npos,
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"ORI should use low64 scalar emission");
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t.IsTrue(oriCode.find("SET_GPR_VEC") == std::string::npos,
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"ORI should not use vector emission");
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Instruction xori{};
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xori.opcode = OPCODE_XORI;
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xori.rs = 8;
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xori.rt = 9;
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xori.immediate = 0x00FF;
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std::string xoriCode = gen.translateInstruction(xori);
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t.IsTrue(xoriCode.find("SET_GPR_U64(ctx, 9, GPR_U64(ctx, 8) ^ (uint64_t)(uint16_t)255);") != std::string::npos,
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"XORI should use low64 scalar emission");
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t.IsTrue(xoriCode.find("SET_GPR_VEC") == std::string::npos,
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"XORI should not use vector emission");
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});
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tc.Run("scalar logical register ops emit low64 operations", [](TestCase &t) {
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CodeGenerator gen({}, {});
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Instruction andInst{};
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andInst.opcode = OPCODE_SPECIAL;
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andInst.function = SPECIAL_AND;
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andInst.rs = 2;
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andInst.rt = 3;
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andInst.rd = 1;
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std::string andCode = gen.translateInstruction(andInst);
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t.IsTrue(andCode.find("SET_GPR_U64(ctx, 1, GPR_U64(ctx, 2) & GPR_U64(ctx, 3));") != std::string::npos,
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"AND should use low64 scalar emission");
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Instruction orInst{};
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orInst.opcode = OPCODE_SPECIAL;
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orInst.function = SPECIAL_OR;
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orInst.rs = 4;
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orInst.rt = 5;
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orInst.rd = 6;
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std::string orCode = gen.translateInstruction(orInst);
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t.IsTrue(orCode.find("SET_GPR_U64(ctx, 6, GPR_U64(ctx, 4) | GPR_U64(ctx, 5));") != std::string::npos,
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"OR should use low64 scalar emission");
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Instruction xorInst{};
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xorInst.opcode = OPCODE_SPECIAL;
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xorInst.function = SPECIAL_XOR;
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xorInst.rs = 7;
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xorInst.rt = 8;
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xorInst.rd = 9;
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std::string xorCode = gen.translateInstruction(xorInst);
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t.IsTrue(xorCode.find("SET_GPR_U64(ctx, 9, GPR_U64(ctx, 7) ^ GPR_U64(ctx, 8));") != std::string::npos,
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"XOR should use low64 scalar emission");
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Instruction norInst{};
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norInst.opcode = OPCODE_SPECIAL;
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norInst.function = SPECIAL_NOR;
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norInst.rs = 10;
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norInst.rt = 11;
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norInst.rd = 12;
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std::string norCode = gen.translateInstruction(norInst);
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t.IsTrue(norCode.find("SET_GPR_U64(ctx, 12, ~(GPR_U64(ctx, 10) | GPR_U64(ctx, 11)));") != std::string::npos,
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"NOR should use low64 scalar emission");
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t.IsTrue(norCode.find("SET_GPR_VEC") == std::string::npos,
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"SPECIAL logical ops should not use vector emission");
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});
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tc.Run("SC requires matching LL reservation address", [](TestCase &t) {
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CodeGenerator gen({}, {});
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Instruction sc{};
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sc.opcode = OPCODE_SC;
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sc.rs = 9;
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sc.rt = 10;
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sc.simmediate = static_cast<uint32_t>(static_cast<int16_t>(4));
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std::string out = gen.translateInstruction(sc);
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t.IsTrue(out.find("ctx->llbit && ctx->lladdr == addr") != std::string::npos,
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"SC must require both llbit and matching lladdr");
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t.IsTrue(out.find("ctx->llbit = 0; ctx->lladdr = 0;") != std::string::npos,
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"SC must clear reservation state after attempting the store");
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});
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tc.Run("QFSRV translation uses runtime helper macro", [](TestCase &t) {
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CodeGenerator gen({}, {});
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Instruction qfsrv{};
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qfsrv.isMMI = true;
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qfsrv.opcode = OPCODE_MMI;
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qfsrv.function = MMI_MMI1;
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qfsrv.sa = MMI1_QFSRV;
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qfsrv.rd = 3;
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qfsrv.rs = 4;
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qfsrv.rt = 5;
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std::string out = gen.translateInstruction(qfsrv);
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t.IsTrue(out.find("PS2_QFSRV(GPR_VEC(ctx, 4), GPR_VEC(ctx, 5), ctx->sa & 0x7F)") != std::string::npos,
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"QFSRV should map to PS2_QFSRV with rs/rt ordering");
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});
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tc.Run("PCPYLD and PEXEW use runtime helper macros", [](TestCase &t) {
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CodeGenerator gen({}, {});
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Instruction pcpyld{};
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pcpyld.isMMI = true;
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pcpyld.opcode = OPCODE_MMI;
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pcpyld.function = MMI_MMI2;
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pcpyld.sa = MMI2_PCPYLD;
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pcpyld.rd = 6;
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pcpyld.rs = 7;
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pcpyld.rt = 8;
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std::string pcpyldOut = gen.translateInstruction(pcpyld);
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t.IsTrue(pcpyldOut.find("PS2_PCPYLD(GPR_VEC(ctx, 7), GPR_VEC(ctx, 8))") != std::string::npos,
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"PCPYLD should use PS2_PCPYLD helper");
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Instruction pexew{};
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pexew.isMMI = true;
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pexew.opcode = OPCODE_MMI;
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pexew.function = MMI_MMI2;
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pexew.sa = MMI2_PEXEW;
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pexew.rd = 9;
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pexew.rs = 10;
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std::string pexewOut = gen.translateInstruction(pexew);
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t.IsTrue(pexewOut.find("PS2_PEXEW(GPR_VEC(ctx, 10))") != std::string::npos,
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"PEXEW should use PS2_PEXEW helper");
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});
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tc.Run("VU0 macro mappings cover all S1/S2 enums", [](TestCase &t) {
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const std::vector<std::string> candidates = {
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"ps2xRecomp/include/ps2recomp/instructions.h",
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@@ -737,6 +929,82 @@ void register_code_generator_tests()
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"switch should include other in-function labels");
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});
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tc.Run("configured jump table addresses drive JR dispatch targets", [](TestCase &t) {
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Function func;
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func.name = "jr_configured_jump_table";
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func.start = 0x1600;
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func.end = 0x1640;
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func.isRecompiled = true;
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func.isStub = false;
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constexpr uint32_t tableAddress = 0x00200000u;
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Instruction lui{};
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lui.address = 0x1600;
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lui.opcode = OPCODE_LUI;
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lui.rt = 9;
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lui.immediate = static_cast<uint16_t>((tableAddress >> 16) & 0xFFFFu);
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Instruction addiu{};
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addiu.address = 0x1604;
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addiu.opcode = OPCODE_ADDIU;
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addiu.rs = 9;
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addiu.rt = 9;
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addiu.immediate = static_cast<uint16_t>(tableAddress & 0xFFFFu);
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addiu.simmediate = addiu.immediate;
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Instruction sll{};
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sll.address = 0x1608;
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sll.opcode = OPCODE_SPECIAL;
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sll.function = SPECIAL_SLL;
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sll.rd = 8;
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sll.rt = 4;
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sll.sa = 2;
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Instruction addu{};
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addu.address = 0x160C;
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addu.opcode = OPCODE_SPECIAL;
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addu.function = SPECIAL_ADDU;
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addu.rs = 9;
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addu.rt = 8;
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addu.rd = 9;
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Instruction lw{};
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lw.address = 0x1610;
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lw.opcode = OPCODE_LW;
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lw.rs = 9;
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lw.rt = 10;
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lw.immediate = 0;
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lw.simmediate = 0;
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Instruction jr = makeJr(0x1614, 10);
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Instruction jrDelay = makeNop(0x1618);
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Instruction target0 = makeNop(0x1620);
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Instruction target1 = makeNop(0x1630);
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JumpTable configured{};
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configured.address = tableAddress;
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configured.entries.push_back({0u, 0x1620u});
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configured.entries.push_back({1u, 0x1630u});
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CodeGenerator gen({}, {});
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gen.setConfiguredJumpTables({configured});
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std::string generated = gen.generateFunction(
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func,
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{lui, addiu, sll, addu, lw, jr, jrDelay, target0, target1},
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false);
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printGeneratedCode("configured jump table addresses drive JR dispatch targets", generated);
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t.IsTrue(generated.find("switch (jumpTarget)") != std::string::npos,
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"JR should emit a switch");
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t.IsTrue(generated.find("case 0x1620u: goto label_1620;") != std::string::npos,
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"configured table target 0x1620 should be emitted");
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t.IsTrue(generated.find("case 0x1630u: goto label_1630;") != std::string::npos,
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"configured table target 0x1630 should be emitted");
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t.IsTrue(generated.find("case 0x1600u: goto label_1600;") == std::string::npos,
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"configured table should avoid broad JR fallback labels");
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});
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tc.Run("JALR includes switch and fallback/guard pair", [](TestCase &t) {
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Function func;
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func.name = "jalr_switch_and_fallback";
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@@ -767,6 +1035,71 @@ void register_code_generator_tests()
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"JALR should retain non-fallthrough guard");
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});
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tc.Run("JALR fallback should not expose epilogue tail-jump labels", [](TestCase &t) {
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Function func;
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func.name = "jalr_epilogue_guard";
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func.start = 0x2000;
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func.end = 0x2030;
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func.isRecompiled = true;
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func.isStub = false;
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Instruction prolog{};
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prolog.address = 0x2000;
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prolog.opcode = OPCODE_ADDIU;
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prolog.rs = 29;
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prolog.rt = 29;
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prolog.simmediate = static_cast<uint32_t>(static_cast<int32_t>(-0x20));
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prolog.raw = 0;
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Instruction saveRa{};
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saveRa.address = 0x2004;
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saveRa.opcode = OPCODE_SD;
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saveRa.rs = 29;
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saveRa.rt = 31;
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saveRa.simmediate = 0x10;
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saveRa.raw = 0;
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// Dynamic callback entry point.
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Instruction jalr = makeJalr(0x2008, 2, 31);
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Instruction jalrDelay = makeNop(0x200C);
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Instruction restoreRa{};
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restoreRa.address = 0x2010;
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restoreRa.opcode = OPCODE_LD;
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restoreRa.rs = 29;
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restoreRa.rt = 31;
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restoreRa.simmediate = 0x10;
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restoreRa.raw = 0;
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// Tail jump sequence that must not be reachable from jalr fallback dispatch.
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Instruction tailJump{};
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tailJump.address = 0x2014;
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tailJump.opcode = OPCODE_J;
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tailJump.target = (0x3000u >> 2) & 0x3FFFFFFu;
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tailJump.hasDelaySlot = true;
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tailJump.raw = 0;
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Instruction tailDelay{};
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tailDelay.address = 0x2018;
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tailDelay.opcode = OPCODE_ADDIU;
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tailDelay.rs = 29;
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tailDelay.rt = 29;
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tailDelay.simmediate = 0x20;
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tailDelay.raw = 0;
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CodeGenerator gen({}, {});
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std::string generated = gen.generateFunction(
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func,
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{prolog, saveRa, jalr, jalrDelay, restoreRa, tailJump, tailDelay},
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false);
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printGeneratedCode("JALR fallback should not expose epilogue tail-jump labels", generated);
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t.IsTrue(generated.find("case 0x2014u: goto label_2014;") == std::string::npos,
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"jalr fallback should not dispatch directly to epilogue tail-jump block");
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t.IsTrue(generated.find("case 0x2018u: goto label_2018;") == std::string::npos,
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"jalr fallback should not dispatch directly to tail-jump delay slot");
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});
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tc.Run("resolveStubTarget allows leading underscore alias", [](TestCase &t) {
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t.Equals(PS2Recompiler::resolveStubTarget("_rand"), StubTarget::Stub,
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"_rand should resolve via rand stub alias");
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