mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-10-02 10:46:18 -04:00
refactor: from guest threads to EE scheduler
This commit is contained in:
Ran-j
@@ -1,8 +1,7 @@
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#include "MiniTest.h"
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#include "ps2_runtime.h"
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#include "ps2_syscalls.h"
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#include "Stubs/DMA.h"
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#include "runtime/ps2_gs_gpu.h"
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#include "runtime/ee_scheduler.h"
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#include <atomic>
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#include <chrono>
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@@ -46,12 +45,32 @@ namespace
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}
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};
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std::atomic<uint32_t> g_vblankStartHits{0u};
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std::atomic<uint32_t> g_vblankEndHits{0u};
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std::atomic<uint32_t> g_lastIntcArg{0u};
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std::atomic<uint32_t> g_dmacSendHits{0u};
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std::atomic<uint32_t> g_dmacSendLastCause{0u};
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std::atomic<uint32_t> g_dmacSendLastChcr{0u};
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constexpr uint32_t kIdleVSyncWaitPc = 0x00160000u;
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constexpr uint32_t kVSyncWaitPc = 0x00160100u;
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constexpr uint32_t kVSyncResumePc = 0x00160110u;
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constexpr uint32_t kIrqWaitPc = 0x00160200u;
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constexpr uint32_t kIrqResumePc = 0x00160210u;
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constexpr uint32_t kIntcHandlerPc = 0x00160220u;
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constexpr uint32_t kISemaWaitPc = 0x00160300u;
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constexpr uint32_t kISemaResumePc = 0x00160310u;
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constexpr uint32_t kISemaDriverPc = 0x00160320u;
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constexpr uint32_t kISemaHandlerPc = 0x00160330u;
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constexpr uint32_t kEventWaitPc = 0x00160400u;
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constexpr uint32_t kEventResumePc = 0x00160410u;
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constexpr uint32_t kEventProducerPc = 0x00160420u;
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constexpr uint32_t kVSyncFlagAddr = 0x1800u;
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constexpr uint32_t kVSyncTickAddr = 0x1810u;
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constexpr uint32_t kEventResultAddr = 0x1820u;
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std::vector<int> g_dispatchTrace;
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int g_testSemaphoreId = 0;
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int g_testEventFlagId = 0;
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int32_t g_resumedResult = 0;
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uint32_t g_vsyncFlag = 0;
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uint64_t g_vsyncTick = 0;
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uint64_t g_vsyncCsr = 0;
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void setRegU32(R5900Context &ctx, int reg, uint32_t value)
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{
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@@ -73,25 +92,6 @@ namespace
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std::memcpy(rdram + addr, &value, sizeof(value));
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}
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void writeGuestU64(uint8_t *rdram, uint32_t addr, uint64_t value)
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{
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std::memcpy(rdram + addr, &value, sizeof(value));
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}
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uint64_t makeDmaTag(uint16_t qwc, uint8_t id, uint32_t addr, bool irq = false)
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{
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return static_cast<uint64_t>(qwc) |
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(static_cast<uint64_t>(id & 0x7u) << 28) |
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(irq ? (1ull << 31) : 0ull) |
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(static_cast<uint64_t>(addr & 0x7FFFFFFFu) << 32);
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}
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void writeDmaTag(uint8_t *rdram, uint32_t tagAddr, uint64_t tagLo)
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{
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std::memset(rdram + tagAddr, 0, 16);
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std::memcpy(rdram + tagAddr, &tagLo, sizeof(tagLo));
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}
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uint32_t readGuestU32(const uint8_t *rdram, uint32_t addr)
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{
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uint32_t value = 0;
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@@ -124,58 +124,128 @@ namespace
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void cleanupRuntime(TestEnv &env)
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{
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env.runtime.requestStop();
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notifyRuntimeStop();
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}
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void testIntcHandler(uint8_t *rdram, R5900Context *ctx, PS2Runtime *runtime)
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void idleVSyncWait(uint8_t *rdram, R5900Context *ctx, PS2Runtime *runtime)
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{
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(void)rdram;
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(void)runtime;
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WaitVSyncTick(rdram, ctx, runtime, -1);
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}
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const uint32_t cause = getRegU32(ctx, 4);
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const uint32_t arg = getRegU32(ctx, 5);
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g_lastIntcArg.store(arg, std::memory_order_relaxed);
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void schedulerVSyncWait(uint8_t *, R5900Context *ctx, PS2Runtime *runtime)
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{
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EeScheduler &scheduler = runtime->eeScheduler();
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scheduler.setVSyncFlag(kVSyncFlagAddr, kVSyncTickAddr);
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ctx->pc = kVSyncResumePc;
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scheduler.waitVSync(scheduler.currentVSyncTick());
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}
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if (cause == 2u)
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{
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g_vblankStartHits.fetch_add(1u, std::memory_order_relaxed);
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}
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else if (cause == 3u)
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{
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g_vblankEndHits.fetch_add(1u, std::memory_order_relaxed);
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}
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void schedulerVSyncResume(uint8_t *rdram, R5900Context *ctx, PS2Runtime *runtime)
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{
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g_vsyncFlag = readGuestU32(rdram, kVSyncFlagAddr);
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g_vsyncTick = readGuestU64(rdram, kVSyncTickAddr);
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g_vsyncCsr = runtime->memory().gs().csr.load(std::memory_order_acquire);
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g_resumedResult = getRegS32(*ctx, 2);
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ctx->pc = 0u;
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runtime->requestStop();
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}
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void schedulerIntcHandler(uint8_t *, R5900Context *ctx, PS2Runtime *)
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{
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g_dispatchTrace.push_back(2);
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g_lastIntcArg.store(getRegU32(ctx, 5), std::memory_order_relaxed);
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ctx->pc = 0u;
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}
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void testDmacSendHandler(uint8_t *rdram, R5900Context *ctx, PS2Runtime *runtime)
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void schedulerIrqWait(uint8_t *, R5900Context *ctx, PS2Runtime *runtime)
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{
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(void)rdram;
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const uint32_t cause = getRegU32(ctx, 4);
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g_dmacSendHits.fetch_add(1u, std::memory_order_relaxed);
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g_dmacSendLastCause.store(cause, std::memory_order_relaxed);
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uint32_t channelBase = 0u;
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if (cause == 0u)
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{
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channelBase = 0x10008000u;
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}
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else if (cause == 1u)
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{
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channelBase = 0x10009000u;
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}
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else if (cause == 2u)
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{
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channelBase = 0x1000A000u;
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}
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if (runtime && channelBase != 0u)
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{
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g_dmacSendLastChcr.store(runtime->memory().readIORegister(channelBase + 0x00u), std::memory_order_relaxed);
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}
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g_dispatchTrace.push_back(1);
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EeScheduler &scheduler = runtime->eeScheduler();
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scheduler.addIrqHandler(false, 2u, kIntcHandlerPc, true, 0xCAFEu, 0u, 0u);
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ctx->pc = kIrqResumePc;
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scheduler.waitVSync(scheduler.currentVSyncTick());
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}
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void schedulerIrqResume(uint8_t *, R5900Context *ctx, PS2Runtime *runtime)
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{
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g_dispatchTrace.push_back(3);
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ctx->pc = 0u;
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runtime->requestStop();
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}
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void schedulerISemaHandler(uint8_t *, R5900Context *ctx, PS2Runtime *runtime)
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{
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g_dispatchTrace.push_back(3);
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runtime->eeScheduler().signalSemaphore(g_testSemaphoreId, true);
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g_dispatchTrace.push_back(4);
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ctx->pc = 0u;
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}
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void schedulerISemaDriver(uint8_t *, R5900Context *ctx, PS2Runtime *runtime)
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{
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g_dispatchTrace.push_back(2);
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ctx->pc = 0u;
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runtime->eeScheduler().dispatchIrq(true, 5u);
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}
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void schedulerISemaWait(uint8_t *, R5900Context *ctx, PS2Runtime *runtime)
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{
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g_dispatchTrace.push_back(1);
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EeScheduler &scheduler = runtime->eeScheduler();
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g_testSemaphoreId = scheduler.createSemaphore(0, 1, 0u, 0u);
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scheduler.addIrqHandler(true, 5u, kISemaHandlerPc, true, 0u, 0u, 0u);
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EeThreadCreateParams driver{};
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driver.entry = kISemaDriverPc;
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driver.stack = 0x1C000u;
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driver.stackSize = 0x1000u;
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driver.priority = 10;
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const int driverId = scheduler.createThread(driver);
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scheduler.startThread(driverId, 0u, *ctx, false);
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ctx->pc = kISemaResumePc;
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scheduler.waitSemaphore(g_testSemaphoreId);
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}
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void schedulerISemaResume(uint8_t *, R5900Context *ctx, PS2Runtime *runtime)
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{
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g_dispatchTrace.push_back(5);
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g_resumedResult = getRegS32(*ctx, 2);
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ctx->pc = 0u;
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runtime->requestStop();
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}
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void schedulerEventProducer(uint8_t *, R5900Context *ctx, PS2Runtime *runtime)
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{
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g_dispatchTrace.push_back(2);
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ctx->pc = 0u;
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runtime->eeScheduler().setEventFlag(g_testEventFlagId, 0x6u, false);
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runtime->eeScheduler().transferIfRequested(false);
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}
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void schedulerEventWait(uint8_t *, R5900Context *ctx, PS2Runtime *runtime)
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{
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g_dispatchTrace.push_back(1);
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EeScheduler &scheduler = runtime->eeScheduler();
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g_testEventFlagId = scheduler.createEventFlag(0u, 0u, 0u);
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EeThreadCreateParams producer{};
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producer.entry = kEventProducerPc;
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producer.stack = 0x1D000u;
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producer.stackSize = 0x1000u;
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producer.priority = 10;
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const int producerId = scheduler.createThread(producer);
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scheduler.startThread(producerId, 0u, *ctx, false);
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ctx->pc = kEventResumePc;
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scheduler.waitEventFlag(g_testEventFlagId, 0x2u, WEF_OR | WEF_CLEAR, kEventResultAddr);
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}
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void schedulerEventResume(uint8_t *, R5900Context *ctx, PS2Runtime *runtime)
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{
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g_dispatchTrace.push_back(3);
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g_resumedResult = getRegS32(*ctx, 2);
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ctx->pc = 0u;
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runtime->requestStop();
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}
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}
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@@ -183,443 +253,8 @@ void register_ps2_runtime_interrupt_tests()
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{
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MiniTest::Case("PS2RuntimeInterrupt", [](TestCase &tc)
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{
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tc.Run("SetVSyncFlag arms a one-shot vblank notification", [](TestCase &t)
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{
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notifyRuntimeStop();
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TestEnv env;
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constexpr uint32_t kFlagAddr = 0x1000u;
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constexpr uint32_t kTickAddr = 0x1010u;
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writeGuestU32(env.rdram.data(), kFlagAddr, 0xDEADBEEFu);
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writeGuestU32(env.rdram.data(), kTickAddr + 0u, 0xAAAAAAAAu);
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writeGuestU32(env.rdram.data(), kTickAddr + 4u, 0xBBBBBBBBu);
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R5900Context ctx{};
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setRegU32(ctx, 4, kFlagAddr);
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setRegU32(ctx, 5, kTickAddr);
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t.IsTrue(callSyscall(0x73u, env.rdram.data(), &ctx, &env.runtime), "SetVSyncFlag syscall should dispatch");
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t.Equals(getRegS32(ctx, 2), KE_OK, "SetVSyncFlag should return KE_OK");
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t.Equals(readGuestU32(env.rdram.data(), kFlagAddr), 0u, "SetVSyncFlag should reset flag to zero");
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t.Equals(readGuestU64(env.rdram.data(), kTickAddr), 0ull, "SetVSyncFlag should reset tick counter to zero");
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const bool firstTickSeen = waitUntil([&]() {
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return readGuestU64(env.rdram.data(), kTickAddr) > 0u;
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}, std::chrono::milliseconds(300));
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t.IsTrue(firstTickSeen, "VSync worker should update tick value");
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const uint64_t firstTick = readGuestU64(env.rdram.data(), kTickAddr);
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t.IsTrue(firstTick > 0u, "First observed VSync tick should be positive");
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t.Equals(readGuestU32(env.rdram.data(), kFlagAddr), 1u, "VSync worker should set flag to one");
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const bool tickRewritten = waitUntil([&]() {
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return readGuestU64(env.rdram.data(), kTickAddr) != firstTick;
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}, std::chrono::milliseconds(100));
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t.IsTrue(!tickRewritten, "consumed registration should not be written again");
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// Re-arming registers a fresh one-shot notification.
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writeGuestU32(env.rdram.data(), kFlagAddr, 0u);
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R5900Context rearmCtx{};
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setRegU32(rearmCtx, 4, kFlagAddr);
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setRegU32(rearmCtx, 5, kTickAddr);
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t.IsTrue(callSyscall(0x73u, env.rdram.data(), &rearmCtx, &env.runtime), "SetVSyncFlag re-arm should dispatch");
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const bool rearmedTickSeen = waitUntil([&]() {
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return readGuestU64(env.rdram.data(), kTickAddr) > firstTick;
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}, std::chrono::milliseconds(300));
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t.IsTrue(rearmedTickSeen, "re-armed registration should observe a later tick");
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t.Equals(readGuestU32(env.rdram.data(), kFlagAddr), 1u, "re-armed registration should set flag to one");
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cleanupRuntime(env);
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});
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tc.Run("VSync worker updates GS CSR FIELD bit for MMIO polling loops", [](TestCase &t)
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{
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notifyRuntimeStop();
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TestEnv env;
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t.IsTrue(env.runtime.memory().initialize(), "runtime memory initialize should succeed");
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constexpr uint32_t kFlagAddr = 0x1080u;
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constexpr uint32_t kTickAddr = 0x1090u;
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constexpr uint64_t kGsCsrFieldMask = 0x2000ull;
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env.runtime.memory().gs().csr = 0x3ull;
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R5900Context ctx{};
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setRegU32(ctx, 4, kFlagAddr);
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setRegU32(ctx, 5, kTickAddr);
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t.IsTrue(callSyscall(0x73u, env.rdram.data(), &ctx, &env.runtime), "SetVSyncFlag syscall should dispatch");
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const uint64_t initialField = env.runtime.memory().gs().csr & kGsCsrFieldMask;
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const bool firstFieldFlip = waitUntil([&]() {
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return (env.runtime.memory().gs().csr & kGsCsrFieldMask) != initialField;
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}, std::chrono::milliseconds(300));
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t.IsTrue(firstFieldFlip, "VSync worker should toggle GS CSR FIELD for direct CSR polling");
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t.Equals(env.runtime.memory().gs().csr & 0x3ull, 0x3ull, "VSync FIELD update should preserve CSR status bits");
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const uint64_t fieldAfterFirstFlip = env.runtime.memory().gs().csr & kGsCsrFieldMask;
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const bool secondFieldFlip = waitUntil([&]() {
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return (env.runtime.memory().gs().csr & kGsCsrFieldMask) != fieldAfterFirstFlip;
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}, std::chrono::milliseconds(300));
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t.IsTrue(secondFieldFlip, "VSync worker should keep alternating GS CSR FIELD");
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cleanupRuntime(env);
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});
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// Regression test for the GS CSR data race: a two-writer word-level
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// lost-update guard. Pre-fix, every CSR update was a plain (non-atomic)
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// 64-bit load-modify-store of the WHOLE word, so two threads that own
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// logically disjoint bits could still clobber each other: thread A's
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// read-modify-write of the word can overwrite thread B's bit with the
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// stale value A loaded before B's update landed.
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//
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// Two racer threads with disjoint bit ownership run concurrently:
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// - racer A owns SIGNAL (bit 0): sets it via the GIF register path
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// (GS_REG_SIGNAL) then W1C-clears ONLY bit 0 via the MMIO write path;
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// - racer B owns FINISH (bit 1): same protocol with GS_REG_FINISH and
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// a W1C write of only bit 1.
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// Each racer checks only its own bit after each half-op. With the fix
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// (std::atomic CSR, every update a single atomic RMW) each racer is the
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// sole writer of its bit, so its bit deterministically reflects its own
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// last operation: zero anomalies are possible. Pre-fix, the racers'
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// whole-word W1C RMWs constantly interleave and lose each other's
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// set/clear, lighting up the anomaly counters.
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//
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// Why racer-vs-racer instead of racer-vs-vsync: the vsync worker (which
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// motivated the fix) writes CSR only once per ~16.7ms tick, a window far
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// too narrow to hit deterministically in a bounded test. The corrupting
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// mechanism -- a non-atomic whole-word RMW clobbering a concurrently
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// written disjoint bit -- is identical, so guarding it with two
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// high-frequency writers also guards the vsync FIELD interleaving. The
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// real vsync worker still runs throughout (started via the same
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// SetVSyncFlag syscall production uses) and its FIELD (bit 13) toggling
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// is asserted when at least two ticks were observed.
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tc.Run("Disjoint-bit GS CSR writers (SIGNAL vs FINISH vs vsync FIELD) never lose word-level updates", [](TestCase &t)
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{
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notifyRuntimeStop();
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TestEnv env;
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t.IsTrue(env.runtime.memory().initialize(), "runtime memory initialize should succeed");
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constexpr uint32_t kFlagAddr = 0x1180u;
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constexpr uint32_t kTickAddr = 0x1190u;
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constexpr uint64_t kGsCsrFieldMask = 0x2000ull;
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constexpr uint32_t kCsrAddr = PS2_GS_PRIV_REG_BASE + 0x1000u;
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constexpr uint32_t kIterations = 80000u;
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GS gs;
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gs.init(env.runtime.memory().getGSVRAM(), static_cast<uint32_t>(PS2_GS_VRAM_SIZE),
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&env.runtime.memory().gs());
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// Drive the real vsync worker via the same syscall path production
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// code uses; it runs on its own thread and toggles CSR.FIELD once
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// per tick via updateGsCsrFieldForVSync.
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R5900Context ctx{};
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setRegU32(ctx, 4, kFlagAddr);
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setRegU32(ctx, 5, kTickAddr);
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t.IsTrue(callSyscall(0x73u, env.rdram.data(), &ctx, &env.runtime), "SetVSyncFlag syscall should dispatch");
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const uint64_t tickBefore = GetCurrentVSyncTick();
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std::atomic<uint32_t> setAnomaliesA{0u}, clearAnomaliesA{0u};
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std::atomic<uint32_t> setAnomaliesB{0u}, clearAnomaliesB{0u};
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std::atomic<uint32_t> racersDone{0u};
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// ownBit: the single CSR status bit this racer exclusively owns.
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// Each iteration: raise the bit via the GIF register-write path,
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// verify it reads back set, W1C-clear only that bit via the guest
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// MMIO path, verify it reads back clear. The other racer and the
|
||||
// vsync worker never touch this bit, so under atomic RMWs both
|
||||
// checks are exact -- any anomaly is a lost word-level update.
|
||||
auto racerBody = [&](uint8_t gifReg, uint64_t gifValue, uint64_t ownBit,
|
||||
std::atomic<uint32_t> &setAnomalies, std::atomic<uint32_t> &clearAnomalies) {
|
||||
for (uint32_t i = 0; i < kIterations; ++i)
|
||||
{
|
||||
gs.writeRegister(gifReg, gifValue);
|
||||
if ((env.runtime.memory().gs().csr.load() & ownBit) == 0ull)
|
||||
{
|
||||
setAnomalies.fetch_add(1u, std::memory_order_relaxed);
|
||||
}
|
||||
|
||||
env.runtime.memory().write64(kCsrAddr, ownBit);
|
||||
if ((env.runtime.memory().gs().csr.load() & ownBit) != 0ull)
|
||||
{
|
||||
clearAnomalies.fetch_add(1u, std::memory_order_relaxed);
|
||||
}
|
||||
}
|
||||
racersDone.fetch_add(1u, std::memory_order_relaxed);
|
||||
};
|
||||
|
||||
const uint64_t signalValue = (0xFFFFFFFFull << 32) | 0x11223344ull;
|
||||
std::thread racerA(racerBody, GS_REG_SIGNAL, signalValue, 0x1ull,
|
||||
std::ref(setAnomaliesA), std::ref(clearAnomaliesA));
|
||||
std::thread racerB(racerBody, GS_REG_FINISH, 0ull, 0x2ull,
|
||||
std::ref(setAnomaliesB), std::ref(clearAnomaliesB));
|
||||
|
||||
// While the racers hammer bits 0..1, watch for CSR.FIELD (bit 13)
|
||||
// flips from the vsync worker. Polling ends when both racers finish,
|
||||
// so this adds no fixed wall-clock cost.
|
||||
const uint64_t initialField = env.runtime.memory().gs().csr.load() & kGsCsrFieldMask;
|
||||
bool fieldFlipped = false;
|
||||
while (racersDone.load(std::memory_order_relaxed) < 2u)
|
||||
{
|
||||
if ((env.runtime.memory().gs().csr.load() & kGsCsrFieldMask) != initialField)
|
||||
{
|
||||
fieldFlipped = true;
|
||||
}
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(1));
|
||||
}
|
||||
|
||||
racerA.join();
|
||||
racerB.join();
|
||||
const uint64_t ticksElapsed = GetCurrentVSyncTick() - tickBefore;
|
||||
|
||||
t.Equals(setAnomaliesA.load(), 0u, "racer A: SIGNAL set must never be lost to a concurrent whole-word CSR RMW");
|
||||
t.Equals(clearAnomaliesA.load(), 0u, "racer A: SIGNAL W1C-clear must never be lost to a concurrent whole-word CSR RMW");
|
||||
t.Equals(setAnomaliesB.load(), 0u, "racer B: FINISH set must never be lost to a concurrent whole-word CSR RMW");
|
||||
t.Equals(clearAnomaliesB.load(), 0u, "racer B: FINISH W1C-clear must never be lost to a concurrent whole-word CSR RMW");
|
||||
t.Equals(env.runtime.memory().gs().csr.load() & 0x3ull, 0x0ull,
|
||||
"final CSR status bits must match both racers' ledgers (last op on each bit was a clear)");
|
||||
if (ticksElapsed >= 2u)
|
||||
{
|
||||
t.IsTrue(fieldFlipped, "VSync worker should toggle GS CSR FIELD while the racers run");
|
||||
}
|
||||
|
||||
cleanupRuntime(env);
|
||||
});
|
||||
|
||||
tc.Run("INTC VBLANK handlers respect EnableIntc and DisableIntc masks", [](TestCase &t)
|
||||
{
|
||||
notifyRuntimeStop();
|
||||
TestEnv env;
|
||||
|
||||
g_vblankStartHits.store(0u, std::memory_order_relaxed);
|
||||
g_vblankEndHits.store(0u, std::memory_order_relaxed);
|
||||
g_lastIntcArg.store(0u, std::memory_order_relaxed);
|
||||
|
||||
constexpr uint32_t kFlagAddr = 0x1100u;
|
||||
constexpr uint32_t kTickAddr = 0x1110u;
|
||||
constexpr uint32_t kHandlerAddr = 0x00ABC100u;
|
||||
|
||||
env.runtime.registerFunction(kHandlerAddr, &testIntcHandler);
|
||||
|
||||
R5900Context addStart{};
|
||||
setRegU32(addStart, 4, 2u); // VBLANK start
|
||||
setRegU32(addStart, 5, kHandlerAddr);
|
||||
setRegU32(addStart, 6, 0u);
|
||||
setRegU32(addStart, 7, 0xCAFE0002u);
|
||||
setRegU32(addStart, 28, 0x12340000u);
|
||||
setRegU32(addStart, 29, 0x001FFFE0u);
|
||||
t.IsTrue(callSyscall(0x10u, env.rdram.data(), &addStart, &env.runtime), "AddIntcHandler syscall should dispatch");
|
||||
t.IsTrue(getRegS32(addStart, 2) > 0, "AddIntcHandler for cause 2 should return handler id");
|
||||
|
||||
R5900Context addEnd{};
|
||||
setRegU32(addEnd, 4, 3u); // VBLANK end
|
||||
setRegU32(addEnd, 5, kHandlerAddr);
|
||||
setRegU32(addEnd, 6, 0u);
|
||||
setRegU32(addEnd, 7, 0xCAFE0003u);
|
||||
setRegU32(addEnd, 28, 0x12340000u);
|
||||
setRegU32(addEnd, 29, 0x001FFFE0u);
|
||||
t.IsTrue(callSyscall(0x10u, env.rdram.data(), &addEnd, &env.runtime), "AddIntcHandler syscall should dispatch");
|
||||
t.IsTrue(getRegS32(addEnd, 2) > 0, "AddIntcHandler for cause 3 should return handler id");
|
||||
|
||||
R5900Context vsyncCtx{};
|
||||
setRegU32(vsyncCtx, 4, kFlagAddr);
|
||||
setRegU32(vsyncCtx, 5, kTickAddr);
|
||||
t.IsTrue(callSyscall(0x73u, env.rdram.data(), &vsyncCtx, &env.runtime), "SetVSyncFlag syscall should dispatch");
|
||||
t.Equals(getRegS32(vsyncCtx, 2), KE_OK, "SetVSyncFlag should succeed");
|
||||
|
||||
const bool startSeen = waitUntil([&]() {
|
||||
return g_vblankStartHits.load(std::memory_order_relaxed) > 0u;
|
||||
}, std::chrono::milliseconds(400));
|
||||
const bool endSeen = waitUntil([&]() {
|
||||
return g_vblankEndHits.load(std::memory_order_relaxed) > 0u;
|
||||
}, std::chrono::milliseconds(400));
|
||||
|
||||
t.IsTrue(startSeen, "VBLANK start handler should fire while cause 2 is enabled");
|
||||
t.IsTrue(endSeen, "VBLANK end handler should fire while cause 3 is enabled");
|
||||
|
||||
R5900Context disableStart{};
|
||||
setRegU32(disableStart, 4, 2u);
|
||||
t.IsTrue(callSyscall(0x15u, env.rdram.data(), &disableStart, &env.runtime), "DisableIntc syscall should dispatch");
|
||||
t.Equals(getRegS32(disableStart, 2), KE_OK, "DisableIntc should return KE_OK");
|
||||
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(40));
|
||||
const uint32_t startAfterDisable = g_vblankStartHits.load(std::memory_order_relaxed);
|
||||
const uint32_t endAfterDisable = g_vblankEndHits.load(std::memory_order_relaxed);
|
||||
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(80));
|
||||
const uint32_t startLater = g_vblankStartHits.load(std::memory_order_relaxed);
|
||||
const uint32_t endLater = g_vblankEndHits.load(std::memory_order_relaxed);
|
||||
|
||||
t.Equals(startLater, startAfterDisable, "cause 2 handler count should stop increasing while cause 2 is disabled");
|
||||
t.IsTrue(endLater > endAfterDisable, "cause 3 handler should keep firing while still enabled");
|
||||
|
||||
R5900Context enableStart{};
|
||||
setRegU32(enableStart, 4, 2u);
|
||||
t.IsTrue(callSyscall(0x14u, env.rdram.data(), &enableStart, &env.runtime), "EnableIntc syscall should dispatch");
|
||||
t.Equals(getRegS32(enableStart, 2), KE_OK, "EnableIntc should return KE_OK");
|
||||
|
||||
const bool startResumed = waitUntil([&]() {
|
||||
return g_vblankStartHits.load(std::memory_order_relaxed) > startLater;
|
||||
}, std::chrono::milliseconds(300));
|
||||
t.IsTrue(startResumed, "cause 2 handler should resume after re-enable");
|
||||
|
||||
const uint32_t lastArg = g_lastIntcArg.load(std::memory_order_relaxed);
|
||||
t.IsTrue(lastArg == 0xCAFE0002u || lastArg == 0xCAFE0003u,
|
||||
"handler should receive configured argument value");
|
||||
|
||||
cleanupRuntime(env);
|
||||
});
|
||||
|
||||
tc.Run("sceDmaSend dispatches completed VIF1 DMAC handler with latched END tag", [](TestCase &t)
|
||||
{
|
||||
notifyRuntimeStop();
|
||||
TestEnv env;
|
||||
t.IsTrue(env.runtime.memory().initialize(), "runtime memory initialize should succeed");
|
||||
|
||||
constexpr uint32_t kHandlerAddr = 0x00ABD100u;
|
||||
constexpr uint32_t kVif1Ch = 0x10009000u;
|
||||
constexpr uint32_t kTag0 = 0x00028000u;
|
||||
constexpr uint32_t kTag1 = kTag0 + 0x20u;
|
||||
|
||||
uint8_t *rdram = env.runtime.memory().getRDRAM();
|
||||
writeDmaTag(rdram, kTag0, makeDmaTag(1u, 1u, 0u, false)); // CNT
|
||||
writeGuestU64(rdram, kTag0 + 0x10u, 0u);
|
||||
writeGuestU64(rdram, kTag0 + 0x18u, 0u);
|
||||
writeDmaTag(rdram, kTag1, makeDmaTag(0u, 7u, 0u, false)); // END
|
||||
|
||||
g_dmacSendHits.store(0u, std::memory_order_relaxed);
|
||||
g_dmacSendLastCause.store(0u, std::memory_order_relaxed);
|
||||
g_dmacSendLastChcr.store(0u, std::memory_order_relaxed);
|
||||
env.runtime.registerFunction(kHandlerAddr, &testDmacSendHandler);
|
||||
|
||||
R5900Context addCtx{};
|
||||
setRegU32(addCtx, 4, 1u);
|
||||
setRegU32(addCtx, 5, kHandlerAddr);
|
||||
setRegU32(addCtx, 6, 0u);
|
||||
setRegU32(addCtx, 7, 0u);
|
||||
ps2_syscalls::AddDmacHandler(rdram, &addCtx, &env.runtime);
|
||||
t.IsTrue(getRegS32(addCtx, 2) > 0, "AddDmacHandler should register VIF1 handler");
|
||||
|
||||
R5900Context enableCtx{};
|
||||
setRegU32(enableCtx, 4, 1u);
|
||||
ps2_syscalls::EnableDmac(rdram, &enableCtx, &env.runtime);
|
||||
t.Equals(getRegS32(enableCtx, 2), KE_OK, "EnableDmac should enable VIF1 cause");
|
||||
|
||||
R5900Context sendCtx{};
|
||||
setRegU32(sendCtx, 4, kVif1Ch);
|
||||
setRegU32(sendCtx, 5, kTag0);
|
||||
ps2_stubs::sceDmaSend(rdram, &sendCtx, &env.runtime);
|
||||
|
||||
t.Equals(getRegS32(sendCtx, 2), 0, "sceDmaSend should succeed");
|
||||
t.Equals(g_dmacSendHits.load(std::memory_order_relaxed), 1u, "sceDmaSend should dispatch the VIF1 DMAC handler");
|
||||
t.Equals(g_dmacSendLastCause.load(std::memory_order_relaxed), 1u, "DMAC handler should observe VIF1 cause");
|
||||
t.Equals(g_dmacSendLastChcr.load(std::memory_order_relaxed) & 0x100u, 0u, "handler should see VIF1 STR cleared");
|
||||
t.Equals(g_dmacSendLastChcr.load(std::memory_order_relaxed) & 0x70000000u, 0x70000000u, "handler should see the latched END tag id");
|
||||
|
||||
cleanupRuntime(env);
|
||||
});
|
||||
|
||||
tc.Run("MMIO VIF1 chain completion dispatches DMAC handler after CHCR store", [](TestCase &t)
|
||||
{
|
||||
notifyRuntimeStop();
|
||||
TestEnv env;
|
||||
t.IsTrue(env.runtime.memory().initialize(), "runtime memory initialize should succeed");
|
||||
|
||||
constexpr uint32_t kHandlerAddr = 0x00ABD180u;
|
||||
constexpr uint32_t kVif1Ch = 0x10009000u;
|
||||
constexpr uint32_t kTag0 = 0x00028200u;
|
||||
constexpr uint32_t kTag1 = kTag0 + 0x20u;
|
||||
|
||||
uint8_t *rdram = env.runtime.memory().getRDRAM();
|
||||
writeDmaTag(rdram, kTag0, makeDmaTag(1u, 1u, 0u, false)); // CNT
|
||||
writeGuestU64(rdram, kTag0 + 0x10u, 0u);
|
||||
writeGuestU64(rdram, kTag0 + 0x18u, 0u);
|
||||
writeDmaTag(rdram, kTag1, makeDmaTag(0u, 7u, 0u, false)); // END
|
||||
|
||||
g_dmacSendHits.store(0u, std::memory_order_relaxed);
|
||||
g_dmacSendLastCause.store(0u, std::memory_order_relaxed);
|
||||
g_dmacSendLastChcr.store(0u, std::memory_order_relaxed);
|
||||
env.runtime.registerFunction(kHandlerAddr, &testDmacSendHandler);
|
||||
|
||||
R5900Context addCtx{};
|
||||
setRegU32(addCtx, 4, 1u);
|
||||
setRegU32(addCtx, 5, kHandlerAddr);
|
||||
setRegU32(addCtx, 6, 0u);
|
||||
setRegU32(addCtx, 7, 0u);
|
||||
ps2_syscalls::AddDmacHandler(rdram, &addCtx, &env.runtime);
|
||||
t.IsTrue(getRegS32(addCtx, 2) > 0, "AddDmacHandler should register VIF1 handler");
|
||||
|
||||
R5900Context enableCtx{};
|
||||
setRegU32(enableCtx, 4, 1u);
|
||||
ps2_syscalls::EnableDmac(rdram, &enableCtx, &env.runtime);
|
||||
t.Equals(getRegS32(enableCtx, 2), KE_OK, "EnableDmac should enable VIF1 cause");
|
||||
|
||||
R5900Context storeCtx{};
|
||||
env.runtime.Store32(rdram, &storeCtx, kVif1Ch + 0x30u, kTag0);
|
||||
env.runtime.Store32(rdram, &storeCtx, kVif1Ch + 0x00u, 0x185u);
|
||||
|
||||
t.Equals(g_dmacSendHits.load(std::memory_order_relaxed), 1u, "CHCR store should dispatch the VIF1 DMAC handler");
|
||||
t.Equals(g_dmacSendLastCause.load(std::memory_order_relaxed), 1u, "DMAC handler should observe VIF1 cause");
|
||||
t.Equals(g_dmacSendLastChcr.load(std::memory_order_relaxed) & 0x100u, 0u, "handler should see VIF1 STR cleared");
|
||||
t.Equals(g_dmacSendLastChcr.load(std::memory_order_relaxed) & 0x70000000u, 0x70000000u, "handler should see the latched END tag id");
|
||||
|
||||
cleanupRuntime(env);
|
||||
});
|
||||
|
||||
tc.Run("native GIF DMA MMIO kick dispatches completed DMAC handler", [](TestCase &t)
|
||||
{
|
||||
notifyRuntimeStop();
|
||||
TestEnv env;
|
||||
t.IsTrue(env.runtime.memory().initialize(), "runtime memory initialize should succeed");
|
||||
|
||||
constexpr uint32_t kHandlerAddr = 0x00ABD1C0u;
|
||||
constexpr uint32_t kDStat = 0x1000E010u;
|
||||
constexpr uint32_t kDPcr = 0x1000E020u;
|
||||
constexpr uint32_t kTag0 = 0x00028400u;
|
||||
|
||||
uint8_t *rdram = env.runtime.memory().getRDRAM();
|
||||
writeDmaTag(rdram, kTag0, makeDmaTag(1u, 7u, 0u, false)); // END
|
||||
writeGuestU64(rdram, kTag0 + 0x10u, 0x1122334455667788ull);
|
||||
writeGuestU64(rdram, kTag0 + 0x18u, 0x99AABBCCDDEEFF00ull);
|
||||
|
||||
g_dmacSendHits.store(0u, std::memory_order_relaxed);
|
||||
g_dmacSendLastCause.store(0u, std::memory_order_relaxed);
|
||||
g_dmacSendLastChcr.store(0u, std::memory_order_relaxed);
|
||||
env.runtime.registerFunction(kHandlerAddr, &testDmacSendHandler);
|
||||
|
||||
R5900Context addCtx{};
|
||||
setRegU32(addCtx, 4, 2u);
|
||||
setRegU32(addCtx, 5, kHandlerAddr);
|
||||
setRegU32(addCtx, 6, 0u);
|
||||
setRegU32(addCtx, 7, 0u);
|
||||
ps2_syscalls::AddDmacHandler(rdram, &addCtx, &env.runtime);
|
||||
t.IsTrue(getRegS32(addCtx, 2) > 0, "AddDmacHandler should register GIF handler");
|
||||
|
||||
R5900Context enableCtx{};
|
||||
setRegU32(enableCtx, 4, 2u);
|
||||
ps2_syscalls::EnableDmac(rdram, &enableCtx, &env.runtime);
|
||||
t.Equals(getRegS32(enableCtx, 2), KE_OK, "EnableDmac should enable GIF cause");
|
||||
|
||||
R5900Context kickCtx{};
|
||||
env.runtime.kickGifDmaChainFromMMIO(rdram, &kickCtx, 4u, 4u, kTag0, 0x105u);
|
||||
|
||||
t.Equals(env.runtime.memory().readIORegister(kDPcr), 4u, "native GIF kick should preserve D_PCR write");
|
||||
t.IsTrue((env.runtime.memory().readIORegister(kDStat) & (1u << 2)) != 0u,
|
||||
"native GIF kick should raise D_STAT GIF completion status");
|
||||
t.Equals(g_dmacSendHits.load(std::memory_order_relaxed), 1u,
|
||||
"native GIF kick should dispatch the GIF DMAC handler");
|
||||
t.Equals(g_dmacSendLastCause.load(std::memory_order_relaxed), 2u,
|
||||
"DMAC handler should observe GIF cause");
|
||||
t.Equals(g_dmacSendLastChcr.load(std::memory_order_relaxed) & 0x100u, 0u,
|
||||
"handler should see GIF STR cleared");
|
||||
t.Equals(g_dmacSendLastChcr.load(std::memory_order_relaxed) & 0x70000000u, 0x70000000u,
|
||||
"handler should see the latched END tag id");
|
||||
|
||||
cleanupRuntime(env);
|
||||
});
|
||||
|
||||
tc.Run("negative interrupt-safe EE syscall ids dispatch", [](TestCase &t)
|
||||
{
|
||||
notifyRuntimeStop();
|
||||
TestEnv env;
|
||||
|
||||
constexpr uint32_t kEventParamAddr = 0x1200u;
|
||||
@@ -684,97 +319,8 @@ void register_ps2_runtime_interrupt_tests()
|
||||
cleanupRuntime(env);
|
||||
});
|
||||
|
||||
tc.Run("WaitEventFlag blocks and wakes when SetEventFlag publishes bits", [](TestCase &t)
|
||||
{
|
||||
notifyRuntimeStop();
|
||||
TestEnv env;
|
||||
|
||||
constexpr uint32_t kParamAddr = 0x1200u;
|
||||
constexpr uint32_t kResBitsAddr = 0x1300u;
|
||||
|
||||
const uint32_t eventParam[3] = {
|
||||
0u, // attr
|
||||
0u, // option
|
||||
0u // init bits
|
||||
};
|
||||
std::memcpy(env.rdram.data() + kParamAddr, eventParam, sizeof(eventParam));
|
||||
|
||||
R5900Context createCtx{};
|
||||
setRegU32(createCtx, 4, kParamAddr);
|
||||
CreateEventFlag(env.rdram.data(), &createCtx, &env.runtime);
|
||||
const int32_t eid = getRegS32(createCtx, 2);
|
||||
t.IsTrue(eid > 0, "CreateEventFlag should return a valid id");
|
||||
|
||||
writeGuestU32(env.rdram.data(), kResBitsAddr, 0u);
|
||||
|
||||
std::atomic<bool> waiterDone{false};
|
||||
std::atomic<bool> waiterThrew{false};
|
||||
std::atomic<int32_t> waiterRet{0x7FFFFFFF};
|
||||
std::atomic<uint32_t> waiterResBits{0u};
|
||||
|
||||
std::thread waiter([&]()
|
||||
{
|
||||
try
|
||||
{
|
||||
R5900Context waitCtx{};
|
||||
setRegU32(waitCtx, 4, static_cast<uint32_t>(eid));
|
||||
setRegU32(waitCtx, 5, 0x4u); // wait bits
|
||||
setRegU32(waitCtx, 6, WEF_OR); // OR mode
|
||||
setRegU32(waitCtx, 7, kResBitsAddr);
|
||||
WaitEventFlag(env.rdram.data(), &waitCtx, &env.runtime);
|
||||
waiterRet.store(getRegS32(waitCtx, 2), std::memory_order_relaxed);
|
||||
waiterResBits.store(readGuestU32(env.rdram.data(), kResBitsAddr), std::memory_order_relaxed);
|
||||
}
|
||||
catch (...)
|
||||
{
|
||||
waiterThrew.store(true, std::memory_order_release);
|
||||
}
|
||||
|
||||
waiterDone.store(true, std::memory_order_release);
|
||||
});
|
||||
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(20));
|
||||
t.IsFalse(waiterDone.load(std::memory_order_acquire), "WaitEventFlag should block before matching bits are set");
|
||||
|
||||
R5900Context signalCtx{};
|
||||
setRegU32(signalCtx, 4, static_cast<uint32_t>(eid));
|
||||
setRegU32(signalCtx, 5, 0x4u);
|
||||
SetEventFlag(env.rdram.data(), &signalCtx, &env.runtime);
|
||||
t.Equals(getRegS32(signalCtx, 2), KE_OK, "SetEventFlag should succeed");
|
||||
|
||||
const bool woke = waitUntil([&]() {
|
||||
return waiterDone.load(std::memory_order_acquire);
|
||||
}, std::chrono::milliseconds(300));
|
||||
if (!woke)
|
||||
{
|
||||
// Force unblock for deterministic test cleanup.
|
||||
R5900Context deleteCtx{};
|
||||
setRegU32(deleteCtx, 4, static_cast<uint32_t>(eid));
|
||||
DeleteEventFlag(env.rdram.data(), &deleteCtx, &env.runtime);
|
||||
}
|
||||
|
||||
if (waiter.joinable())
|
||||
{
|
||||
waiter.join();
|
||||
}
|
||||
|
||||
t.IsFalse(waiterThrew.load(std::memory_order_acquire),
|
||||
"WaitEventFlag waiter thread should not throw");
|
||||
t.IsTrue(woke, "WaitEventFlag should wake after SetEventFlag publishes matching bits");
|
||||
t.Equals(waiterRet.load(std::memory_order_relaxed), KE_OK, "waiter should return KE_OK");
|
||||
t.IsTrue((waiterResBits.load(std::memory_order_relaxed) & 0x4u) != 0u,
|
||||
"waiter result bits should include published bit");
|
||||
|
||||
R5900Context deleteCtx{};
|
||||
setRegU32(deleteCtx, 4, static_cast<uint32_t>(eid));
|
||||
DeleteEventFlag(env.rdram.data(), &deleteCtx, &env.runtime);
|
||||
|
||||
cleanupRuntime(env);
|
||||
});
|
||||
|
||||
tc.Run("PollEventFlag WEF_CLEAR clears only matched bits", [](TestCase &t)
|
||||
{
|
||||
notifyRuntimeStop();
|
||||
TestEnv env;
|
||||
|
||||
constexpr uint32_t kParamAddr = 0x1400u;
|
||||
@@ -830,60 +376,146 @@ void register_ps2_runtime_interrupt_tests()
|
||||
cleanupRuntime(env);
|
||||
});
|
||||
|
||||
tc.Run("WaitVSyncTick returns when runtime stop is requested", [](TestCase &t)
|
||||
tc.Run("VBlank deadline resumes the waiter and publishes flag tick and FIELD atomically", [](TestCase &t)
|
||||
{
|
||||
notifyRuntimeStop();
|
||||
TestEnv env;
|
||||
t.IsTrue(env.runtime.memory().initialize(), "runtime memory initialize should succeed");
|
||||
env.runtime.registerFunction(kVSyncWaitPc, schedulerVSyncWait);
|
||||
env.runtime.registerFunction(kVSyncResumePc, schedulerVSyncResume);
|
||||
|
||||
std::atomic<bool> waiterDone{false};
|
||||
std::atomic<bool> waiterThrew{false};
|
||||
std::thread waiter([&]()
|
||||
g_resumedResult = -1;
|
||||
g_vsyncFlag = 0u;
|
||||
g_vsyncTick = 0u;
|
||||
g_vsyncCsr = 0u;
|
||||
R5900Context mainContext{};
|
||||
mainContext.pc = kVSyncWaitPc;
|
||||
env.runtime.eeScheduler().reset(env.rdram.data(), mainContext);
|
||||
env.runtime.eeScheduler().run();
|
||||
|
||||
t.Equals(g_vsyncFlag, 1u, "VBlank start should set the registered guest flag");
|
||||
t.Equals(g_vsyncTick, 1ull, "the first centralized VBlank deadline should publish tick one");
|
||||
t.Equals(g_resumedResult, 0, "the first VBlank field should return even-field parity");
|
||||
t.Equals(g_vsyncCsr & 0x2000ull, 0x2000ull,
|
||||
"the first VBlank should publish GS CSR.FIELD before resuming guest code");
|
||||
});
|
||||
|
||||
tc.Run("VBlank IRQ invocation completes before the resumed base context", [](TestCase &t)
|
||||
{
|
||||
TestEnv env;
|
||||
env.runtime.registerFunction(kIrqWaitPc, schedulerIrqWait);
|
||||
env.runtime.registerFunction(kIrqResumePc, schedulerIrqResume);
|
||||
env.runtime.registerFunction(kIntcHandlerPc, schedulerIntcHandler);
|
||||
|
||||
g_dispatchTrace.clear();
|
||||
g_lastIntcArg.store(0u, std::memory_order_relaxed);
|
||||
R5900Context mainContext{};
|
||||
mainContext.pc = kIrqWaitPc;
|
||||
env.runtime.eeScheduler().reset(env.rdram.data(), mainContext);
|
||||
env.runtime.eeScheduler().run();
|
||||
|
||||
const std::vector<int> expected{1, 2, 3};
|
||||
t.IsTrue(g_dispatchTrace == expected,
|
||||
"the dispatcher should run wait, IRQ frame, then the resumed base context in exact order");
|
||||
t.Equals(g_lastIntcArg.load(std::memory_order_relaxed), 0xCAFEu,
|
||||
"the IRQ frame should receive its registered argument");
|
||||
});
|
||||
|
||||
tc.Run("iSignalSema defers selection until IRQ return", [](TestCase &t)
|
||||
{
|
||||
TestEnv env;
|
||||
env.runtime.registerFunction(kISemaWaitPc, schedulerISemaWait);
|
||||
env.runtime.registerFunction(kISemaResumePc, schedulerISemaResume);
|
||||
env.runtime.registerFunction(kISemaDriverPc, schedulerISemaDriver);
|
||||
env.runtime.registerFunction(kISemaHandlerPc, schedulerISemaHandler);
|
||||
|
||||
g_dispatchTrace.clear();
|
||||
g_resumedResult = -1;
|
||||
R5900Context mainContext{};
|
||||
mainContext.pc = kISemaWaitPc;
|
||||
env.runtime.eeScheduler().reset(env.rdram.data(), mainContext);
|
||||
env.runtime.eeScheduler().run();
|
||||
|
||||
const std::vector<int> expected{1, 2, 3, 4, 5};
|
||||
t.IsTrue(g_dispatchTrace == expected,
|
||||
"iSignalSema should make the waiter ready but finish the IRQ frame before selecting it");
|
||||
t.Equals(g_resumedResult, g_testSemaphoreId,
|
||||
"the resumed waiter should receive the semaphore id from the direct FIFO handoff");
|
||||
const EeSemaphore *semaphore = env.runtime.eeScheduler().semaphore(g_testSemaphoreId);
|
||||
t.IsTrue(semaphore != nullptr, "the signaled semaphore should still exist");
|
||||
if (semaphore)
|
||||
{
|
||||
t.Equals(semaphore->count, 0, "direct handoff must not increment the semaphore count");
|
||||
t.Equals(static_cast<uint32_t>(semaphore->waiters.size()), 0u,
|
||||
"the awakened waiter must be removed from the semaphore queue");
|
||||
}
|
||||
});
|
||||
|
||||
tc.Run("event-flag completion writes observed bits before strict-priority resume", [](TestCase &t)
|
||||
{
|
||||
TestEnv env;
|
||||
env.runtime.registerFunction(kEventWaitPc, schedulerEventWait);
|
||||
env.runtime.registerFunction(kEventResumePc, schedulerEventResume);
|
||||
env.runtime.registerFunction(kEventProducerPc, schedulerEventProducer);
|
||||
|
||||
g_dispatchTrace.clear();
|
||||
g_resumedResult = -1;
|
||||
R5900Context mainContext{};
|
||||
mainContext.pc = kEventWaitPc;
|
||||
env.runtime.eeScheduler().reset(env.rdram.data(), mainContext);
|
||||
env.runtime.eeScheduler().run();
|
||||
|
||||
const std::vector<int> expected{1, 2, 3};
|
||||
t.IsTrue(g_dispatchTrace == expected,
|
||||
"the higher-priority event waiter should resume at the producer scheduling point");
|
||||
t.Equals(g_resumedResult, KE_OK, "the resumed event waiter should receive KE_OK");
|
||||
t.Equals(readGuestU32(env.rdram.data(), kEventResultAddr), 0x6u,
|
||||
"the event output should contain the bits observed before clear mode is applied");
|
||||
const EeEventFlag *flag = env.runtime.eeScheduler().eventFlag(g_testEventFlagId);
|
||||
t.IsTrue(flag != nullptr, "the event flag should still exist");
|
||||
if (flag)
|
||||
{
|
||||
t.Equals(flag->bits, 0x4u, "WEF_CLEAR should remove only the requested matched bit");
|
||||
}
|
||||
});
|
||||
|
||||
tc.Run("scheduler stop wakes an idle VSync wait without a timeout", [](TestCase &t)
|
||||
{
|
||||
TestEnv env;
|
||||
env.runtime.registerFunction(kIdleVSyncWaitPc, idleVSyncWait);
|
||||
|
||||
R5900Context mainContext{};
|
||||
mainContext.pc = kIdleVSyncWaitPc;
|
||||
std::atomic<bool> schedulerDone{false};
|
||||
std::atomic<bool> schedulerThrew{false};
|
||||
std::thread gameThread([&]()
|
||||
{
|
||||
try
|
||||
{
|
||||
WaitVSyncTick(env.rdram.data(), &env.runtime);
|
||||
env.runtime.eeScheduler().reset(env.rdram.data(), mainContext);
|
||||
env.runtime.eeScheduler().run();
|
||||
}
|
||||
catch (...)
|
||||
{
|
||||
waiterThrew.store(true, std::memory_order_release);
|
||||
schedulerThrew.store(true, std::memory_order_release);
|
||||
}
|
||||
waiterDone.store(true, std::memory_order_release);
|
||||
schedulerDone.store(true, std::memory_order_release);
|
||||
});
|
||||
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(2));
|
||||
env.runtime.requestStop();
|
||||
|
||||
bool wokeOnStop = waitUntil([&]() {
|
||||
return waiterDone.load(std::memory_order_acquire);
|
||||
const bool becameIdle = waitUntil([&]() {
|
||||
const EeKernelSnapshot snapshot = env.runtime.eeScheduler().snapshot();
|
||||
return snapshot.runningThreadId == 0 &&
|
||||
!snapshot.threads.empty() &&
|
||||
snapshot.threads.front().waitReason == EeWaitReason::VSync;
|
||||
}, std::chrono::milliseconds(80));
|
||||
|
||||
if (!wokeOnStop)
|
||||
{
|
||||
// Fallback wake-up for deterministic cleanup: one extra tick on fresh runtime.
|
||||
TestEnv wakeEnv;
|
||||
R5900Context setCtx{};
|
||||
constexpr uint32_t kWakeFlagAddr = 0x1500u;
|
||||
constexpr uint32_t kWakeTickAddr = 0x1510u;
|
||||
setRegU32(setCtx, 4, kWakeFlagAddr);
|
||||
setRegU32(setCtx, 5, kWakeTickAddr);
|
||||
(void)callSyscall(0x73u, wakeEnv.rdram.data(), &setCtx, &wakeEnv.runtime);
|
||||
(void)waitUntil([&]() {
|
||||
return readGuestU64(wakeEnv.rdram.data(), kWakeTickAddr) > 0u;
|
||||
}, std::chrono::milliseconds(300));
|
||||
wakeEnv.runtime.requestStop();
|
||||
wokeOnStop = waitUntil([&]() {
|
||||
return waiterDone.load(std::memory_order_acquire);
|
||||
}, std::chrono::milliseconds(80));
|
||||
}
|
||||
env.runtime.requestStop();
|
||||
gameThread.join();
|
||||
|
||||
if (waiter.joinable())
|
||||
{
|
||||
waiter.join();
|
||||
}
|
||||
|
||||
t.IsFalse(waiterThrew.load(std::memory_order_acquire),
|
||||
"WaitVSyncTick waiter thread should not throw");
|
||||
t.IsTrue(wokeOnStop, "WaitVSyncTick waiter should unblock when runtime is stopping");
|
||||
t.IsTrue(becameIdle, "VSync wait should leave the sole guest thread waiting");
|
||||
t.IsTrue(schedulerDone.load(std::memory_order_acquire),
|
||||
"requestStop should wake the scheduler's event wait");
|
||||
t.IsFalse(schedulerThrew.load(std::memory_order_acquire),
|
||||
"the scheduler stop path should not throw");
|
||||
|
||||
cleanupRuntime(env);
|
||||
});
|
||||
|
||||
Reference in New Issue
Block a user