mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-09-26 16:59:35 -04:00
Ran-j
e27a658b32
feat: added parallel gs feat: optmized IOP emulator feat: added guest and game fps count feat: small vu1 optmization and guards
231 lines
9.0 KiB
C++
231 lines
9.0 KiB
C++
#include "iop_compat_test_support.h"
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#include "emulator/iop_emulator.h"
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#include "emulator/core/iop_cpu.h"
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#include "emulator/core/iop_memory.h"
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#include "emulator/imports/iop_imports.h"
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namespace
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{
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using namespace iop_test;
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using namespace ps2x::iop::detail;
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// Real guest stores start SPU DMA; intrman invokes the guest handler below.
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struct DmaFixture
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{
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Host host;
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IopEmulator iop{host};
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Irx image{0x10000, 0x900};
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uint32_t offset = 0;
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std::array<uint32_t, 2> starts{};
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std::array<uint32_t, 2> delays{};
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std::array<uint64_t, 2> deadlines{};
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DmaFixture()
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{
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emit({0x27bdfff0, 0xafbf000c}); // save ra
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for (unsigned irq : {0x24u, 0x28u})
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{
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emit({0x24040000 | irq, 0x24050000, 0x3c060001, 0x34c60300,
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0x24070000 | irq, 0x0c004185, 0}); // RegisterIntrHandler
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emit({0x24040000 | irq, 0x0c004187, 0}); // EnableIntr
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}
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image.words(0x600, {0x41e00000, 0, 0x0101, 0x72746e69, 0x006e616d,
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0x03e00008, 0x24000004, 0x03e00008, 0x24000006, 0, 0});
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image.words(0x300, {
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0x3c080001, 0x8d090800, 0, // t1 = completed count (load delay)
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0x00095080, 0x01485021, 0xad440810, // trace[count] = irq
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0x25290001, 0xad090800,
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0x8d090804, 0, 0x1120000c, 0, // optionally rearm DMA from the handler
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0xad000804, 0x3c091f80, 0x352910c0,
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0x240a0020, 0xad2a0004, 0x3c0a0100, 0xad2a0008,
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0x24090050, 0x2529ffff, 0x1520fffe, 0, // handler runs past the new deadline
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0x03e00008, 0,
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});
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}
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void emit(std::initializer_list<uint32_t> words)
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{
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image.words(offset, words);
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offset += uint32_t(words.size()) * 4;
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}
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void start(unsigned channel, uint32_t delay)
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{
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emit({0x3c081f80, channel ? 0x35081500u : 0x350810c0u,
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0x24090000 | (delay / 2), 0xad090004, 0x3c090100});
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starts[channel] = offset;
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delays[channel] = delay;
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emit({0xad090008});
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}
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void load()
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{
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const std::initializer_list<uint32_t> epilogue{0x8fbf000c, 0x27bd0010, 0x00001021, 0x03e00008, 0};
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image.words(offset, epilogue);
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const uint32_t entryEnd = offset + uint32_t(epilogue.size()) * 4;
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image.install(host);
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const auto result = iop.loadModuleBuffer(0x1000, nullptr, 0);
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require(result.moduleId > 0 && result.startResult == 0, "DMA IRX initialization failed");
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for (unsigned channel = 0; channel < 2; ++channel)
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if (delays[channel])
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deadlines[channel] = iop.cycles() - (entryEnd - starts[channel]) / 4 + delays[channel];
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}
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uint32_t word(uint32_t address)
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{
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uint32_t value = 0;
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require(iop.readMemory(address, &value, sizeof(value)), "IOP trace read failed");
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return value;
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}
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void advanceTo(uint64_t cycle)
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{
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require(cycle >= iop.cycles(), "test attempted to reverse time");
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iop.runEeCycles((cycle - iop.cycles()) * 8);
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}
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};
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void dmaDeadlines()
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{
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DmaFixture f;
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f.start(0, 1000);
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f.start(1, 200);
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f.load();
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f.advanceTo(f.deadlines[1]);
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require(f.word(0x10800) == 0, "idle DMA dispatched before its deadline was serviced");
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f.iop.runEeCycles(8);
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require(f.word(0x10800) == 1 && f.word(0x10810) == 0x28, "earliest DMA did not wake the idle IOP");
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f.advanceTo(f.deadlines[0]);
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require(f.word(0x10800) == 1, "later DMA dispatched early");
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f.iop.runEeCycles(8);
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require(f.word(0x10800) == 2 && f.word(0x10814) == 0x24, "later DMA was lost");
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f.iop.runEeCycles(8000);
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require(f.word(0x10800) == 2, "DMA completion dispatched twice");
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}
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void dmaReplacementAndReset()
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{
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DmaFixture f;
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f.start(0, 200);
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f.start(1, 400);
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f.start(0, 1000); // replace the earliest event with a later one
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f.load();
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f.advanceTo(f.deadlines[1]);
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require(f.word(0x10800) == 0, "replaced DMA deadline survived");
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f.iop.runEeCycles(8);
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require(f.word(0x10800) == 1 && f.word(0x10810) == 0x28, "replacement hid the other channel");
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f.iop.reset();
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f.iop.runEeCycles(16000);
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require(f.iop.instructions() == 0, "reset retained a DMA callback");
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f.load();
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f.advanceTo(f.deadlines[1]);
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f.iop.runEeCycles(8);
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require(f.word(0x10800) == 1, "DMA scheduling did not recover after reset");
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}
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void dmaReentrantHandler()
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{
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DmaFixture f;
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f.start(0, 200);
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f.image.words(0x804, {1});
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f.load();
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f.advanceTo(f.deadlines[0]);
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f.iop.runEeCycles(8);
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require(f.word(0x10800) == 1, "DMA handler recursively dispatched a new completion");
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f.iop.runEeCycles(8);
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require(f.word(0x10800) == 2 && f.word(0x10814) == 0x24,
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"DMA started inside its handler was lost");
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}
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void dmaEqualDeadlines()
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{
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DmaFixture f;
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f.start(1, 206);
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f.start(0, 200); // Six instructions later: same completion cycle.
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f.load();
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require(f.deadlines[0] == f.deadlines[1], "fixture deadlines differ");
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f.advanceTo(f.deadlines[0]);
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f.iop.runEeCycles(8);
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require(f.word(0x10800) == 2 && f.word(0x10810) == 0x24 && f.word(0x10814) == 0x28,
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"simultaneous DMA callbacks changed IRQ order");
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}
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void dmaWhileExecuting()
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{
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DmaFixture f;
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f.start(0, 200);
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// Keep guest execution active beyond completion; no idle path is involved.
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f.emit({0x24100050, 0x2610ffff, 0x1600fffe, 0});
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f.load();
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require(f.word(0x10800) == 1 && f.word(0x10810) == 0x24,
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"DMA did not dispatch during guest execution");
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}
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void instructionChanges()
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{
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IopMemory memory;
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IopCpuCore core(memory);
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IopImportRegistry imports(memory);
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IopCpuState cpu{};
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const auto step = [&]()
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{
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const uint32_t instruction = memory.read32(cpu.pc);
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require(!imports.decode(cpu.pc, instruction), "ordinary instruction mistaken for an import");
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return core.executeInstruction(cpu, instruction);
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};
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cpu.pc = 0x80001000;
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memory.write32(0x1000, 0x24020011); // addiu v0, zero, 0x11
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require(step() && cpu.gpr[2] == 0x11, "first instruction failed");
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cpu.pc = 0x80001000;
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memory.write32(0x1000, 0x24020022);
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require(step() && cpu.gpr[2] == 0x22, "modified instruction was not refetched");
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cpu.pc = 0x1000;
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memory.write32(0x1000, 0x8c020800); // lw v0, 0x800(zero)
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memory.write32(0x1004, 0x24430001); // addiu v1, v0, 1 (sees old v0)
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memory.write32(0x800, 0x44);
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require(step() && cpu.gpr[2] == 0x22, "load delay changed");
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require(step() && cpu.gpr[2] == 0x44 && cpu.gpr[3] == 0x23,
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"instruction sharing changed load delay semantics");
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cpu.pc = 0x1000;
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memory.write32(0x1000, 0x10000001); // beq zero, zero, +1
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memory.write32(0x1004, 0x24020033);
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require(step() && cpu.pc == 0x1004 && cpu.branchPending, "branch delay slot was skipped");
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require(step() && cpu.pc == 0x1008 && cpu.gpr[2] == 0x33, "branch delay slot did not execute");
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}
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void modifiedImportStub()
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{
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IopMemory memory;
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IopImportRegistry imports(memory);
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memory.write32(0x1000, 0x41e00000);
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memory.write16(0x1008, 0x0101);
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constexpr char name[8] = "tstlib";
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require(memory.writeRam(0x100c, name, sizeof(name)), "import name write failed");
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memory.write32(0x1014, 0x03e00008);
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memory.write32(0x1018, 0x24000003);
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const auto decode = [&]() { return imports.decode(0x80001014, memory.read32(0x80001014)); };
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auto call = decode();
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require(call && call->ordinal == 3 && call->version == 0x0101, "shared fetch lost import metadata");
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memory.write16(0x1008, 0x0102);
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memory.write32(0x1018, 0x24000007);
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call = decode();
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require(call && call->ordinal == 7 && call->version == 0x0102, "import metadata became stale");
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memory.write32(0x1014, 0x24020011);
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require(!decode(), "patched import stub still dispatched as an import");
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}
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}
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int main()
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{
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const Test tests[] = {
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{"DMA deadlines and idle wakeup", dmaDeadlines},
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{"DMA replacement and reset", dmaReplacementAndReset},
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{"DMA scheduled from a running IRQ handler", dmaReentrantHandler},
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{"Simultaneous DMA IRQ order", dmaEqualDeadlines},
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{"DMA dispatch while guest instructions execute", dmaWhileExecuting},
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{"Modified instructions and load delay", instructionChanges},
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{"Modified import stub and metadata", modifiedImportStub},
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};
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return run(tests);
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}
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