mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-09-26 08:51:05 -04:00
Ranieri
75d729ce40
* refactor: from guest threads to EE scheduler * feat: bad wip mpeg fix for code veronica * feat: cheap copy from host feat: small perf o vsync tick * feat: added EE clock Hz fix: fix MPEG out of sync with new EE refactor * fix: fix lotr tests * fix: fix cri dtx loading fix: fix wrong mmi instruction translation fix: fix thread info params feat: added EE timers decoder and consumer feat: split SFI and IOP memory to prevent collision and overrides * feat: revert wrong changes * refactor: change GS architecture * feat: IOP emulator refactor: codegen to catch callbacks on mips code feat: added a lot of entries or IOP emulator * feat: analyzer resolve the complete constant-producing sequence with five-instruction backward scan stopped at LUI and therefore * feat: remove recompiled version of GetRomName refactor: split IOP emulator logic feat: added more HLE IOP modules feat: added ps2_path * eat: enhance ELF parser with improved callable entry detection and control flow analysis * feat: update memory hint handling and enhance entry point discovery logic * feat: add SET_GPR_ZE32 macro for zero-extending loads with unsigned semantics * refactor: Refactor PS2 IOP Host Adapter and Memory Management feat: Added PS2Vfs for virtual file system operations, including file opening, reading, writing, and path resolution. feat: Improve VIF1 data processing to handle GIF image packets more efficiently. * feat: added a lot of tests * fix: fix texture caching feat: wip multi version on dbcman * feat: remove LLE IOPs
805 lines
32 KiB
C++
805 lines
32 KiB
C++
#ifndef PS2RECOMP_INSTRUCTIONS_H
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#define PS2RECOMP_INSTRUCTIONS_H
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#include <cstdint>
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namespace ps2recomp
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{
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inline constexpr uint32_t MIPS_INSTRUCTION_SIZE = sizeof(uint32_t);
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inline constexpr uint16_t MIPS_IMMEDIATE_SIGN_BIT = 0x8000u;
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inline constexpr uint32_t MIPS_JUMP_TARGET_SHIFT = 2u;
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inline constexpr uint32_t MIPS_JUMP_REGION_MASK = 0xF0000000u;
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// R5900 general-purpose register indices used by the encoded RS/RT/RD fields.
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enum GprRegisters : uint32_t
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{
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GPR_ZERO = 0,
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GPR_AT = 1,
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GPR_V0 = 2,
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GPR_V1 = 3,
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GPR_A0 = 4,
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GPR_A1 = 5,
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GPR_A2 = 6,
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GPR_A3 = 7,
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GPR_T0 = 8,
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GPR_T1 = 9,
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GPR_T2 = 10,
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GPR_T3 = 11,
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GPR_T4 = 12,
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GPR_T5 = 13,
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GPR_T6 = 14,
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GPR_T7 = 15,
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GPR_S0 = 16,
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GPR_S1 = 17,
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GPR_S2 = 18,
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GPR_S3 = 19,
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GPR_S4 = 20,
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GPR_S5 = 21,
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GPR_S6 = 22,
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GPR_S7 = 23,
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GPR_T8 = 24,
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GPR_T9 = 25,
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GPR_K0 = 26,
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GPR_K1 = 27,
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GPR_GP = 28,
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GPR_SP = 29,
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GPR_FP = 30,
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GPR_RA = 31,
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};
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// Basic MIPS opcodes (shared with R4300i)
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enum MipsOpcodes
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{
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OPCODE_SPECIAL = 0x00, // Special instructions group (see SpecialFunctions)
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OPCODE_REGIMM = 0x01, // RegImm instructions group (see RegimmFunctions)
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OPCODE_J = 0x02, // Jump
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OPCODE_JAL = 0x03, // Jump and Link
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OPCODE_BEQ = 0x04, // Branch on Equal
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OPCODE_BNE = 0x05, // Branch on Not Equal
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OPCODE_BLEZ = 0x06, // Branch on Less Than or Equal to Zero
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OPCODE_BGTZ = 0x07, // Branch on Greater Than Zero
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OPCODE_ADDI = 0x08, // Add Immediate Word
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OPCODE_ADDIU = 0x09, // Add Immediate Unsigned Word
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OPCODE_SLTI = 0x0A, // Set on Less Than Immediate
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OPCODE_SLTIU = 0x0B, // Set on Less Than Immediate Unsigned
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OPCODE_ANDI = 0x0C, // AND Immediate
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OPCODE_ORI = 0x0D, // OR Immediate
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OPCODE_XORI = 0x0E, // XOR Immediate
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OPCODE_LUI = 0x0F, // Load Upper Immediate
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OPCODE_COP0 = 0x10, // Coprocessor 0 instructions (see Cop0Format)
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OPCODE_COP1 = 0x11, // Coprocessor 1 (FPU) instructions (see Cop1Format)
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OPCODE_COP2 = 0x12, // Coprocessor 2 (VU0 Macro) instructions (see Cop2Format)
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OPCODE_COP3 = 0x13, // Unused on PS2
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OPCODE_BEQL = 0x14, // Branch on Equal Likely
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OPCODE_BNEL = 0x15, // Branch on Not Equal Likely
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OPCODE_BLEZL = 0x16, // Branch on Less Than or Equal to Zero Likely
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OPCODE_BGTZL = 0x17, // Branch on Greater Than Zero Likely
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OPCODE_DADDI = 0x18, // Doubleword Add Immediate
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OPCODE_DADDIU = 0x19, // Doubleword Add Immediate Unsigned
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OPCODE_LDL = 0x1A, // Load Doubleword Left
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OPCODE_LDR = 0x1B, // Load Doubleword Right
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OPCODE_MMI = 0x1C, // PS2 specific MMI instructions group (see MMIFunctions)
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OPCODE_LQ = 0x1E, // PS2 specific 128-bit load
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OPCODE_SQ = 0x1F, // PS2 specific 128-bit store
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OPCODE_LB = 0x20, // Load Byte
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OPCODE_LH = 0x21, // Load Halfword
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OPCODE_LWL = 0x22, // Load Word Left
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OPCODE_LW = 0x23, // Load Word
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OPCODE_LBU = 0x24, // Load Byte Unsigned
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OPCODE_LHU = 0x25, // Load Halfword Unsigned
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OPCODE_LWR = 0x26, // Load Word Right
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OPCODE_LWU = 0x27, // Load Word Unsigned
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OPCODE_SB = 0x28, // Store Byte
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OPCODE_SH = 0x29, // Store Halfword
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OPCODE_SWL = 0x2A, // Store Word Left
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OPCODE_SW = 0x2B, // Store Word
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OPCODE_SDL = 0x2C, // Store Doubleword Left
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OPCODE_SDR = 0x2D, // Store Doubleword Right
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OPCODE_SWR = 0x2E, // Store Word Right
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OPCODE_CACHE = 0x2F, // Cache Operation
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OPCODE_LL = 0x30, // LL - Load Linked Word, maybe omitted/unused
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OPCODE_LWC1 = 0x31, // Load Word to Coprocessor 1 (FPU)
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OPCODE_LWC2 = 0x32, // Load Word to Coprocessor 2, maybe omitted/unused
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OPCODE_PREF = 0x33, // Prefetch
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OPCODE_LLD = 0x34, // Load Linked Doubleword, maybe omitted/unused
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OPCODE_LDC1 = 0x35, // Load Doubleword to Coprocessor 1, FPU is single-precision
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OPCODE_LDC2 = 0x36, // Load Quadword to Coprocessor 2 (VU0) - Overrides standard MIPS LDC2
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OPCODE_LD = 0x37, // Load Doubleword
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OPCODE_SC = 0x38, // Store Conditional Word, maybe omitted/unused?
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OPCODE_SWC1 = 0x39, // Store Word from Coprocessor 1 (FPU)
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OPCODE_SWC2 = 0x3A, // SWC2 - Store Word from Coprocessor 2, maybe omitted/unused
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OPCODE_SCD = 0x3C, // SCD - Store Conditional Doubleword, maybe omitted/unused?
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OPCODE_SDC1 = 0x3D, // SDC1 - Store Doubleword from Coprocessor 1, FPU is single-precision
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OPCODE_SDC2 = 0x3E, // PS2 specific Store Quadword from Coprocessor 2 (VU0) - Overrides standard MIPS SDC2
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OPCODE_SD = 0x3F, // Store Doubleword
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OPCODE_LQC2 = OPCODE_LDC2,
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OPCODE_SQC2 = OPCODE_SDC2
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};
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// SPECIAL Function (bits 5-0) for OPCODE_SPECIAL
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enum SpecialFunctions
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{
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SPECIAL_SLL = 0x00, // Shift Word Left Logical
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SPECIAL_SRL = 0x02, // Shift Word Right Logical
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SPECIAL_SRA = 0x03, // Shift Word Right Arithmetic
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SPECIAL_SLLV = 0x04, // Shift Word Left Logical Variable
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SPECIAL_SRLV = 0x06, // Shift Word Right Logical Variable
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SPECIAL_SRAV = 0x07, // Shift Word Right Arithmetic Variable
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SPECIAL_JR = 0x08, // Jump Register
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SPECIAL_JALR = 0x09, // Jump and Link Register
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SPECIAL_MOVZ = 0x0A, // Move Conditional on Zero
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SPECIAL_MOVN = 0x0B, // Move Conditional on Not Zero
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SPECIAL_SYSCALL = 0x0C, // System Call
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SPECIAL_BREAK = 0x0D, // Breakpoint
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SPECIAL_SYNC = 0x0F, // Synchronize Shared Memory
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SPECIAL_MFHI = 0x10, // Move From HI Register
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SPECIAL_MTHI = 0x11, // Move To HI Register
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SPECIAL_MFLO = 0x12, // Move From LO Register
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SPECIAL_MTLO = 0x13, // Move To LO Register
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SPECIAL_DSLLV = 0x14, // Doubleword Shift Left Logical Variable
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SPECIAL_DSRLV = 0x16, // Doubleword Shift Right Logical Variable
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SPECIAL_DSRAV = 0x17, // Doubleword Shift Right Arithmetic Variable
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SPECIAL_MULT = 0x18, // Multiply Word
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SPECIAL_MULTU = 0x19, // Multiply Unsigned Word
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SPECIAL_DIV = 0x1A, // Divide Word
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SPECIAL_DIVU = 0x1B, // Divide Unsigned Word
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SPECIAL_ADD = 0x20, // Add Word
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SPECIAL_ADDU = 0x21, // Add Unsigned Word
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SPECIAL_SUB = 0x22, // Subtract Word
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SPECIAL_SUBU = 0x23, // Subtract Unsigned Word
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SPECIAL_AND = 0x24, // AND
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SPECIAL_OR = 0x25, // OR
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SPECIAL_XOR = 0x26, // XOR
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SPECIAL_NOR = 0x27, // NOR
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SPECIAL_MFSA = 0x28, // Move From SA Register (PS2 specific)
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SPECIAL_MTSA = 0x29, // Move To SA Register (PS2 specific)
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SPECIAL_SLT = 0x2A, // Set on Less Than
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SPECIAL_SLTU = 0x2B, // Set on Less Than Unsigned
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SPECIAL_DADD = 0x2C, // Doubleword Add
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SPECIAL_DADDU = 0x2D, // Doubleword Add Unsigned
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SPECIAL_DSUB = 0x2E, // Doubleword Subtract
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SPECIAL_DSUBU = 0x2F, // Doubleword Subtract Unsigned
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SPECIAL_TGE = 0x30, // Trap if Greater or Equal
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SPECIAL_TGEU = 0x31, // Trap if Greater or Equal Unsigned
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SPECIAL_TLT = 0x32, // Trap if Less Than
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SPECIAL_TLTU = 0x33, // Trap if Less Than Unsigned
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SPECIAL_TEQ = 0x34, // Trap if Equal
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SPECIAL_TNE = 0x36, // Trap if Not Equal
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SPECIAL_DSLL = 0x38, // Doubleword Shift Left Logical
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SPECIAL_DSRL = 0x3A, // Doubleword Shift Right Logical
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SPECIAL_DSRA = 0x3B, // Doubleword Shift Right Arithmetic
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SPECIAL_DSLL32 = 0x3C, // Doubleword Shift Left Logical +32
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SPECIAL_DSRL32 = 0x3E, // Doubleword Shift Right Logical +32
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SPECIAL_DSRA32 = 0x3F, // Doubleword Shift Right Arithmetic +32
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};
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// REGIMM RT Field (bits 20-16) for OPCODE_REGIMM
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enum RegimmFunctions
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{
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REGIMM_BLTZ = 0x00, // Branch on Less Than Zero
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REGIMM_BGEZ = 0x01, // Branch on Greater Than or Equal to Zero
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REGIMM_BLTZL = 0x02, // Branch on Less Than Zero Likely
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REGIMM_BGEZL = 0x03, // Branch on Greater Than or Equal to Zero Likely
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REGIMM_TGEI = 0x08, // Trap if Greater or Equal Immediate
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REGIMM_TGEIU = 0x09, // Trap if Greater or Equal Immediate Unsigned
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REGIMM_TLTI = 0x0A, // Trap if Less Than Immediate
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REGIMM_TLTIU = 0x0B, // Trap if Less Than Immediate Unsigned
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REGIMM_TEQI = 0x0C, // Trap if Equal Immediate
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REGIMM_TNEI = 0x0E, // Trap if Not Equal Immediate
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REGIMM_BLTZAL = 0x10, // Branch on Less Than Zero and Link
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REGIMM_BGEZAL = 0x11, // Branch on Greater Than or Equal to Zero and Link
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REGIMM_BLTZALL = 0x12, // Branch on Less Than Zero and Link Likely
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REGIMM_BGEZALL = 0x13, // Branch on Greater Than or Equal to Zero and Link Likely
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REGIMM_MTSAB = 0x18, // Move To SA Register Byte (PS2 specific)
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REGIMM_MTSAH = 0x19, // Move To SA Register Halfword (PS2 specific)
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};
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// MMI Function Field (bits 5-0) for OPCODE_MMI (0x1C)
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enum MMIFunctions
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{
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MMI_MADD = 0x00, // Multiply Add Word (to LO/HI)
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MMI_MADDU = 0x01, // Multiply Add Unsigned Word (to LO/HI)
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MMI_MSUB = 0x02, // Multiply Subtract Word (Not listed in provided doc table, but valid MMI)
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MMI_MSUBU = 0x03, // Multiply Subtract Unsigned Word (Not listed in provided doc table, but valid MMI)
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MMI_PLZCW = 0x04, // Parallel Leading Zero/One Count Word
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MMI_MMI0 = 0x08, // Group MMI0 instructions (see MMI0Functions)
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MMI_MMI2 = 0x09, // Group MMI2 instructions (see MMI2Functions)
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MMI_MFHI1 = 0x10, // Move From HI1 Register
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MMI_MTHI1 = 0x11, // Move To HI1 Register
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MMI_MFLO1 = 0x12, // Move From LO1 Register
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MMI_MTLO1 = 0x13, // Move To LO1 Register
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MMI_MULT1 = 0x18, // Multiply Word to LO1/HI1
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MMI_MULTU1 = 0x19, // Multiply Unsigned Word to LO1/HI1
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MMI_DIV1 = 0x1A, // Divide Word using LO1/HI1
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MMI_DIVU1 = 0x1B, // Divide Unsigned Word using LO1/HI1
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MMI_MADD1 = 0x20, // Multiply Add Word to LO1/HI1
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MMI_MADDU1 = 0x21, // Multiply Add Unsigned Word to LO1/HI1
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MMI_MMI1 = 0x28, // Group MMI1 instructions (see MMI1Functions)
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MMI_MMI3 = 0x29, // Group MMI3 instructions (see MMI3Functions)
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MMI_PMFHL = 0x30, // Parallel Move From HI/LO Register (see PMFHLFunctions for 'sa' field)
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MMI_PMTHL = 0x31, // Parallel Move To HI/LO Register (see PMFHLFunctions for 'sa' field)
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MMI_PSLLH = 0x34, // Parallel Shift Left Logical Halfword
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MMI_PSRLH = 0x36, // Parallel Shift Right Logical Halfword
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MMI_PSRAH = 0x37, // Parallel Shift Right Arithmetic Halfword
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MMI_PSLLW = 0x3C, // Parallel Shift Left Logical Word
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MMI_PSRLW = 0x3E, // Parallel Shift Right Logical Word
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MMI_PSRAW = 0x3F // Parallel Shift Right Arithmetic Word
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};
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// PS2-specific MMI0 Sub-Function Field (bits 0-5 within MMI_MMI0 group)
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enum MMI0Functions
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{
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MMI0_PADDW = 0x00,
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MMI0_PSUBW = 0x01,
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MMI0_PCGTW = 0x02,
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MMI0_PMAXW = 0x03,
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MMI0_PADDH = 0x04,
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MMI0_PSUBH = 0x05,
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MMI0_PCGTH = 0x06,
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MMI0_PMAXH = 0x07,
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MMI0_PADDB = 0x08,
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MMI0_PSUBB = 0x09,
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MMI0_PCGTB = 0x0A,
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MMI0_PADDSW = 0x10,
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MMI0_PSUBSW = 0x11,
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MMI0_PEXTLW = 0x12,
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MMI0_PPACW = 0x13,
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MMI0_PADDSH = 0x14,
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MMI0_PSUBSH = 0x15,
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MMI0_PEXTLH = 0x16,
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MMI0_PPACH = 0x17,
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MMI0_PADDSB = 0x18,
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MMI0_PSUBSB = 0x19,
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MMI0_PEXTLB = 0x1A,
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MMI0_PPACB = 0x1B,
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MMI0_PEXT5 = 0x1E,
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MMI0_PPAC5 = 0x1F
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};
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// PS2-specific MMI1 Sub-Function Field (bits 0-5 within MMI_MMI1 group)
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enum MMI1Functions
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{
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MMI1_PABSW = 0x01,
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MMI1_PCEQW = 0x02,
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MMI1_PMINW = 0x03,
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MMI1_PADSBH = 0x04,
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MMI1_PABSH = 0x05,
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MMI1_PCEQH = 0x06,
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MMI1_PMINH = 0x07,
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MMI1_PCEQB = 0x0A,
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MMI1_PADDUW = 0x10,
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MMI1_PSUBUW = 0x11,
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MMI1_PEXTUW = 0x12,
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MMI1_PADDUH = 0x14,
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MMI1_PSUBUH = 0x15,
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MMI1_PEXTUH = 0x16,
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MMI1_PADDUB = 0x18,
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MMI1_PSUBUB = 0x19,
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MMI1_PEXTUB = 0x1A,
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MMI1_QFSRV = 0x1B
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};
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// PS2-specific MMI2 Sub-Function Field (bits 0-5 within MMI_MMI2 group)
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enum MMI2Functions
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{
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MMI2_PMADDW = 0x00,
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MMI2_PSLLVW = 0x02,
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MMI2_PSRLVW = 0x03,
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MMI2_PMSUBW = 0x04,
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MMI2_PMFHI = 0x08,
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MMI2_PMFLO = 0x09,
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MMI2_PINTH = 0x0A,
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MMI2_PMULTW = 0x0C,
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MMI2_PDIVW = 0x0D,
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MMI2_PCPYLD = 0x0E,
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MMI2_PMADDH = 0x10,
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MMI2_PHMADH = 0x11,
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MMI2_PAND = 0x12,
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MMI2_PXOR = 0x13,
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MMI2_PMSUBH = 0x14,
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MMI2_PHMSBH = 0x15,
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MMI2_PEXEH = 0x1A,
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MMI2_PREVH = 0x1B,
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MMI2_PMULTH = 0x1C,
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MMI2_PDIVBW = 0x1D,
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MMI2_PEXEW = 0x1E,
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MMI2_PROT3W = 0x1F
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};
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// PS2-specific MMI3 Sub-Function Field (bits 0-5 within MMI_MMI3 group)
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enum MMI3Functions
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{
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MMI3_PMADDUW = 0x00,
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MMI3_PSRAVW = 0x03,
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MMI3_PMTHI = 0x08, // Move To HI register
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MMI3_PMTLO = 0x09, // Move To LO register
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MMI3_PINTEH = 0x0A,
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MMI3_PMULTUW = 0x0C,
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MMI3_PDIVUW = 0x0D,
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MMI3_PCPYUD = 0x0E,
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MMI3_POR = 0x12,
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MMI3_PNOR = 0x13,
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MMI3_PEXCH = 0x1A,
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MMI3_PCPYH = 0x1B,
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MMI3_PEXCW = 0x1E
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};
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// PMFHL/PMTHL Sub-Function Field ('sa' field, bits 10-6)
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enum PMFHLFunctions
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{
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PMFHL_LW = 0x00, // Load Word / Lower Word
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PMFHL_UW = 0x01, // Upper Word
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PMFHL_SLW = 0x02, // Signed Lower Word
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PMFHL_LH = 0x03, // Load Halfword / Lower Halfword
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PMFHL_SH = 0x04 // Store Halfword / Signed Upper Halfword? (Doc name varies)
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};
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// COP0 Format Field ('fmt' or 'rs' field, bits 25-21) for OPCODE_COP0
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enum COP0Format
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{
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COP0_MF = 0x00, // Move From COP0 - MFC0 (fmt=00000)
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COP0_MT = 0x04, // Move To COP0 - MTC0 (fmt=00100)
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COP0_BC = 0x08, // BC0 group (fmt=01000) (see Cop0BranchCondition)
|
|
COP0_CO = 0x10 // COP0 Operation group (fmt=10000) (see Cop0CoFunctions)
|
|
};
|
|
|
|
// COP0 CO Function Field (bits 5-0) for COP0_CO Format
|
|
enum Cop0CoFunctions
|
|
{
|
|
COP0_CO_TLBR = 0x01, // TLB Read
|
|
COP0_CO_TLBWI = 0x02, // TLB Write Indexed
|
|
|
|
COP0_CO_TLBWR = 0x06, // TLB Write Random
|
|
|
|
COP0_CO_TLBP = 0x08, // TLB Probe
|
|
|
|
COP0_CO_ERET = 0x18, // Return from Exception
|
|
|
|
COP0_CO_EI = 0x38, // Enable Interrupts
|
|
COP0_CO_DI = 0x39 // Disable Interrupts
|
|
};
|
|
|
|
// COP0 BC Condition Field ('fmt' or 'rt' field, bits 20-16) for COP0_BC Format
|
|
enum Cop0BranchCondition
|
|
{
|
|
COP0_BC_BCF = 0x00, // Branch on Condition False
|
|
COP0_BC_BCT = 0x01, // Branch on Condition True
|
|
COP0_BC_BCFL = 0x02, // Branch on Condition False Likely
|
|
COP0_BC_BCTL = 0x03, // Branch on Condition True Likely
|
|
};
|
|
|
|
// COP0 Register Numbers (used with MFC0/MTC0)
|
|
enum COP0Reg
|
|
{
|
|
COP0_REG_INDEX = 0, // Index into TLB array
|
|
COP0_REG_RANDOM = 1, // Randomly generated index into TLB array
|
|
COP0_REG_ENTRYLO0 = 2, // Low half of TLB entry for even-numbered virtual pages
|
|
COP0_REG_ENTRYLO1 = 3, // Low half of TLB entry for odd-numbered virtual pages
|
|
COP0_REG_CONTEXT = 4, // Context
|
|
COP0_REG_PAGEMASK = 5, // TLB page size mask
|
|
COP0_REG_WIRED = 6, // Controls which TLB entries are affected by random replacement
|
|
|
|
COP0_REG_BADVADDR = 8, // Virtual address of most recent address-related exception
|
|
COP0_REG_COUNT = 9, // Timer count
|
|
COP0_REG_ENTRYHI = 10, // High half of TLB entry
|
|
COP0_REG_COMPARE = 11, // Timer compare value
|
|
COP0_REG_STATUS = 12, // Processor status and control
|
|
COP0_REG_CAUSE = 13, // Cause of last exception
|
|
COP0_REG_EPC = 14, // Exception program counter
|
|
COP0_REG_PRID = 15, // Processor identification and revision
|
|
COP0_REG_CONFIG = 16, // Configuration register
|
|
|
|
COP0_REG_BADPADDR = 23, // Bad physical address
|
|
COP0_REG_DEBUG = 24, // Debug register
|
|
COP0_REG_PERF = 25, // Performance counter
|
|
|
|
COP0_REG_TAGLO = 28, // Cache TagLo (I-Cache & D-Cache)
|
|
COP0_REG_TAGHI = 29, // High bits of cache tag ( Cache TagHi )
|
|
COP0_REG_ERROREPC = 30 // Error exception program counter
|
|
};
|
|
|
|
// COP1 (FPU) Format Field ('fmt' or 'rs' field, bits 25-21) for OPCODE_COP1
|
|
enum Cop1Format
|
|
{
|
|
COP1_MF = 0x00, // Move From FPU Register
|
|
COP1_CF = 0x02, // Move From FPU Control Register
|
|
COP1_MT = 0x04, // Move To FPU Register
|
|
COP1_CT = 0x06, // Move To FPU Control Register
|
|
COP1_BC = 0x08, // Branch on FPU Condition (see Cop1BranchCondition)
|
|
|
|
COP1_D = 0x11, // Standard MIPS Double format; EE FPU is single-precision, (unused on PS2 FPU?)
|
|
COP1_L = 0x15, // Long (64-bit integer) Operation (unused on PS2 FPU?)
|
|
|
|
COP1_S = 0x10, // Single Precision Operation (see Cop1FunctionsS)
|
|
COP1_W = 0x14 // Word (integer) Operation (see Cop1FunctionsW)
|
|
};
|
|
|
|
// COP1 Function Field (bits 5-0) for COP1_S Format (Single-Precision)
|
|
enum Cop1FunctionsS
|
|
{
|
|
COP1_S_ADD = 0x00, // ADD.S
|
|
COP1_S_SUB = 0x01, // SUB.S
|
|
COP1_S_MUL = 0x02, // MUL.S
|
|
COP1_S_DIV = 0x03, // DIV.S
|
|
COP1_S_SQRT = 0x04, // SQRT.S
|
|
COP1_S_ABS = 0x05, // ABS.S
|
|
COP1_S_MOV = 0x06, // MOV.S
|
|
COP1_S_NEG = 0x07, // NEG.S
|
|
|
|
COP1_S_ROUND_L = 0x08, // ROUND.L.S - Requires 64-bit int dest, likely unused
|
|
COP1_S_TRUNC_L = 0x09, // TRUNC.L.S - Requires 64-bit int dest, likely unused
|
|
COP1_S_CEIL_L = 0x0A, // CEIL.L.S - Requires 64-bit int dest, likely unused
|
|
COP1_S_FLOOR_L = 0x0B, // FLOOR.L.S - Requires 64-bit int dest, likely unused
|
|
COP1_S_ROUND_W = 0x0C, // ROUND.W.S
|
|
COP1_S_TRUNC_W = 0x0D, // TRUNC.W.S
|
|
COP1_S_CEIL_W = 0x0E, // CEIL.W.S
|
|
COP1_S_FLOOR_W = 0x0F, // FLOOR.W.S
|
|
|
|
// --- Additional Arithmetic/Functions (from FPU.S table) ---
|
|
COP1_S_RSQRT = 0x16, // RSQRT.S (Reciprocal Square Root)
|
|
COP1_S_ADDA = 0x18, // ADDA.S (Add Accumulator)
|
|
COP1_S_SUBA = 0x19, // SUBA.S (Subtract Accumulator)
|
|
COP1_S_MULA = 0x1A, // MULA.S (Multiply Accumulator)
|
|
COP1_S_MADD = 0x1C, // MADD.S (Multiply Add)
|
|
COP1_S_MSUB = 0x1D, // MSUB.S (Multiply Subtract)
|
|
COP1_S_MADDA = 0x1E, // MADDA.S (Multiply Add Accumulator)
|
|
COP1_S_MSUBA = 0x1F, // MSUBA.S (Multiply Subtract Accumulator)
|
|
|
|
// --- Conversions (from FPU.S table) ---
|
|
COP1_S_CVT_D = 0x21, // CVT.D.S - Requires double-precision FPU
|
|
COP1_S_CVT_W = 0x24, // CVT.W.S (Convert to Word)
|
|
COP1_S_CVT_L = 0x25, // CVT.L.S - Requires 64-bit int dest, likely unused
|
|
|
|
// --- Min/Max (from FPU.S table) ---
|
|
COP1_S_MAX = 0x28, // MAX.S
|
|
COP1_S_MIN = 0x29, // MIN.S
|
|
|
|
COP1_S_C_F = 0x30, // C.F.S (False)
|
|
COP1_S_C_UN = 0x31, // C.UN.S (Unordered)
|
|
COP1_S_C_EQ = 0x32, // C.EQ.S (Equal)
|
|
COP1_S_C_UEQ = 0x33, // C.UEQ.S (Unordered or Equal)
|
|
COP1_S_C_OLT = 0x34, // C.OLT.S (Ordered Less Than)
|
|
COP1_S_C_ULT = 0x35, // C.ULT.S (Unordered or Less Than)
|
|
COP1_S_C_OLE = 0x36, // C.OLE.S (Ordered Less Than or Equal)
|
|
COP1_S_C_ULE = 0x37, // C.ULE.S (Unordered or Less Than or Equal)
|
|
COP1_S_C_SF = 0x38, // C.SF.S (Signaling False)
|
|
COP1_S_C_NGLE = 0x39, // C.NGLE.S (Not Greater or Less or Equal - Unordered)
|
|
COP1_S_C_SEQ = 0x3A, // C.SEQ.S (Signaling Equal)
|
|
COP1_S_C_NGL = 0x3B, // C.NGL.S (Not Greater or Less - Unordered or Equal)
|
|
COP1_S_C_LT = 0x3C, // C.LT.S (Signaling Less Than)
|
|
COP1_S_C_NGE = 0x3D, // C.NGE.S (Not Greater or Equal - Unordered or Less Than)
|
|
COP1_S_C_LE = 0x3E, // C.LE.S (Signaling Less Than or Equal)
|
|
COP1_S_C_NGT = 0x3F, // C.NGT.S (Not Greater Than - Unordered or Less Than or Equal)
|
|
};
|
|
|
|
// COP1 Function Field (bits 5-0) for COP1_W Format (Word/Integer source)
|
|
enum Cop1FunctionsW
|
|
{
|
|
COP1_W_CVT_S = 0x20, // CVT.S.W (Convert Word Integer to Single Float)
|
|
// 0x21 --- (Standard MIPS: CVT.D.W - requires double-precision)
|
|
// 0x24 --- (Standard MIPS: CVT.W.W - Nop?)
|
|
// 0x25 --- (Standard MIPS: CVT.L.W - requires 64-bit int dest)
|
|
};
|
|
|
|
// COP1 BC Condition Field ('fmt' or 'rt' field, bits 20-16) for COP1_BC Format
|
|
enum Cop1BranchCondition
|
|
{
|
|
COP1_BC_BCF = 0x00, // Branch on FPU Condition False (BC1F)
|
|
COP1_BC_BCT = 0x01, // Branch on FPU Condition True (BC1T)
|
|
COP1_BC_BCFL = 0x02, // Branch on FPU Condition False Likely (BC1FL)
|
|
COP1_BC_BCTL = 0x03, // Branch on FPU Condition True Likely (BC1TL)
|
|
};
|
|
|
|
// COP2 (VU0 Macro) Format Field ('fmt' or 'rs' field, bits 25-21) for OPCODE_COP2
|
|
enum Cop2Format
|
|
{
|
|
// Note: Standard MIPS MFC2/MTC2 use fmt 0x00/0x04, EE uses QMFC2/QMTC2
|
|
COP2_QMFC2 = 0x01, // QMFC2 (fmt=00001) - Load Quadword From Coprocessor 2
|
|
COP2_CFC2 = 0x02, // CFC2 (fmt=00010) - Load Control Word From Coprocessor 2
|
|
COP2_QMTC2 = 0x05, // QMTC2 (fmt=00101) - Store Quadword To Coprocessor 2
|
|
COP2_CTC2 = 0x06, // CTC2 (fmt=00110) - Store Control Word To Coprocessor 2
|
|
COP2_BC = 0x08, // BC2 group (fmt=01000) (see Cop2BranchCondition)
|
|
COP2_CO = 0x10, // VU0 Macro Operation group (fmt=1xxxx)
|
|
};
|
|
|
|
// COP2 BC Condition Field ('fmt' or 'rt' field, bits 20-16) for COP2_BC Format
|
|
enum Cop2BranchCondition
|
|
{
|
|
COP2_BC_BCF = 0x00, // Branch on VU0 Condition False (BC2F)
|
|
COP2_BC_BCT = 0x01, // Branch on VU0 Condition True (BC2T)
|
|
COP2_BC_BCFL = 0x02, // Branch on VU0 Condition False Likely (BC2FL)
|
|
COP2_BC_BCTL = 0x03, // Branch on VU0 Condition True Likely (BC2TL)
|
|
};
|
|
|
|
// VU0 Macro Function Field (bits 5-0) for COP2_CO Format (Special1 Table)
|
|
enum VU0MacroSpecial1Functions : uint8_t
|
|
{
|
|
VU0_S1_VADDx = 0x00,
|
|
VU0_S1_VADDy = 0x01,
|
|
VU0_S1_VADDz = 0x02,
|
|
VU0_S1_VADDw = 0x03,
|
|
VU0_S1_VSUBx = 0x04,
|
|
VU0_S1_VSUBy = 0x05,
|
|
VU0_S1_VSUBz = 0x06,
|
|
VU0_S1_VSUBw = 0x07,
|
|
VU0_S1_VMADDx = 0x08,
|
|
VU0_S1_VMADDy = 0x09,
|
|
VU0_S1_VMADDz = 0x0A,
|
|
VU0_S1_VMADDw = 0x0B,
|
|
VU0_S1_VMSUBx = 0x0C,
|
|
VU0_S1_VMSUBy = 0x0D,
|
|
VU0_S1_VMSUBz = 0x0E,
|
|
VU0_S1_VMSUBw = 0x0F,
|
|
VU0_S1_VMAXx = 0x10,
|
|
VU0_S1_VMAXy = 0x11,
|
|
VU0_S1_VMAXz = 0x12,
|
|
VU0_S1_VMAXw = 0x13,
|
|
VU0_S1_VMINIx = 0x14,
|
|
VU0_S1_VMINIy = 0x15,
|
|
VU0_S1_VMINIz = 0x16,
|
|
VU0_S1_VMINIw = 0x17,
|
|
VU0_S1_VMULx = 0x18,
|
|
VU0_S1_VMULy = 0x19,
|
|
VU0_S1_VMULz = 0x1A,
|
|
VU0_S1_VMULw = 0x1B,
|
|
VU0_S1_VMULq = 0x1C,
|
|
VU0_S1_VMAXi = 0x1D,
|
|
VU0_S1_VMULi = 0x1E,
|
|
VU0_S1_VMINIi = 0x1F,
|
|
VU0_S1_VADDq = 0x20,
|
|
VU0_S1_VMADDq = 0x21,
|
|
VU0_S1_VADDi = 0x22,
|
|
VU0_S1_VMADDi = 0x23,
|
|
VU0_S1_VSUBq = 0x24,
|
|
VU0_S1_VMSUBq = 0x25,
|
|
VU0_S1_VSUBi = 0x26,
|
|
VU0_S1_VMSUBi = 0x27,
|
|
VU0_S1_VADD = 0x28,
|
|
VU0_S1_VMADD = 0x29,
|
|
VU0_S1_VMUL = 0x2A,
|
|
VU0_S1_VMAX = 0x2B,
|
|
VU0_S1_VSUB = 0x2C,
|
|
VU0_S1_VMSUB = 0x2D,
|
|
VU0_S1_VOPMSUB = 0x2E,
|
|
VU0_S1_VMINI = 0x2F,
|
|
VU0_S1_VIADD = 0x30,
|
|
VU0_S1_VISUB = 0x31,
|
|
VU0_S1_VIADDI = 0x32,
|
|
VU0_S1_VIAND = 0x34,
|
|
VU0_S1_VIOR = 0x35,
|
|
VU0_S1_VCALLMS = 0x38,
|
|
VU0_S1_VCALLMSR = 0x39,
|
|
};
|
|
|
|
// VU0 Macro Function Field (bits 5-0) for COP2_CO Format (Special2 Table)
|
|
enum VU0MacroSpecial2Functions : uint8_t
|
|
{
|
|
VU0_S2_VADDAx = 0x00,
|
|
VU0_S2_VADDAy = 0x01,
|
|
VU0_S2_VADDAz = 0x02,
|
|
VU0_S2_VADDAw = 0x03,
|
|
VU0_S2_VSUBAx = 0x04,
|
|
VU0_S2_VSUBAy = 0x05,
|
|
VU0_S2_VSUBAz = 0x06,
|
|
VU0_S2_VSUBAw = 0x07,
|
|
VU0_S2_VMADDAx = 0x08,
|
|
VU0_S2_VMADDAy = 0x09,
|
|
VU0_S2_VMADDAz = 0x0A,
|
|
VU0_S2_VMADDAw = 0x0B,
|
|
VU0_S2_VMSUBAx = 0x0C,
|
|
VU0_S2_VMSUBAy = 0x0D,
|
|
VU0_S2_VMSUBAz = 0x0E,
|
|
VU0_S2_VMSUBAw = 0x0F,
|
|
VU0_S2_VITOF0 = 0x10,
|
|
VU0_S2_VITOF4 = 0x11,
|
|
VU0_S2_VITOF12 = 0x12,
|
|
VU0_S2_VITOF15 = 0x13,
|
|
VU0_S2_VFTOI0 = 0x14,
|
|
VU0_S2_VFTOI4 = 0x15,
|
|
VU0_S2_VFTOI12 = 0x16,
|
|
VU0_S2_VFTOI15 = 0x17,
|
|
VU0_S2_VMULAx = 0x18,
|
|
VU0_S2_VMULAy = 0x19,
|
|
VU0_S2_VMULAz = 0x1A,
|
|
VU0_S2_VMULAw = 0x1B,
|
|
VU0_S2_VMULAq = 0x1C,
|
|
VU0_S2_VABS = 0x1D,
|
|
VU0_S2_VMULAi = 0x1E,
|
|
VU0_S2_VCLIPw = 0x1F,
|
|
VU0_S2_VADDAq = 0x20,
|
|
VU0_S2_VMADDAq = 0x21,
|
|
VU0_S2_VADDAi = 0x22,
|
|
VU0_S2_VMADDAi = 0x23,
|
|
VU0_S2_VSUBAq = 0x24,
|
|
VU0_S2_VMSUBAq = 0x25,
|
|
VU0_S2_VSUBAi = 0x26,
|
|
VU0_S2_VMSUBAi = 0x27,
|
|
VU0_S2_VADDA = 0x28,
|
|
VU0_S2_VMADDA = 0x29,
|
|
VU0_S2_VMULA = 0x2A,
|
|
VU0_S2_VSUBA = 0x2C,
|
|
VU0_S2_VMSUBA = 0x2D,
|
|
VU0_S2_VOPMULA = 0x2E,
|
|
VU0_S2_VNOP = 0x2F,
|
|
VU0_S2_VMOVE = 0x30,
|
|
VU0_S2_VMR32 = 0x31,
|
|
VU0_S2_VLQI = 0x34,
|
|
VU0_S2_VSQI = 0x35,
|
|
VU0_S2_VLQD = 0x36,
|
|
VU0_S2_VSQD = 0x37,
|
|
VU0_S2_VDIV = 0x38,
|
|
VU0_S2_VSQRT = 0x39,
|
|
VU0_S2_VRSQRT = 0x3A,
|
|
VU0_S2_VWAITQ = 0x3B,
|
|
VU0_S2_VMTIR = 0x3C,
|
|
VU0_S2_VMFIR = 0x3D,
|
|
VU0_S2_VILWR = 0x3E,
|
|
VU0_S2_VISWR = 0x3F,
|
|
VU0_S2_VRNEXT = 0x40,
|
|
VU0_S2_VRGET = 0x41,
|
|
VU0_S2_VRINIT = 0x42,
|
|
VU0_S2_VRXOR = 0x43
|
|
};
|
|
|
|
// // VU0 macro instruction function codes (subset - there are many more)
|
|
// enum VU0MacroFunctions
|
|
// {
|
|
// VU0_VADD = 0x00,
|
|
// VU0_VSUB = 0x01,
|
|
// VU0_VMUL = 0x02,
|
|
// VU0_VDIV = 0x03,
|
|
// VU0_VSQRT = 0x04,
|
|
// VU0_VRSQRT = 0x05,
|
|
// VU0_VMULQ = 0x06,
|
|
// VU0_VIADD = 0x10,
|
|
// VU0_VISUB = 0x11,
|
|
// VU0_VIADDI = 0x12,
|
|
// VU0_VIAND = 0x13,
|
|
// VU0_VIOR = 0x14,
|
|
// VU0_VILWR = 0x15,
|
|
// VU0_VISWR = 0x16,
|
|
// VU0_VCALLMS = 0x20,
|
|
// VU0_VCALLMSR = 0x21,
|
|
// VU0_VRGET = 0x3F, // Get VU0 R register
|
|
// VU0_VSUB_XYZ = 0x38 // Subtract with component selection
|
|
// };
|
|
|
|
// enum VU0SpecialFormats
|
|
// {
|
|
// VU0_BC2F = 0x11, // Branch on VU0 condition false
|
|
// VU0_MTVUCF = 0x13, // Move To VU0 control/flag register
|
|
// VU0_CTCVU = 0x18, // Control To VU0 with specific functionality
|
|
// VU0_VMTIR = 0x1C, // Move To VU0 I Register
|
|
// VU0_VCLIP = 0x1E, // VU0 Clipping operation
|
|
// VU0_VLDQ = 0x1F // VU0 Load/Store Quad with Decrement
|
|
// };
|
|
|
|
// VU0 COP2 control register numbers used by CFC2/CTC2.
|
|
// Registers 0..15 address VI0..VI15 directly.
|
|
enum VU0ControlRegisters
|
|
{
|
|
VU0_CR_STATUS = 16,
|
|
VU0_CR_MAC = 17,
|
|
VU0_CR_CLIP = 18,
|
|
VU0_CR_R = 20,
|
|
VU0_CR_I = 21,
|
|
VU0_CR_Q = 22,
|
|
VU0_CR_TPC = 26,
|
|
VU0_CR_CMSAR0 = 27,
|
|
VU0_CR_FBRST = 28,
|
|
VU0_CR_VPU_STAT = 29,
|
|
VU0_CR_CMSAR1 = 31
|
|
};
|
|
enum VU0OPSFunctions
|
|
{
|
|
VU0OPS_QMFC2_NI = 0x00, // Non-incrementing QMFC2
|
|
VU0OPS_QMFC2_I = 0x01, // Incrementing QMFC2
|
|
VU0OPS_QMTC2_NI = 0x02, // Non-incrementing QMTC2
|
|
VU0OPS_QMTC2_I = 0x03, // Incrementing QMTC2
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VU0OPS_VMFIR = 0x04, // Move From Integer Register
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VU0OPS_VXITOP = 0x08, // Execute Interrupt on VU0
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VU0OPS_VWAITQ = 0x3B, // Wait for Q register operations to complete
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VU0OPS_VMFHL = 0x1C, // Move from High / Low(similar to PMFHL)
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VU0OPS_VMTIR = 0x3C // Move to VU0 I Register with function code
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};
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enum VU0OPSFunctionsExtra
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{
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VU0_VCALLMS_DIRECT = 0x00,
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VU0_VCALLMS_REG = 0x01
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};
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enum VU0SpecialMasks
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{
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VU0_FIELD_MASK = 0xF, // Mask for vector field selection
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VU0_FIELD_SHIFT = 21, // Shift amount for field selection
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VU0_STORE_BIT = 0x80, // Bit indicating store operation
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VU0_SUBOP_MASK = 0x1F, // Mask for sub-operation code
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VU0_SUBOP_SHIFT = 6, // Shift amount for sub-operation
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VU0_SQC0 = 0x8 // SQC0 instruction code
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};
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enum VU0FormatsExtra
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{
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VU0_FMT_MACRO_MOVE = 0x1, // Move between VU registers format
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VU0_FMT_VIF_STATUS = 0x5, // VIF status operations
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VU0_FMT_VCALLMS = 0x14, // VU0 microprogram call format
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VU0_FMT_LQSQ_COP0 = 0x1B // Load/store quad VU0 format
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};
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// Instruction decoding helper macros
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#define OPCODE(inst) ((inst >> 26) & 0x3F)
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#define RS(inst) ((inst >> 21) & 0x1F)
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#define RT(inst) ((inst >> 16) & 0x1F)
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#define RD(inst) ((inst >> 11) & 0x1F)
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#define SA(inst) ((inst >> 6) & 0x1F)
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#define FUNCTION(inst) ((inst) & 0x3F)
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#define IMMEDIATE(inst) ((inst) & 0xFFFF)
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#define SIMMEDIATE(inst) ((int32_t)(int16_t)((inst) & 0xFFFF))
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#define TARGET(inst) ((inst) & 0x3FFFFFF)
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#define COP_FUNCT(inst) ((uint8_t)((inst) & 0x3F)) // Function field for COPz CO instructions
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#define FPU_FMT(inst) ((uint8_t)(((inst) >> 21) & 0x1F)) // Format field for FPU instructions
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#define FT(inst) RT(inst) // Target FPU register
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#define FS(inst) RD(inst) // Source FPU register
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#define FD(inst) SA(inst) // Destination FPU register
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#define VU_I(inst) ((inst >> 25) & 0x1) // VU Upper I bit
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#define VU_E(inst) ((inst >> 24) & 0x1) // VU Upper E bit
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#define VU_M(inst) ((inst >> 23) & 0x1) // VU Upper M bit (VU0 only)
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#define VU_D(inst) ((inst >> 22) & 0x1) // VU Upper D bit
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#define VU_T(inst) ((inst >> 21) & 0x1) // VU Upper T bit
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#define VU_DEST(inst) ((uint8_t)(((inst) >> 16) & 0xF)) // VU Destination mask
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#define VU_FSF(inst) ((uint8_t)(((inst) >> 10) & 0x3)) // VU Source Field F
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#define VU_FTF(inst) ((uint8_t)(((inst) >> 8) & 0x3)) // VU Target Field F
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#define VU_FD(inst) ((uint8_t)(((inst) >> 11) & 0x1F)) // VU Destination Vector Register
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#define VU_FS(inst) ((uint8_t)(((inst) >> 6) & 0x1F)) // VU Source Vector Register
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#define VU_FT(inst) ((uint8_t)((inst) & 0x1F)) // VU Target Vector Register
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#define VU_IS(inst) RT(inst) // VU Source Integer Register
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#define VU_IT(inst) RD(inst) // VU Target Integer Register
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#define VU_ID(inst) SA(inst) // VU Destination Integer Register
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#define VU_IMM5(inst) ((uint8_t)((inst >> 6) & 0x1F)) // VU 5-bit immediate
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#define VU_IMM11(inst) ((uint16_t)((inst) & 0x7FF)) // VU 11-bit immediate
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#define VU_SIMM11(inst) ((int16_t)(((inst & 0x7FF) ^ 0x400) - 0x400)) // VU 11-bit signed immediate
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#define VU_IMM15(inst) ((uint16_t)((inst) & 0x7FFF)) // VU 15-bit immediate
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} // namespace ps2recomp
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#endif // PS2RECOMP_INSTRUCTIONS_H
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