mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-09-26 16:59:35 -04:00
Ranieri
669114f3f6
* feat: small fixes on code gen * feat: added code gen test * feat: rename IOP * fix: fix special case on JR feat: added code generator test * feat: ps2 logs now need special macros * feat: a lot of regressions test feat: use test to fix bugs on runtime fix: fix incorrect instructions on code generator feat: added missing decode on r5900 decoder feat: added scissor on rasterizer * feat: better ghidra plugin analyzer fix: fix real bug on function finding on elf analyzer * feat: some logs on GS feat: added more syscalls stubs feat: added more ps2 stubs * feat: added missing stub
221 lines
10 KiB
C++
221 lines
10 KiB
C++
#include "MiniTest.h"
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#include "ps2recomp/r5900_decoder.h"
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using namespace ps2recomp;
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void register_r5900_decoder_tests()
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{
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MiniTest::Case("R5900Decoder", [](TestCase &tc)
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{
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tc.Run("decodes JAL with jump target and call flag", [](TestCase &t) {
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// jal 0x00400000 at address 0x1000 => opcode 0x0C100000 (target = 0x00400000 >> 2)
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uint32_t address = 0x1000;
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uint32_t target = 0x00400000;
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uint32_t raw = (OPCODE_JAL << 26) | ((target >> 2) & 0x03FFFFFF);
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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t.IsTrue(inst.isJump, "jal should be marked as jump");
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t.IsTrue(inst.isCall, "jal should be marked as call");
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t.IsTrue(inst.hasDelaySlot, "jal has a delay slot");
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t.Equals(decoder.getJumpTarget(inst), target, "jal jump target should match encoded target");
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});
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tc.Run("J computes target with upper PC bits", [](TestCase &t) {
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// Place J at address 0x8FFF_FFFC targeting 0x8123_4560 (upper bits from PC+4)
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uint32_t address = 0x8FFFFFFC;
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uint32_t encodedTarget = 0x0123456; // 0x048D1598 >> 2, but we want lower bits of 0x1234560
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uint32_t raw = (OPCODE_J << 26) | (encodedTarget & 0x03FFFFFF);
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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uint32_t expectedPcUpper = (address + 4) & 0xF0000000;
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uint32_t expected = expectedPcUpper | (encodedTarget << 2);
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t.Equals(decoder.getJumpTarget(inst), expected, "J target should combine PC upper bits with encoded target");
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});
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tc.Run("JR/JALR jump target is zero (dynamic)", [](TestCase &t) {
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uint32_t address = 0x1200;
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uint32_t jrRaw = (OPCODE_SPECIAL << 26) | (2 << 21) | SPECIAL_JR;
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uint32_t jalrRaw = (OPCODE_SPECIAL << 26) | (3 << 21) | (31 << 11) | SPECIAL_JALR;
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R5900Decoder decoder;
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Instruction jr = decoder.decodeInstruction(address, jrRaw);
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Instruction jalr = decoder.decodeInstruction(address + 4, jalrRaw);
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t.Equals(decoder.getJumpTarget(jr), 0u, "JR jump target should be unknown (0)");
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t.Equals(decoder.getJumpTarget(jalr), 0u, "JALR jump target should be unknown (0)");
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});
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tc.Run("decodes BEQ sets branch flags and target", [](TestCase &t) {
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// beq r1, r2, offset 0x4 (word offset) at address 0x2000
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uint32_t address = 0x2000;
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uint16_t offset = 0x0004;
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uint32_t raw = (OPCODE_BEQ << 26) | (1 << 21) | (2 << 16) | offset;
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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t.IsTrue(inst.isBranch, "beq should be marked as branch");
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t.IsTrue(inst.hasDelaySlot, "beq has a delay slot");
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uint32_t expectedTarget = address + 4 + (static_cast<int16_t>(offset) << 2);
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t.Equals(decoder.getBranchTarget(inst), expectedTarget, "beq target should be computed from simmediate");
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});
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tc.Run("branch target sign-extends negative offset", [](TestCase &t) {
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uint32_t address = 0x2100;
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int16_t negOffset = -4; // jump back 16 bytes
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uint32_t raw = (OPCODE_BNE << 26) | (1 << 21) | (2 << 16) | (negOffset & 0xFFFF);
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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uint32_t expectedTarget = address + 4 + (static_cast<int16_t>(negOffset) << 2);
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t.Equals(decoder.getBranchTarget(inst), expectedTarget, "negative branch offsets should sign-extend");
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});
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tc.Run("decodes load/store flags", [](TestCase &t) {
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uint32_t address = 0x3000;
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uint32_t lwRaw = (OPCODE_LW << 26) | (1 << 21) | (2 << 16) | 0x10;
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uint32_t swRaw = (OPCODE_SW << 26) | (3 << 21) | (4 << 16) | 0x20;
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R5900Decoder decoder;
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Instruction lw = decoder.decodeInstruction(address, lwRaw);
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Instruction sw = decoder.decodeInstruction(address + 4, swRaw);
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t.IsTrue(lw.isLoad, "lw should be marked as load");
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t.IsFalse(lw.isStore, "lw should not be marked as store");
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t.IsTrue(sw.isStore, "sw should be marked as store");
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t.IsFalse(sw.isLoad, "sw should not be marked as load");
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});
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tc.Run("JR is marked as return when rs is $ra", [](TestCase &t) {
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uint32_t address = 0x4000;
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uint32_t raw = (OPCODE_SPECIAL << 26) | (31 << 21) | SPECIAL_JR; // jr $ra
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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t.IsTrue(inst.isJump, "jr should be jump");
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t.IsTrue(inst.isReturn, "jr $ra should be marked as return");
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t.IsTrue(inst.hasDelaySlot, "jr has delay slot");
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});
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tc.Run("JALR marks call and writes rd when non-zero", [](TestCase &t) {
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uint32_t address = 0x5000;
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uint32_t rd = 5;
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uint32_t raw = (OPCODE_SPECIAL << 26) | (2 << 21) | (rd << 11) | SPECIAL_JALR; // jalr $v0, $a0
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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t.IsTrue(inst.isJump, "jalr should be jump");
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t.IsTrue(inst.isCall, "jalr should be call");
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t.IsTrue(inst.hasDelaySlot, "jalr has delay slot");
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t.IsTrue(inst.modificationInfo.modifiesGPR, "jalr with rd!=0 should mark GPR modification");
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});
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tc.Run("R5900 MULT marks rd modification when rd is non-zero", [](TestCase &t) {
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uint32_t address = 0x5800;
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uint32_t rawWithRd = (OPCODE_SPECIAL << 26) | (4 << 21) | (5 << 16) | (3 << 11) | SPECIAL_MULT;
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uint32_t rawRdZero = (OPCODE_SPECIAL << 26) | (4 << 21) | (5 << 16) | (0 << 11) | SPECIAL_MULT;
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R5900Decoder decoder;
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Instruction withRd = decoder.decodeInstruction(address, rawWithRd);
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Instruction rdZero = decoder.decodeInstruction(address + 4, rawRdZero);
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t.IsTrue(withRd.modificationInfo.modifiesControl, "MULT should modify HI/LO");
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t.IsTrue(withRd.modificationInfo.modifiesGPR, "MULT should mark rd modification when rd!=0");
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t.IsFalse(rdZero.modificationInfo.modifiesGPR, "MULT should not mark rd modification when rd==0");
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});
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tc.Run("R5900 MMI MULT1 marks rd modification when rd is non-zero", [](TestCase &t) {
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uint32_t address = 0x5900;
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uint32_t raw = (OPCODE_MMI << 26) | (6 << 21) | (7 << 16) | (8 << 11) | MMI_MULT1;
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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t.IsTrue(inst.modificationInfo.modifiesControl, "MULT1 should modify HI1/LO1");
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t.IsTrue(inst.modificationInfo.modifiesGPR, "MULT1 should mark rd modification when rd!=0");
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});
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tc.Run("MMI instruction sets MMI flags", [](TestCase &t) {
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uint32_t address = 0x6000;
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// Use opcode 0x1C (MMI), rs=1, rt=2, rd=3, sa=MMI0_PADDW (0)
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uint32_t raw = (OPCODE_MMI << 26) | (1 << 21) | (2 << 16) | (3 << 11) | MMI0_PADDW;
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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t.IsTrue(inst.isMMI, "MMI opcode should set isMMI");
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t.IsTrue(inst.isMultimedia, "MMI opcode should set multimedia flag");
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t.Equals(inst.mmiType, static_cast<uint8_t>(0), "MMI0 should set mmiType to 0");
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t.Equals(inst.mmiFunction, static_cast<uint8_t>(MMI0_PADDW), "MMI function should match sa field");
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});
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tc.Run("COP2 VU macro op marks VU flags", [](TestCase &t) {
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uint32_t address = 0x7000;
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uint8_t s2op = VU0_S2_VDIV; // 0x38
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uint8_t fhi = s2op >> 2; // 0x0E -> bits[10:6]
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uint8_t flo = s2op & 0x3; // 0x00 -> bits[1:0]
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uint32_t raw = (OPCODE_COP2 << 26) | (COP2_CO << 21) | (fhi << 6) | (0x3C | flo);
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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t.IsTrue(inst.isVU, "VU macro should set isVU");
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t.IsTrue(inst.isMultimedia, "VU macro should set multimedia");
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t.IsTrue(inst.modificationInfo.modifiesControl, "VDIV should mark control modification");
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t.IsTrue(inst.vectorInfo.usesQReg, "VDIV should use Q register");
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uint8_t expectedVecField = static_cast<uint8_t>((raw >> 21) & 0xF);
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t.Equals(inst.vectorInfo.vectorField, expectedVecField, "vector field should reflect encoding");
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});
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tc.Run("REGIMM branch and link marks call and GPR modification", [](TestCase &t) {
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uint32_t address = 0x8000;
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uint16_t offset = 0x2;
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uint32_t raw = (OPCODE_REGIMM << 26) | (1 << 21) | (REGIMM_BGEZAL << 16) | offset;
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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t.IsTrue(inst.isBranch, "bgezal should be branch");
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t.IsTrue(inst.isCall, "bgezal should be call (link)");
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t.IsTrue(inst.hasDelaySlot, "bgezal has delay slot");
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t.IsTrue(inst.modificationInfo.modifiesGPR, "bgezal should mark GPR modification for $ra");
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uint32_t expectedTarget = address + 4 + (static_cast<int16_t>(offset) << 2);
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t.Equals(decoder.getBranchTarget(inst), expectedTarget, "bgezal target should be computed");
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});
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tc.Run("LL/SC modify control and set load/store flags", [](TestCase &t) {
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uint32_t address = 0x9000;
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uint32_t llRaw = (OPCODE_LL << 26) | (2 << 21) | (3 << 16) | 0x10;
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uint32_t scRaw = (OPCODE_SC << 26) | (4 << 21) | (5 << 16) | 0x20;
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R5900Decoder decoder;
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Instruction ll = decoder.decodeInstruction(address, llRaw);
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Instruction sc = decoder.decodeInstruction(address + 4, scRaw);
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t.IsTrue(ll.isLoad, "ll should be load");
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t.IsTrue(ll.modificationInfo.modifiesControl, "ll should modify control (LL bit)");
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t.IsTrue(sc.isStore, "sc should be store");
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t.IsTrue(sc.modificationInfo.modifiesControl, "sc should modify control (LL bit)");
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t.IsTrue(sc.modificationInfo.modifiesGPR, "sc writes success flag to rt");
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});
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tc.Run("COP0 ERET is marked as return without delay slot", [](TestCase &t) {
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uint32_t address = 0xA000;
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uint32_t raw = (OPCODE_COP0 << 26) | (COP0_CO << 21) | COP0_CO_ERET;
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R5900Decoder decoder;
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Instruction inst = decoder.decodeInstruction(address, raw);
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t.IsTrue(inst.isReturn, "eret should be marked as return");
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t.IsFalse(inst.hasDelaySlot, "eret should not have a delay slot");
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t.IsTrue(inst.modificationInfo.modifiesControl, "eret changes control state");
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}); });
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}
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