mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-10-01 10:26:07 -04:00
Antonio Guastella
4961710407
* Add missing VU0 Special1 macro translations * Fix VU0 macro decode and field ops Align Special2 decoding with fhi_flo, implement VCLIPw/VABS, and fix field variants (VADDx/VSUBx/VMULx). Keep C++17 compatibility by replacing unordered_set::contains and remove dead ADDIU return. Update Special2 metadata for VWAITQ. * vu0: complete macro mappings and add coverage test * review: clean up vu macro handling * fix: restore C++20 contains in code generator * fix: correct VU0 Special2 instruction encoding in decoder test --------- Co-authored-by: Antonio Guastella <antonioguastella@energine.it> Co-authored-by: Ranieri <ran-junior@hotmail.com>
1001 lines
30 KiB
C++
1001 lines
30 KiB
C++
#include "ps2recomp/r5900_decoder.h"
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#include "rabbitizer.h"
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#include <iostream>
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namespace ps2recomp
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{
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R5900Decoder::R5900Decoder()
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{
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}
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R5900Decoder::~R5900Decoder()
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{
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}
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Instruction R5900Decoder::decodeInstruction(uint32_t address, uint32_t rawInstruction) const
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{
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Instruction inst;
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inst.address = address;
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inst.raw = rawInstruction;
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inst.opcode = OPCODE(rawInstruction);
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inst.rs = RS(rawInstruction);
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inst.rt = RT(rawInstruction);
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inst.rd = RD(rawInstruction);
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inst.sa = SA(rawInstruction);
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inst.function = FUNCTION(rawInstruction);
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inst.immediate = IMMEDIATE(rawInstruction);
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inst.simmediate = SIMMEDIATE(rawInstruction);
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inst.target = TARGET(rawInstruction);
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inst.isMMI = false;
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inst.isVU = false;
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inst.isBranch = false;
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inst.isJump = false;
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inst.isCall = false;
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inst.isReturn = false;
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inst.hasDelaySlot = false;
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inst.isMultimedia = false;
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inst.isLoad = false;
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inst.isStore = false;
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inst.isMmio = false;
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// Initialize the enhanced fields
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inst.mmiType = 0;
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inst.mmiFunction = 0;
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inst.pmfhlVariation = 0;
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inst.vuFunction = 0;
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inst.mmioAddress = 0;
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inst.vectorInfo.isVector = false;
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inst.vectorInfo.usesQReg = false;
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inst.vectorInfo.usesPReg = false;
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inst.vectorInfo.modifiesMAC = false;
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inst.vectorInfo.vectorField = 0xF; // All fields (xyzw)
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inst.modificationInfo.modifiesGPR = false;
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inst.modificationInfo.modifiesFPR = false;
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inst.modificationInfo.modifiesVFR = false;
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inst.modificationInfo.modifiesVIR = false;
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inst.modificationInfo.modifiesVIC = false;
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inst.modificationInfo.modifiesMemory = false;
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inst.modificationInfo.modifiesControl = false;
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RabbitizerInstruction rabbitizerInst;
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RabbitizerInstructionR5900_init(&rabbitizerInst, rawInstruction, address);
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RabbitizerInstructionR5900_processUniqueId(&rabbitizerInst);
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const RabbitizerInstrDescriptor *desc = rabbitizerInst.descriptor;
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inst.isBranch = RabbitizerInstrDescriptor_isBranch(desc);
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inst.isJump = RabbitizerInstrDescriptor_isJump(desc);
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inst.isCall = RabbitizerInstruction_isFunctionCall(&rabbitizerInst);
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inst.isReturn = RabbitizerInstruction_isReturn(&rabbitizerInst) ||
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rabbitizerInst.uniqueId == RABBITIZER_INSTR_ID_cpu_eret;
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inst.hasDelaySlot = RabbitizerInstruction_hasDelaySlot(&rabbitizerInst);
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inst.isLoad = RabbitizerInstrDescriptor_doesLoad(desc);
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inst.isStore = RabbitizerInstrDescriptor_doesStore(desc);
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inst.isMMI = inst.opcode == OPCODE_MMI;
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inst.isVU = inst.opcode == OPCODE_COP2 ||
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inst.opcode == OPCODE_LWC2 ||
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inst.opcode == OPCODE_LDC2 ||
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inst.opcode == OPCODE_SWC2 ||
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inst.opcode == OPCODE_SDC2;
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bool modifiesGpr = false;
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if (RabbitizerInstrDescriptor_modifiesRs(desc) && inst.rs != 0)
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{
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modifiesGpr = true;
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}
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if (RabbitizerInstrDescriptor_modifiesRt(desc) && inst.rt != 0)
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{
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modifiesGpr = true;
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}
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if (RabbitizerInstrDescriptor_modifiesRd(desc) && inst.rd != 0)
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{
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modifiesGpr = true;
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}
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if (RabbitizerInstrDescriptor_doesLink(desc))
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{
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modifiesGpr = true;
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}
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inst.modificationInfo.modifiesGPR = modifiesGpr;
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inst.modificationInfo.modifiesFPR = RabbitizerInstrDescriptor_modifiesFs(desc) ||
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RabbitizerInstrDescriptor_modifiesFt(desc) ||
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RabbitizerInstrDescriptor_modifiesFd(desc);
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inst.modificationInfo.modifiesMemory = RabbitizerInstrDescriptor_doesStore(desc);
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inst.modificationInfo.modifiesControl = RabbitizerInstrDescriptor_isBranch(desc) ||
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RabbitizerInstrDescriptor_isJump(desc) ||
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RabbitizerInstrDescriptor_isTrap(desc) ||
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RabbitizerInstrDescriptor_modifiesHI(desc) ||
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RabbitizerInstrDescriptor_modifiesLO(desc);
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if (rabbitizerInst.uniqueId == RABBITIZER_INSTR_ID_cpu_eret)
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{
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inst.isReturn = true;
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inst.hasDelaySlot = false;
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inst.modificationInfo.modifiesControl = true;
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}
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if (inst.opcode == OPCODE_LL || inst.opcode == OPCODE_LLD)
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{
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inst.isLoad = true;
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inst.modificationInfo.modifiesControl = true;
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if (inst.rt != 0)
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{
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inst.modificationInfo.modifiesGPR = true;
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}
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}
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if (inst.opcode == OPCODE_SC || inst.opcode == OPCODE_SCD)
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{
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inst.isStore = true;
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inst.modificationInfo.modifiesControl = true;
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if (inst.rt != 0)
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{
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inst.modificationInfo.modifiesGPR = true; // success flag to rt
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}
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}
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if (inst.opcode == OPCODE_COP2)
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{
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decodeCOP2(inst);
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}
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else if (inst.opcode == OPCODE_LWC2 || inst.opcode == OPCODE_LDC2)
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{
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inst.isVU = true;
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inst.modificationInfo.modifiesVFR = true;
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}
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else if (inst.opcode == OPCODE_SWC2 || inst.opcode == OPCODE_SDC2)
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{
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inst.isVU = true;
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inst.modificationInfo.modifiesMemory = true;
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}
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if (inst.opcode == OPCODE_LQ || inst.opcode == OPCODE_SQ)
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{
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inst.isMultimedia = true;
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}
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if (inst.isMMI || inst.isVU)
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{
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inst.isMultimedia = true;
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inst.vectorInfo.isVector = inst.isVU; // Only VU ops are truly vector
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}
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RabbitizerInstructionR5900_destroy(&rabbitizerInst);
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return inst;
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}
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void R5900Decoder::decodeRType(Instruction &inst) const
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{
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// R-type instructions already have all fields set correctly
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if (inst.rd != 0)
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inst.modificationInfo.modifiesGPR = true;
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}
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void R5900Decoder::decodeIType(Instruction &inst) const
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{
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// I-type instructions already have all fields set correctly
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if (!inst.isStore && !inst.isBranch && inst.rt != 0)
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{
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inst.modificationInfo.modifiesGPR = true;
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}
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}
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void R5900Decoder::decodeJType(Instruction &inst) const
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{
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// J-type instructions already have all fields set correctly
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inst.isJump = true;
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inst.hasDelaySlot = true;
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inst.modificationInfo.modifiesControl = true; // PC
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if (inst.opcode == OPCODE_JAL)
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{
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inst.isCall = true;
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inst.modificationInfo.modifiesGPR = true; // $ra (r[31])
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}
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}
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void R5900Decoder::decodeSpecial(Instruction &inst) const
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{
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if (inst.rd != 0)
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inst.modificationInfo.modifiesGPR = true;
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switch (inst.function)
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{
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case SPECIAL_JR:
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inst.isJump = true;
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inst.hasDelaySlot = true;
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inst.modificationInfo.modifiesGPR = false; // Doesn't modify GPR itself
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inst.modificationInfo.modifiesControl = true; // PC
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if (inst.rs == 31)
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{
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// jr $ra is typically a return
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inst.isReturn = true;
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}
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break;
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case SPECIAL_JALR:
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inst.isJump = true;
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inst.isCall = true;
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inst.hasDelaySlot = true;
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if (inst.rd == 0)
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inst.modificationInfo.modifiesGPR = false; // JALR $zero, $rs is like JR $rs
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else
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inst.modificationInfo.modifiesGPR = true;
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inst.modificationInfo.modifiesControl = true; // PC
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break;
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case SPECIAL_SYSCALL:
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case SPECIAL_BREAK:
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// Special handling for syscall/break
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inst.modificationInfo.modifiesGPR = false; // No GPR change
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inst.modificationInfo.modifiesControl = true; // Changes control flow, potentially registers via handler
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break;
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case SPECIAL_MFHI:
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case SPECIAL_MFLO:
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if (inst.rd == 0)
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inst.modificationInfo.modifiesGPR = false;
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break;
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case SPECIAL_MTHI:
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case SPECIAL_MTLO:
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// HI/LO register operations
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inst.modificationInfo.modifiesGPR = false; // Doesn't modify rd
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inst.modificationInfo.modifiesControl = true; // HI/LO
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break;
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case SPECIAL_MULT:
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case SPECIAL_MULTU:
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case SPECIAL_DIV:
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case SPECIAL_DIVU:
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// Multiplication and division operations
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inst.modificationInfo.modifiesGPR = false; // Doesn't modify rd
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inst.modificationInfo.modifiesControl = true; // HI/LO
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break;
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case SPECIAL_ADD:
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case SPECIAL_ADDU:
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case SPECIAL_SUB:
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case SPECIAL_SUBU:
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case SPECIAL_AND:
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case SPECIAL_OR:
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case SPECIAL_XOR:
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case SPECIAL_NOR:
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// ALU operations
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if (inst.rd == 0)
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inst.modificationInfo.modifiesGPR = false;
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break;
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case SPECIAL_SLL:
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case SPECIAL_SRL:
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case SPECIAL_SRA:
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case SPECIAL_SLLV:
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case SPECIAL_SRLV:
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case SPECIAL_SRAV:
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// Shift operations
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if (inst.rd == 0)
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inst.modificationInfo.modifiesGPR = false;
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break;
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// 64-bit specific operations
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case SPECIAL_DADD:
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case SPECIAL_DADDU:
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case SPECIAL_DSUB:
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case SPECIAL_DSUBU:
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case SPECIAL_DSLL:
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case SPECIAL_DSRL:
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case SPECIAL_DSRA:
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case SPECIAL_DSLL32:
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case SPECIAL_DSRL32:
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case SPECIAL_DSRA32:
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case SPECIAL_DSLLV:
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case SPECIAL_DSRLV:
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case SPECIAL_DSRAV:
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// 64-bit operations
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if (inst.rd == 0)
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inst.modificationInfo.modifiesGPR = false;
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break;
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case SPECIAL_MOVZ:
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case SPECIAL_MOVN:
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if (inst.rd == 0)
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inst.modificationInfo.modifiesGPR = false;
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break;
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// Set on Less Than
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case SPECIAL_SLT:
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case SPECIAL_SLTU:
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if (inst.rd == 0)
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inst.modificationInfo.modifiesGPR = false;
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break;
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case SPECIAL_TGE:
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case SPECIAL_TGEU:
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case SPECIAL_TLT:
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case SPECIAL_TLTU:
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case SPECIAL_TEQ:
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case SPECIAL_TNE:
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inst.modificationInfo.modifiesGPR = false;
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inst.modificationInfo.modifiesControl = true; // Control flow change via trap
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break;
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// PS2 Specific (MFSA/MTSA)
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case SPECIAL_MFSA: // Modifies rd GPR
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if (inst.rd == 0)
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inst.modificationInfo.modifiesGPR = false;
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break;
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case SPECIAL_MTSA: // Modifies SA control register
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inst.modificationInfo.modifiesGPR = false;
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inst.modificationInfo.modifiesControl = true; // SA reg
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break;
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case SPECIAL_SYNC:
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inst.modificationInfo.modifiesGPR = false;
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inst.modificationInfo.modifiesControl = true;
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break;
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}
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}
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void R5900Decoder::decodeRegimm(Instruction &inst) const
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{
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uint32_t rt = inst.rt;
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switch (rt)
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{
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case REGIMM_BLTZ:
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case REGIMM_BGEZ:
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case REGIMM_BLTZL:
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case REGIMM_BGEZL:
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// Branches
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inst.isBranch = true;
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inst.hasDelaySlot = true;
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inst.modificationInfo.modifiesControl = true; // PC potentially
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break;
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case REGIMM_BLTZAL:
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case REGIMM_BGEZAL:
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case REGIMM_BLTZALL:
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case REGIMM_BGEZALL:
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// Branch and Link
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inst.isBranch = true;
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inst.isCall = true;
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inst.hasDelaySlot = true;
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inst.modificationInfo.modifiesGPR = true; // $ra (r[31])
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inst.modificationInfo.modifiesControl = true; // PC
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break;
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case REGIMM_TGEI:
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case REGIMM_TGEIU:
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case REGIMM_TLTI:
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case REGIMM_TLTIU:
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case REGIMM_TEQI:
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case REGIMM_TNEI:
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// Trap Instructions
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inst.modificationInfo.modifiesControl = true;
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break;
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case REGIMM_MTSAB:
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case REGIMM_MTSAH:
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// PS2 specific MTSAB/MTSAH instructions (for QMFC2/QMTC2)
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inst.isMultimedia = true;
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inst.modificationInfo.modifiesControl = true; // SA register
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break;
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default:
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// Unknown REGIMM instructions
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std::cerr << "Unknown REGIMM instruction: " << std::hex << inst.raw << std::endl;
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break;
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}
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}
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void R5900Decoder::decodeMMI(Instruction &inst) const
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{
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inst.isMMI = true;
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inst.isMultimedia = true;
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inst.modificationInfo.modifiesGPR = true; // Most MMI ops write to rd GPR
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if (inst.rd == 0)
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inst.modificationInfo.modifiesGPR = false; // Except if rd is $zero
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// The function field is actually determined by the lowest 6 bits (as in R-type)
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uint32_t mmiFunction = inst.function;
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uint32_t rs = inst.rs;
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if (mmiFunction == MMI_MMI0)
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{
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decodeMMI0(inst);
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return;
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}
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if (mmiFunction == MMI_MMI1)
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{
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decodeMMI1(inst);
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return;
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}
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if (mmiFunction == MMI_MMI2)
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{
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decodeMMI2(inst);
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return;
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}
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if (mmiFunction == MMI_MMI3)
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{
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decodeMMI3(inst);
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return;
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}
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switch (mmiFunction)
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{
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case MMI_PLZCW:
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// Parallel leading zero/one count word
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break;
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case MMI_MFHI1:
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case MMI_MFLO1:
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// Move from HI1/LO1 -> rd
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if (inst.rd == 0)
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{
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inst.modificationInfo.modifiesGPR = false;
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}
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inst.modificationInfo.modifiesControl = false;
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break;
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case MMI_MTHI1:
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case MMI_MTLO1:
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// Move to HI1/LO1
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inst.modificationInfo.modifiesGPR = false;
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inst.modificationInfo.modifiesControl = true;
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break;
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case MMI_PSLLH:
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case MMI_PSRLH:
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case MMI_PSRAH:
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case MMI_PSLLW:
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case MMI_PSRLW:
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case MMI_PSRAW:
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// Packed shift instructions; defaults already mark GPR modify (unless rd==0)
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break;
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// HI/LO or HI1/LO1 producers/consumers
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case MMI_MADD:
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case MMI_MADDU:
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case MMI_MSUB:
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case MMI_MSUBU:
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case MMI_MADD1:
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case MMI_MADDU1:
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case MMI_MULT1:
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case MMI_MULTU1:
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case MMI_DIV1:
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case MMI_DIVU1:
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inst.modificationInfo.modifiesGPR = false; // Writes to HI/LO or HI1/LO1
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inst.modificationInfo.modifiesControl = true;
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break;
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case MMI_PMTHL:
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case MMI3_PMTHI:
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case MMI3_PMTLO:
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inst.modificationInfo.modifiesGPR = false; // Writes to HI/LO or HI1/LO1
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inst.modificationInfo.modifiesControl = true;
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break;
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case MMI_PMFHL:
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decodePMFHL(inst);
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break;
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default:
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// Unknown or unsupported MMI function
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std::cerr << "Unknown MMI function: " << std::hex << mmiFunction << std::endl;
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break;
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}
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}
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void R5900Decoder::decodeMMI0(Instruction &inst) const
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{
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inst.mmiType = 0;
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inst.mmiFunction = inst.sa;
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uint32_t sa = inst.sa;
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switch (sa)
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{
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case MMI0_PADDW:
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case MMI0_PSUBW:
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case MMI0_PCGTW:
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case MMI0_PMAXW:
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case MMI0_PADDH:
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case MMI0_PSUBH:
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case MMI0_PCGTH:
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case MMI0_PMAXH:
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case MMI0_PADDB:
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case MMI0_PSUBB:
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case MMI0_PCGTB:
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// Arithmetic and comparison operations
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break;
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case MMI0_PADDSW:
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case MMI0_PSUBSW:
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case MMI0_PADDSH:
|
|
case MMI0_PSUBSH:
|
|
case MMI0_PADDSB:
|
|
case MMI0_PSUBSB:
|
|
// Saturated arithmetic operations
|
|
break;
|
|
|
|
case MMI0_PEXTLW:
|
|
case MMI0_PPACW:
|
|
case MMI0_PEXTLH:
|
|
case MMI0_PPACH:
|
|
case MMI0_PEXTLB:
|
|
case MMI0_PPACB:
|
|
case MMI0_PEXT5:
|
|
case MMI0_PPAC5:
|
|
// Data packing/unpacking operations
|
|
break;
|
|
|
|
default:
|
|
// Unknown MMI0 operation
|
|
break;
|
|
}
|
|
}
|
|
|
|
void R5900Decoder::decodeMMI1(Instruction &inst) const
|
|
{
|
|
inst.mmiType = 1;
|
|
inst.mmiFunction = inst.sa;
|
|
|
|
uint32_t subFunction = inst.function & 0x3F;
|
|
|
|
uint32_t sa = inst.sa;
|
|
|
|
switch (sa)
|
|
{
|
|
case MMI1_PABSW:
|
|
case MMI1_PABSH:
|
|
// Absolute value operations
|
|
break;
|
|
|
|
case MMI1_PCEQW:
|
|
case MMI1_PCEQH:
|
|
case MMI1_PCEQB:
|
|
// Equality comparison operations
|
|
break;
|
|
|
|
case MMI1_PMINW:
|
|
case MMI1_PMINH:
|
|
// Minimum value operations
|
|
break;
|
|
|
|
case MMI1_PADDUW:
|
|
case MMI1_PSUBUW:
|
|
case MMI1_PEXTUW:
|
|
case MMI1_PADDUH:
|
|
case MMI1_PSUBUH:
|
|
case MMI1_PEXTUH:
|
|
case MMI1_PADDUB:
|
|
case MMI1_PSUBUB:
|
|
case MMI1_PEXTUB:
|
|
// Unsigned arithmetic and extension operations
|
|
break;
|
|
|
|
case MMI1_QFSRV:
|
|
// Quadword funnel shift right variable
|
|
inst.isMultimedia = true;
|
|
break;
|
|
|
|
default:
|
|
// Unknown MMI1 operation
|
|
break;
|
|
}
|
|
}
|
|
|
|
void R5900Decoder::decodeMMI2(Instruction &inst) const
|
|
{
|
|
inst.mmiType = 2;
|
|
inst.mmiFunction = inst.sa;
|
|
|
|
if (inst.sa == MMI2_PMADDW || inst.sa == MMI2_PMSUBW ||
|
|
inst.sa == MMI2_PMULTW || inst.sa == MMI2_PDIVW || inst.sa == MMI2_PDIVBW ||
|
|
inst.sa == MMI2_PMADDH || inst.sa == MMI2_PHMADH ||
|
|
inst.sa == MMI2_PMSUBH || inst.sa == MMI2_PHMSBH || inst.sa == MMI2_PMULTH)
|
|
{
|
|
inst.modificationInfo.modifiesControl = true; // HI/LO
|
|
}
|
|
|
|
uint32_t sa = inst.sa;
|
|
|
|
switch (sa)
|
|
{
|
|
case MMI2_PMADDW:
|
|
case MMI2_PMSUBW:
|
|
case MMI2_PMADDH:
|
|
case MMI2_PHMADH:
|
|
case MMI2_PMSUBH:
|
|
case MMI2_PHMSBH:
|
|
case MMI2_PMULTH:
|
|
// Multiply/multiply-add operations
|
|
inst.isMultimedia = true;
|
|
break;
|
|
|
|
case MMI2_PSLLVW:
|
|
case MMI2_PSRLVW:
|
|
// Variable shift operations
|
|
break;
|
|
|
|
case MMI2_PMFHI:
|
|
case MMI2_PMFLO:
|
|
// Move from HI/LO registers
|
|
break;
|
|
|
|
case MMI2_PINTH:
|
|
// Interleave half words
|
|
break;
|
|
|
|
case MMI2_PMULTW:
|
|
case MMI2_PDIVW:
|
|
case MMI2_PDIVBW:
|
|
// Multiply/divide operations
|
|
inst.isMultimedia = true;
|
|
break;
|
|
|
|
case MMI2_PCPYLD:
|
|
// Copy lower doubleword
|
|
break;
|
|
|
|
case MMI2_PAND:
|
|
case MMI2_PXOR:
|
|
// Logical operations
|
|
break;
|
|
|
|
case MMI2_PEXEH:
|
|
case MMI2_PREVH:
|
|
case MMI2_PEXEW:
|
|
case MMI2_PROT3W:
|
|
// Data permutation operations
|
|
break;
|
|
|
|
default:
|
|
// Unknown MMI2 operation
|
|
break;
|
|
}
|
|
}
|
|
|
|
void R5900Decoder::decodeMMI3(Instruction &inst) const
|
|
{
|
|
inst.mmiType = 3;
|
|
inst.mmiFunction = inst.sa;
|
|
|
|
uint32_t sa = inst.sa;
|
|
|
|
switch (sa)
|
|
{
|
|
case MMI3_PMADDUW:
|
|
// Unsigned multiply-add
|
|
inst.isMultimedia = true;
|
|
inst.modificationInfo.modifiesControl = true; // HI/LO
|
|
break;
|
|
|
|
case MMI3_PSRAVW:
|
|
// Packed shift right arithmetic variable word
|
|
break;
|
|
|
|
case MMI3_PMTHI:
|
|
inst.mmiFunction = MMI3_PMTHI;
|
|
inst.modificationInfo.modifiesGPR = false;
|
|
inst.modificationInfo.modifiesControl = true; // HI register is modified
|
|
break;
|
|
|
|
case MMI3_PMTLO:
|
|
inst.mmiFunction = MMI3_PMTLO;
|
|
inst.modificationInfo.modifiesGPR = false;
|
|
inst.modificationInfo.modifiesControl = true; // LO register is modified
|
|
break;
|
|
|
|
case MMI3_PINTEH:
|
|
// Interleave even halfwords
|
|
break;
|
|
|
|
case MMI3_PMULTUW:
|
|
case MMI3_PDIVUW:
|
|
// Unsigned multiply/divide operations
|
|
inst.isMultimedia = true;
|
|
inst.modificationInfo.modifiesControl = true; // HI/LO
|
|
break;
|
|
|
|
case MMI3_PCPYUD:
|
|
// Copy upper doubleword
|
|
break;
|
|
|
|
case MMI3_POR:
|
|
case MMI3_PNOR:
|
|
// Logical operations
|
|
break;
|
|
|
|
case MMI3_PEXCH:
|
|
case MMI3_PCPYH:
|
|
case MMI3_PEXCW:
|
|
// Data permutation operations
|
|
break;
|
|
|
|
default:
|
|
// Unknown MMI3 operation
|
|
break;
|
|
}
|
|
}
|
|
|
|
void R5900Decoder::decodeCOP0(Instruction &inst) const
|
|
{
|
|
// COP0 (System Control) instructions
|
|
uint8_t format = inst.rs;
|
|
inst.modificationInfo.modifiesControl = true; // Assume COP0 always modifies some control state
|
|
if (format == COP0_MF && inst.rt != 0)
|
|
{
|
|
inst.modificationInfo.modifiesGPR = true;
|
|
}
|
|
else if (format == COP0_CO && inst.function == COP0_CO_ERET)
|
|
{
|
|
inst.isReturn = true;
|
|
inst.hasDelaySlot = false;
|
|
} // ERET is special
|
|
else if (format == COP0_BC)
|
|
{
|
|
inst.isBranch = true;
|
|
inst.hasDelaySlot = true;
|
|
}
|
|
}
|
|
|
|
void R5900Decoder::decodeCOP1(Instruction &inst) const
|
|
{
|
|
uint8_t format = inst.rs;
|
|
if (format == COP1_MF || format == COP1_CF)
|
|
{
|
|
if (inst.rt != 0)
|
|
inst.modificationInfo.modifiesGPR = true;
|
|
}
|
|
else if (format == COP1_BC)
|
|
{
|
|
inst.isBranch = true;
|
|
inst.hasDelaySlot = true;
|
|
inst.modificationInfo.modifiesControl = true;
|
|
}
|
|
else if (format == COP1_S || format == COP1_W || format == COP1_L)
|
|
{
|
|
inst.modificationInfo.modifiesFPR = true;
|
|
}
|
|
if (format == COP1_CT || (format == COP1_S && inst.function >= COP1_S_C_F))
|
|
{
|
|
inst.modificationInfo.modifiesControl = true;
|
|
} // FCR31
|
|
}
|
|
|
|
void R5900Decoder::decodeCOP2(Instruction &inst) const
|
|
{
|
|
uint8_t format = inst.rs;
|
|
inst.isVU = true;
|
|
inst.isMultimedia = true;
|
|
|
|
switch (format)
|
|
{
|
|
case COP2_QMFC2:
|
|
case COP2_CFC2:
|
|
if (inst.rt != 0)
|
|
inst.modificationInfo.modifiesGPR = true;
|
|
break;
|
|
case COP2_QMTC2:
|
|
inst.modificationInfo.modifiesVFR = true;
|
|
break; // Modifies VU state
|
|
case COP2_CTC2:
|
|
inst.modificationInfo.modifiesControl = true;
|
|
break; // Modifies VU control state
|
|
case COP2_BC:
|
|
inst.isBranch = true;
|
|
inst.hasDelaySlot = true;
|
|
inst.modificationInfo.modifiesControl = true;
|
|
break;
|
|
case COP2_CO: // VU Macro instructions (format >= 0x10)
|
|
case COP2_CO + 1:
|
|
case COP2_CO + 2:
|
|
case COP2_CO + 3:
|
|
case COP2_CO + 4:
|
|
case COP2_CO + 5:
|
|
case COP2_CO + 6:
|
|
case COP2_CO + 7:
|
|
case COP2_CO + 8:
|
|
case COP2_CO + 9:
|
|
case COP2_CO + 10:
|
|
case COP2_CO + 11:
|
|
case COP2_CO + 12:
|
|
case COP2_CO + 13:
|
|
case COP2_CO + 14:
|
|
case COP2_CO + 15:
|
|
{ // Refine based on specific VU function
|
|
uint8_t vu_func = inst.function;
|
|
bool is_special2 = vu_func >= 0x3C;
|
|
uint8_t vu_fhi_flo = 0;
|
|
|
|
if (is_special2)
|
|
{
|
|
vu_fhi_flo = static_cast<uint8_t>((((inst.raw >> 6) & 0x1F) << 2) | (inst.raw & 0x3));
|
|
}
|
|
|
|
if (is_special2 && (vu_fhi_flo == VU0_S2_VDIV || vu_fhi_flo == VU0_S2_VSQRT || vu_fhi_flo == VU0_S2_VRSQRT))
|
|
{
|
|
inst.vectorInfo.fsf = (inst.raw >> 10) & 0x3; // Extract bits 10-11
|
|
inst.vectorInfo.ftf = (inst.raw >> 8) & 0x3; // Extract bits 8-9
|
|
}
|
|
|
|
inst.vectorInfo.vectorField = (inst.raw >> 21) & 0xF;
|
|
|
|
inst.modificationInfo.modifiesVFR = true; // Default: Modifies Vector Float Reg
|
|
inst.modificationInfo.modifiesControl = true; // Default: Modifies Flags/Special Regs (Q, P, I, MAC, Clip...)
|
|
|
|
if (is_special2) // Special2 Table
|
|
{
|
|
switch (vu_fhi_flo)
|
|
{
|
|
case VU0_S2_VDIV:
|
|
case VU0_S2_VSQRT:
|
|
case VU0_S2_VRSQRT:
|
|
inst.vectorInfo.usesQReg = true;
|
|
break;
|
|
case VU0_S2_VMTIR:
|
|
inst.modificationInfo.modifiesVFR = false;
|
|
inst.modificationInfo.modifiesVIC = true;
|
|
break;
|
|
case VU0_S2_VMFIR:
|
|
inst.modificationInfo.modifiesVIR = false;
|
|
break; // Reads VI, writes VF
|
|
case VU0_S2_VILWR:
|
|
inst.modificationInfo.modifiesVFR = false;
|
|
inst.modificationInfo.modifiesVIR = true;
|
|
inst.isLoad = true;
|
|
break;
|
|
case VU0_S2_VISWR:
|
|
inst.modificationInfo.modifiesVFR = false;
|
|
inst.modificationInfo.modifiesVIR = false;
|
|
inst.isStore = true;
|
|
inst.modificationInfo.modifiesMemory = true;
|
|
break;
|
|
|
|
case VU0_S2_VRINIT:
|
|
case VU0_S2_VRXOR:
|
|
inst.modificationInfo.modifiesVFR = false; /* Modifies R */
|
|
break; // Modifies R
|
|
case VU0_S2_VRGET:
|
|
inst.modificationInfo.modifiesControl = false; /* Reads R, writes VF */
|
|
break;
|
|
case VU0_S2_VRNEXT:
|
|
inst.modificationInfo.modifiesControl = true; /* Modifies R */
|
|
inst.modificationInfo.modifiesVFR = false;
|
|
break; // Writes R
|
|
case VU0_S2_VWAITQ:
|
|
inst.modificationInfo.modifiesVFR = false;
|
|
inst.modificationInfo.modifiesControl = false;
|
|
break;
|
|
case VU0_S2_VABS:
|
|
case VU0_S2_VMOVE:
|
|
case VU0_S2_VMR32:
|
|
inst.modificationInfo.modifiesControl = false;
|
|
break; // Only VF
|
|
case VU0_S2_VNOP:
|
|
inst.modificationInfo.modifiesVFR = false;
|
|
inst.modificationInfo.modifiesControl = false;
|
|
break;
|
|
case VU0_S2_VCLIPw:
|
|
inst.modificationInfo.modifiesVFR = false; /* Modifies Clip flags */
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void R5900Decoder::decodePMFHL(Instruction &inst) const
|
|
{
|
|
uint32_t saField = inst.sa;
|
|
|
|
switch (saField)
|
|
{
|
|
case PMFHL_LW:
|
|
inst.pmfhlVariation = PMFHL_LW;
|
|
break;
|
|
case PMFHL_UW:
|
|
inst.pmfhlVariation = PMFHL_UW;
|
|
break;
|
|
case PMFHL_SLW:
|
|
inst.pmfhlVariation = PMFHL_SLW;
|
|
break;
|
|
case PMFHL_LH:
|
|
inst.pmfhlVariation = PMFHL_LH;
|
|
break;
|
|
case PMFHL_SH:
|
|
inst.pmfhlVariation = PMFHL_SH;
|
|
break;
|
|
default:
|
|
inst.pmfhlVariation = 0xFF;
|
|
break;
|
|
}
|
|
}
|
|
|
|
bool R5900Decoder::isBranchInstruction(const Instruction &inst) const
|
|
{
|
|
return inst.isBranch;
|
|
}
|
|
|
|
bool R5900Decoder::isJumpInstruction(const Instruction &inst) const
|
|
{
|
|
return inst.isJump;
|
|
}
|
|
|
|
bool R5900Decoder::isCallInstruction(const Instruction &inst) const
|
|
{
|
|
return inst.isCall;
|
|
}
|
|
|
|
bool R5900Decoder::isReturnInstruction(const Instruction &inst) const
|
|
{
|
|
return inst.isReturn;
|
|
}
|
|
|
|
bool R5900Decoder::isMMIInstruction(const Instruction &inst) const
|
|
{
|
|
return inst.isMMI;
|
|
}
|
|
|
|
bool R5900Decoder::isVUInstruction(const Instruction &inst) const
|
|
{
|
|
return inst.isVU;
|
|
}
|
|
|
|
bool R5900Decoder::isStore(const Instruction &inst) const
|
|
{
|
|
return inst.isStore;
|
|
}
|
|
|
|
bool R5900Decoder::isLoad(const Instruction &inst) const
|
|
{
|
|
return inst.isLoad;
|
|
}
|
|
|
|
bool R5900Decoder::hasDelaySlot(const Instruction &inst) const
|
|
{
|
|
return inst.hasDelaySlot;
|
|
}
|
|
|
|
uint32_t R5900Decoder::getBranchTarget(const Instruction &inst) const
|
|
{
|
|
if (!inst.isBranch)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int32_t offset = inst.simmediate << 2;
|
|
return inst.address + 4 + offset;
|
|
}
|
|
|
|
uint32_t R5900Decoder::getJumpTarget(const Instruction &inst) const
|
|
{
|
|
if (!inst.isJump)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
if (inst.opcode == OPCODE_SPECIAL &&
|
|
(inst.function == SPECIAL_JR || inst.function == SPECIAL_JALR))
|
|
{
|
|
// JR/JALR: target is in the rs register (can't be determined statically)
|
|
return 0;
|
|
}
|
|
|
|
if (inst.opcode == OPCODE_J || inst.opcode == OPCODE_JAL)
|
|
{
|
|
// J/JAL: target is in the lower 26 bits, shifted left by 2
|
|
// and combined with the upper 4 bits of PC + 4
|
|
uint32_t pc_upper = (inst.address + 4) & 0xF0000000;
|
|
return pc_upper | (inst.target << 2);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
} // namespace ps2recomp
|