mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-09-26 08:51:05 -04:00
Ranieri
5196a6672a
* feat: added guestBranchKind enum to categorize branch types feat: added missingFunctionPolicy enum to define behaviors for missing function scenarios refactor: added handle guest branches and report missing functions feat lookupFunction to utilize new dispatch logic and improve error handling for unregistered functions * fix: fix test conflict * feat: added debug sound driver logs * feat: emmiter for return * feat: added recompiler reporter feat: added strict diagnostics flag for heavy debug calls * feat: staticc table insted of hashmap for runtime * feat: back file to ignore * feat: explode code across helpers and classes * feat: update codegen test feat: better guest nop check * feat: fix link problem on linux * feat: fix Segmentation fault
58 lines
2.6 KiB
C++
58 lines
2.6 KiB
C++
#include "ps2recomp/Translators/regimm_translator.h"
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#include "ps2recomp/code_generator.h"
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#include "ps2recomp/codegen_helpers.h"
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#include "ps2recomp/instructions.h"
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#include "ps2recomp/types.h"
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#include <fmt/format.h>
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#include <sstream>
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#include <cmath>
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namespace ps2recomp
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{
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RegimmTranslator::RegimmTranslator(CodeGenerator &codeGenerator)
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: m_codeGenerator(codeGenerator)
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{
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}
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std::string RegimmTranslator::translate(const Instruction &inst)
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{
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switch (inst.rt)
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{
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case REGIMM_BLTZ:
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case REGIMM_BGEZ:
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case REGIMM_BLTZL:
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case REGIMM_BGEZL:
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case REGIMM_BLTZAL:
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case REGIMM_BGEZAL:
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case REGIMM_BLTZALL:
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case REGIMM_BGEZALL:
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{
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const int32_t offsetBytes = (static_cast<int32_t>(static_cast<int16_t>(inst.simmediate)) << 2);
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const uint32_t target = static_cast<uint32_t>(static_cast<int64_t>(inst.address + 4u) + static_cast<int64_t>(offsetBytes));
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return fmt::format("// REGIMM branch instruction to 0x{:X} - Handled by branch logic", target);
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}
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case REGIMM_MTSAB:
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return fmt::format("ctx->sa = ((GPR_U32(ctx, {}) ^ (uint32_t){}) & 0xF) << 3;", inst.rs, inst.simmediate);
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case REGIMM_MTSAH:
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return fmt::format("ctx->sa = ((GPR_U32(ctx, {}) ^ (uint32_t){}) & 0x7) << 4;", inst.rs, inst.simmediate);
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case REGIMM_TGEI:
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return fmt::format("if (GPR_S64(ctx, {}) >= (int64_t)(int32_t){}) {{ runtime->handleTrap(rdram, ctx); }}", inst.rs, inst.simmediate);
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case REGIMM_TGEIU:
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return fmt::format("if (GPR_U64(ctx, {}) >= (uint64_t)(int64_t)(int32_t){}) {{ runtime->handleTrap(rdram, ctx); }}", inst.rs, inst.simmediate);
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case REGIMM_TLTI:
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return fmt::format("if (GPR_S64(ctx, {}) < (int64_t)(int32_t){}) {{ runtime->handleTrap(rdram, ctx); }}", inst.rs, inst.simmediate);
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case REGIMM_TLTIU:
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return fmt::format("if (GPR_U64(ctx, {}) < (uint64_t)(int64_t)(int32_t){}) {{ runtime->handleTrap(rdram, ctx); }}", inst.rs, inst.simmediate);
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case REGIMM_TEQI:
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return fmt::format("if (GPR_S64(ctx, {}) == (int64_t)(int32_t){}) {{ runtime->handleTrap(rdram, ctx); }}", inst.rs, inst.simmediate);
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case REGIMM_TNEI:
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return fmt::format("if (GPR_S64(ctx, {}) != (int64_t)(int32_t){}) {{ runtime->handleTrap(rdram, ctx); }}", inst.rs, inst.simmediate);
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default:
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return m_codeGenerator.emitUnhandledInstruction(inst, fmt::format("Unhandled REGIMM instruction: 0x{:X}", inst.rt));
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}
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}
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}
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