mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-09-26 08:51:05 -04:00
M. Sami Gürpınar
5d3be0e2e7
* refactor: update function name checks to use contains method * refactor: update code generation to use static_cast * refactor: made member methods const * refactor: made range-based loop * refactor: make one variable constructor explicit * refactor: remove redundant else * refactor: turn includes to forward declarations * refactor: brace placements turned into allman style * refactor: structed binding for readability and clarity, used emplace_back to prevent extra-copied object * fix: add dwarf_private.h include * fix: update GPR_U32 and GPR_S32 macros to use _mm_extract_epi32 for SSE/AVX intrinsics
506 lines
16 KiB
C++
506 lines
16 KiB
C++
#ifndef PS2_RUNTIME_H
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#define PS2_RUNTIME_H
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#include <cstdint>
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#include <vector>
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#include <unordered_map>
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#include <string>
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#include <functional>
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#include <immintrin.h> // For SSE/AVX instructions
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#include <smmintrin.h>
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#include <atomic>
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#include <filesystem>
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#include <iostream>
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constexpr uint32_t PS2_RAM_SIZE = 32 * 1024 * 1024; // 32MB
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constexpr uint32_t PS2_RAM_MASK = 0x1FFFFFF; // Mask for 32MB alignment
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constexpr uint32_t PS2_RAM_BASE = 0x00000000; // Physical base of RDRAM
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constexpr uint32_t PS2_SCRATCHPAD_BASE = 0x70000000;
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constexpr uint32_t PS2_SCRATCHPAD_SIZE = 16 * 1024; // 16KB
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constexpr uint32_t PS2_IO_BASE = 0x10000000; // Base for many I/O regs (Timers, DMAC, INTC)
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constexpr uint32_t PS2_IO_SIZE = 0x10000; // 64KB
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constexpr uint32_t PS2_BIOS_BASE = 0x1FC00000; // Or BFC00000 depending on KSEG
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constexpr uint32_t PS2_BIOS_SIZE = 4 * 1024 * 1024; // 4MB
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constexpr uint32_t PS2_VU0_CODE_BASE = 0x11000000; // Base address as seen from EE
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constexpr uint32_t PS2_VU0_DATA_BASE = 0x11004000;
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constexpr uint32_t PS2_VU0_CODE_SIZE = 4 * 1024; // 4KB Micro Memory
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constexpr uint32_t PS2_VU0_DATA_SIZE = 4 * 1024; // 4KB Data Memory (VU Mem)
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constexpr uint32_t PS2_VU1_MEM_BASE = 0x11008000; // Base address as seen from EE
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constexpr uint32_t PS2_VU1_CODE_SIZE = 16 * 1024; // 16KB Micro Memory
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constexpr uint32_t PS2_VU1_DATA_SIZE = 16 * 1024; // 16KB Data Memory (VU Mem)
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constexpr uint32_t PS2_VU1_CODE_BASE = 0x11008000;
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constexpr uint32_t PS2_VU1_DATA_BASE = 0x1100C000;
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constexpr uint32_t PS2_GS_BASE = 0x12000000;
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constexpr uint32_t PS2_GS_PRIV_REG_BASE = 0x12000000; // GS Privileged Registers
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constexpr uint32_t PS2_GS_PRIV_REG_SIZE = 0x2000;
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constexpr size_t PS2_GS_VRAM_SIZE = 4 * 1024 * 1024; // 4MB GS VRAM
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#define PS2_FIO_O_RDONLY 0x0001
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#define PS2_FIO_O_WRONLY 0x0002
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#define PS2_FIO_O_RDWR 0x0003
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#define PS2_FIO_O_APPEND 0x0100
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#define PS2_FIO_O_CREAT 0x0200
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#define PS2_FIO_O_TRUNC 0x0400
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#define PS2_FIO_O_EXCL 0x0800
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#define PS2_FIO_SEEK_SET 0
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#define PS2_FIO_SEEK_CUR 1
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#define PS2_FIO_SEEK_END 2
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#define PS2_FIO_S_IFDIR 0x1000
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#define PS2_FIO_S_IFREG 0x2000
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enum PS2Exception
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{
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EXCEPTION_INTEGER_OVERFLOW = 0x0C, // From MIPS spec
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};
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// PS2 CPU context (R5900)
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struct alignas(16) R5900Context
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{
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// General Purpose Registers (128-bit)
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__m128i r[32]; // Main registers
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// Control registers
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uint32_t pc; // Program counter
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uint64_t insn_count; // Instruction counter
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uint64_t hi, lo; // HI/LO registers for mult/div results
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uint64_t hi1, lo1; // Secondary HI/LO registers for MULT1/DIV1
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uint32_t sa; // Shift amount register
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// VU0 registers (when used in macro mode)
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__m128 vu0_vf[32]; // VU0 vector float registers
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uint16_t vi[16]; // VU0 vector integer registers
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float vu0_q; // VU0 Q register (quotient)
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float vu0_p; // VU0 P register (EFU result)
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float vu0_i; // VU0 I register (integer value)
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__m128 vu0_r; // VU0 R register
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__m128 vu0_acc; // VU0 ACC accumulator register
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uint16_t vu0_status; // VU0 status register
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uint32_t vu0_mac_flags; // VU0 MAC flags
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uint32_t vu0_clip_flags; // VU0 clipping flags
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uint32_t vu0_clip_flags2; // VU0 clipping flags
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uint32_t vu0_cmsar0; // VU0 microprogram start address
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uint32_t vu0_cmsar1; // VU0 microprogram start address
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uint32_t vu0_cmsar2; // VU0 microprogram start address
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uint32_t vu0_cmsar3; // VU0 microprogram start address
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uint32_t vu0_vpu_stat;
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uint32_t vu0_vpu_stat2; // extra VPU status (used by CR_VPU_STAT2)
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uint32_t vu0_vpu_stat3; // extra VPU status 3
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uint32_t vu0_vpu_stat4; // extra VPU status 4
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uint32_t vu0_tpc; // TPC (VU0 PC)
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uint32_t vu0_tpc2; // second TPC
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uint32_t vu0_fbrst; // VIF/VU reset register
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uint32_t vu0_fbrst2; // FBRST2
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uint32_t vu0_fbrst3; // FBRST3
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uint32_t vu0_fbrst4; // FBRST4
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uint32_t vu0_itop;
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uint32_t vu0_info;
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uint32_t vu0_xitop; // VU0 XITOP - input ITOP for VIF/VU sync
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uint32_t vu0_pc;
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float vu0_cf[4]; // VU0 FMAC control floating-point registers
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// COP0 System control registers
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uint32_t cop0_index;
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uint32_t cop0_random;
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uint32_t cop0_entrylo0;
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uint32_t cop0_entrylo1;
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uint32_t cop0_context;
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uint32_t cop0_pagemask;
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uint32_t cop0_wired;
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uint32_t cop0_badvaddr;
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uint32_t cop0_count;
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uint32_t cop0_entryhi;
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uint32_t cop0_compare;
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uint32_t cop0_status;
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uint32_t cop0_cause;
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uint32_t cop0_epc;
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uint32_t cop0_prid;
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uint32_t cop0_config;
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uint32_t cop0_badpaddr;
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uint32_t cop0_debug;
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uint32_t cop0_perf;
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uint32_t cop0_taglo;
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uint32_t cop0_taghi;
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uint32_t cop0_errorepc;
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// COP2 control registers (VU0 integer + control)
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uint32_t cop2_ccr[32];
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// FPU registers (COP1)
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float f[32];
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uint32_t fcr31; // Control/status register
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R5900Context()
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{
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for (int i = 0; i < 32; i++)
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{
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r[i] = _mm_setzero_si128();
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f[i] = 0.0f;
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vu0_vf[i] = _mm_setzero_ps();
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}
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for (int i = 0; i < 4; i++)
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{
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vu0_cf[i] = 0.0f;
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}
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for (int i = 0; i < 16; ++i)
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{
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vi[i] = 0;
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}
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pc = 0;
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insn_count = 0;
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lo = hi = lo1 = hi1 = 0;
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sa = 0;
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// Initialize VU0 registers
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vu0_q = 1.0f; // Q register usually initialized to 1.0
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vu0_p = 0.0f;
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vu0_i = 0.0f;
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vu0_r = _mm_setzero_ps();
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vu0_acc = _mm_setzero_ps();
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vu0_status = 0;
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vu0_mac_flags = 0;
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vu0_clip_flags = 0;
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vu0_cmsar0 = 0;
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vu0_fbrst = 0;
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vu0_fbrst2 = 0;
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vu0_fbrst3 = 0;
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vu0_fbrst4 = 0;
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vu0_xitop = 0;
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vu0_pc = 0;
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vu0_tpc = 0;
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vu0_vpu_stat2 = 0;
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vu0_tpc2 = 0;
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vu0_cmsar1 = 0;
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vu0_vpu_stat3 = 0;
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vu0_cmsar2 = 0;
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vu0_vpu_stat4 = 0;
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vu0_itop = 0;
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vu0_info = 0;
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// Reset COP0 registers
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cop0_index = 0;
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cop0_random = 47; // Start at maximum value
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cop0_entrylo0 = 0;
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cop0_entrylo1 = 0;
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cop0_context = 0;
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cop0_pagemask = 0;
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cop0_wired = 0;
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cop0_badvaddr = 0;
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cop0_count = 0;
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cop0_entryhi = 0;
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cop0_compare = 0;
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cop0_status = 0x400000; // BEV set, ERL clear, kernel mode
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cop0_cause = 0;
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cop0_epc = 0;
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cop0_prid = 0x00002e20; // CPU ID for R5900
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cop0_config = 0;
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cop0_badpaddr = 0;
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cop0_debug = 0;
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cop0_perf = 0;
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cop0_taglo = 0;
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cop0_taghi = 0;
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cop0_errorepc = 0;
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// Reset COP1 state
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fcr31 = 0;
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}
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void dump() const
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{
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std::ios_base::fmtflags flags = std::cout.flags();
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std::cout << std::hex << std::setfill('0');
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std::cout << "--- R5900 Context Dump ---\n";
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std::cout << "PC: 0x" << std::setw(8) << pc << "\n";
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std::cout << "HI: 0x" << std::setw(8) << hi << " LO: 0x" << std::setw(8) << lo << "\n";
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std::cout << "HI1:0x" << std::setw(8) << hi1 << " LO1:0x" << std::setw(8) << lo1 << "\n";
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std::cout << "SA: 0x" << std::setw(8) << sa << "\n";
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for (int i = 0; i < 32; ++i)
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{
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std::cout << "R" << std::setw(2) << std::dec << i << ": 0x" << std::hex
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<< std::setw(8) << static_cast<uint32_t>(_mm_extract_epi32(r[i], 3))
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<< std::setw(8) << static_cast<uint32_t>(_mm_extract_epi32(r[i], 2)) << "_"
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<< std::setw(8) << static_cast<uint32_t>(_mm_extract_epi32(r[i], 1))
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<< std::setw(8) << static_cast<uint32_t>(_mm_extract_epi32(r[i], 0)) << "\n";
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}
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std::cout << "Status: 0x" << std::setw(8) << cop0_status
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<< " Cause: 0x" << std::setw(8) << cop0_cause
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<< " EPC: 0x" << std::setw(8) << cop0_epc << "\n";
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std::cout << "--- End Context Dump ---\n";
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std::cout.flags(flags); // Restore format flags
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}
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~R5900Context() = default;
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};
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inline uint32_t getRegU32(const R5900Context *ctx, int reg)
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{
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// Check if reg is valid (0-31)
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if (reg < 0 || reg > 31)
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return 0;
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return static_cast<uint32_t>(_mm_extract_epi32(ctx->r[reg], 0));
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}
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inline void setReturnU32(R5900Context *ctx, uint32_t value)
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{
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ctx->r[2] = _mm_set_epi32(0, 0, 0, value); // $v0
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}
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inline void setReturnS32(R5900Context *ctx, int32_t value)
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{
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ctx->r[2] = _mm_set_epi32(0, 0, 0, value); // $v0 Sign extension handled by cast? TODO Check MIPS ABI.
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}
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inline void setReturnU64(R5900Context *ctx, uint64_t value)
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{
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// 64-bit returns use $v0/$v1 (r2/r3)
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ctx->r[2] = _mm_set_epi32(0, 0, 0, static_cast<uint32_t>(value));
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ctx->r[3] = _mm_set_epi32(0, 0, 0, static_cast<uint32_t>(value >> 32));
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}
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inline uint8_t *getMemPtr(uint8_t *rdram, uint32_t addr)
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{
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constexpr uint32_t PS2_RAM_MASK = PS2_RAM_SIZE - 1;
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return rdram + (addr & PS2_RAM_MASK);
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}
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inline const uint8_t *getConstMemPtr(uint8_t *rdram, uint32_t addr)
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{
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constexpr uint32_t PS2_RAM_MASK = PS2_RAM_SIZE - 1;
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return rdram + (addr & PS2_RAM_MASK);
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}
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// PS2 GS (Graphics Synthesizer) registers
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struct GSRegisters
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{
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uint64_t pmode; // Pixel mode
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uint64_t smode1; // Sync mode 1
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uint64_t smode2; // Sync mode 2
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uint64_t srfsh; // Refresh control
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uint64_t synch1; // Synchronization control 1
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uint64_t synch2; // Synchronization control 2
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uint64_t syncv; // Synchronization control V
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uint64_t dispfb1; // Display buffer 1
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uint64_t display1; // Display area 1
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uint64_t dispfb2; // Display buffer 2
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uint64_t display2; // Display area 2
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uint64_t extbuf; // External buffer
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uint64_t extdata; // External data
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uint64_t extwrite; // External write
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uint64_t bgcolor; // Background color
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uint64_t csr; // Status
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uint64_t imr; // Interrupt mask
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uint64_t busdir; // Bus direction
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uint64_t siglblid; // Signal label ID
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};
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// PS2 VIF (VPU Interface) registers
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struct VIFRegisters
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{
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uint32_t stat; // Status
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uint32_t fbrst; // VIF Force Break
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uint32_t err; // Error status
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uint32_t mark; // Interrupt control
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uint32_t cycle; // Transfer mode
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uint32_t mode; // Mode control
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uint32_t num; // Data amount counter
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uint32_t mask; // Data mask
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uint32_t code; // VIFcode
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uint32_t itops; // ITOP save
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uint32_t base; // Base address
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uint32_t ofst; // Offset
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uint32_t tops; // TOPS
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uint32_t itop; // ITOP
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uint32_t top; // TOP
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uint32_t row[4]; // Transfer row data
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uint32_t col[4]; // Transfer column data
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};
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// PS2 DMA registers
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struct DMARegisters
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{
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uint32_t chcr; // Channel control
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uint32_t madr; // Memory address
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uint32_t qwc; // Quadword count
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uint32_t tadr; // Tag address
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uint32_t asr0; // Address stack 0
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uint32_t asr1; // Address stack 1
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uint32_t sadr; // Source address
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};
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struct JumpTable
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{
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uint32_t address; // Base address of the jump table
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uint32_t baseRegister; // Register used for index
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std::vector<uint32_t> targets; // Jump targets
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};
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class PS2Memory
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{
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public:
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PS2Memory();
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~PS2Memory();
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// Initialize memory
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bool initialize(size_t ramSize = PS2_RAM_SIZE);
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// Memory access methods
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uint8_t *getRDRAM() { return m_rdram; }
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uint8_t *getScratchpad() { return m_scratchpad; }
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uint8_t *getIOPRAM() { return iop_ram; }
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uint64_t dmaStartCount() const { return m_dmaStartCount.load(std::memory_order_relaxed); }
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uint64_t gifCopyCount() const { return m_gifCopyCount.load(std::memory_order_relaxed); }
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uint64_t gsWriteCount() const { return m_gsWriteCount.load(std::memory_order_relaxed); }
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uint64_t vifWriteCount() const { return m_vifWriteCount.load(std::memory_order_relaxed); }
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// Read/write memory
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uint8_t read8(uint32_t address);
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uint16_t read16(uint32_t address);
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uint32_t read32(uint32_t address);
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uint64_t read64(uint32_t address);
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__m128i read128(uint32_t address);
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void write8(uint32_t address, uint8_t value);
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void write16(uint32_t address, uint16_t value);
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void write32(uint32_t address, uint32_t value);
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void write64(uint32_t address, uint64_t value);
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void write128(uint32_t address, __m128i value);
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// TLB handling
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uint32_t translateAddress(uint32_t virtualAddress);
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// Hardware register interface
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bool writeIORegister(uint32_t address, uint32_t value);
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uint32_t readIORegister(uint32_t address);
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// Track code modifications for self-modifying code
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void registerCodeRegion(uint32_t start, uint32_t end);
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bool isCodeModified(uint32_t address, uint32_t size);
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void clearModifiedFlag(uint32_t address, uint32_t size);
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// GS register accessors
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GSRegisters &gs() { return gs_regs; }
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const GSRegisters &gs() const { return gs_regs; }
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uint8_t *getGSVRAM() { return m_gsVRAM; }
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const uint8_t *getGSVRAM() const { return m_gsVRAM; }
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bool hasSeenGifCopy() const { return m_seenGifCopy; }
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// Main RAM (32MB)
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uint8_t *m_rdram;
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// Scratchpad memory (16KB)
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uint8_t *m_scratchpad;
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// IOP RAM (2MB)
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uint8_t *iop_ram;
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bool m_seenGifCopy;
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std::atomic<uint64_t> m_dmaStartCount{0};
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std::atomic<uint64_t> m_gifCopyCount{0};
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std::atomic<uint64_t> m_gsWriteCount{0};
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std::atomic<uint64_t> m_vifWriteCount{0};
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// I/O registers
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std::unordered_map<uint32_t, uint32_t> m_ioRegisters;
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// Registers
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GSRegisters gs_regs;
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uint8_t *m_gsVRAM;
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VIFRegisters vif0_regs;
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VIFRegisters vif1_regs;
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DMARegisters dma_regs[10]; // 10 DMA channels
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// TLB entries
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struct TLBEntry
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{
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uint32_t vpn;
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uint32_t pfn;
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uint32_t mask;
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bool valid;
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};
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|
|
std::vector<TLBEntry> m_tlbEntries;
|
|
|
|
struct CodeRegion
|
|
{
|
|
uint32_t start;
|
|
uint32_t end;
|
|
std::vector<bool> modified; // Bitmap of modified 4-byte blocks
|
|
};
|
|
std::vector<CodeRegion> m_codeRegions;
|
|
|
|
bool isAddressInRegion(uint32_t address, const CodeRegion ®ion);
|
|
void markModified(uint32_t address, uint32_t size);
|
|
bool isScratchpad(uint32_t address) const;
|
|
};
|
|
|
|
class PS2Runtime
|
|
{
|
|
public:
|
|
PS2Runtime();
|
|
~PS2Runtime();
|
|
|
|
bool initialize(const char *title = "PS2 Game");
|
|
bool loadELF(const std::string &elfPath);
|
|
void run();
|
|
|
|
using RecompiledFunction = void (*)(uint8_t *, R5900Context *, PS2Runtime *);
|
|
|
|
void registerFunction(uint32_t address, RecompiledFunction func);
|
|
RecompiledFunction lookupFunction(uint32_t address);
|
|
bool hasFunction(uint32_t address) const;
|
|
|
|
void SignalException(R5900Context *ctx, PS2Exception exception);
|
|
|
|
void executeVU0Microprogram(uint8_t *rdram, R5900Context *ctx, uint32_t address);
|
|
void vu0StartMicroProgram(uint8_t *rdram, R5900Context *ctx, uint32_t address);
|
|
|
|
public:
|
|
void handleSyscall(uint8_t *rdram, R5900Context *ctx);
|
|
void handleBreak(uint8_t *rdram, R5900Context *ctx);
|
|
|
|
void handleTrap(uint8_t *rdram, R5900Context *ctx);
|
|
void handleTLBR(uint8_t *rdram, R5900Context *ctx);
|
|
void handleTLBWI(uint8_t *rdram, R5900Context *ctx);
|
|
void handleTLBWR(uint8_t *rdram, R5900Context *ctx);
|
|
void handleTLBP(uint8_t *rdram, R5900Context *ctx);
|
|
void clearLLBit(R5900Context *ctx);
|
|
|
|
public:
|
|
inline R5900Context &cpu() { return m_cpuContext; }
|
|
inline const R5900Context &cpu() const { return m_cpuContext; }
|
|
|
|
inline PS2Memory &memory() { return m_memory; }
|
|
inline const PS2Memory &memory() const { return m_memory; }
|
|
|
|
public:
|
|
bool check_overflow = false;
|
|
|
|
private:
|
|
void HandleIntegerOverflow(R5900Context *ctx);
|
|
|
|
private:
|
|
PS2Memory m_memory;
|
|
R5900Context m_cpuContext;
|
|
|
|
std::unordered_map<uint32_t, RecompiledFunction> m_functionTable;
|
|
|
|
struct LoadedModule
|
|
{
|
|
std::string name;
|
|
uint32_t baseAddress;
|
|
size_t size;
|
|
bool active;
|
|
};
|
|
|
|
std::vector<LoadedModule> m_loadedModules;
|
|
};
|
|
|
|
#endif // PS2_RUNTIME_H
|