mirror of
https://github.com/ran-j/PS2Recomp.git
synced 2026-09-26 16:59:35 -04:00
Ranieri
819 lines
28 KiB
C++
819 lines
28 KiB
C++
#ifndef PS2_RUNTIME_H
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#define PS2_RUNTIME_H
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#include <cstring>
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#include <cstdint>
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#include <vector>
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#include <unordered_map>
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#include <string>
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#include <functional>
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#if defined(_MSC_VER)
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#include <intrin.h>
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#elif defined(USE_SSE2NEON)
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#include "sse2neon.h"
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#else
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#include <immintrin.h> // For SSE/AVX instructions
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#include <smmintrin.h> // For SSE4.1 instructions
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#endif
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#include <atomic>
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#include <mutex>
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#include <filesystem>
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#include <iostream>
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#include <iomanip>
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constexpr uint32_t PS2_RAM_SIZE = 32u * 1024u * 1024u; // 32MB
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constexpr uint32_t PS2_RAM_MASK = PS2_RAM_SIZE - 1u; // Mask for 32MB alignment
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constexpr uint32_t PS2_RAM_BASE = 0x00000000; // Physical base of RDRAM
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constexpr uint32_t PS2_SCRATCHPAD_BASE = 0x70000000;
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constexpr uint32_t PS2_SCRATCHPAD_SIZE = 16u * 1024u; // 16KB
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constexpr uint32_t PS2_IO_BASE = 0x10000000; // Base for many I/O regs (Timers, DMAC, INTC)
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constexpr uint32_t PS2_IO_SIZE = 0x10000; // 64KB
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constexpr uint32_t PS2_BIOS_BASE = 0x1FC00000; // Or BFC00000 depending on KSEG
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constexpr uint32_t PS2_BIOS_SIZE = 4u * 1024u * 1024u; // 4MB
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constexpr uint32_t PS2_VU0_CODE_BASE = 0x11000000; // Base address as seen from EE
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constexpr uint32_t PS2_VU0_DATA_BASE = 0x11004000;
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constexpr uint32_t PS2_VU0_CODE_SIZE = 4u * 1024u; // 4KB Micro Memory
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constexpr uint32_t PS2_VU0_DATA_SIZE = 4u * 1024u; // 4KB Data Memory (VU Mem)
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constexpr uint32_t PS2_VU1_CODE_BASE = 0x11008000;
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constexpr uint32_t PS2_VU1_DATA_BASE = 0x1100C000;
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constexpr uint32_t PS2_VU1_MEM_BASE = PS2_VU1_CODE_BASE; // Alias used by older code paths
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constexpr uint32_t PS2_VU1_CODE_SIZE = 16u * 1024u; // 16KB Micro Memory
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constexpr uint32_t PS2_VU1_DATA_SIZE = 16u * 1024u; // 16KB Data Memory (VU Mem)
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constexpr uint32_t PS2_GS_BASE = 0x12000000;
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constexpr uint32_t PS2_GS_PRIV_REG_BASE = PS2_GS_BASE; // GS Privileged Registers
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constexpr uint32_t PS2_GS_PRIV_REG_SIZE = 0x2000;
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constexpr size_t PS2_GS_VRAM_SIZE = 4u * 1024u * 1024u; // 4MB GS VRAM
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inline constexpr uint32_t PS2_FIO_O_RDONLY = 0x0001;
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inline constexpr uint32_t PS2_FIO_O_WRONLY = 0x0002;
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inline constexpr uint32_t PS2_FIO_O_RDWR = 0x0003;
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inline constexpr uint32_t PS2_FIO_O_NBLOCK = 0x0010;
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inline constexpr uint32_t PS2_FIO_O_APPEND = 0x0100;
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inline constexpr uint32_t PS2_FIO_O_CREAT = 0x0200;
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inline constexpr uint32_t PS2_FIO_O_TRUNC = 0x0400;
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inline constexpr uint32_t PS2_FIO_O_EXCL = 0x0800;
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inline constexpr uint32_t PS2_FIO_O_NOWAIT = 0x8000;
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inline constexpr uint32_t PS2_FIO_SEEK_SET = 0;
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inline constexpr uint32_t PS2_FIO_SEEK_CUR = 1;
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inline constexpr uint32_t PS2_FIO_SEEK_END = 2;
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inline constexpr uint32_t PS2_FIO_S_IFDIR = 0x1000;
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inline constexpr uint32_t PS2_FIO_S_IFREG = 0x2000;
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static_assert((PS2_RAM_SIZE & (PS2_RAM_SIZE - 1u)) == 0u, "PS2_RAM_SIZE must be a power of two");
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static_assert(PS2_RAM_MASK == (PS2_RAM_SIZE - 1u), "PS2_RAM_MASK must match PS2_RAM_SIZE");
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enum PS2Exception
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{
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EXCEPTION_TLB_REFILL = 0x02, // TLB refill/load exception
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EXCEPTION_ADDRESS_ERROR_LOAD = 0x04, // Address error on load
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EXCEPTION_ADDRESS_ERROR_STORE = 0x05, // Address error on store
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EXCEPTION_SYSCALL = 0x08, // SYSCALL instruction
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EXCEPTION_BREAKPOINT = 0x09, // BREAK instruction
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EXCEPTION_RESERVED_INSTRUCTION = 0x0A,
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EXCEPTION_INTEGER_OVERFLOW = 0x0C, // From MIPS spec
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EXCEPTION_TRAP = 0x0D, // Trap instruction condition met
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};
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// PS2 CPU context (R5900)
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struct alignas(16) R5900Context
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{
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// General Purpose Registers (128-bit)
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__m128i r[32]; // Main registers
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// Control registers
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uint32_t pc; // Program counter
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uint64_t insn_count; // Instruction counter
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uint64_t hi, lo; // HI/LO registers for mult/div results
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uint64_t hi1, lo1; // Secondary HI/LO registers for MULT1/DIV1
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uint32_t sa; // Shift amount register
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// VU0 registers (when used in macro mode)
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__m128 vu0_vf[32]; // VU0 vector float registers
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uint16_t vi[16]; // VU0 vector integer registers
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float vu0_q; // VU0 Q register (quotient)
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float vu0_p; // VU0 P register (EFU result)
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float vu0_i; // VU0 I register (integer value)
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__m128 vu0_r; // VU0 R register
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__m128 vu0_acc; // VU0 ACC accumulator register
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uint16_t vu0_status; // VU0 status register
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uint32_t vu0_mac_flags; // VU0 MAC flags
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uint32_t vu0_clip_flags; // VU0 clipping flags
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uint32_t vu0_clip_flags2; // VU0 clipping flags
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uint32_t vu0_cmsar0; // VU0 microprogram start address
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uint32_t vu0_cmsar1; // VU0 microprogram start address
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uint32_t vu0_cmsar2; // VU0 microprogram start address
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uint32_t vu0_cmsar3; // VU0 microprogram start address
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uint32_t vu0_vpu_stat;
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uint32_t vu0_vpu_stat2; // extra VPU status (used by CR_VPU_STAT2)
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uint32_t vu0_vpu_stat3; // extra VPU status 3
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uint32_t vu0_vpu_stat4; // extra VPU status 4
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uint32_t vu0_tpc; // TPC (VU0 PC)
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uint32_t vu0_tpc2; // second TPC
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uint32_t vu0_fbrst; // VIF/VU reset register
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uint32_t vu0_fbrst2; // FBRST2
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uint32_t vu0_fbrst3; // FBRST3
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uint32_t vu0_fbrst4; // FBRST4
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uint32_t vu0_itop;
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uint32_t vu0_info;
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uint32_t vu0_xitop; // VU0 XITOP - input ITOP for VIF/VU sync
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uint32_t vu0_pc;
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float vu0_cf[4]; // VU0 FMAC control floating-point registers
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// COP0 System control registers
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uint32_t cop0_index;
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uint32_t cop0_random;
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uint32_t cop0_entrylo0;
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uint32_t cop0_entrylo1;
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uint32_t cop0_context;
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uint32_t cop0_pagemask;
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uint32_t cop0_wired;
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uint32_t cop0_badvaddr;
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uint32_t cop0_count;
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uint32_t cop0_entryhi;
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uint32_t cop0_compare;
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uint32_t cop0_status;
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uint32_t cop0_cause;
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uint32_t cop0_epc;
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uint32_t cop0_prid;
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uint32_t cop0_config;
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uint32_t cop0_badpaddr;
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uint32_t cop0_debug;
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uint32_t cop0_perf;
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uint32_t cop0_taglo;
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uint32_t cop0_taghi;
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uint32_t cop0_errorepc;
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// LL/SC reservation state (not part of COP0 Status bits).
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uint32_t llbit;
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uint32_t lladdr;
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// COP2 control registers (VU0 integer + control)
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uint32_t cop2_ccr[32];
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// FPU registers (COP1)
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float f[32];
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uint32_t fcr31; // Control/status register
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R5900Context()
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{
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std::memset(this, 0, sizeof(*this));
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// Initialize VU0 registers
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vu0_q = 1.0f; // Q register usually initialized to 1.0
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// Reset COP0 registers
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cop0_random = 47; // Start at maximum value
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// cop0_status = 0x400000; // BEV set, ERL clear, kernel mode
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// 0x00400000 = BEV (Boot Exception Vectors).
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// 0x00000000 = Normal mode (after BIOS handoff).
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cop0_status = 0x00000000;
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cop0_prid = 0x00002e20; // CPU ID for R5900
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}
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void dump() const
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{
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std::ios_base::fmtflags flags = std::cout.flags();
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std::cout << std::hex << std::setfill('0');
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std::cout << "--- R5900 Context Dump ---\n";
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std::cout << "PC: 0x" << std::setw(8) << pc << "\n";
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std::cout << "HI: 0x" << std::setw(8) << hi << " LO: 0x" << std::setw(8) << lo << "\n";
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std::cout << "HI1:0x" << std::setw(8) << hi1 << " LO1:0x" << std::setw(8) << lo1 << "\n";
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std::cout << "SA: 0x" << std::setw(8) << sa << "\n";
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for (int i = 0; i < 32; ++i)
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{
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std::cout << "R" << std::setw(2) << std::dec << i << ": 0x" << std::hex
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<< std::setw(8) << static_cast<uint32_t>(_mm_extract_epi32(r[i], 3))
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<< std::setw(8) << static_cast<uint32_t>(_mm_extract_epi32(r[i], 2)) << "_"
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<< std::setw(8) << static_cast<uint32_t>(_mm_extract_epi32(r[i], 1))
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<< std::setw(8) << static_cast<uint32_t>(_mm_extract_epi32(r[i], 0)) << "\n";
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}
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std::cout << "Status: 0x" << std::setw(8) << cop0_status
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<< " Cause: 0x" << std::setw(8) << cop0_cause
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<< " EPC: 0x" << std::setw(8) << cop0_epc << "\n";
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std::cout << "--- End Context Dump ---\n";
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std::cout.flags(flags); // Restore format flags
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}
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~R5900Context() = default;
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};
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inline uint32_t getRegU32(const R5900Context *ctx, int reg)
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{
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// Check if reg is valid (0-31)
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if (reg < 0 || reg > 31)
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return 0;
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if (reg == 0)
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return 0;
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return static_cast<uint32_t>(_mm_extract_epi32(ctx->r[reg], 0));
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}
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inline void setReturnU32(R5900Context *ctx, uint32_t value)
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{
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// Keep low 64-bits coherent for helpers that read GPRs as 64-bit.
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ctx->r[2] = _mm_set_epi64x(0, static_cast<int64_t>(value)); // $v0
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}
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inline void setReturnS32(R5900Context *ctx, int32_t value)
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{
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// Signed 32-bit return should be sign-extended when observed as 64-bit.
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ctx->r[2] = _mm_set_epi64x(0, static_cast<int64_t>(value)); // $v0
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}
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inline void setReturnU64(R5900Context *ctx, uint64_t value)
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{
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// Keep both conventions: full 64-bit value in $v0 and high 32-bit in $v1.
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ctx->r[2] = _mm_set_epi64x(0, static_cast<int64_t>(value));
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ctx->r[3] = _mm_set_epi64x(0, static_cast<int64_t>(static_cast<uint32_t>(value >> 32)));
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}
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inline constexpr uint32_t PS2_PATH_WATCH_ADDR = 0x00369F2Fu;
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inline constexpr uint32_t PS2_PATH_WATCH_BYTES = 32u;
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inline constexpr uint32_t PS2_PATH_WATCH_MAX_LOGS = 512u;
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inline std::atomic<uint32_t> g_ps2PathWatchLogCount{0};
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inline uint32_t ps2PathWatchPhysAddr()
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{
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return PS2_PATH_WATCH_ADDR & PS2_RAM_MASK;
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}
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inline bool ps2PathWatchIntersects(uint32_t writeAddr, uint32_t writeSize)
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{
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const uint64_t writeStart = writeAddr;
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const uint64_t writeEnd = writeStart + static_cast<uint64_t>(writeSize);
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const uint64_t watchStart = ps2PathWatchPhysAddr();
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const uint64_t watchEnd = watchStart + static_cast<uint64_t>(PS2_PATH_WATCH_BYTES);
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return writeEnd > watchStart && writeStart < watchEnd;
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}
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inline void ps2PathWatchDumpPrefix(const uint8_t *rdram)
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{
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if (!rdram)
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{
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return;
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}
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const uint32_t base = ps2PathWatchPhysAddr();
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auto flags = std::cout.flags();
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std::cout << " buf=" << std::hex;
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for (uint32_t i = 0; i < 16u; ++i)
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{
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const uint32_t addr = (base + i) & PS2_RAM_MASK;
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std::cout << static_cast<uint32_t>(rdram[addr]);
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if (i + 1u < 16u)
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{
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std::cout << '.';
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}
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}
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std::cout.flags(flags);
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}
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inline uint8_t ps2PathWatchExtractByteFromWrite(uint32_t writeAddr, uint32_t watchAddr, uint64_t valueLo, uint64_t valueHi)
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{
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const uint32_t byteIndex = watchAddr - writeAddr;
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if (byteIndex < 8u)
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{
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return static_cast<uint8_t>((valueLo >> (byteIndex * 8u)) & 0xFFu);
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}
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return static_cast<uint8_t>((valueHi >> ((byteIndex - 8u) * 8u)) & 0xFFu);
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}
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inline void ps2TraceGuestWrite(uint8_t *rdram,
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uint32_t guestAddr,
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uint32_t size,
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uint64_t valueLo,
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uint64_t valueHi,
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const char *op,
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const R5900Context *ctx)
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{
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if (!rdram || size == 0u)
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{
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return;
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}
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const uint32_t writeAddr = guestAddr & PS2_RAM_MASK;
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if (!ps2PathWatchIntersects(writeAddr, size))
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{
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return;
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}
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const uint32_t logIndex = g_ps2PathWatchLogCount.fetch_add(1, std::memory_order_relaxed);
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if (logIndex >= PS2_PATH_WATCH_MAX_LOGS)
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{
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return;
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}
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const uint32_t watchAddr = ps2PathWatchPhysAddr();
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const bool touchesFirstByte = (watchAddr >= writeAddr) && (watchAddr < writeAddr + size);
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const uint8_t oldByte = rdram[watchAddr];
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const uint8_t newByte = touchesFirstByte ? ps2PathWatchExtractByteFromWrite(writeAddr, watchAddr, valueLo, valueHi) : oldByte;
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const uint32_t pc = ctx ? ctx->pc : 0u;
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const uint32_t ra = ctx ? static_cast<uint32_t>(_mm_extract_epi32(ctx->r[31], 0)) : 0u;
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const uint32_t sp = ctx ? static_cast<uint32_t>(_mm_extract_epi32(ctx->r[29], 0)) : 0u;
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auto flags = std::cout.flags();
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std::cout << "[watch:path-write] #" << (logIndex + 1u)
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<< " op=" << op
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<< " addr=0x" << std::hex << writeAddr
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<< " size=0x" << size
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<< " pc=0x" << pc
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<< " ra=0x" << ra
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<< " sp=0x" << sp
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<< " vLo=0x" << valueLo;
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if (size > 8u)
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{
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std::cout << " vHi=0x" << valueHi;
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}
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if (touchesFirstByte)
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{
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std::cout << " firstByte:" << static_cast<uint32_t>(oldByte)
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<< "->" << static_cast<uint32_t>(newByte);
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if (oldByte != 0u && newByte == 0u)
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{
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std::cout << " (ZEROED)";
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}
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}
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ps2PathWatchDumpPrefix(rdram);
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std::cout.flags(flags);
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std::cout << std::endl;
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}
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inline void ps2TraceGuestRangeWrite(uint8_t *rdram,
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uint32_t guestAddr,
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uint32_t size,
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const char *op,
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const R5900Context *ctx)
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{
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if (!rdram || size == 0u)
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{
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return;
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}
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const uint32_t writeAddr = guestAddr & PS2_RAM_MASK;
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if (!ps2PathWatchIntersects(writeAddr, size))
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{
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return;
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}
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const uint32_t logIndex = g_ps2PathWatchLogCount.fetch_add(1, std::memory_order_relaxed);
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if (logIndex >= PS2_PATH_WATCH_MAX_LOGS)
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{
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return;
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}
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const uint32_t pc = ctx ? ctx->pc : 0u;
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const uint32_t ra = ctx ? static_cast<uint32_t>(_mm_extract_epi32(ctx->r[31], 0)) : 0u;
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const uint32_t sp = ctx ? static_cast<uint32_t>(_mm_extract_epi32(ctx->r[29], 0)) : 0u;
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const uint8_t firstByte = rdram[ps2PathWatchPhysAddr()];
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auto flags = std::cout.flags();
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std::cout << "[watch:path-range] #" << (logIndex + 1u)
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<< " op=" << op
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<< " addr=0x" << std::hex << writeAddr
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<< " size=0x" << size
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<< " pc=0x" << pc
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<< " ra=0x" << ra
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<< " sp=0x" << sp
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<< " firstByte=" << static_cast<uint32_t>(firstByte);
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ps2PathWatchDumpPrefix(rdram);
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std::cout.flags(flags);
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std::cout << std::endl;
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}
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inline std::atomic<uint8_t *> &ps2ScratchpadHostPtrStorage()
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{
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static std::atomic<uint8_t *> ptr{nullptr};
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return ptr;
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}
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inline void ps2SetScratchpadHostPtr(uint8_t *ptr)
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{
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ps2ScratchpadHostPtrStorage().store(ptr, std::memory_order_relaxed);
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}
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inline uint8_t *ps2GetScratchpadHostPtr()
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{
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return ps2ScratchpadHostPtrStorage().load(std::memory_order_relaxed);
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}
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inline bool ps2ResolveGuestPointer(uint32_t addr, uint32_t &offset, bool &scratch)
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{
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if (addr >= PS2_SCRATCHPAD_BASE && addr < (PS2_SCRATCHPAD_BASE + PS2_SCRATCHPAD_SIZE))
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{
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scratch = true;
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offset = addr - PS2_SCRATCHPAD_BASE;
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return true;
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}
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uint32_t phys = 0;
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if (addr < 0x20000000u)
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{
|
|
phys = addr;
|
|
}
|
|
else if ((addr >= 0x20000000u && addr < 0x40000000u) ||
|
|
(addr >= 0x80000000u && addr < 0xC0000000u))
|
|
{
|
|
phys = addr & 0x1FFFFFFFu;
|
|
}
|
|
else
|
|
{
|
|
// Keep legacy runtime behavior for odd upper-bit aliases used by game code.
|
|
phys = addr & PS2_RAM_MASK;
|
|
}
|
|
|
|
if (phys >= PS2_RAM_SIZE)
|
|
{
|
|
phys &= PS2_RAM_MASK;
|
|
}
|
|
|
|
scratch = false;
|
|
offset = phys;
|
|
return true;
|
|
}
|
|
inline uint8_t *getMemPtr(uint8_t *rdram, uint32_t addr)
|
|
{
|
|
if (rdram == nullptr)
|
|
{
|
|
return nullptr;
|
|
}
|
|
|
|
uint32_t offset = 0;
|
|
bool scratch = false;
|
|
if (!ps2ResolveGuestPointer(addr, offset, scratch))
|
|
{
|
|
return nullptr;
|
|
}
|
|
|
|
if (scratch)
|
|
{
|
|
uint8_t *scratchpad = ps2GetScratchpadHostPtr();
|
|
return scratchpad ? (scratchpad + offset) : nullptr;
|
|
}
|
|
return rdram + offset;
|
|
}
|
|
|
|
inline const uint8_t *getConstMemPtr(const uint8_t *rdram, uint32_t addr)
|
|
{
|
|
if (rdram == nullptr)
|
|
{
|
|
return nullptr;
|
|
}
|
|
|
|
uint32_t offset = 0;
|
|
bool scratch = false;
|
|
if (!ps2ResolveGuestPointer(addr, offset, scratch))
|
|
{
|
|
return nullptr;
|
|
}
|
|
|
|
if (scratch)
|
|
{
|
|
const uint8_t *scratchpad = ps2GetScratchpadHostPtr();
|
|
return scratchpad ? (scratchpad + offset) : nullptr;
|
|
}
|
|
return rdram + offset;
|
|
}
|
|
|
|
// PS2 GS (Graphics Synthesizer) registers
|
|
struct GSRegisters
|
|
{
|
|
uint64_t pmode; // Pixel mode
|
|
uint64_t smode1; // Sync mode 1
|
|
uint64_t smode2; // Sync mode 2
|
|
uint64_t srfsh; // Refresh control
|
|
uint64_t synch1; // Synchronization control 1
|
|
uint64_t synch2; // Synchronization control 2
|
|
uint64_t syncv; // Synchronization control V
|
|
uint64_t dispfb1; // Display buffer 1
|
|
uint64_t display1; // Display area 1
|
|
uint64_t dispfb2; // Display buffer 2
|
|
uint64_t display2; // Display area 2
|
|
uint64_t extbuf; // External buffer
|
|
uint64_t extdata; // External data
|
|
uint64_t extwrite; // External write
|
|
uint64_t bgcolor; // Background color
|
|
uint64_t csr; // Status
|
|
uint64_t imr; // Interrupt mask
|
|
uint64_t busdir; // Bus direction
|
|
uint64_t siglblid; // Signal label ID
|
|
};
|
|
static_assert(sizeof(GSRegisters) == (19u * sizeof(uint64_t)), "GSRegisters layout changed unexpectedly");
|
|
static_assert(alignof(GSRegisters) == alignof(uint64_t), "GSRegisters alignment must remain 64-bit");
|
|
|
|
// PS2 VIF (VPU Interface) registers
|
|
struct VIFRegisters
|
|
{
|
|
uint32_t stat; // Status
|
|
uint32_t fbrst; // VIF Force Break
|
|
uint32_t err; // Error status
|
|
uint32_t mark; // Interrupt control
|
|
uint32_t cycle; // Transfer mode
|
|
uint32_t mode; // Mode control
|
|
uint32_t num; // Data amount counter
|
|
uint32_t mask; // Data mask
|
|
uint32_t code; // VIFcode
|
|
uint32_t itops; // ITOP save
|
|
uint32_t base; // Base address
|
|
uint32_t ofst; // Offset
|
|
uint32_t tops; // TOPS
|
|
uint32_t itop; // ITOP
|
|
uint32_t top; // TOP
|
|
uint32_t row[4]; // Transfer row data
|
|
uint32_t col[4]; // Transfer column data
|
|
};
|
|
static_assert(sizeof(VIFRegisters) == (23u * sizeof(uint32_t)), "VIFRegisters layout changed unexpectedly");
|
|
|
|
// PS2 DMA registers
|
|
struct DMARegisters
|
|
{
|
|
uint32_t chcr; // Channel control
|
|
uint32_t madr; // Memory address
|
|
uint32_t qwc; // Quadword count
|
|
uint32_t tadr; // Tag address
|
|
uint32_t asr0; // Address stack 0
|
|
uint32_t asr1; // Address stack 1
|
|
uint32_t sadr; // Source address
|
|
};
|
|
static_assert(sizeof(DMARegisters) == (7u * sizeof(uint32_t)), "DMARegisters layout changed unexpectedly");
|
|
|
|
struct JumpTable
|
|
{
|
|
uint32_t address = 0; // Base address of the jump table
|
|
uint32_t baseRegister = 0; // Register used for index
|
|
std::vector<uint32_t> targets; // Jump targets
|
|
};
|
|
|
|
class PS2Memory
|
|
{
|
|
public:
|
|
PS2Memory();
|
|
~PS2Memory();
|
|
|
|
PS2Memory(const PS2Memory &) = delete;
|
|
PS2Memory &operator=(const PS2Memory &) = delete;
|
|
PS2Memory(PS2Memory &&) = delete;
|
|
PS2Memory &operator=(PS2Memory &&) = delete;
|
|
|
|
// Initialize memory
|
|
bool initialize(size_t ramSize = PS2_RAM_SIZE);
|
|
|
|
// Memory access methods
|
|
uint8_t *getRDRAM() { return m_rdram; }
|
|
uint8_t *getScratchpad() { return m_scratchpad; }
|
|
uint8_t *getIOPRAM() { return iop_ram; }
|
|
uint64_t dmaStartCount() const { return m_dmaStartCount.load(std::memory_order_relaxed); }
|
|
uint64_t gifCopyCount() const { return m_gifCopyCount.load(std::memory_order_relaxed); }
|
|
uint64_t gsWriteCount() const { return m_gsWriteCount.load(std::memory_order_relaxed); }
|
|
uint64_t vifWriteCount() const { return m_vifWriteCount.load(std::memory_order_relaxed); }
|
|
|
|
// Read/write memory
|
|
uint8_t read8(uint32_t address);
|
|
uint16_t read16(uint32_t address);
|
|
uint32_t read32(uint32_t address);
|
|
uint64_t read64(uint32_t address);
|
|
__m128i read128(uint32_t address);
|
|
|
|
void write8(uint32_t address, uint8_t value);
|
|
void write16(uint32_t address, uint16_t value);
|
|
void write32(uint32_t address, uint32_t value);
|
|
void write64(uint32_t address, uint64_t value);
|
|
void write128(uint32_t address, __m128i value);
|
|
|
|
// TLB handling
|
|
uint32_t translateAddress(uint32_t virtualAddress);
|
|
bool tlbRead(uint32_t index, uint32_t &vpn, uint32_t &pfn, uint32_t &mask, bool &valid) const;
|
|
bool tlbWrite(uint32_t index, uint32_t vpn, uint32_t pfn, uint32_t mask, bool valid);
|
|
int32_t tlbProbe(uint32_t vpn) const;
|
|
size_t tlbEntryCount() const { return m_tlbEntries.size(); }
|
|
|
|
// Hardware register interface
|
|
bool writeIORegister(uint32_t address, uint32_t value);
|
|
uint32_t readIORegister(uint32_t address);
|
|
|
|
// Track code modifications for self-modifying code
|
|
void registerCodeRegion(uint32_t start, uint32_t end);
|
|
bool isCodeModified(uint32_t address, uint32_t size);
|
|
void clearModifiedFlag(uint32_t address, uint32_t size);
|
|
|
|
// GS register accessors
|
|
GSRegisters &gs() { return gs_regs; }
|
|
const GSRegisters &gs() const { return gs_regs; }
|
|
uint8_t *getGSVRAM() { return m_gsVRAM; }
|
|
const uint8_t *getGSVRAM() const { return m_gsVRAM; }
|
|
bool hasSeenGifCopy() const { return m_seenGifCopy; }
|
|
// Main RAM (32MB)
|
|
uint8_t *m_rdram;
|
|
|
|
// Scratchpad memory (16KB)
|
|
uint8_t *m_scratchpad;
|
|
|
|
// IOP RAM (2MB)
|
|
uint8_t *iop_ram;
|
|
|
|
bool m_seenGifCopy;
|
|
std::atomic<uint64_t> m_dmaStartCount{0};
|
|
std::atomic<uint64_t> m_gifCopyCount{0};
|
|
std::atomic<uint64_t> m_gsWriteCount{0};
|
|
std::atomic<uint64_t> m_vifWriteCount{0};
|
|
// I/O registers
|
|
std::unordered_map<uint32_t, uint32_t> m_ioRegisters;
|
|
|
|
// Registers
|
|
GSRegisters gs_regs;
|
|
uint8_t *m_gsVRAM;
|
|
VIFRegisters vif0_regs;
|
|
VIFRegisters vif1_regs;
|
|
DMARegisters dma_regs[10]; // 10 DMA channels
|
|
|
|
// TLB entries
|
|
struct TLBEntry
|
|
{
|
|
uint32_t vpn;
|
|
uint32_t pfn;
|
|
uint32_t mask;
|
|
bool valid;
|
|
};
|
|
|
|
std::vector<TLBEntry> m_tlbEntries;
|
|
|
|
struct CodeRegion
|
|
{
|
|
uint32_t start;
|
|
uint32_t end;
|
|
std::vector<bool> modified; // Bitmap of modified 4-byte blocks
|
|
};
|
|
std::vector<CodeRegion> m_codeRegions;
|
|
|
|
bool isAddressInRegion(uint32_t address, const CodeRegion ®ion);
|
|
void markModified(uint32_t address, uint32_t size);
|
|
bool isScratchpad(uint32_t address) const;
|
|
};
|
|
|
|
class PS2Runtime
|
|
{
|
|
public:
|
|
struct IoPaths
|
|
{
|
|
std::filesystem::path elfPath;
|
|
std::filesystem::path elfDirectory;
|
|
std::filesystem::path hostRoot;
|
|
std::filesystem::path cdRoot;
|
|
std::filesystem::path cdImage;
|
|
};
|
|
|
|
PS2Runtime();
|
|
~PS2Runtime();
|
|
|
|
bool initialize(const char *title = "PS2 Game");
|
|
bool loadELF(const std::string &elfPath);
|
|
void run();
|
|
|
|
using RecompiledFunction = void (*)(uint8_t *, R5900Context *, PS2Runtime *);
|
|
|
|
void registerFunction(uint32_t address, RecompiledFunction func);
|
|
RecompiledFunction lookupFunction(uint32_t address);
|
|
bool hasFunction(uint32_t address) const;
|
|
|
|
static const IoPaths &getIoPaths();
|
|
static void setIoPaths(const IoPaths &paths);
|
|
static void configureIoPathsFromElf(const std::string &elfPath);
|
|
|
|
void SignalException(R5900Context *ctx, PS2Exception exception);
|
|
|
|
void executeVU0Microprogram(uint8_t *rdram, R5900Context *ctx, uint32_t address);
|
|
void vu0StartMicroProgram(uint8_t *rdram, R5900Context *ctx, uint32_t address);
|
|
|
|
public:
|
|
void handleSyscall(uint8_t *rdram, R5900Context *ctx);
|
|
void handleSyscall(uint8_t *rdram, R5900Context *ctx, uint32_t encodedSyscallId);
|
|
void handleBreak(uint8_t *rdram, R5900Context *ctx);
|
|
|
|
void handleTrap(uint8_t *rdram, R5900Context *ctx);
|
|
void handleTLBR(uint8_t *rdram, R5900Context *ctx);
|
|
void handleTLBWI(uint8_t *rdram, R5900Context *ctx);
|
|
void handleTLBWR(uint8_t *rdram, R5900Context *ctx);
|
|
void handleTLBP(uint8_t *rdram, R5900Context *ctx);
|
|
void clearLLBit(R5900Context *ctx);
|
|
void configureGuestHeap(uint32_t guestBase, uint32_t guestLimit = PS2_RAM_SIZE);
|
|
uint32_t guestMalloc(uint32_t size, uint32_t alignment = 16u);
|
|
uint32_t guestCalloc(uint32_t count, uint32_t size, uint32_t alignment = 16u);
|
|
uint32_t guestRealloc(uint32_t guestAddr, uint32_t newSize, uint32_t alignment = 16u);
|
|
void guestFree(uint32_t guestAddr);
|
|
uint32_t guestHeapBase() const;
|
|
uint32_t guestHeapEnd() const;
|
|
void dispatchLoop(uint8_t *rdram, R5900Context *ctx);
|
|
void requestStop();
|
|
bool isStopRequested() const;
|
|
|
|
uint8_t Load8(uint8_t *rdram, R5900Context *ctx, uint32_t vaddr);
|
|
uint16_t Load16(uint8_t *rdram, R5900Context *ctx, uint32_t vaddr);
|
|
uint32_t Load32(uint8_t *rdram, R5900Context *ctx, uint32_t vaddr);
|
|
uint64_t Load64(uint8_t *rdram, R5900Context *ctx, uint32_t vaddr);
|
|
__m128i Load128(uint8_t *rdram, R5900Context *ctx, uint32_t vaddr);
|
|
|
|
void Store8(uint8_t *rdram, R5900Context *ctx, uint32_t vaddr, uint8_t value);
|
|
void Store16(uint8_t *rdram, R5900Context *ctx, uint32_t vaddr, uint16_t value);
|
|
void Store32(uint8_t *rdram, R5900Context *ctx, uint32_t vaddr, uint32_t value);
|
|
void Store64(uint8_t *rdram, R5900Context *ctx, uint32_t vaddr, uint64_t value);
|
|
void Store128(uint8_t *rdram, R5900Context *ctx, uint32_t vaddr, __m128i value);
|
|
|
|
static inline bool isSpecialAddress(uint32_t addr)
|
|
{
|
|
// BIOS (physical + cached/uncached aliases)
|
|
if ((addr >= PS2_BIOS_BASE && addr < (PS2_BIOS_BASE + PS2_BIOS_SIZE)) ||
|
|
(addr >= 0xBFC00000u && addr < (0xBFC00000u + PS2_BIOS_SIZE)))
|
|
{
|
|
return true;
|
|
}
|
|
|
|
// Scratchpad (16KB)
|
|
if (addr >= PS2_SCRATCHPAD_BASE && addr < (PS2_SCRATCHPAD_BASE + PS2_SCRATCHPAD_SIZE))
|
|
return true;
|
|
|
|
// EE MMIO window (Timers, DMAC, INTC, etc)
|
|
if (addr >= PS2_IO_BASE && addr < (PS2_IO_BASE + PS2_IO_SIZE))
|
|
return true;
|
|
|
|
// GS privileged regs
|
|
if (addr >= PS2_GS_PRIV_REG_BASE && addr < (PS2_GS_PRIV_REG_BASE + PS2_GS_PRIV_REG_SIZE))
|
|
return true;
|
|
|
|
// KSEG2/KSEG3 (TLB mapped)
|
|
if (addr >= 0xC0000000u)
|
|
return true;
|
|
|
|
// VU Memory (Micro/Data) mapped into EE space
|
|
if (addr >= PS2_VU0_CODE_BASE && addr < (PS2_VU1_DATA_BASE + PS2_VU1_DATA_SIZE))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
public:
|
|
inline R5900Context &cpu() { return m_cpuContext; }
|
|
inline const R5900Context &cpu() const { return m_cpuContext; }
|
|
|
|
inline PS2Memory &memory() { return m_memory; }
|
|
inline const PS2Memory &memory() const { return m_memory; }
|
|
|
|
private:
|
|
struct GuestHeapBlock
|
|
{
|
|
uint32_t addr = 0;
|
|
uint32_t size = 0;
|
|
bool free = true;
|
|
};
|
|
|
|
static uint32_t alignGuestHeapValue(uint32_t value, uint32_t alignment);
|
|
static bool isGuestHeapAlignmentValid(uint32_t alignment);
|
|
static uint32_t normalizeGuestHeapAlignment(uint32_t alignment);
|
|
uint32_t clampGuestHeapBase(uint32_t guestBase) const;
|
|
uint32_t clampGuestHeapLimit(uint32_t guestLimit) const;
|
|
void resetGuestHeapLocked(uint32_t guestBase, uint32_t guestLimit);
|
|
void ensureGuestHeapInitializedLocked();
|
|
int32_t findGuestHeapBlockIndexLocked(uint32_t guestAddr) const;
|
|
uint32_t allocateGuestBlockLocked(uint32_t size, uint32_t alignment);
|
|
void freeGuestBlockLocked(uint32_t guestAddr);
|
|
void coalesceGuestHeapLocked();
|
|
|
|
void HandleIntegerOverflow(R5900Context *ctx);
|
|
|
|
private:
|
|
PS2Memory m_memory;
|
|
R5900Context m_cpuContext;
|
|
mutable std::mutex m_guestHeapMutex;
|
|
std::vector<GuestHeapBlock> m_guestHeapBlocks;
|
|
uint32_t m_guestHeapBase = 0x00100000u;
|
|
uint32_t m_guestHeapEnd = 0x00100000u;
|
|
uint32_t m_guestHeapLimit = PS2_RAM_SIZE;
|
|
uint32_t m_guestHeapSuggestedBase = 0x00100000u;
|
|
bool m_guestHeapConfigured = false;
|
|
|
|
std::unordered_map<uint32_t, RecompiledFunction> m_functionTable;
|
|
std::atomic<bool> m_stopRequested{false};
|
|
|
|
// TODO remove this later
|
|
std::atomic<uint32_t> m_debugPc{0};
|
|
std::atomic<uint32_t> m_debugRa{0};
|
|
std::atomic<uint32_t> m_debugSp{0};
|
|
std::atomic<uint32_t> m_debugGp{0};
|
|
|
|
struct LoadedModule
|
|
{
|
|
std::string name;
|
|
uint32_t baseAddress;
|
|
size_t size;
|
|
bool active;
|
|
};
|
|
|
|
std::vector<LoadedModule> m_loadedModules;
|
|
};
|
|
|
|
#endif // PS2_RUNTIME_H
|