mirror of
https://github.com/HarbourMasters/Shipwright
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Pepe20129
9bed5af33b
* Remove unused headers * Move all "ResourceMgr_" functions to a new file * Don't transitively include SaveManager * Move cvar prefixes to a new header * Add missing includes * Update OTRGlobals.cpp * Fix build * Address review * Fix some of the errors * Update gameplaystats.h * Update z_en_in.c * Hopefully fix the linux issues * Fix Linux issues for real this time, I checked * Update ResourceManagerHelpers.cpp * Update z_obj_mure2.c * Post-merge fixes * Fix build (hopefully) * Post-merge fixes * Update z_file_nameset_PAL.c * cleanup some unnecessary headers (#7) --------- Co-authored-by: Archez <Archez@users.noreply.github.com>
74 lines
2.4 KiB
C
74 lines
2.4 KiB
C
#include <libultraship/libultra.h>
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#include "global.h"
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#include "soh/OTRGlobals.h"
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#include <stdio.h>
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#include <assert.h>
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#if 0
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typedef struct {
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/* 0x00 */ OSPiHandle piHandle;
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/* 0x74 */ OSIoMesg ioMesg;
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/* 0x8C */ OSMesgQueue mesgQ;
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} SsSramContext; // size = 0xA4
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SsSramContext sSsSramContext = { 0 };
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void SsSram_Init(uintptr_t addr, u8 handleType, u8 handleDomain, u8 handleLatency, u8 handlePageSize, u8 handleRelDuration,
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u8 handlePulse, u32 handleSpeed) {
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u32 prevInt;
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OSPiHandle* handle = &sSsSramContext.piHandle;
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if ((uintptr_t)OS_PHYSICAL_TO_K1(addr) != (*handle).baseAddress) {
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sSsSramContext.piHandle.type = handleType;
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(*handle).baseAddress = OS_PHYSICAL_TO_K1(addr);
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sSsSramContext.piHandle.latency = handleLatency;
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sSsSramContext.piHandle.pulse = handlePulse;
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sSsSramContext.piHandle.pageSize = handlePageSize;
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sSsSramContext.piHandle.relDuration = handleRelDuration;
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sSsSramContext.piHandle.domain = handleDomain;
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sSsSramContext.piHandle.speed = handleSpeed;
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bzero(&sSsSramContext.piHandle.transferInfo, sizeof(__OSTranxInfo));
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prevInt = __osDisableInt();
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//sSsSramContext.piHandle.next = __osPiTable;
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//__osPiTable = &sSsSramContext.piHandle;
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__osRestoreInt(prevInt);
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sSsSramContext.ioMesg.hdr.pri = OS_MESG_PRI_NORMAL;
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sSsSramContext.ioMesg.hdr.retQueue = &sSsSramContext.mesgQ;
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sSsSramContext.ioMesg.devAddr = addr;
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}
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}
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void SsSram_Dma(void* dramAddr, size_t size, s32 direction) {
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OSMesg mesg;
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osCreateMesgQueue(&sSsSramContext.mesgQ, &mesg, 1);
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sSsSramContext.ioMesg.dramAddr = dramAddr;
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sSsSramContext.ioMesg.size = size;
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osWritebackDCache(dramAddr, size);
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osEPiStartDma(&sSsSramContext.piHandle, &sSsSramContext.ioMesg, direction);
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osRecvMesg(&sSsSramContext.mesgQ, &mesg, OS_MESG_BLOCK);
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osInvalDCache(dramAddr, size);
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}
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#endif
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void SsSram_ReadWrite(uintptr_t addr, void* dramAddr, size_t size, s32 direction) {
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osSyncPrintf("ssSRAMReadWrite:%08x %08x %08x %d\n", addr, (uintptr_t)dramAddr, size, direction);
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switch (direction) {
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case OS_WRITE: {
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Ctx_WriteSaveFile(addr, dramAddr, size);
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} break;
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case OS_READ: {
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Ctx_ReadSaveFile(addr, dramAddr, size);
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} break;
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}
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//SsSram_Init(addr, DEVICE_TYPE_SRAM, PI_DOMAIN2, 5, 0xD, 2, 0xC, 0);
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//SsSram_Dma(dramAddr, size, direction);
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}
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