mirror of
https://github.com/ACreTeam/ac-decomp
synced 2026-05-23 06:34:18 -04:00
Luke Street
101 lines
4.3 KiB
C
101 lines
4.3 KiB
C
#ifndef PPCARCH_H
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#define PPCARCH_H
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#include "types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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u32 PPCMfmsr(void);
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void PPCMtmsr(u32);
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u32 PPCMfhid0(void);
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void PPCMthid0(u32);
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u32 PPCMfl2cr(void);
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void PPCMtl2cr(u32);
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void PPCMtdec(u32);
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void PPCSync(void);
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void PPCHalt(void);
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u32 PPCMfhid2(void);
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void PPCMthid2(u32);
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void PPCMtwpar(u32);
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void PPCDisableSpeculation(void);
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void PPCSetFpNonIEEEMode(void);
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#define HID0_EMCP 0x80000000u // Enable MCP
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#define HID0_DBP 0x40000000u // Enable 60x bus address and data parity chk
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#define HID0_EBA 0x20000000u // Enable 60x address parity checking
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#define HID0_EBD 0x10000000u // Enable 60x data parity checking
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#define HID0_BCLK 0x08000000u // CLK_OUT output enable and clk selection
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#define HID0_ECLK 0x02000000u // CLK_OUT output enable and clk selection
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#define HID0_PAR 0x01000000u // Disable !ARTRY precharge
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#define HID0_DOZE 0x00800000u // Doze mode enable
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#define HID0_NAP 0x00400000u // Nap mode enable
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#define HID0_SLEEP 0x00200000u // Sleep mode enable
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#define HID0_DPM 0x00100000u // Dynamic power management enable
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#define HID0_NHR 0x00010000u // Not hard reset (0 hard reset if s/w set it)
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#define HID0_ICE 0x00008000u // Instruction cache enable
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#define HID0_DCE 0x00004000u // Data cache enable
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#define HID0_ILOCK 0x00002000u // ICache lock
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#define HID0_DLOCK 0x00001000u // DCache lock
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#define HID0_ICFI 0x00000800u // ICache flash invalidate
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#define HID0_DCFI 0x00000400u // DCache flash invalidate
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#define HID0_SPD 0x00000200u // Speculative cache access enable (0 enable)
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#define HID0_IFEM 0x00000100u // Enable M bit on bus for Ifetch
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#define HID0_SGE 0x00000080u // Store gathering enable
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#define HID0_DCFA 0x00000040u // DCache flush assist - set before a flush
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#define HID0_BTIC 0x00000020u // Branch target icache enable
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#define HID0_ABE 0x00000008u // Address bcast enable
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#define HID0_BHT 0x00000004u // Branch history table enable
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#define HID0_NOOPTI 0x00000001u // No-op Dcache touch instructions
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#define HID2_DCHERR 0x00800000 // ERROR: dcbz_l cache hit
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#define HID2_DNCERR 0x00400000 // ERROR: DMA access to normal cache
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#define HID2_DCMERR 0x00200000 // ERROR: DMA cache miss error
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#define HID2_DQOERR 0x00100000 // ERROR: DMA queue overflow
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#define HID2_DCHEE 0x00080000 // dcbz_l cache hit error enable
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#define HID2_DNCEE 0x00040000 // DMA access to normal cache error enable
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#define HID2_DCMEE 0x00020000 // DMA cache miss error error enable
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#define HID2_DQOEE 0x00010000 // DMA queue overflow error enable
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#define SRR1_DMA_BIT 0x00200000
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#define SRR1_L2DP_BIT 0x00100000
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#define L2CR_L2E 0x80000000 // L2 Enable
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#define L2CR_L2PE 0x40000000 // L2 data parity generation and checking enable
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#define L2CR_L2DO 0x00400000 // Data only
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#define L2CR_L2I 0x00200000 // Global invalidate
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#define L2CR_L2CTL 0x00100000 // ZZ enable
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#define L2CR_L2WT 0x00080000 // L2 write through
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#define L2CR_L2TS 0x00040000 // L2 test support
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#define MSR_POW 0x00040000 // Power Management
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#define MSR_ILE 0x00010000 // Interrupt Little Endian
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#define MSR_EE 0x00008000 // external interrupt
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#define MSR_PR 0x00004000 // privilege level(should be 0)
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#define MSR_FP 0x00002000 // floating point available
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#define MSR_ME 0x00001000 // machine check enable
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#define MSR_FE0 0x00000800 // floating point exception enable
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#define MSR_SE 0x00000400 // single step trace enable
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#define MSR_BE 0x00000200 // branch trace enable
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#define MSR_FE1 0x00000100 // floating point exception enable
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#define MSR_IP 0x00000040 // Exception prefix
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#define MSR_IR 0x00000020 // instruction relocate
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#define MSR_DR 0x00000010 // data relocate
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#define MSR_PM 0x00000004 // Performance monitor marked mode
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#define MSR_RI 0x00000002 // Recoverable interrupt
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#define MSR_LE 0x00000001 // Little Endian
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#ifdef __cplusplus
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}
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#endif
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#endif
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